1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "hw/pci/pci.h" 27 #include "hw/nvram/eeprom93xx.h" 28 #include "hw/scsi/esp.h" 29 #include "trace.h" 30 #include "qemu/log.h" 31 32 #define TYPE_AM53C974_DEVICE "am53c974" 33 34 #define DMA_CMD 0x0 35 #define DMA_STC 0x1 36 #define DMA_SPA 0x2 37 #define DMA_WBC 0x3 38 #define DMA_WAC 0x4 39 #define DMA_STAT 0x5 40 #define DMA_SMDLA 0x6 41 #define DMA_WMAC 0x7 42 43 #define DMA_CMD_MASK 0x03 44 #define DMA_CMD_DIAG 0x04 45 #define DMA_CMD_MDL 0x10 46 #define DMA_CMD_INTE_P 0x20 47 #define DMA_CMD_INTE_D 0x40 48 #define DMA_CMD_DIR 0x80 49 50 #define DMA_STAT_PWDN 0x01 51 #define DMA_STAT_ERROR 0x02 52 #define DMA_STAT_ABORT 0x04 53 #define DMA_STAT_DONE 0x08 54 #define DMA_STAT_SCSIINT 0x10 55 #define DMA_STAT_BCMBLT 0x20 56 57 #define SBAC_STATUS 0x1000 58 59 typedef struct PCIESPState { 60 PCIDevice dev; 61 MemoryRegion io; 62 uint32_t dma_regs[8]; 63 uint32_t sbac; 64 ESPState esp; 65 } PCIESPState; 66 67 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val) 68 { 69 trace_esp_pci_dma_idle(val); 70 esp_dma_enable(&pci->esp, 0, 0); 71 } 72 73 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val) 74 { 75 trace_esp_pci_dma_blast(val); 76 qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n"); 77 } 78 79 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val) 80 { 81 trace_esp_pci_dma_abort(val); 82 if (pci->esp.current_req) { 83 scsi_req_cancel(pci->esp.current_req); 84 } 85 } 86 87 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val) 88 { 89 trace_esp_pci_dma_start(val); 90 91 pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC]; 92 pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA]; 93 pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA]; 94 95 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT 96 | DMA_STAT_DONE | DMA_STAT_ABORT 97 | DMA_STAT_ERROR | DMA_STAT_PWDN); 98 99 esp_dma_enable(&pci->esp, 0, 1); 100 } 101 102 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val) 103 { 104 trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val); 105 switch (saddr) { 106 case DMA_CMD: 107 pci->dma_regs[saddr] = val; 108 switch (val & DMA_CMD_MASK) { 109 case 0x0: /* IDLE */ 110 esp_pci_handle_idle(pci, val); 111 break; 112 case 0x1: /* BLAST */ 113 esp_pci_handle_blast(pci, val); 114 break; 115 case 0x2: /* ABORT */ 116 esp_pci_handle_abort(pci, val); 117 break; 118 case 0x3: /* START */ 119 esp_pci_handle_start(pci, val); 120 break; 121 default: /* can't happen */ 122 abort(); 123 } 124 break; 125 case DMA_STC: 126 case DMA_SPA: 127 case DMA_SMDLA: 128 pci->dma_regs[saddr] = val; 129 break; 130 case DMA_STAT: 131 if (!(pci->sbac & SBAC_STATUS)) { 132 /* clear some bits on write */ 133 uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE; 134 pci->dma_regs[DMA_STAT] &= ~(val & mask); 135 } 136 break; 137 default: 138 trace_esp_pci_error_invalid_write_dma(val, saddr); 139 return; 140 } 141 } 142 143 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr) 144 { 145 uint32_t val; 146 147 val = pci->dma_regs[saddr]; 148 if (saddr == DMA_STAT) { 149 if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) { 150 val |= DMA_STAT_SCSIINT; 151 } 152 if (pci->sbac & SBAC_STATUS) { 153 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT | 154 DMA_STAT_DONE); 155 } 156 } 157 158 trace_esp_pci_dma_read(saddr, val); 159 return val; 160 } 161 162 static void esp_pci_io_write(void *opaque, hwaddr addr, 163 uint64_t val, unsigned int size) 164 { 165 PCIESPState *pci = opaque; 166 167 if (size < 4 || addr & 3) { 168 /* need to upgrade request: we only support 4-bytes accesses */ 169 uint32_t current = 0, mask; 170 int shift; 171 172 if (addr < 0x40) { 173 current = pci->esp.wregs[addr >> 2]; 174 } else if (addr < 0x60) { 175 current = pci->dma_regs[(addr - 0x40) >> 2]; 176 } else if (addr < 0x74) { 177 current = pci->sbac; 178 } 179 180 shift = (4 - size) * 8; 181 mask = (~(uint32_t)0 << shift) >> shift; 182 183 shift = ((4 - (addr & 3)) & 3) * 8; 184 val <<= shift; 185 val |= current & ~(mask << shift); 186 addr &= ~3; 187 size = 4; 188 } 189 190 if (addr < 0x40) { 191 /* SCSI core reg */ 192 esp_reg_write(&pci->esp, addr >> 2, val); 193 } else if (addr < 0x60) { 194 /* PCI DMA CCB */ 195 esp_pci_dma_write(pci, (addr - 0x40) >> 2, val); 196 } else if (addr == 0x70) { 197 /* DMA SCSI Bus and control */ 198 trace_esp_pci_sbac_write(pci->sbac, val); 199 pci->sbac = val; 200 } else { 201 trace_esp_pci_error_invalid_write((int)addr); 202 } 203 } 204 205 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr, 206 unsigned int size) 207 { 208 PCIESPState *pci = opaque; 209 uint32_t ret; 210 211 if (addr < 0x40) { 212 /* SCSI core reg */ 213 ret = esp_reg_read(&pci->esp, addr >> 2); 214 } else if (addr < 0x60) { 215 /* PCI DMA CCB */ 216 ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2); 217 } else if (addr == 0x70) { 218 /* DMA SCSI Bus and control */ 219 trace_esp_pci_sbac_read(pci->sbac); 220 ret = pci->sbac; 221 } else { 222 /* Invalid region */ 223 trace_esp_pci_error_invalid_read((int)addr); 224 ret = 0; 225 } 226 227 /* give only requested data */ 228 ret >>= (addr & 3) * 8; 229 ret &= ~(~(uint64_t)0 << (8 * size)); 230 231 return ret; 232 } 233 234 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len, 235 DMADirection dir) 236 { 237 dma_addr_t addr; 238 DMADirection expected_dir; 239 240 if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) { 241 expected_dir = DMA_DIRECTION_FROM_DEVICE; 242 } else { 243 expected_dir = DMA_DIRECTION_TO_DEVICE; 244 } 245 246 if (dir != expected_dir) { 247 trace_esp_pci_error_invalid_dma_direction(); 248 return; 249 } 250 251 if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) { 252 qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n"); 253 } 254 255 addr = pci->dma_regs[DMA_SPA]; 256 if (pci->dma_regs[DMA_WBC] < len) { 257 len = pci->dma_regs[DMA_WBC]; 258 } 259 260 pci_dma_rw(&pci->dev, addr, buf, len, dir); 261 262 /* update status registers */ 263 pci->dma_regs[DMA_WBC] -= len; 264 pci->dma_regs[DMA_WAC] += len; 265 } 266 267 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len) 268 { 269 PCIESPState *pci = opaque; 270 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE); 271 } 272 273 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len) 274 { 275 PCIESPState *pci = opaque; 276 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE); 277 } 278 279 static const MemoryRegionOps esp_pci_io_ops = { 280 .read = esp_pci_io_read, 281 .write = esp_pci_io_write, 282 .endianness = DEVICE_LITTLE_ENDIAN, 283 .impl = { 284 .min_access_size = 1, 285 .max_access_size = 4, 286 }, 287 }; 288 289 static void esp_pci_hard_reset(DeviceState *dev) 290 { 291 PCIESPState *pci = DO_UPCAST(PCIESPState, dev.qdev, dev); 292 esp_hard_reset(&pci->esp); 293 pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P 294 | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK); 295 pci->dma_regs[DMA_WBC] &= ~0xffff; 296 pci->dma_regs[DMA_WAC] = 0xffffffff; 297 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT 298 | DMA_STAT_DONE | DMA_STAT_ABORT 299 | DMA_STAT_ERROR); 300 pci->dma_regs[DMA_WMAC] = 0xfffffffd; 301 } 302 303 static const VMStateDescription vmstate_esp_pci_scsi = { 304 .name = "pciespscsi", 305 .version_id = 0, 306 .minimum_version_id = 0, 307 .minimum_version_id_old = 0, 308 .fields = (VMStateField[]) { 309 VMSTATE_PCI_DEVICE(dev, PCIESPState), 310 VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)), 311 VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState), 312 VMSTATE_END_OF_LIST() 313 } 314 }; 315 316 static void esp_pci_command_complete(SCSIRequest *req, uint32_t status, 317 size_t resid) 318 { 319 ESPState *s = req->hba_private; 320 PCIESPState *pci = container_of(s, PCIESPState, esp); 321 322 esp_command_complete(req, status, resid); 323 pci->dma_regs[DMA_WBC] = 0; 324 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE; 325 } 326 327 static const struct SCSIBusInfo esp_pci_scsi_info = { 328 .tcq = false, 329 .max_target = ESP_MAX_DEVS, 330 .max_lun = 7, 331 332 .transfer_data = esp_transfer_data, 333 .complete = esp_pci_command_complete, 334 .cancel = esp_request_cancelled, 335 }; 336 337 static int esp_pci_scsi_init(PCIDevice *dev) 338 { 339 PCIESPState *pci = DO_UPCAST(PCIESPState, dev, dev); 340 ESPState *s = &pci->esp; 341 uint8_t *pci_conf; 342 343 pci_conf = pci->dev.config; 344 345 /* Interrupt pin A */ 346 pci_conf[PCI_INTERRUPT_PIN] = 0x01; 347 348 s->dma_memory_read = esp_pci_dma_memory_read; 349 s->dma_memory_write = esp_pci_dma_memory_write; 350 s->dma_opaque = pci; 351 s->chip_id = TCHI_AM53C974; 352 memory_region_init_io(&pci->io, &esp_pci_io_ops, pci, "esp-io", 0x80); 353 354 pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io); 355 s->irq = pci->dev.irq[0]; 356 357 scsi_bus_new(&s->bus, &dev->qdev, &esp_pci_scsi_info, NULL); 358 if (!dev->qdev.hotplugged) { 359 return scsi_bus_legacy_handle_cmdline(&s->bus); 360 } 361 return 0; 362 } 363 364 static void esp_pci_scsi_uninit(PCIDevice *d) 365 { 366 PCIESPState *pci = DO_UPCAST(PCIESPState, dev, d); 367 368 memory_region_destroy(&pci->io); 369 } 370 371 static void esp_pci_class_init(ObjectClass *klass, void *data) 372 { 373 DeviceClass *dc = DEVICE_CLASS(klass); 374 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 375 376 k->init = esp_pci_scsi_init; 377 k->exit = esp_pci_scsi_uninit; 378 k->vendor_id = PCI_VENDOR_ID_AMD; 379 k->device_id = PCI_DEVICE_ID_AMD_SCSI; 380 k->revision = 0x10; 381 k->class_id = PCI_CLASS_STORAGE_SCSI; 382 dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter"; 383 dc->reset = esp_pci_hard_reset; 384 dc->vmsd = &vmstate_esp_pci_scsi; 385 } 386 387 static const TypeInfo esp_pci_info = { 388 .name = TYPE_AM53C974_DEVICE, 389 .parent = TYPE_PCI_DEVICE, 390 .instance_size = sizeof(PCIESPState), 391 .class_init = esp_pci_class_init, 392 }; 393 394 typedef struct { 395 PCIESPState pci; 396 eeprom_t *eeprom; 397 } DC390State; 398 399 #define TYPE_DC390_DEVICE "dc390" 400 #define DC390(obj) \ 401 OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE) 402 403 #define EE_ADAPT_SCSI_ID 64 404 #define EE_MODE2 65 405 #define EE_DELAY 66 406 #define EE_TAG_CMD_NUM 67 407 #define EE_ADAPT_OPTIONS 68 408 #define EE_BOOT_SCSI_ID 69 409 #define EE_BOOT_SCSI_LUN 70 410 #define EE_CHKSUM1 126 411 #define EE_CHKSUM2 127 412 413 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT 0x01 414 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02 415 #define EE_ADAPT_OPTION_INT13 0x04 416 #define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08 417 418 419 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l) 420 { 421 DC390State *pci = DC390(dev); 422 uint32_t val; 423 424 val = pci_default_read_config(dev, addr, l); 425 426 if (addr == 0x00 && l == 1) { 427 /* First byte of address space is AND-ed with EEPROM DO line */ 428 if (!eeprom93xx_read(pci->eeprom)) { 429 val &= ~0xff; 430 } 431 } 432 433 return val; 434 } 435 436 static void dc390_write_config(PCIDevice *dev, 437 uint32_t addr, uint32_t val, int l) 438 { 439 DC390State *pci = DC390(dev); 440 if (addr == 0x80) { 441 /* EEPROM write */ 442 int eesk = val & 0x80 ? 1 : 0; 443 int eedi = val & 0x40 ? 1 : 0; 444 eeprom93xx_write(pci->eeprom, 1, eesk, eedi); 445 } else if (addr == 0xc0) { 446 /* EEPROM CS low */ 447 eeprom93xx_write(pci->eeprom, 0, 0, 0); 448 } else { 449 pci_default_write_config(dev, addr, val, l); 450 } 451 } 452 453 static int dc390_scsi_init(PCIDevice *dev) 454 { 455 DC390State *pci = DC390(dev); 456 uint8_t *contents; 457 uint16_t chksum = 0; 458 int i, ret; 459 460 /* init base class */ 461 ret = esp_pci_scsi_init(dev); 462 if (ret < 0) { 463 return ret; 464 } 465 466 /* EEPROM */ 467 pci->eeprom = eeprom93xx_new(DEVICE(dev), 64); 468 469 /* set default eeprom values */ 470 contents = (uint8_t *)eeprom93xx_data(pci->eeprom); 471 472 for (i = 0; i < 16; i++) { 473 contents[i * 2] = 0x57; 474 contents[i * 2 + 1] = 0x00; 475 } 476 contents[EE_ADAPT_SCSI_ID] = 7; 477 contents[EE_MODE2] = 0x0f; 478 contents[EE_TAG_CMD_NUM] = 0x04; 479 contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT 480 | EE_ADAPT_OPTION_BOOT_FROM_CDROM 481 | EE_ADAPT_OPTION_INT13; 482 483 /* update eeprom checksum */ 484 for (i = 0; i < EE_CHKSUM1; i += 2) { 485 chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8); 486 } 487 chksum = 0x1234 - chksum; 488 contents[EE_CHKSUM1] = chksum & 0xff; 489 contents[EE_CHKSUM2] = chksum >> 8; 490 491 return 0; 492 } 493 494 static void dc390_class_init(ObjectClass *klass, void *data) 495 { 496 DeviceClass *dc = DEVICE_CLASS(klass); 497 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 498 499 k->init = dc390_scsi_init; 500 k->config_read = dc390_read_config; 501 k->config_write = dc390_write_config; 502 dc->desc = "Tekram DC-390 SCSI adapter"; 503 } 504 505 static const TypeInfo dc390_info = { 506 .name = "dc390", 507 .parent = TYPE_AM53C974_DEVICE, 508 .instance_size = sizeof(DC390State), 509 .class_init = dc390_class_init, 510 }; 511 512 static void esp_pci_register_types(void) 513 { 514 type_register_static(&esp_pci_info); 515 type_register_static(&dc390_info); 516 } 517 518 type_init(esp_pci_register_types) 519