1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/pci/pci.h" 28 #include "hw/irq.h" 29 #include "hw/nvram/eeprom93xx.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qapi/error.h" 33 #include "qemu/log.h" 34 #include "qemu/module.h" 35 36 #define TYPE_AM53C974_DEVICE "am53c974" 37 38 #define PCI_ESP(obj) \ 39 OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE) 40 41 #define DMA_CMD 0x0 42 #define DMA_STC 0x1 43 #define DMA_SPA 0x2 44 #define DMA_WBC 0x3 45 #define DMA_WAC 0x4 46 #define DMA_STAT 0x5 47 #define DMA_SMDLA 0x6 48 #define DMA_WMAC 0x7 49 50 #define DMA_CMD_MASK 0x03 51 #define DMA_CMD_DIAG 0x04 52 #define DMA_CMD_MDL 0x10 53 #define DMA_CMD_INTE_P 0x20 54 #define DMA_CMD_INTE_D 0x40 55 #define DMA_CMD_DIR 0x80 56 57 #define DMA_STAT_PWDN 0x01 58 #define DMA_STAT_ERROR 0x02 59 #define DMA_STAT_ABORT 0x04 60 #define DMA_STAT_DONE 0x08 61 #define DMA_STAT_SCSIINT 0x10 62 #define DMA_STAT_BCMBLT 0x20 63 64 #define SBAC_STATUS (1 << 24) 65 66 typedef struct PCIESPState { 67 /*< private >*/ 68 PCIDevice parent_obj; 69 /*< public >*/ 70 71 MemoryRegion io; 72 uint32_t dma_regs[8]; 73 uint32_t sbac; 74 ESPState esp; 75 } PCIESPState; 76 77 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val) 78 { 79 trace_esp_pci_dma_idle(val); 80 esp_dma_enable(&pci->esp, 0, 0); 81 } 82 83 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val) 84 { 85 trace_esp_pci_dma_blast(val); 86 qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n"); 87 } 88 89 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val) 90 { 91 trace_esp_pci_dma_abort(val); 92 if (pci->esp.current_req) { 93 scsi_req_cancel(pci->esp.current_req); 94 } 95 } 96 97 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val) 98 { 99 trace_esp_pci_dma_start(val); 100 101 pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC]; 102 pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA]; 103 pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA]; 104 105 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT 106 | DMA_STAT_DONE | DMA_STAT_ABORT 107 | DMA_STAT_ERROR | DMA_STAT_PWDN); 108 109 esp_dma_enable(&pci->esp, 0, 1); 110 } 111 112 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val) 113 { 114 trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val); 115 switch (saddr) { 116 case DMA_CMD: 117 pci->dma_regs[saddr] = val; 118 switch (val & DMA_CMD_MASK) { 119 case 0x0: /* IDLE */ 120 esp_pci_handle_idle(pci, val); 121 break; 122 case 0x1: /* BLAST */ 123 esp_pci_handle_blast(pci, val); 124 break; 125 case 0x2: /* ABORT */ 126 esp_pci_handle_abort(pci, val); 127 break; 128 case 0x3: /* START */ 129 esp_pci_handle_start(pci, val); 130 break; 131 default: /* can't happen */ 132 abort(); 133 } 134 break; 135 case DMA_STC: 136 case DMA_SPA: 137 case DMA_SMDLA: 138 pci->dma_regs[saddr] = val; 139 break; 140 case DMA_STAT: 141 if (pci->sbac & SBAC_STATUS) { 142 /* clear some bits on write */ 143 uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE; 144 pci->dma_regs[DMA_STAT] &= ~(val & mask); 145 } 146 break; 147 default: 148 trace_esp_pci_error_invalid_write_dma(val, saddr); 149 return; 150 } 151 } 152 153 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr) 154 { 155 uint32_t val; 156 157 val = pci->dma_regs[saddr]; 158 if (saddr == DMA_STAT) { 159 if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) { 160 val |= DMA_STAT_SCSIINT; 161 } 162 if (!(pci->sbac & SBAC_STATUS)) { 163 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT | 164 DMA_STAT_DONE); 165 } 166 } 167 168 trace_esp_pci_dma_read(saddr, val); 169 return val; 170 } 171 172 static void esp_pci_io_write(void *opaque, hwaddr addr, 173 uint64_t val, unsigned int size) 174 { 175 PCIESPState *pci = opaque; 176 177 if (size < 4 || addr & 3) { 178 /* need to upgrade request: we only support 4-bytes accesses */ 179 uint32_t current = 0, mask; 180 int shift; 181 182 if (addr < 0x40) { 183 current = pci->esp.wregs[addr >> 2]; 184 } else if (addr < 0x60) { 185 current = pci->dma_regs[(addr - 0x40) >> 2]; 186 } else if (addr < 0x74) { 187 current = pci->sbac; 188 } 189 190 shift = (4 - size) * 8; 191 mask = (~(uint32_t)0 << shift) >> shift; 192 193 shift = ((4 - (addr & 3)) & 3) * 8; 194 val <<= shift; 195 val |= current & ~(mask << shift); 196 addr &= ~3; 197 size = 4; 198 } 199 200 if (addr < 0x40) { 201 /* SCSI core reg */ 202 esp_reg_write(&pci->esp, addr >> 2, val); 203 } else if (addr < 0x60) { 204 /* PCI DMA CCB */ 205 esp_pci_dma_write(pci, (addr - 0x40) >> 2, val); 206 } else if (addr == 0x70) { 207 /* DMA SCSI Bus and control */ 208 trace_esp_pci_sbac_write(pci->sbac, val); 209 pci->sbac = val; 210 } else { 211 trace_esp_pci_error_invalid_write((int)addr); 212 } 213 } 214 215 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr, 216 unsigned int size) 217 { 218 PCIESPState *pci = opaque; 219 uint32_t ret; 220 221 if (addr < 0x40) { 222 /* SCSI core reg */ 223 ret = esp_reg_read(&pci->esp, addr >> 2); 224 } else if (addr < 0x60) { 225 /* PCI DMA CCB */ 226 ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2); 227 } else if (addr == 0x70) { 228 /* DMA SCSI Bus and control */ 229 trace_esp_pci_sbac_read(pci->sbac); 230 ret = pci->sbac; 231 } else { 232 /* Invalid region */ 233 trace_esp_pci_error_invalid_read((int)addr); 234 ret = 0; 235 } 236 237 /* give only requested data */ 238 ret >>= (addr & 3) * 8; 239 ret &= ~(~(uint64_t)0 << (8 * size)); 240 241 return ret; 242 } 243 244 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len, 245 DMADirection dir) 246 { 247 dma_addr_t addr; 248 DMADirection expected_dir; 249 250 if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) { 251 expected_dir = DMA_DIRECTION_FROM_DEVICE; 252 } else { 253 expected_dir = DMA_DIRECTION_TO_DEVICE; 254 } 255 256 if (dir != expected_dir) { 257 trace_esp_pci_error_invalid_dma_direction(); 258 return; 259 } 260 261 if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) { 262 qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n"); 263 } 264 265 addr = pci->dma_regs[DMA_SPA]; 266 if (pci->dma_regs[DMA_WBC] < len) { 267 len = pci->dma_regs[DMA_WBC]; 268 } 269 270 pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir); 271 272 /* update status registers */ 273 pci->dma_regs[DMA_WBC] -= len; 274 pci->dma_regs[DMA_WAC] += len; 275 if (pci->dma_regs[DMA_WBC] == 0) { 276 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE; 277 } 278 } 279 280 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len) 281 { 282 PCIESPState *pci = opaque; 283 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE); 284 } 285 286 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len) 287 { 288 PCIESPState *pci = opaque; 289 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE); 290 } 291 292 static const MemoryRegionOps esp_pci_io_ops = { 293 .read = esp_pci_io_read, 294 .write = esp_pci_io_write, 295 .endianness = DEVICE_LITTLE_ENDIAN, 296 .impl = { 297 .min_access_size = 1, 298 .max_access_size = 4, 299 }, 300 }; 301 302 static void esp_pci_hard_reset(DeviceState *dev) 303 { 304 PCIESPState *pci = PCI_ESP(dev); 305 esp_hard_reset(&pci->esp); 306 pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P 307 | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK); 308 pci->dma_regs[DMA_WBC] &= ~0xffff; 309 pci->dma_regs[DMA_WAC] = 0xffffffff; 310 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT 311 | DMA_STAT_DONE | DMA_STAT_ABORT 312 | DMA_STAT_ERROR); 313 pci->dma_regs[DMA_WMAC] = 0xfffffffd; 314 } 315 316 static const VMStateDescription vmstate_esp_pci_scsi = { 317 .name = "pciespscsi", 318 .version_id = 1, 319 .minimum_version_id = 1, 320 .fields = (VMStateField[]) { 321 VMSTATE_PCI_DEVICE(parent_obj, PCIESPState), 322 VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)), 323 VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState), 324 VMSTATE_END_OF_LIST() 325 } 326 }; 327 328 static void esp_pci_command_complete(SCSIRequest *req, uint32_t status, 329 size_t resid) 330 { 331 ESPState *s = req->hba_private; 332 PCIESPState *pci = container_of(s, PCIESPState, esp); 333 334 esp_command_complete(req, status, resid); 335 pci->dma_regs[DMA_WBC] = 0; 336 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE; 337 } 338 339 static const struct SCSIBusInfo esp_pci_scsi_info = { 340 .tcq = false, 341 .max_target = ESP_MAX_DEVS, 342 .max_lun = 7, 343 344 .transfer_data = esp_transfer_data, 345 .complete = esp_pci_command_complete, 346 .cancel = esp_request_cancelled, 347 }; 348 349 static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp) 350 { 351 PCIESPState *pci = PCI_ESP(dev); 352 DeviceState *d = DEVICE(dev); 353 ESPState *s = &pci->esp; 354 uint8_t *pci_conf; 355 356 pci_conf = dev->config; 357 358 /* Interrupt pin A */ 359 pci_conf[PCI_INTERRUPT_PIN] = 0x01; 360 361 s->dma_memory_read = esp_pci_dma_memory_read; 362 s->dma_memory_write = esp_pci_dma_memory_write; 363 s->dma_opaque = pci; 364 s->chip_id = TCHI_AM53C974; 365 memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci, 366 "esp-io", 0x80); 367 368 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io); 369 s->irq = pci_allocate_irq(dev); 370 371 scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL); 372 } 373 374 static void esp_pci_scsi_uninit(PCIDevice *d) 375 { 376 PCIESPState *pci = PCI_ESP(d); 377 378 qemu_free_irq(pci->esp.irq); 379 } 380 381 static void esp_pci_class_init(ObjectClass *klass, void *data) 382 { 383 DeviceClass *dc = DEVICE_CLASS(klass); 384 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 385 386 k->realize = esp_pci_scsi_realize; 387 k->exit = esp_pci_scsi_uninit; 388 k->vendor_id = PCI_VENDOR_ID_AMD; 389 k->device_id = PCI_DEVICE_ID_AMD_SCSI; 390 k->revision = 0x10; 391 k->class_id = PCI_CLASS_STORAGE_SCSI; 392 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 393 dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter"; 394 dc->reset = esp_pci_hard_reset; 395 dc->vmsd = &vmstate_esp_pci_scsi; 396 } 397 398 static const TypeInfo esp_pci_info = { 399 .name = TYPE_AM53C974_DEVICE, 400 .parent = TYPE_PCI_DEVICE, 401 .instance_size = sizeof(PCIESPState), 402 .class_init = esp_pci_class_init, 403 .interfaces = (InterfaceInfo[]) { 404 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 405 { }, 406 }, 407 }; 408 409 typedef struct { 410 PCIESPState pci; 411 eeprom_t *eeprom; 412 } DC390State; 413 414 #define TYPE_DC390_DEVICE "dc390" 415 #define DC390(obj) \ 416 OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE) 417 418 #define EE_ADAPT_SCSI_ID 64 419 #define EE_MODE2 65 420 #define EE_DELAY 66 421 #define EE_TAG_CMD_NUM 67 422 #define EE_ADAPT_OPTIONS 68 423 #define EE_BOOT_SCSI_ID 69 424 #define EE_BOOT_SCSI_LUN 70 425 #define EE_CHKSUM1 126 426 #define EE_CHKSUM2 127 427 428 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT 0x01 429 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02 430 #define EE_ADAPT_OPTION_INT13 0x04 431 #define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08 432 433 434 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l) 435 { 436 DC390State *pci = DC390(dev); 437 uint32_t val; 438 439 val = pci_default_read_config(dev, addr, l); 440 441 if (addr == 0x00 && l == 1) { 442 /* First byte of address space is AND-ed with EEPROM DO line */ 443 if (!eeprom93xx_read(pci->eeprom)) { 444 val &= ~0xff; 445 } 446 } 447 448 return val; 449 } 450 451 static void dc390_write_config(PCIDevice *dev, 452 uint32_t addr, uint32_t val, int l) 453 { 454 DC390State *pci = DC390(dev); 455 if (addr == 0x80) { 456 /* EEPROM write */ 457 int eesk = val & 0x80 ? 1 : 0; 458 int eedi = val & 0x40 ? 1 : 0; 459 eeprom93xx_write(pci->eeprom, 1, eesk, eedi); 460 } else if (addr == 0xc0) { 461 /* EEPROM CS low */ 462 eeprom93xx_write(pci->eeprom, 0, 0, 0); 463 } else { 464 pci_default_write_config(dev, addr, val, l); 465 } 466 } 467 468 static void dc390_scsi_realize(PCIDevice *dev, Error **errp) 469 { 470 DC390State *pci = DC390(dev); 471 Error *err = NULL; 472 uint8_t *contents; 473 uint16_t chksum = 0; 474 int i; 475 476 /* init base class */ 477 esp_pci_scsi_realize(dev, &err); 478 if (err) { 479 error_propagate(errp, err); 480 return; 481 } 482 483 /* EEPROM */ 484 pci->eeprom = eeprom93xx_new(DEVICE(dev), 64); 485 486 /* set default eeprom values */ 487 contents = (uint8_t *)eeprom93xx_data(pci->eeprom); 488 489 for (i = 0; i < 16; i++) { 490 contents[i * 2] = 0x57; 491 contents[i * 2 + 1] = 0x00; 492 } 493 contents[EE_ADAPT_SCSI_ID] = 7; 494 contents[EE_MODE2] = 0x0f; 495 contents[EE_TAG_CMD_NUM] = 0x04; 496 contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT 497 | EE_ADAPT_OPTION_BOOT_FROM_CDROM 498 | EE_ADAPT_OPTION_INT13; 499 500 /* update eeprom checksum */ 501 for (i = 0; i < EE_CHKSUM1; i += 2) { 502 chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8); 503 } 504 chksum = 0x1234 - chksum; 505 contents[EE_CHKSUM1] = chksum & 0xff; 506 contents[EE_CHKSUM2] = chksum >> 8; 507 } 508 509 static void dc390_class_init(ObjectClass *klass, void *data) 510 { 511 DeviceClass *dc = DEVICE_CLASS(klass); 512 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 513 514 k->realize = dc390_scsi_realize; 515 k->config_read = dc390_read_config; 516 k->config_write = dc390_write_config; 517 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 518 dc->desc = "Tekram DC-390 SCSI adapter"; 519 } 520 521 static const TypeInfo dc390_info = { 522 .name = "dc390", 523 .parent = TYPE_AM53C974_DEVICE, 524 .instance_size = sizeof(DC390State), 525 .class_init = dc390_class_init, 526 }; 527 528 static void esp_pci_register_types(void) 529 { 530 type_register_static(&esp_pci_info); 531 type_register_static(&dc390_info); 532 } 533 534 type_init(esp_pci_register_types) 535