1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/pci/pci.h" 28 #include "hw/irq.h" 29 #include "hw/nvram/eeprom93xx.h" 30 #include "hw/scsi/esp.h" 31 #include "migration/vmstate.h" 32 #include "trace.h" 33 #include "qapi/error.h" 34 #include "qemu/log.h" 35 #include "qemu/module.h" 36 #include "qom/object.h" 37 38 #define TYPE_AM53C974_DEVICE "am53c974" 39 40 typedef struct PCIESPState PCIESPState; 41 DECLARE_INSTANCE_CHECKER(PCIESPState, PCI_ESP, 42 TYPE_AM53C974_DEVICE) 43 44 #define DMA_CMD 0x0 45 #define DMA_STC 0x1 46 #define DMA_SPA 0x2 47 #define DMA_WBC 0x3 48 #define DMA_WAC 0x4 49 #define DMA_STAT 0x5 50 #define DMA_SMDLA 0x6 51 #define DMA_WMAC 0x7 52 53 #define DMA_CMD_MASK 0x03 54 #define DMA_CMD_DIAG 0x04 55 #define DMA_CMD_MDL 0x10 56 #define DMA_CMD_INTE_P 0x20 57 #define DMA_CMD_INTE_D 0x40 58 #define DMA_CMD_DIR 0x80 59 60 #define DMA_STAT_PWDN 0x01 61 #define DMA_STAT_ERROR 0x02 62 #define DMA_STAT_ABORT 0x04 63 #define DMA_STAT_DONE 0x08 64 #define DMA_STAT_SCSIINT 0x10 65 #define DMA_STAT_BCMBLT 0x20 66 67 #define SBAC_STATUS (1 << 24) 68 69 struct PCIESPState { 70 /*< private >*/ 71 PCIDevice parent_obj; 72 /*< public >*/ 73 74 MemoryRegion io; 75 uint32_t dma_regs[8]; 76 uint32_t sbac; 77 ESPState esp; 78 }; 79 80 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val) 81 { 82 trace_esp_pci_dma_idle(val); 83 esp_dma_enable(&pci->esp, 0, 0); 84 } 85 86 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val) 87 { 88 trace_esp_pci_dma_blast(val); 89 qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n"); 90 } 91 92 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val) 93 { 94 trace_esp_pci_dma_abort(val); 95 if (pci->esp.current_req) { 96 scsi_req_cancel(pci->esp.current_req); 97 } 98 } 99 100 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val) 101 { 102 trace_esp_pci_dma_start(val); 103 104 pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC]; 105 pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA]; 106 pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA]; 107 108 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT 109 | DMA_STAT_DONE | DMA_STAT_ABORT 110 | DMA_STAT_ERROR | DMA_STAT_PWDN); 111 112 esp_dma_enable(&pci->esp, 0, 1); 113 } 114 115 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val) 116 { 117 trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val); 118 switch (saddr) { 119 case DMA_CMD: 120 pci->dma_regs[saddr] = val; 121 switch (val & DMA_CMD_MASK) { 122 case 0x0: /* IDLE */ 123 esp_pci_handle_idle(pci, val); 124 break; 125 case 0x1: /* BLAST */ 126 esp_pci_handle_blast(pci, val); 127 break; 128 case 0x2: /* ABORT */ 129 esp_pci_handle_abort(pci, val); 130 break; 131 case 0x3: /* START */ 132 esp_pci_handle_start(pci, val); 133 break; 134 default: /* can't happen */ 135 abort(); 136 } 137 break; 138 case DMA_STC: 139 case DMA_SPA: 140 case DMA_SMDLA: 141 pci->dma_regs[saddr] = val; 142 break; 143 case DMA_STAT: 144 if (pci->sbac & SBAC_STATUS) { 145 /* clear some bits on write */ 146 uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE; 147 pci->dma_regs[DMA_STAT] &= ~(val & mask); 148 } 149 break; 150 default: 151 trace_esp_pci_error_invalid_write_dma(val, saddr); 152 return; 153 } 154 } 155 156 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr) 157 { 158 uint32_t val; 159 160 val = pci->dma_regs[saddr]; 161 if (saddr == DMA_STAT) { 162 if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) { 163 val |= DMA_STAT_SCSIINT; 164 } 165 if (!(pci->sbac & SBAC_STATUS)) { 166 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT | 167 DMA_STAT_DONE); 168 } 169 } 170 171 trace_esp_pci_dma_read(saddr, val); 172 return val; 173 } 174 175 static void esp_pci_io_write(void *opaque, hwaddr addr, 176 uint64_t val, unsigned int size) 177 { 178 PCIESPState *pci = opaque; 179 180 if (size < 4 || addr & 3) { 181 /* need to upgrade request: we only support 4-bytes accesses */ 182 uint32_t current = 0, mask; 183 int shift; 184 185 if (addr < 0x40) { 186 current = pci->esp.wregs[addr >> 2]; 187 } else if (addr < 0x60) { 188 current = pci->dma_regs[(addr - 0x40) >> 2]; 189 } else if (addr < 0x74) { 190 current = pci->sbac; 191 } 192 193 shift = (4 - size) * 8; 194 mask = (~(uint32_t)0 << shift) >> shift; 195 196 shift = ((4 - (addr & 3)) & 3) * 8; 197 val <<= shift; 198 val |= current & ~(mask << shift); 199 addr &= ~3; 200 size = 4; 201 } 202 g_assert(size >= 4); 203 204 if (addr < 0x40) { 205 /* SCSI core reg */ 206 esp_reg_write(&pci->esp, addr >> 2, val); 207 } else if (addr < 0x60) { 208 /* PCI DMA CCB */ 209 esp_pci_dma_write(pci, (addr - 0x40) >> 2, val); 210 } else if (addr == 0x70) { 211 /* DMA SCSI Bus and control */ 212 trace_esp_pci_sbac_write(pci->sbac, val); 213 pci->sbac = val; 214 } else { 215 trace_esp_pci_error_invalid_write((int)addr); 216 } 217 } 218 219 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr, 220 unsigned int size) 221 { 222 PCIESPState *pci = opaque; 223 uint32_t ret; 224 225 if (addr < 0x40) { 226 /* SCSI core reg */ 227 ret = esp_reg_read(&pci->esp, addr >> 2); 228 } else if (addr < 0x60) { 229 /* PCI DMA CCB */ 230 ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2); 231 } else if (addr == 0x70) { 232 /* DMA SCSI Bus and control */ 233 trace_esp_pci_sbac_read(pci->sbac); 234 ret = pci->sbac; 235 } else { 236 /* Invalid region */ 237 trace_esp_pci_error_invalid_read((int)addr); 238 ret = 0; 239 } 240 241 /* give only requested data */ 242 ret >>= (addr & 3) * 8; 243 ret &= ~(~(uint64_t)0 << (8 * size)); 244 245 return ret; 246 } 247 248 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len, 249 DMADirection dir) 250 { 251 dma_addr_t addr; 252 DMADirection expected_dir; 253 254 if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) { 255 expected_dir = DMA_DIRECTION_FROM_DEVICE; 256 } else { 257 expected_dir = DMA_DIRECTION_TO_DEVICE; 258 } 259 260 if (dir != expected_dir) { 261 trace_esp_pci_error_invalid_dma_direction(); 262 return; 263 } 264 265 if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) { 266 qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n"); 267 } 268 269 addr = pci->dma_regs[DMA_SPA]; 270 if (pci->dma_regs[DMA_WBC] < len) { 271 len = pci->dma_regs[DMA_WBC]; 272 } 273 274 pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir); 275 276 /* update status registers */ 277 pci->dma_regs[DMA_WBC] -= len; 278 pci->dma_regs[DMA_WAC] += len; 279 if (pci->dma_regs[DMA_WBC] == 0) { 280 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE; 281 } 282 } 283 284 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len) 285 { 286 PCIESPState *pci = opaque; 287 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE); 288 } 289 290 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len) 291 { 292 PCIESPState *pci = opaque; 293 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE); 294 } 295 296 static const MemoryRegionOps esp_pci_io_ops = { 297 .read = esp_pci_io_read, 298 .write = esp_pci_io_write, 299 .endianness = DEVICE_LITTLE_ENDIAN, 300 .impl = { 301 .min_access_size = 1, 302 .max_access_size = 4, 303 }, 304 }; 305 306 static void esp_pci_hard_reset(DeviceState *dev) 307 { 308 PCIESPState *pci = PCI_ESP(dev); 309 esp_hard_reset(&pci->esp); 310 pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P 311 | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK); 312 pci->dma_regs[DMA_WBC] &= ~0xffff; 313 pci->dma_regs[DMA_WAC] = 0xffffffff; 314 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT 315 | DMA_STAT_DONE | DMA_STAT_ABORT 316 | DMA_STAT_ERROR); 317 pci->dma_regs[DMA_WMAC] = 0xfffffffd; 318 } 319 320 static const VMStateDescription vmstate_esp_pci_scsi = { 321 .name = "pciespscsi", 322 .version_id = 1, 323 .minimum_version_id = 1, 324 .fields = (VMStateField[]) { 325 VMSTATE_PCI_DEVICE(parent_obj, PCIESPState), 326 VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)), 327 VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState), 328 VMSTATE_END_OF_LIST() 329 } 330 }; 331 332 static void esp_pci_command_complete(SCSIRequest *req, uint32_t status, 333 size_t resid) 334 { 335 ESPState *s = req->hba_private; 336 PCIESPState *pci = container_of(s, PCIESPState, esp); 337 338 esp_command_complete(req, status, resid); 339 pci->dma_regs[DMA_WBC] = 0; 340 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE; 341 } 342 343 static const struct SCSIBusInfo esp_pci_scsi_info = { 344 .tcq = false, 345 .max_target = ESP_MAX_DEVS, 346 .max_lun = 7, 347 348 .transfer_data = esp_transfer_data, 349 .complete = esp_pci_command_complete, 350 .cancel = esp_request_cancelled, 351 }; 352 353 static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp) 354 { 355 PCIESPState *pci = PCI_ESP(dev); 356 DeviceState *d = DEVICE(dev); 357 ESPState *s = &pci->esp; 358 uint8_t *pci_conf; 359 360 pci_conf = dev->config; 361 362 /* Interrupt pin A */ 363 pci_conf[PCI_INTERRUPT_PIN] = 0x01; 364 365 s->dma_memory_read = esp_pci_dma_memory_read; 366 s->dma_memory_write = esp_pci_dma_memory_write; 367 s->dma_opaque = pci; 368 s->chip_id = TCHI_AM53C974; 369 memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci, 370 "esp-io", 0x80); 371 372 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io); 373 s->irq = pci_allocate_irq(dev); 374 375 scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL); 376 } 377 378 static void esp_pci_scsi_uninit(PCIDevice *d) 379 { 380 PCIESPState *pci = PCI_ESP(d); 381 382 qemu_free_irq(pci->esp.irq); 383 } 384 385 static void esp_pci_class_init(ObjectClass *klass, void *data) 386 { 387 DeviceClass *dc = DEVICE_CLASS(klass); 388 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 389 390 k->realize = esp_pci_scsi_realize; 391 k->exit = esp_pci_scsi_uninit; 392 k->vendor_id = PCI_VENDOR_ID_AMD; 393 k->device_id = PCI_DEVICE_ID_AMD_SCSI; 394 k->revision = 0x10; 395 k->class_id = PCI_CLASS_STORAGE_SCSI; 396 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 397 dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter"; 398 dc->reset = esp_pci_hard_reset; 399 dc->vmsd = &vmstate_esp_pci_scsi; 400 } 401 402 static const TypeInfo esp_pci_info = { 403 .name = TYPE_AM53C974_DEVICE, 404 .parent = TYPE_PCI_DEVICE, 405 .instance_size = sizeof(PCIESPState), 406 .class_init = esp_pci_class_init, 407 .interfaces = (InterfaceInfo[]) { 408 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 409 { }, 410 }, 411 }; 412 413 struct DC390State { 414 PCIESPState pci; 415 eeprom_t *eeprom; 416 }; 417 typedef struct DC390State DC390State; 418 419 #define TYPE_DC390_DEVICE "dc390" 420 DECLARE_INSTANCE_CHECKER(DC390State, DC390, 421 TYPE_DC390_DEVICE) 422 423 #define EE_ADAPT_SCSI_ID 64 424 #define EE_MODE2 65 425 #define EE_DELAY 66 426 #define EE_TAG_CMD_NUM 67 427 #define EE_ADAPT_OPTIONS 68 428 #define EE_BOOT_SCSI_ID 69 429 #define EE_BOOT_SCSI_LUN 70 430 #define EE_CHKSUM1 126 431 #define EE_CHKSUM2 127 432 433 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT 0x01 434 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02 435 #define EE_ADAPT_OPTION_INT13 0x04 436 #define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08 437 438 439 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l) 440 { 441 DC390State *pci = DC390(dev); 442 uint32_t val; 443 444 val = pci_default_read_config(dev, addr, l); 445 446 if (addr == 0x00 && l == 1) { 447 /* First byte of address space is AND-ed with EEPROM DO line */ 448 if (!eeprom93xx_read(pci->eeprom)) { 449 val &= ~0xff; 450 } 451 } 452 453 return val; 454 } 455 456 static void dc390_write_config(PCIDevice *dev, 457 uint32_t addr, uint32_t val, int l) 458 { 459 DC390State *pci = DC390(dev); 460 if (addr == 0x80) { 461 /* EEPROM write */ 462 int eesk = val & 0x80 ? 1 : 0; 463 int eedi = val & 0x40 ? 1 : 0; 464 eeprom93xx_write(pci->eeprom, 1, eesk, eedi); 465 } else if (addr == 0xc0) { 466 /* EEPROM CS low */ 467 eeprom93xx_write(pci->eeprom, 0, 0, 0); 468 } else { 469 pci_default_write_config(dev, addr, val, l); 470 } 471 } 472 473 static void dc390_scsi_realize(PCIDevice *dev, Error **errp) 474 { 475 DC390State *pci = DC390(dev); 476 Error *err = NULL; 477 uint8_t *contents; 478 uint16_t chksum = 0; 479 int i; 480 481 /* init base class */ 482 esp_pci_scsi_realize(dev, &err); 483 if (err) { 484 error_propagate(errp, err); 485 return; 486 } 487 488 /* EEPROM */ 489 pci->eeprom = eeprom93xx_new(DEVICE(dev), 64); 490 491 /* set default eeprom values */ 492 contents = (uint8_t *)eeprom93xx_data(pci->eeprom); 493 494 for (i = 0; i < 16; i++) { 495 contents[i * 2] = 0x57; 496 contents[i * 2 + 1] = 0x00; 497 } 498 contents[EE_ADAPT_SCSI_ID] = 7; 499 contents[EE_MODE2] = 0x0f; 500 contents[EE_TAG_CMD_NUM] = 0x04; 501 contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT 502 | EE_ADAPT_OPTION_BOOT_FROM_CDROM 503 | EE_ADAPT_OPTION_INT13; 504 505 /* update eeprom checksum */ 506 for (i = 0; i < EE_CHKSUM1; i += 2) { 507 chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8); 508 } 509 chksum = 0x1234 - chksum; 510 contents[EE_CHKSUM1] = chksum & 0xff; 511 contents[EE_CHKSUM2] = chksum >> 8; 512 } 513 514 static void dc390_class_init(ObjectClass *klass, void *data) 515 { 516 DeviceClass *dc = DEVICE_CLASS(klass); 517 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 518 519 k->realize = dc390_scsi_realize; 520 k->config_read = dc390_read_config; 521 k->config_write = dc390_write_config; 522 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 523 dc->desc = "Tekram DC-390 SCSI adapter"; 524 } 525 526 static const TypeInfo dc390_info = { 527 .name = TYPE_DC390_DEVICE, 528 .parent = TYPE_AM53C974_DEVICE, 529 .instance_size = sizeof(DC390State), 530 .class_init = dc390_class_init, 531 }; 532 533 static void esp_pci_register_types(void) 534 { 535 type_register_static(&esp_pci_info); 536 type_register_static(&dc390_info); 537 } 538 539 type_init(esp_pci_register_types) 540