1 /* 2 * s390 PCI instructions 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "cpu.h" 16 #include "exec/memop.h" 17 #include "exec/memory-internal.h" 18 #include "qemu/error-report.h" 19 #include "sysemu/hw_accel.h" 20 #include "hw/s390x/s390-pci-inst.h" 21 #include "hw/s390x/s390-pci-bus.h" 22 #include "hw/s390x/tod.h" 23 24 #ifndef DEBUG_S390PCI_INST 25 #define DEBUG_S390PCI_INST 0 26 #endif 27 28 #define DPRINTF(fmt, ...) \ 29 do { \ 30 if (DEBUG_S390PCI_INST) { \ 31 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \ 32 } \ 33 } while (0) 34 35 static inline void inc_dma_avail(S390PCIIOMMU *iommu) 36 { 37 if (iommu->dma_limit) { 38 iommu->dma_limit->avail++; 39 } 40 } 41 42 static inline void dec_dma_avail(S390PCIIOMMU *iommu) 43 { 44 if (iommu->dma_limit) { 45 iommu->dma_limit->avail--; 46 } 47 } 48 49 static void s390_set_status_code(CPUS390XState *env, 50 uint8_t r, uint64_t status_code) 51 { 52 env->regs[r] &= ~0xff000000ULL; 53 env->regs[r] |= (status_code & 0xff) << 24; 54 } 55 56 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) 57 { 58 S390PCIBusDevice *pbdev = NULL; 59 S390pciState *s = s390_get_phb(); 60 uint32_t res_code, initial_l2, g_l2; 61 int rc, i; 62 uint64_t resume_token; 63 64 rc = 0; 65 if (lduw_p(&rrb->request.hdr.len) != 32) { 66 res_code = CLP_RC_LEN; 67 rc = -EINVAL; 68 goto out; 69 } 70 71 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) { 72 res_code = CLP_RC_FMT; 73 rc = -EINVAL; 74 goto out; 75 } 76 77 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 || 78 ldq_p(&rrb->request.reserved1) != 0) { 79 res_code = CLP_RC_RESNOT0; 80 rc = -EINVAL; 81 goto out; 82 } 83 84 resume_token = ldq_p(&rrb->request.resume_token); 85 86 if (resume_token) { 87 pbdev = s390_pci_find_dev_by_idx(s, resume_token); 88 if (!pbdev) { 89 res_code = CLP_RC_LISTPCI_BADRT; 90 rc = -EINVAL; 91 goto out; 92 } 93 } else { 94 pbdev = s390_pci_find_next_avail_dev(s, NULL); 95 } 96 97 if (lduw_p(&rrb->response.hdr.len) < 48) { 98 res_code = CLP_RC_8K; 99 rc = -EINVAL; 100 goto out; 101 } 102 103 initial_l2 = lduw_p(&rrb->response.hdr.len); 104 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry) 105 != 0) { 106 res_code = CLP_RC_LEN; 107 rc = -EINVAL; 108 *cc = 3; 109 goto out; 110 } 111 112 stl_p(&rrb->response.fmt, 0); 113 stq_p(&rrb->response.reserved1, 0); 114 stl_p(&rrb->response.mdd, FH_MASK_SHM); 115 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS); 116 rrb->response.flags = UID_CHECKING_ENABLED; 117 rrb->response.entry_size = sizeof(ClpFhListEntry); 118 119 i = 0; 120 g_l2 = LIST_PCI_HDR_LEN; 121 while (g_l2 < initial_l2 && pbdev) { 122 stw_p(&rrb->response.fh_list[i].device_id, 123 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID)); 124 stw_p(&rrb->response.fh_list[i].vendor_id, 125 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID)); 126 /* Ignore RESERVED devices. */ 127 stl_p(&rrb->response.fh_list[i].config, 128 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31); 129 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid); 130 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh); 131 132 g_l2 += sizeof(ClpFhListEntry); 133 /* Add endian check for DPRINTF? */ 134 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n", 135 g_l2, 136 lduw_p(&rrb->response.fh_list[i].vendor_id), 137 lduw_p(&rrb->response.fh_list[i].device_id), 138 ldl_p(&rrb->response.fh_list[i].fid), 139 ldl_p(&rrb->response.fh_list[i].fh)); 140 pbdev = s390_pci_find_next_avail_dev(s, pbdev); 141 i++; 142 } 143 144 if (!pbdev) { 145 resume_token = 0; 146 } else { 147 resume_token = pbdev->fh & FH_MASK_INDEX; 148 } 149 stq_p(&rrb->response.resume_token, resume_token); 150 stw_p(&rrb->response.hdr.len, g_l2); 151 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK); 152 out: 153 if (rc) { 154 DPRINTF("list pci failed rc 0x%x\n", rc); 155 stw_p(&rrb->response.hdr.rsp, res_code); 156 } 157 return rc; 158 } 159 160 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) 161 { 162 ClpReqHdr *reqh; 163 ClpRspHdr *resh; 164 S390PCIBusDevice *pbdev; 165 uint32_t req_len; 166 uint32_t res_len; 167 uint8_t buffer[4096 * 2]; 168 uint8_t cc = 0; 169 CPUS390XState *env = &cpu->env; 170 S390pciState *s = s390_get_phb(); 171 int i; 172 173 if (env->psw.mask & PSW_MASK_PSTATE) { 174 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 175 return 0; 176 } 177 178 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) { 179 s390_cpu_virt_mem_handle_exc(cpu, ra); 180 return 0; 181 } 182 reqh = (ClpReqHdr *)buffer; 183 req_len = lduw_p(&reqh->len); 184 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) { 185 s390_program_interrupt(env, PGM_OPERAND, ra); 186 return 0; 187 } 188 189 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 190 req_len + sizeof(*resh))) { 191 s390_cpu_virt_mem_handle_exc(cpu, ra); 192 return 0; 193 } 194 resh = (ClpRspHdr *)(buffer + req_len); 195 res_len = lduw_p(&resh->len); 196 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) { 197 s390_program_interrupt(env, PGM_OPERAND, ra); 198 return 0; 199 } 200 if ((req_len + res_len) > 8192) { 201 s390_program_interrupt(env, PGM_OPERAND, ra); 202 return 0; 203 } 204 205 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 206 req_len + res_len)) { 207 s390_cpu_virt_mem_handle_exc(cpu, ra); 208 return 0; 209 } 210 211 if (req_len != 32) { 212 stw_p(&resh->rsp, CLP_RC_LEN); 213 goto out; 214 } 215 216 switch (lduw_p(&reqh->cmd)) { 217 case CLP_LIST_PCI: { 218 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer; 219 list_pci(rrb, &cc); 220 break; 221 } 222 case CLP_SET_PCI_FN: { 223 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh; 224 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh; 225 226 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh)); 227 if (!pbdev) { 228 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); 229 goto out; 230 } 231 232 switch (reqsetpci->oc) { 233 case CLP_SET_ENABLE_PCI_FN: 234 switch (reqsetpci->ndas) { 235 case 0: 236 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS); 237 goto out; 238 case 1: 239 break; 240 default: 241 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES); 242 goto out; 243 } 244 245 if (pbdev->fh & FH_MASK_ENABLE) { 246 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 247 goto out; 248 } 249 250 pbdev->fh |= FH_MASK_ENABLE; 251 pbdev->state = ZPCI_FS_ENABLED; 252 stl_p(&ressetpci->fh, pbdev->fh); 253 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 254 break; 255 case CLP_SET_DISABLE_PCI_FN: 256 if (!(pbdev->fh & FH_MASK_ENABLE)) { 257 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 258 goto out; 259 } 260 device_legacy_reset(DEVICE(pbdev)); 261 pbdev->fh &= ~FH_MASK_ENABLE; 262 pbdev->state = ZPCI_FS_DISABLED; 263 stl_p(&ressetpci->fh, pbdev->fh); 264 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 265 break; 266 default: 267 DPRINTF("unknown set pci command\n"); 268 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 269 break; 270 } 271 break; 272 } 273 case CLP_QUERY_PCI_FN: { 274 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh; 275 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh; 276 277 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh)); 278 if (!pbdev) { 279 DPRINTF("query pci no pci dev\n"); 280 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH); 281 goto out; 282 } 283 284 stq_p(&resquery->sdma, pbdev->zpci_fn.sdma); 285 stq_p(&resquery->edma, pbdev->zpci_fn.edma); 286 stw_p(&resquery->pchid, pbdev->zpci_fn.pchid); 287 resquery->flags = pbdev->zpci_fn.flags; 288 resquery->pfgid = pbdev->zpci_fn.pfgid; 289 stl_p(&resquery->fid, pbdev->zpci_fn.fid); 290 stl_p(&resquery->uid, pbdev->zpci_fn.uid); 291 292 for (i = 0; i < PCI_BAR_COUNT; i++) { 293 uint32_t data = pci_get_long(pbdev->pdev->config + 294 PCI_BASE_ADDRESS_0 + (i * 4)); 295 296 stl_p(&resquery->bar[i], data); 297 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ? 298 ctz64(pbdev->pdev->io_regions[i].size) : 0; 299 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i, 300 ldl_p(&resquery->bar[i]), 301 pbdev->pdev->io_regions[i].size, 302 resquery->bar_size[i]); 303 } 304 305 stw_p(&resquery->hdr.rsp, CLP_RC_OK); 306 break; 307 } 308 case CLP_QUERY_PCI_FNGRP: { 309 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh; 310 311 ClpReqQueryPciGrp *reqgrp = (ClpReqQueryPciGrp *)reqh; 312 S390PCIGroup *group; 313 314 group = s390_group_find(reqgrp->g); 315 if (!group) { 316 /* We do not allow access to unknown groups */ 317 /* The group must have been obtained with a vfio device */ 318 stw_p(&resgrp->hdr.rsp, CLP_RC_QUERYPCIFG_PFGID); 319 goto out; 320 } 321 resgrp->fr = group->zpci_group.fr; 322 stq_p(&resgrp->dasm, group->zpci_group.dasm); 323 stq_p(&resgrp->msia, group->zpci_group.msia); 324 stw_p(&resgrp->mui, group->zpci_group.mui); 325 stw_p(&resgrp->i, group->zpci_group.i); 326 stw_p(&resgrp->maxstbl, group->zpci_group.maxstbl); 327 resgrp->version = group->zpci_group.version; 328 stw_p(&resgrp->hdr.rsp, CLP_RC_OK); 329 break; 330 } 331 default: 332 DPRINTF("unknown clp command\n"); 333 stw_p(&resh->rsp, CLP_RC_CMD); 334 break; 335 } 336 337 out: 338 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer, 339 req_len + res_len)) { 340 s390_cpu_virt_mem_handle_exc(cpu, ra); 341 return 0; 342 } 343 setcc(cpu, cc); 344 return 0; 345 } 346 347 /** 348 * Swap data contained in s390x big endian registers to little endian 349 * PCI bars. 350 * 351 * @ptr: a pointer to a uint64_t data field 352 * @len: the length of the valid data, must be 1,2,4 or 8 353 */ 354 static int zpci_endian_swap(uint64_t *ptr, uint8_t len) 355 { 356 uint64_t data = *ptr; 357 358 switch (len) { 359 case 1: 360 break; 361 case 2: 362 data = bswap16(data); 363 break; 364 case 4: 365 data = bswap32(data); 366 break; 367 case 8: 368 data = bswap64(data); 369 break; 370 default: 371 return -EINVAL; 372 } 373 *ptr = data; 374 return 0; 375 } 376 377 static MemoryRegion *s390_get_subregion(MemoryRegion *mr, uint64_t offset, 378 uint8_t len) 379 { 380 MemoryRegion *subregion; 381 uint64_t subregion_size; 382 383 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) { 384 subregion_size = int128_get64(subregion->size); 385 if ((offset >= subregion->addr) && 386 (offset + len) <= (subregion->addr + subregion_size)) { 387 mr = subregion; 388 break; 389 } 390 } 391 return mr; 392 } 393 394 static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias, 395 uint64_t offset, uint64_t *data, uint8_t len) 396 { 397 MemoryRegion *mr; 398 399 mr = pbdev->pdev->io_regions[pcias].memory; 400 mr = s390_get_subregion(mr, offset, len); 401 offset -= mr->addr; 402 return memory_region_dispatch_read(mr, offset, data, 403 size_memop(len) | MO_BE, 404 MEMTXATTRS_UNSPECIFIED); 405 } 406 407 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 408 { 409 CPUS390XState *env = &cpu->env; 410 S390PCIBusDevice *pbdev; 411 uint64_t offset; 412 uint64_t data; 413 MemTxResult result; 414 uint8_t len; 415 uint32_t fh; 416 uint8_t pcias; 417 418 if (env->psw.mask & PSW_MASK_PSTATE) { 419 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 420 return 0; 421 } 422 423 if (r2 & 0x1) { 424 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 425 return 0; 426 } 427 428 fh = env->regs[r2] >> 32; 429 pcias = (env->regs[r2] >> 16) & 0xf; 430 len = env->regs[r2] & 0xf; 431 offset = env->regs[r2 + 1]; 432 433 if (!(fh & FH_MASK_ENABLE)) { 434 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 435 return 0; 436 } 437 438 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 439 if (!pbdev) { 440 DPRINTF("pcilg no pci dev\n"); 441 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 442 return 0; 443 } 444 445 switch (pbdev->state) { 446 case ZPCI_FS_PERMANENT_ERROR: 447 case ZPCI_FS_ERROR: 448 setcc(cpu, ZPCI_PCI_LS_ERR); 449 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 450 return 0; 451 default: 452 break; 453 } 454 455 switch (pcias) { 456 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 457 if (!len || (len > (8 - (offset & 0x7)))) { 458 s390_program_interrupt(env, PGM_OPERAND, ra); 459 return 0; 460 } 461 result = zpci_read_bar(pbdev, pcias, offset, &data, len); 462 if (result != MEMTX_OK) { 463 s390_program_interrupt(env, PGM_OPERAND, ra); 464 return 0; 465 } 466 break; 467 case ZPCI_CONFIG_BAR: 468 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 469 s390_program_interrupt(env, PGM_OPERAND, ra); 470 return 0; 471 } 472 data = pci_host_config_read_common( 473 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len); 474 475 if (zpci_endian_swap(&data, len)) { 476 s390_program_interrupt(env, PGM_OPERAND, ra); 477 return 0; 478 } 479 break; 480 default: 481 DPRINTF("pcilg invalid space\n"); 482 setcc(cpu, ZPCI_PCI_LS_ERR); 483 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 484 return 0; 485 } 486 487 pbdev->fmb.counter[ZPCI_FMB_CNT_LD]++; 488 489 env->regs[r1] = data; 490 setcc(cpu, ZPCI_PCI_LS_OK); 491 return 0; 492 } 493 494 static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias, 495 uint64_t offset, uint64_t data, uint8_t len) 496 { 497 MemoryRegion *mr; 498 499 mr = pbdev->pdev->io_regions[pcias].memory; 500 mr = s390_get_subregion(mr, offset, len); 501 offset -= mr->addr; 502 return memory_region_dispatch_write(mr, offset, data, 503 size_memop(len) | MO_BE, 504 MEMTXATTRS_UNSPECIFIED); 505 } 506 507 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 508 { 509 CPUS390XState *env = &cpu->env; 510 uint64_t offset, data; 511 S390PCIBusDevice *pbdev; 512 MemTxResult result; 513 uint8_t len; 514 uint32_t fh; 515 uint8_t pcias; 516 517 if (env->psw.mask & PSW_MASK_PSTATE) { 518 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 519 return 0; 520 } 521 522 if (r2 & 0x1) { 523 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 524 return 0; 525 } 526 527 fh = env->regs[r2] >> 32; 528 pcias = (env->regs[r2] >> 16) & 0xf; 529 len = env->regs[r2] & 0xf; 530 offset = env->regs[r2 + 1]; 531 data = env->regs[r1]; 532 533 if (!(fh & FH_MASK_ENABLE)) { 534 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 535 return 0; 536 } 537 538 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 539 if (!pbdev) { 540 DPRINTF("pcistg no pci dev\n"); 541 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 542 return 0; 543 } 544 545 switch (pbdev->state) { 546 /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED 547 * are already covered by the FH_MASK_ENABLE check above 548 */ 549 case ZPCI_FS_PERMANENT_ERROR: 550 case ZPCI_FS_ERROR: 551 setcc(cpu, ZPCI_PCI_LS_ERR); 552 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 553 return 0; 554 default: 555 break; 556 } 557 558 switch (pcias) { 559 /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */ 560 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 561 /* Check length: 562 * A length of 0 is invalid and length should not cross a double word 563 */ 564 if (!len || (len > (8 - (offset & 0x7)))) { 565 s390_program_interrupt(env, PGM_OPERAND, ra); 566 return 0; 567 } 568 569 result = zpci_write_bar(pbdev, pcias, offset, data, len); 570 if (result != MEMTX_OK) { 571 s390_program_interrupt(env, PGM_OPERAND, ra); 572 return 0; 573 } 574 break; 575 case ZPCI_CONFIG_BAR: 576 /* ZPCI uses the pseudo BAR number 15 as configuration space */ 577 /* possible access lengths are 1,2,4 and must not cross a word */ 578 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 579 s390_program_interrupt(env, PGM_OPERAND, ra); 580 return 0; 581 } 582 /* len = 1,2,4 so we do not need to test */ 583 zpci_endian_swap(&data, len); 584 pci_host_config_write_common(pbdev->pdev, offset, 585 pci_config_size(pbdev->pdev), 586 data, len); 587 break; 588 default: 589 DPRINTF("pcistg invalid space\n"); 590 setcc(cpu, ZPCI_PCI_LS_ERR); 591 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 592 return 0; 593 } 594 595 pbdev->fmb.counter[ZPCI_FMB_CNT_ST]++; 596 597 setcc(cpu, ZPCI_PCI_LS_OK); 598 return 0; 599 } 600 601 static uint32_t s390_pci_update_iotlb(S390PCIIOMMU *iommu, 602 S390IOTLBEntry *entry) 603 { 604 S390IOTLBEntry *cache = g_hash_table_lookup(iommu->iotlb, &entry->iova); 605 IOMMUTLBEvent event = { 606 .type = entry->perm ? IOMMU_NOTIFIER_MAP : IOMMU_NOTIFIER_UNMAP, 607 .entry = { 608 .target_as = &address_space_memory, 609 .iova = entry->iova, 610 .translated_addr = entry->translated_addr, 611 .perm = entry->perm, 612 .addr_mask = ~PAGE_MASK, 613 }, 614 }; 615 616 if (event.type == IOMMU_NOTIFIER_UNMAP) { 617 if (!cache) { 618 goto out; 619 } 620 g_hash_table_remove(iommu->iotlb, &entry->iova); 621 inc_dma_avail(iommu); 622 } else { 623 if (cache) { 624 if (cache->perm == entry->perm && 625 cache->translated_addr == entry->translated_addr) { 626 goto out; 627 } 628 629 event.type = IOMMU_NOTIFIER_UNMAP; 630 event.entry.perm = IOMMU_NONE; 631 memory_region_notify_iommu(&iommu->iommu_mr, 0, event); 632 event.type = IOMMU_NOTIFIER_MAP; 633 event.entry.perm = entry->perm; 634 } 635 636 cache = g_new(S390IOTLBEntry, 1); 637 cache->iova = entry->iova; 638 cache->translated_addr = entry->translated_addr; 639 cache->len = PAGE_SIZE; 640 cache->perm = entry->perm; 641 g_hash_table_replace(iommu->iotlb, &cache->iova, cache); 642 dec_dma_avail(iommu); 643 } 644 645 memory_region_notify_iommu(&iommu->iommu_mr, 0, event); 646 647 out: 648 return iommu->dma_limit ? iommu->dma_limit->avail : 1; 649 } 650 651 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 652 { 653 CPUS390XState *env = &cpu->env; 654 uint32_t fh; 655 uint16_t error = 0; 656 S390PCIBusDevice *pbdev; 657 S390PCIIOMMU *iommu; 658 S390IOTLBEntry entry; 659 hwaddr start, end; 660 uint32_t dma_avail; 661 662 if (env->psw.mask & PSW_MASK_PSTATE) { 663 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 664 return 0; 665 } 666 667 if (r2 & 0x1) { 668 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 669 return 0; 670 } 671 672 fh = env->regs[r1] >> 32; 673 start = env->regs[r2]; 674 end = start + env->regs[r2 + 1]; 675 676 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 677 if (!pbdev) { 678 DPRINTF("rpcit no pci dev\n"); 679 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 680 return 0; 681 } 682 683 switch (pbdev->state) { 684 case ZPCI_FS_RESERVED: 685 case ZPCI_FS_STANDBY: 686 case ZPCI_FS_DISABLED: 687 case ZPCI_FS_PERMANENT_ERROR: 688 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 689 return 0; 690 case ZPCI_FS_ERROR: 691 setcc(cpu, ZPCI_PCI_LS_ERR); 692 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER); 693 return 0; 694 default: 695 break; 696 } 697 698 iommu = pbdev->iommu; 699 if (iommu->dma_limit) { 700 dma_avail = iommu->dma_limit->avail; 701 } else { 702 dma_avail = 1; 703 } 704 if (!iommu->g_iota) { 705 error = ERR_EVENT_INVALAS; 706 goto err; 707 } 708 709 if (end < iommu->pba || start > iommu->pal) { 710 error = ERR_EVENT_OORANGE; 711 goto err; 712 } 713 714 while (start < end) { 715 error = s390_guest_io_table_walk(iommu->g_iota, start, &entry); 716 if (error) { 717 break; 718 } 719 720 start += entry.len; 721 while (entry.iova < start && entry.iova < end && 722 (dma_avail > 0 || entry.perm == IOMMU_NONE)) { 723 dma_avail = s390_pci_update_iotlb(iommu, &entry); 724 entry.iova += PAGE_SIZE; 725 entry.translated_addr += PAGE_SIZE; 726 } 727 } 728 err: 729 if (error) { 730 pbdev->state = ZPCI_FS_ERROR; 731 setcc(cpu, ZPCI_PCI_LS_ERR); 732 s390_set_status_code(env, r1, ZPCI_PCI_ST_FUNC_IN_ERR); 733 s390_pci_generate_error_event(error, pbdev->fh, pbdev->fid, start, 0); 734 } else { 735 pbdev->fmb.counter[ZPCI_FMB_CNT_RPCIT]++; 736 if (dma_avail > 0) { 737 setcc(cpu, ZPCI_PCI_LS_OK); 738 } else { 739 /* vfio DMA mappings are exhausted, trigger a RPCIT */ 740 setcc(cpu, ZPCI_PCI_LS_ERR); 741 s390_set_status_code(env, r1, ZPCI_RPCIT_ST_INSUFF_RES); 742 } 743 } 744 return 0; 745 } 746 747 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, 748 uint8_t ar, uintptr_t ra) 749 { 750 CPUS390XState *env = &cpu->env; 751 S390PCIBusDevice *pbdev; 752 MemoryRegion *mr; 753 MemTxResult result; 754 uint64_t offset; 755 int i; 756 uint32_t fh; 757 uint8_t pcias; 758 uint16_t len; 759 uint8_t buffer[128]; 760 761 if (env->psw.mask & PSW_MASK_PSTATE) { 762 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 763 return 0; 764 } 765 766 fh = env->regs[r1] >> 32; 767 pcias = (env->regs[r1] >> 16) & 0xf; 768 len = env->regs[r1] & 0x1fff; 769 offset = env->regs[r3]; 770 771 if (!(fh & FH_MASK_ENABLE)) { 772 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 773 return 0; 774 } 775 776 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 777 if (!pbdev) { 778 DPRINTF("pcistb no pci dev fh 0x%x\n", fh); 779 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 780 return 0; 781 } 782 783 switch (pbdev->state) { 784 case ZPCI_FS_PERMANENT_ERROR: 785 case ZPCI_FS_ERROR: 786 setcc(cpu, ZPCI_PCI_LS_ERR); 787 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED); 788 return 0; 789 default: 790 break; 791 } 792 793 if (pcias > ZPCI_IO_BAR_MAX) { 794 DPRINTF("pcistb invalid space\n"); 795 setcc(cpu, ZPCI_PCI_LS_ERR); 796 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS); 797 return 0; 798 } 799 800 /* Verify the address, offset and length */ 801 /* offset must be a multiple of 8 */ 802 if (offset % 8) { 803 goto specification_error; 804 } 805 /* Length must be greater than 8, a multiple of 8 */ 806 /* and not greater than maxstbl */ 807 if ((len <= 8) || (len % 8) || 808 (len > pbdev->pci_group->zpci_group.maxstbl)) { 809 goto specification_error; 810 } 811 /* Do not cross a 4K-byte boundary */ 812 if (((offset & 0xfff) + len) > 0x1000) { 813 goto specification_error; 814 } 815 /* Guest address must be double word aligned */ 816 if (gaddr & 0x07UL) { 817 goto specification_error; 818 } 819 820 mr = pbdev->pdev->io_regions[pcias].memory; 821 mr = s390_get_subregion(mr, offset, len); 822 offset -= mr->addr; 823 824 for (i = 0; i < len; i += 8) { 825 if (!memory_region_access_valid(mr, offset + i, 8, true, 826 MEMTXATTRS_UNSPECIFIED)) { 827 s390_program_interrupt(env, PGM_OPERAND, ra); 828 return 0; 829 } 830 } 831 832 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) { 833 s390_cpu_virt_mem_handle_exc(cpu, ra); 834 return 0; 835 } 836 837 for (i = 0; i < len / 8; i++) { 838 result = memory_region_dispatch_write(mr, offset + i * 8, 839 ldq_p(buffer + i * 8), 840 MO_64, MEMTXATTRS_UNSPECIFIED); 841 if (result != MEMTX_OK) { 842 s390_program_interrupt(env, PGM_OPERAND, ra); 843 return 0; 844 } 845 } 846 847 pbdev->fmb.counter[ZPCI_FMB_CNT_STB]++; 848 849 setcc(cpu, ZPCI_PCI_LS_OK); 850 return 0; 851 852 specification_error: 853 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 854 return 0; 855 } 856 857 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib) 858 { 859 int ret, len; 860 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data)); 861 862 pbdev->routes.adapter.adapter_id = css_get_adapter_id( 863 CSS_IO_ADAPTER_PCI, isc); 864 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t)); 865 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long); 866 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len); 867 868 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 869 if (ret) { 870 goto out; 871 } 872 873 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator); 874 if (ret) { 875 goto out; 876 } 877 878 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb); 879 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data)); 880 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv); 881 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data)); 882 pbdev->isc = isc; 883 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data)); 884 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data)); 885 886 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 887 return 0; 888 out: 889 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 890 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 891 pbdev->summary_ind = NULL; 892 pbdev->indicator = NULL; 893 return ret; 894 } 895 896 int pci_dereg_irqs(S390PCIBusDevice *pbdev) 897 { 898 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 899 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 900 901 pbdev->summary_ind = NULL; 902 pbdev->indicator = NULL; 903 pbdev->routes.adapter.summary_addr = 0; 904 pbdev->routes.adapter.summary_offset = 0; 905 pbdev->routes.adapter.ind_addr = 0; 906 pbdev->routes.adapter.ind_offset = 0; 907 pbdev->isc = 0; 908 pbdev->noi = 0; 909 pbdev->sum = 0; 910 911 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 912 return 0; 913 } 914 915 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib, 916 uintptr_t ra) 917 { 918 uint64_t pba = ldq_p(&fib.pba); 919 uint64_t pal = ldq_p(&fib.pal); 920 uint64_t g_iota = ldq_p(&fib.iota); 921 uint8_t dt = (g_iota >> 2) & 0x7; 922 uint8_t t = (g_iota >> 11) & 0x1; 923 924 pba &= ~0xfff; 925 pal |= 0xfff; 926 if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) { 927 s390_program_interrupt(env, PGM_OPERAND, ra); 928 return -EINVAL; 929 } 930 931 /* currently we only support designation type 1 with translation */ 932 if (!(dt == ZPCI_IOTA_RTTO && t)) { 933 error_report("unsupported ioat dt %d t %d", dt, t); 934 s390_program_interrupt(env, PGM_OPERAND, ra); 935 return -EINVAL; 936 } 937 938 iommu->pba = pba; 939 iommu->pal = pal; 940 iommu->g_iota = g_iota; 941 942 s390_pci_iommu_enable(iommu); 943 944 return 0; 945 } 946 947 void pci_dereg_ioat(S390PCIIOMMU *iommu) 948 { 949 s390_pci_iommu_disable(iommu); 950 iommu->pba = 0; 951 iommu->pal = 0; 952 iommu->g_iota = 0; 953 } 954 955 void fmb_timer_free(S390PCIBusDevice *pbdev) 956 { 957 if (pbdev->fmb_timer) { 958 timer_free(pbdev->fmb_timer); 959 pbdev->fmb_timer = NULL; 960 } 961 pbdev->fmb_addr = 0; 962 memset(&pbdev->fmb, 0, sizeof(ZpciFmb)); 963 } 964 965 static int fmb_do_update(S390PCIBusDevice *pbdev, int offset, uint64_t val, 966 int len) 967 { 968 MemTxResult ret; 969 uint64_t dst = pbdev->fmb_addr + offset; 970 971 switch (len) { 972 case 8: 973 address_space_stq_be(&address_space_memory, dst, val, 974 MEMTXATTRS_UNSPECIFIED, 975 &ret); 976 break; 977 case 4: 978 address_space_stl_be(&address_space_memory, dst, val, 979 MEMTXATTRS_UNSPECIFIED, 980 &ret); 981 break; 982 case 2: 983 address_space_stw_be(&address_space_memory, dst, val, 984 MEMTXATTRS_UNSPECIFIED, 985 &ret); 986 break; 987 case 1: 988 address_space_stb(&address_space_memory, dst, val, 989 MEMTXATTRS_UNSPECIFIED, 990 &ret); 991 break; 992 default: 993 ret = MEMTX_ERROR; 994 break; 995 } 996 if (ret != MEMTX_OK) { 997 s390_pci_generate_error_event(ERR_EVENT_FMBA, pbdev->fh, pbdev->fid, 998 pbdev->fmb_addr, 0); 999 fmb_timer_free(pbdev); 1000 } 1001 1002 return ret; 1003 } 1004 1005 static void fmb_update(void *opaque) 1006 { 1007 S390PCIBusDevice *pbdev = opaque; 1008 int64_t t = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); 1009 int i; 1010 1011 /* Update U bit */ 1012 pbdev->fmb.last_update *= 2; 1013 pbdev->fmb.last_update |= UPDATE_U_BIT; 1014 if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update), 1015 pbdev->fmb.last_update, 1016 sizeof(pbdev->fmb.last_update))) { 1017 return; 1018 } 1019 1020 /* Update FMB sample count */ 1021 if (fmb_do_update(pbdev, offsetof(ZpciFmb, sample), 1022 pbdev->fmb.sample++, 1023 sizeof(pbdev->fmb.sample))) { 1024 return; 1025 } 1026 1027 /* Update FMB counters */ 1028 for (i = 0; i < ZPCI_FMB_CNT_MAX; i++) { 1029 if (fmb_do_update(pbdev, offsetof(ZpciFmb, counter[i]), 1030 pbdev->fmb.counter[i], 1031 sizeof(pbdev->fmb.counter[0]))) { 1032 return; 1033 } 1034 } 1035 1036 /* Clear U bit and update the time */ 1037 pbdev->fmb.last_update = time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 1038 pbdev->fmb.last_update *= 2; 1039 if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update), 1040 pbdev->fmb.last_update, 1041 sizeof(pbdev->fmb.last_update))) { 1042 return; 1043 } 1044 timer_mod(pbdev->fmb_timer, t + DEFAULT_MUI); 1045 } 1046 1047 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 1048 uintptr_t ra) 1049 { 1050 CPUS390XState *env = &cpu->env; 1051 uint8_t oc, dmaas; 1052 uint32_t fh; 1053 ZpciFib fib; 1054 S390PCIBusDevice *pbdev; 1055 uint64_t cc = ZPCI_PCI_LS_OK; 1056 1057 if (env->psw.mask & PSW_MASK_PSTATE) { 1058 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 1059 return 0; 1060 } 1061 1062 oc = env->regs[r1] & 0xff; 1063 dmaas = (env->regs[r1] >> 16) & 0xff; 1064 fh = env->regs[r1] >> 32; 1065 1066 if (fiba & 0x7) { 1067 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 1068 return 0; 1069 } 1070 1071 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 1072 if (!pbdev) { 1073 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh); 1074 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1075 return 0; 1076 } 1077 1078 switch (pbdev->state) { 1079 case ZPCI_FS_RESERVED: 1080 case ZPCI_FS_STANDBY: 1081 case ZPCI_FS_DISABLED: 1082 case ZPCI_FS_PERMANENT_ERROR: 1083 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1084 return 0; 1085 default: 1086 break; 1087 } 1088 1089 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 1090 s390_cpu_virt_mem_handle_exc(cpu, ra); 1091 return 0; 1092 } 1093 1094 if (fib.fmt != 0) { 1095 s390_program_interrupt(env, PGM_OPERAND, ra); 1096 return 0; 1097 } 1098 1099 switch (oc) { 1100 case ZPCI_MOD_FC_REG_INT: 1101 if (pbdev->summary_ind) { 1102 cc = ZPCI_PCI_LS_ERR; 1103 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1104 } else if (reg_irqs(env, pbdev, fib)) { 1105 cc = ZPCI_PCI_LS_ERR; 1106 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL); 1107 } 1108 break; 1109 case ZPCI_MOD_FC_DEREG_INT: 1110 if (!pbdev->summary_ind) { 1111 cc = ZPCI_PCI_LS_ERR; 1112 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1113 } else { 1114 pci_dereg_irqs(pbdev); 1115 } 1116 break; 1117 case ZPCI_MOD_FC_REG_IOAT: 1118 if (dmaas != 0) { 1119 cc = ZPCI_PCI_LS_ERR; 1120 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 1121 } else if (pbdev->iommu->enabled) { 1122 cc = ZPCI_PCI_LS_ERR; 1123 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1124 } else if (reg_ioat(env, pbdev->iommu, fib, ra)) { 1125 cc = ZPCI_PCI_LS_ERR; 1126 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 1127 } 1128 break; 1129 case ZPCI_MOD_FC_DEREG_IOAT: 1130 if (dmaas != 0) { 1131 cc = ZPCI_PCI_LS_ERR; 1132 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 1133 } else if (!pbdev->iommu->enabled) { 1134 cc = ZPCI_PCI_LS_ERR; 1135 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1136 } else { 1137 pci_dereg_ioat(pbdev->iommu); 1138 } 1139 break; 1140 case ZPCI_MOD_FC_REREG_IOAT: 1141 if (dmaas != 0) { 1142 cc = ZPCI_PCI_LS_ERR; 1143 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 1144 } else if (!pbdev->iommu->enabled) { 1145 cc = ZPCI_PCI_LS_ERR; 1146 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1147 } else { 1148 pci_dereg_ioat(pbdev->iommu); 1149 if (reg_ioat(env, pbdev->iommu, fib, ra)) { 1150 cc = ZPCI_PCI_LS_ERR; 1151 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 1152 } 1153 } 1154 break; 1155 case ZPCI_MOD_FC_RESET_ERROR: 1156 switch (pbdev->state) { 1157 case ZPCI_FS_BLOCKED: 1158 case ZPCI_FS_ERROR: 1159 pbdev->state = ZPCI_FS_ENABLED; 1160 break; 1161 default: 1162 cc = ZPCI_PCI_LS_ERR; 1163 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1164 } 1165 break; 1166 case ZPCI_MOD_FC_RESET_BLOCK: 1167 switch (pbdev->state) { 1168 case ZPCI_FS_ERROR: 1169 pbdev->state = ZPCI_FS_BLOCKED; 1170 break; 1171 default: 1172 cc = ZPCI_PCI_LS_ERR; 1173 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1174 } 1175 break; 1176 case ZPCI_MOD_FC_SET_MEASURE: { 1177 uint64_t fmb_addr = ldq_p(&fib.fmb_addr); 1178 1179 if (fmb_addr & FMBK_MASK) { 1180 cc = ZPCI_PCI_LS_ERR; 1181 s390_pci_generate_error_event(ERR_EVENT_FMBPRO, pbdev->fh, 1182 pbdev->fid, fmb_addr, 0); 1183 fmb_timer_free(pbdev); 1184 break; 1185 } 1186 1187 if (!fmb_addr) { 1188 /* Stop updating FMB. */ 1189 fmb_timer_free(pbdev); 1190 break; 1191 } 1192 1193 if (!pbdev->fmb_timer) { 1194 pbdev->fmb_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 1195 fmb_update, pbdev); 1196 } else if (timer_pending(pbdev->fmb_timer)) { 1197 /* Remove pending timer to update FMB address. */ 1198 timer_del(pbdev->fmb_timer); 1199 } 1200 pbdev->fmb_addr = fmb_addr; 1201 timer_mod(pbdev->fmb_timer, 1202 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + DEFAULT_MUI); 1203 break; 1204 } 1205 default: 1206 s390_program_interrupt(&cpu->env, PGM_OPERAND, ra); 1207 cc = ZPCI_PCI_LS_ERR; 1208 } 1209 1210 setcc(cpu, cc); 1211 return 0; 1212 } 1213 1214 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 1215 uintptr_t ra) 1216 { 1217 CPUS390XState *env = &cpu->env; 1218 uint8_t dmaas; 1219 uint32_t fh; 1220 ZpciFib fib; 1221 S390PCIBusDevice *pbdev; 1222 uint32_t data; 1223 uint64_t cc = ZPCI_PCI_LS_OK; 1224 1225 if (env->psw.mask & PSW_MASK_PSTATE) { 1226 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 1227 return 0; 1228 } 1229 1230 fh = env->regs[r1] >> 32; 1231 dmaas = (env->regs[r1] >> 16) & 0xff; 1232 1233 if (dmaas) { 1234 setcc(cpu, ZPCI_PCI_LS_ERR); 1235 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS); 1236 return 0; 1237 } 1238 1239 if (fiba & 0x7) { 1240 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 1241 return 0; 1242 } 1243 1244 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX); 1245 if (!pbdev) { 1246 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1247 return 0; 1248 } 1249 1250 memset(&fib, 0, sizeof(fib)); 1251 1252 switch (pbdev->state) { 1253 case ZPCI_FS_RESERVED: 1254 case ZPCI_FS_STANDBY: 1255 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1256 return 0; 1257 case ZPCI_FS_DISABLED: 1258 if (fh & FH_MASK_ENABLE) { 1259 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1260 return 0; 1261 } 1262 goto out; 1263 /* BLOCKED bit is set to one coincident with the setting of ERROR bit. 1264 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */ 1265 case ZPCI_FS_ERROR: 1266 fib.fc |= 0x20; 1267 /* fallthrough */ 1268 case ZPCI_FS_BLOCKED: 1269 fib.fc |= 0x40; 1270 /* fallthrough */ 1271 case ZPCI_FS_ENABLED: 1272 fib.fc |= 0x80; 1273 if (pbdev->iommu->enabled) { 1274 fib.fc |= 0x10; 1275 } 1276 if (!(fh & FH_MASK_ENABLE)) { 1277 env->regs[r1] |= 1ULL << 63; 1278 } 1279 break; 1280 case ZPCI_FS_PERMANENT_ERROR: 1281 setcc(cpu, ZPCI_PCI_LS_ERR); 1282 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR); 1283 return 0; 1284 } 1285 1286 stq_p(&fib.pba, pbdev->iommu->pba); 1287 stq_p(&fib.pal, pbdev->iommu->pal); 1288 stq_p(&fib.iota, pbdev->iommu->g_iota); 1289 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr); 1290 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr); 1291 stq_p(&fib.fmb_addr, pbdev->fmb_addr); 1292 1293 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) | 1294 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) | 1295 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset; 1296 stl_p(&fib.data, data); 1297 1298 out: 1299 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 1300 s390_cpu_virt_mem_handle_exc(cpu, ra); 1301 return 0; 1302 } 1303 1304 setcc(cpu, cc); 1305 return 0; 1306 } 1307