1 /* 2 * s390 PCI instructions 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "exec/memop.h" 16 #include "exec/memory-internal.h" 17 #include "qemu/error-report.h" 18 #include "sysemu/hw_accel.h" 19 #include "hw/s390x/s390-pci-inst.h" 20 #include "hw/s390x/s390-pci-bus.h" 21 #include "hw/s390x/s390-pci-kvm.h" 22 #include "hw/s390x/s390-pci-vfio.h" 23 #include "hw/s390x/tod.h" 24 25 #ifndef DEBUG_S390PCI_INST 26 #define DEBUG_S390PCI_INST 0 27 #endif 28 29 #define DPRINTF(fmt, ...) \ 30 do { \ 31 if (DEBUG_S390PCI_INST) { \ 32 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \ 33 } \ 34 } while (0) 35 36 static inline void inc_dma_avail(S390PCIIOMMU *iommu) 37 { 38 if (iommu->dma_limit) { 39 iommu->dma_limit->avail++; 40 } 41 } 42 43 static inline void dec_dma_avail(S390PCIIOMMU *iommu) 44 { 45 if (iommu->dma_limit) { 46 iommu->dma_limit->avail--; 47 } 48 } 49 50 static void s390_set_status_code(CPUS390XState *env, 51 uint8_t r, uint64_t status_code) 52 { 53 env->regs[r] &= ~0xff000000ULL; 54 env->regs[r] |= (status_code & 0xff) << 24; 55 } 56 57 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) 58 { 59 S390PCIBusDevice *pbdev = NULL; 60 S390pciState *s = s390_get_phb(); 61 uint32_t res_code, initial_l2, g_l2; 62 int rc, i; 63 uint64_t resume_token; 64 65 rc = 0; 66 if (lduw_p(&rrb->request.hdr.len) != 32) { 67 res_code = CLP_RC_LEN; 68 rc = -EINVAL; 69 goto out; 70 } 71 72 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) { 73 res_code = CLP_RC_FMT; 74 rc = -EINVAL; 75 goto out; 76 } 77 78 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 || 79 ldq_p(&rrb->request.reserved1) != 0) { 80 res_code = CLP_RC_RESNOT0; 81 rc = -EINVAL; 82 goto out; 83 } 84 85 resume_token = ldq_p(&rrb->request.resume_token); 86 87 if (resume_token) { 88 pbdev = s390_pci_find_dev_by_idx(s, resume_token); 89 if (!pbdev) { 90 res_code = CLP_RC_LISTPCI_BADRT; 91 rc = -EINVAL; 92 goto out; 93 } 94 } else { 95 pbdev = s390_pci_find_next_avail_dev(s, NULL); 96 } 97 98 if (lduw_p(&rrb->response.hdr.len) < 48) { 99 res_code = CLP_RC_8K; 100 rc = -EINVAL; 101 goto out; 102 } 103 104 initial_l2 = lduw_p(&rrb->response.hdr.len); 105 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry) 106 != 0) { 107 res_code = CLP_RC_LEN; 108 rc = -EINVAL; 109 *cc = 3; 110 goto out; 111 } 112 113 stl_p(&rrb->response.fmt, 0); 114 stq_p(&rrb->response.reserved1, 0); 115 stl_p(&rrb->response.mdd, FH_MASK_SHM); 116 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS); 117 rrb->response.flags = UID_CHECKING_ENABLED; 118 rrb->response.entry_size = sizeof(ClpFhListEntry); 119 120 i = 0; 121 g_l2 = LIST_PCI_HDR_LEN; 122 while (g_l2 < initial_l2 && pbdev) { 123 stw_p(&rrb->response.fh_list[i].device_id, 124 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID)); 125 stw_p(&rrb->response.fh_list[i].vendor_id, 126 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID)); 127 /* Ignore RESERVED devices. */ 128 stl_p(&rrb->response.fh_list[i].config, 129 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31); 130 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid); 131 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh); 132 133 g_l2 += sizeof(ClpFhListEntry); 134 /* Add endian check for DPRINTF? */ 135 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n", 136 g_l2, 137 lduw_p(&rrb->response.fh_list[i].vendor_id), 138 lduw_p(&rrb->response.fh_list[i].device_id), 139 ldl_p(&rrb->response.fh_list[i].fid), 140 ldl_p(&rrb->response.fh_list[i].fh)); 141 pbdev = s390_pci_find_next_avail_dev(s, pbdev); 142 i++; 143 } 144 145 if (!pbdev) { 146 resume_token = 0; 147 } else { 148 resume_token = pbdev->fh & FH_MASK_INDEX; 149 } 150 stq_p(&rrb->response.resume_token, resume_token); 151 stw_p(&rrb->response.hdr.len, g_l2); 152 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK); 153 out: 154 if (rc) { 155 DPRINTF("list pci failed rc 0x%x\n", rc); 156 stw_p(&rrb->response.hdr.rsp, res_code); 157 } 158 return rc; 159 } 160 161 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) 162 { 163 ClpReqHdr *reqh; 164 ClpRspHdr *resh; 165 S390PCIBusDevice *pbdev; 166 uint32_t req_len; 167 uint32_t res_len; 168 uint8_t buffer[4096 * 2]; 169 uint8_t cc = 0; 170 CPUS390XState *env = &cpu->env; 171 S390pciState *s = s390_get_phb(); 172 int i; 173 174 if (env->psw.mask & PSW_MASK_PSTATE) { 175 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 176 return 0; 177 } 178 179 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) { 180 s390_cpu_virt_mem_handle_exc(cpu, ra); 181 return 0; 182 } 183 reqh = (ClpReqHdr *)buffer; 184 req_len = lduw_p(&reqh->len); 185 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) { 186 s390_program_interrupt(env, PGM_OPERAND, ra); 187 return 0; 188 } 189 190 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 191 req_len + sizeof(*resh))) { 192 s390_cpu_virt_mem_handle_exc(cpu, ra); 193 return 0; 194 } 195 resh = (ClpRspHdr *)(buffer + req_len); 196 res_len = lduw_p(&resh->len); 197 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) { 198 s390_program_interrupt(env, PGM_OPERAND, ra); 199 return 0; 200 } 201 if ((req_len + res_len) > 8192) { 202 s390_program_interrupt(env, PGM_OPERAND, ra); 203 return 0; 204 } 205 206 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 207 req_len + res_len)) { 208 s390_cpu_virt_mem_handle_exc(cpu, ra); 209 return 0; 210 } 211 212 if (req_len != 32) { 213 stw_p(&resh->rsp, CLP_RC_LEN); 214 goto out; 215 } 216 217 switch (lduw_p(&reqh->cmd)) { 218 case CLP_LIST_PCI: { 219 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer; 220 list_pci(rrb, &cc); 221 break; 222 } 223 case CLP_SET_PCI_FN: { 224 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh; 225 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh; 226 227 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh)); 228 if (!pbdev) { 229 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); 230 goto out; 231 } 232 233 switch (reqsetpci->oc) { 234 case CLP_SET_ENABLE_PCI_FN: 235 switch (reqsetpci->ndas) { 236 case 0: 237 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS); 238 goto out; 239 case 1: 240 break; 241 default: 242 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES); 243 goto out; 244 } 245 246 if (pbdev->fh & FH_MASK_ENABLE) { 247 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 248 goto out; 249 } 250 251 /* 252 * Take this opportunity to make sure we still have an accurate 253 * host fh. It's possible part of the handle changed while the 254 * device was disabled to the guest (e.g. vfio hot reset for 255 * ISM during plug) 256 */ 257 if (pbdev->interp) { 258 /* Take this opportunity to make sure we are sync'd with host */ 259 if (!s390_pci_get_host_fh(pbdev, &pbdev->fh) || 260 !(pbdev->fh & FH_MASK_ENABLE)) { 261 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); 262 goto out; 263 } 264 } 265 pbdev->fh |= FH_MASK_ENABLE; 266 pbdev->state = ZPCI_FS_ENABLED; 267 stl_p(&ressetpci->fh, pbdev->fh); 268 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 269 break; 270 case CLP_SET_DISABLE_PCI_FN: 271 if (!(pbdev->fh & FH_MASK_ENABLE)) { 272 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 273 goto out; 274 } 275 device_legacy_reset(DEVICE(pbdev)); 276 pbdev->fh &= ~FH_MASK_ENABLE; 277 pbdev->state = ZPCI_FS_DISABLED; 278 stl_p(&ressetpci->fh, pbdev->fh); 279 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 280 break; 281 default: 282 DPRINTF("unknown set pci command\n"); 283 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 284 break; 285 } 286 break; 287 } 288 case CLP_QUERY_PCI_FN: { 289 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh; 290 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh; 291 292 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh)); 293 if (!pbdev) { 294 DPRINTF("query pci no pci dev\n"); 295 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH); 296 goto out; 297 } 298 299 stq_p(&resquery->sdma, pbdev->zpci_fn.sdma); 300 stq_p(&resquery->edma, pbdev->zpci_fn.edma); 301 stw_p(&resquery->pchid, pbdev->zpci_fn.pchid); 302 stw_p(&resquery->vfn, pbdev->zpci_fn.vfn); 303 resquery->flags = pbdev->zpci_fn.flags; 304 resquery->pfgid = pbdev->zpci_fn.pfgid; 305 resquery->pft = pbdev->zpci_fn.pft; 306 resquery->fmbl = pbdev->zpci_fn.fmbl; 307 stl_p(&resquery->fid, pbdev->zpci_fn.fid); 308 stl_p(&resquery->uid, pbdev->zpci_fn.uid); 309 memcpy(resquery->pfip, pbdev->zpci_fn.pfip, CLP_PFIP_NR_SEGMENTS); 310 memcpy(resquery->util_str, pbdev->zpci_fn.util_str, CLP_UTIL_STR_LEN); 311 312 for (i = 0; i < PCI_BAR_COUNT; i++) { 313 uint32_t data = pci_get_long(pbdev->pdev->config + 314 PCI_BASE_ADDRESS_0 + (i * 4)); 315 316 stl_p(&resquery->bar[i], data); 317 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ? 318 ctz64(pbdev->pdev->io_regions[i].size) : 0; 319 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i, 320 ldl_p(&resquery->bar[i]), 321 pbdev->pdev->io_regions[i].size, 322 resquery->bar_size[i]); 323 } 324 325 stw_p(&resquery->hdr.rsp, CLP_RC_OK); 326 break; 327 } 328 case CLP_QUERY_PCI_FNGRP: { 329 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh; 330 331 ClpReqQueryPciGrp *reqgrp = (ClpReqQueryPciGrp *)reqh; 332 S390PCIGroup *group; 333 334 group = s390_group_find(reqgrp->g); 335 if (!group) { 336 /* We do not allow access to unknown groups */ 337 /* The group must have been obtained with a vfio device */ 338 stw_p(&resgrp->hdr.rsp, CLP_RC_QUERYPCIFG_PFGID); 339 goto out; 340 } 341 resgrp->fr = group->zpci_group.fr; 342 stq_p(&resgrp->dasm, group->zpci_group.dasm); 343 stq_p(&resgrp->msia, group->zpci_group.msia); 344 stw_p(&resgrp->mui, group->zpci_group.mui); 345 stw_p(&resgrp->i, group->zpci_group.i); 346 stw_p(&resgrp->maxstbl, group->zpci_group.maxstbl); 347 resgrp->version = group->zpci_group.version; 348 resgrp->dtsm = group->zpci_group.dtsm; 349 stw_p(&resgrp->hdr.rsp, CLP_RC_OK); 350 break; 351 } 352 default: 353 DPRINTF("unknown clp command\n"); 354 stw_p(&resh->rsp, CLP_RC_CMD); 355 break; 356 } 357 358 out: 359 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer, 360 req_len + res_len)) { 361 s390_cpu_virt_mem_handle_exc(cpu, ra); 362 return 0; 363 } 364 setcc(cpu, cc); 365 return 0; 366 } 367 368 /** 369 * Swap data contained in s390x big endian registers to little endian 370 * PCI bars. 371 * 372 * @ptr: a pointer to a uint64_t data field 373 * @len: the length of the valid data, must be 1,2,4 or 8 374 */ 375 static int zpci_endian_swap(uint64_t *ptr, uint8_t len) 376 { 377 uint64_t data = *ptr; 378 379 switch (len) { 380 case 1: 381 break; 382 case 2: 383 data = bswap16(data); 384 break; 385 case 4: 386 data = bswap32(data); 387 break; 388 case 8: 389 data = bswap64(data); 390 break; 391 default: 392 return -EINVAL; 393 } 394 *ptr = data; 395 return 0; 396 } 397 398 static MemoryRegion *s390_get_subregion(MemoryRegion *mr, uint64_t offset, 399 uint8_t len) 400 { 401 MemoryRegion *subregion; 402 uint64_t subregion_size; 403 404 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) { 405 subregion_size = int128_get64(subregion->size); 406 if ((offset >= subregion->addr) && 407 (offset + len) <= (subregion->addr + subregion_size)) { 408 mr = subregion; 409 break; 410 } 411 } 412 return mr; 413 } 414 415 static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias, 416 uint64_t offset, uint64_t *data, uint8_t len) 417 { 418 MemoryRegion *mr; 419 420 mr = pbdev->pdev->io_regions[pcias].memory; 421 mr = s390_get_subregion(mr, offset, len); 422 offset -= mr->addr; 423 return memory_region_dispatch_read(mr, offset, data, 424 size_memop(len) | MO_BE, 425 MEMTXATTRS_UNSPECIFIED); 426 } 427 428 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 429 { 430 CPUS390XState *env = &cpu->env; 431 S390PCIBusDevice *pbdev; 432 uint64_t offset; 433 uint64_t data; 434 MemTxResult result; 435 uint8_t len; 436 uint32_t fh; 437 uint8_t pcias; 438 439 if (env->psw.mask & PSW_MASK_PSTATE) { 440 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 441 return 0; 442 } 443 444 if (r2 & 0x1) { 445 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 446 return 0; 447 } 448 449 fh = env->regs[r2] >> 32; 450 pcias = (env->regs[r2] >> 16) & 0xf; 451 len = env->regs[r2] & 0xf; 452 offset = env->regs[r2 + 1]; 453 454 if (!(fh & FH_MASK_ENABLE)) { 455 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 456 return 0; 457 } 458 459 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 460 if (!pbdev) { 461 DPRINTF("pcilg no pci dev\n"); 462 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 463 return 0; 464 } 465 466 switch (pbdev->state) { 467 case ZPCI_FS_PERMANENT_ERROR: 468 case ZPCI_FS_ERROR: 469 setcc(cpu, ZPCI_PCI_LS_ERR); 470 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 471 return 0; 472 default: 473 break; 474 } 475 476 switch (pcias) { 477 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 478 if (!len || (len > (8 - (offset & 0x7)))) { 479 s390_program_interrupt(env, PGM_OPERAND, ra); 480 return 0; 481 } 482 result = zpci_read_bar(pbdev, pcias, offset, &data, len); 483 if (result != MEMTX_OK) { 484 s390_program_interrupt(env, PGM_OPERAND, ra); 485 return 0; 486 } 487 break; 488 case ZPCI_CONFIG_BAR: 489 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 490 s390_program_interrupt(env, PGM_OPERAND, ra); 491 return 0; 492 } 493 data = pci_host_config_read_common( 494 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len); 495 496 if (zpci_endian_swap(&data, len)) { 497 s390_program_interrupt(env, PGM_OPERAND, ra); 498 return 0; 499 } 500 break; 501 default: 502 DPRINTF("pcilg invalid space\n"); 503 setcc(cpu, ZPCI_PCI_LS_ERR); 504 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 505 return 0; 506 } 507 508 pbdev->fmb.counter[ZPCI_FMB_CNT_LD]++; 509 510 env->regs[r1] = data; 511 setcc(cpu, ZPCI_PCI_LS_OK); 512 return 0; 513 } 514 515 static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias, 516 uint64_t offset, uint64_t data, uint8_t len) 517 { 518 MemoryRegion *mr; 519 520 mr = pbdev->pdev->io_regions[pcias].memory; 521 mr = s390_get_subregion(mr, offset, len); 522 offset -= mr->addr; 523 return memory_region_dispatch_write(mr, offset, data, 524 size_memop(len) | MO_BE, 525 MEMTXATTRS_UNSPECIFIED); 526 } 527 528 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 529 { 530 CPUS390XState *env = &cpu->env; 531 uint64_t offset, data; 532 S390PCIBusDevice *pbdev; 533 MemTxResult result; 534 uint8_t len; 535 uint32_t fh; 536 uint8_t pcias; 537 538 if (env->psw.mask & PSW_MASK_PSTATE) { 539 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 540 return 0; 541 } 542 543 if (r2 & 0x1) { 544 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 545 return 0; 546 } 547 548 fh = env->regs[r2] >> 32; 549 pcias = (env->regs[r2] >> 16) & 0xf; 550 len = env->regs[r2] & 0xf; 551 offset = env->regs[r2 + 1]; 552 data = env->regs[r1]; 553 554 if (!(fh & FH_MASK_ENABLE)) { 555 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 556 return 0; 557 } 558 559 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 560 if (!pbdev) { 561 DPRINTF("pcistg no pci dev\n"); 562 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 563 return 0; 564 } 565 566 switch (pbdev->state) { 567 /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED 568 * are already covered by the FH_MASK_ENABLE check above 569 */ 570 case ZPCI_FS_PERMANENT_ERROR: 571 case ZPCI_FS_ERROR: 572 setcc(cpu, ZPCI_PCI_LS_ERR); 573 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 574 return 0; 575 default: 576 break; 577 } 578 579 switch (pcias) { 580 /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */ 581 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 582 /* Check length: 583 * A length of 0 is invalid and length should not cross a double word 584 */ 585 if (!len || (len > (8 - (offset & 0x7)))) { 586 s390_program_interrupt(env, PGM_OPERAND, ra); 587 return 0; 588 } 589 590 result = zpci_write_bar(pbdev, pcias, offset, data, len); 591 if (result != MEMTX_OK) { 592 s390_program_interrupt(env, PGM_OPERAND, ra); 593 return 0; 594 } 595 break; 596 case ZPCI_CONFIG_BAR: 597 /* ZPCI uses the pseudo BAR number 15 as configuration space */ 598 /* possible access lengths are 1,2,4 and must not cross a word */ 599 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 600 s390_program_interrupt(env, PGM_OPERAND, ra); 601 return 0; 602 } 603 /* len = 1,2,4 so we do not need to test */ 604 zpci_endian_swap(&data, len); 605 pci_host_config_write_common(pbdev->pdev, offset, 606 pci_config_size(pbdev->pdev), 607 data, len); 608 break; 609 default: 610 DPRINTF("pcistg invalid space\n"); 611 setcc(cpu, ZPCI_PCI_LS_ERR); 612 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 613 return 0; 614 } 615 616 pbdev->fmb.counter[ZPCI_FMB_CNT_ST]++; 617 618 setcc(cpu, ZPCI_PCI_LS_OK); 619 return 0; 620 } 621 622 static uint32_t s390_pci_update_iotlb(S390PCIIOMMU *iommu, 623 S390IOTLBEntry *entry) 624 { 625 S390IOTLBEntry *cache = g_hash_table_lookup(iommu->iotlb, &entry->iova); 626 IOMMUTLBEvent event = { 627 .type = entry->perm ? IOMMU_NOTIFIER_MAP : IOMMU_NOTIFIER_UNMAP, 628 .entry = { 629 .target_as = &address_space_memory, 630 .iova = entry->iova, 631 .translated_addr = entry->translated_addr, 632 .perm = entry->perm, 633 .addr_mask = ~TARGET_PAGE_MASK, 634 }, 635 }; 636 637 if (event.type == IOMMU_NOTIFIER_UNMAP) { 638 if (!cache) { 639 goto out; 640 } 641 g_hash_table_remove(iommu->iotlb, &entry->iova); 642 inc_dma_avail(iommu); 643 } else { 644 if (cache) { 645 if (cache->perm == entry->perm && 646 cache->translated_addr == entry->translated_addr) { 647 goto out; 648 } 649 650 event.type = IOMMU_NOTIFIER_UNMAP; 651 event.entry.perm = IOMMU_NONE; 652 memory_region_notify_iommu(&iommu->iommu_mr, 0, event); 653 event.type = IOMMU_NOTIFIER_MAP; 654 event.entry.perm = entry->perm; 655 } 656 657 cache = g_new(S390IOTLBEntry, 1); 658 cache->iova = entry->iova; 659 cache->translated_addr = entry->translated_addr; 660 cache->len = TARGET_PAGE_SIZE; 661 cache->perm = entry->perm; 662 g_hash_table_replace(iommu->iotlb, &cache->iova, cache); 663 dec_dma_avail(iommu); 664 } 665 666 memory_region_notify_iommu(&iommu->iommu_mr, 0, event); 667 668 out: 669 return iommu->dma_limit ? iommu->dma_limit->avail : 1; 670 } 671 672 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 673 { 674 CPUS390XState *env = &cpu->env; 675 uint32_t fh; 676 uint16_t error = 0; 677 S390PCIBusDevice *pbdev; 678 S390PCIIOMMU *iommu; 679 S390IOTLBEntry entry; 680 hwaddr start, end; 681 uint32_t dma_avail; 682 683 if (env->psw.mask & PSW_MASK_PSTATE) { 684 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 685 return 0; 686 } 687 688 if (r2 & 0x1) { 689 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 690 return 0; 691 } 692 693 fh = env->regs[r1] >> 32; 694 start = env->regs[r2]; 695 end = start + env->regs[r2 + 1]; 696 697 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 698 if (!pbdev) { 699 DPRINTF("rpcit no pci dev\n"); 700 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 701 return 0; 702 } 703 704 switch (pbdev->state) { 705 case ZPCI_FS_RESERVED: 706 case ZPCI_FS_STANDBY: 707 case ZPCI_FS_DISABLED: 708 case ZPCI_FS_PERMANENT_ERROR: 709 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 710 return 0; 711 case ZPCI_FS_ERROR: 712 setcc(cpu, ZPCI_PCI_LS_ERR); 713 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER); 714 return 0; 715 default: 716 break; 717 } 718 719 iommu = pbdev->iommu; 720 if (iommu->dma_limit) { 721 dma_avail = iommu->dma_limit->avail; 722 } else { 723 dma_avail = 1; 724 } 725 if (!iommu->g_iota) { 726 error = ERR_EVENT_INVALAS; 727 goto err; 728 } 729 730 if (end < iommu->pba || start > iommu->pal) { 731 error = ERR_EVENT_OORANGE; 732 goto err; 733 } 734 735 while (start < end) { 736 error = s390_guest_io_table_walk(iommu->g_iota, start, &entry); 737 if (error) { 738 break; 739 } 740 741 start += entry.len; 742 while (entry.iova < start && entry.iova < end && 743 (dma_avail > 0 || entry.perm == IOMMU_NONE)) { 744 dma_avail = s390_pci_update_iotlb(iommu, &entry); 745 entry.iova += TARGET_PAGE_SIZE; 746 entry.translated_addr += TARGET_PAGE_SIZE; 747 } 748 } 749 err: 750 if (error) { 751 pbdev->state = ZPCI_FS_ERROR; 752 setcc(cpu, ZPCI_PCI_LS_ERR); 753 s390_set_status_code(env, r1, ZPCI_PCI_ST_FUNC_IN_ERR); 754 s390_pci_generate_error_event(error, pbdev->fh, pbdev->fid, start, 0); 755 } else { 756 pbdev->fmb.counter[ZPCI_FMB_CNT_RPCIT]++; 757 if (dma_avail > 0) { 758 setcc(cpu, ZPCI_PCI_LS_OK); 759 } else { 760 /* vfio DMA mappings are exhausted, trigger a RPCIT */ 761 setcc(cpu, ZPCI_PCI_LS_ERR); 762 s390_set_status_code(env, r1, ZPCI_RPCIT_ST_INSUFF_RES); 763 } 764 } 765 return 0; 766 } 767 768 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, 769 uint8_t ar, uintptr_t ra) 770 { 771 CPUS390XState *env = &cpu->env; 772 S390PCIBusDevice *pbdev; 773 MemoryRegion *mr; 774 MemTxResult result; 775 uint64_t offset; 776 int i; 777 uint32_t fh; 778 uint8_t pcias; 779 uint16_t len; 780 uint8_t buffer[128]; 781 782 if (env->psw.mask & PSW_MASK_PSTATE) { 783 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 784 return 0; 785 } 786 787 fh = env->regs[r1] >> 32; 788 pcias = (env->regs[r1] >> 16) & 0xf; 789 len = env->regs[r1] & 0x1fff; 790 offset = env->regs[r3]; 791 792 if (!(fh & FH_MASK_ENABLE)) { 793 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 794 return 0; 795 } 796 797 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 798 if (!pbdev) { 799 DPRINTF("pcistb no pci dev fh 0x%x\n", fh); 800 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 801 return 0; 802 } 803 804 switch (pbdev->state) { 805 case ZPCI_FS_PERMANENT_ERROR: 806 case ZPCI_FS_ERROR: 807 setcc(cpu, ZPCI_PCI_LS_ERR); 808 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED); 809 return 0; 810 default: 811 break; 812 } 813 814 if (pcias > ZPCI_IO_BAR_MAX) { 815 DPRINTF("pcistb invalid space\n"); 816 setcc(cpu, ZPCI_PCI_LS_ERR); 817 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS); 818 return 0; 819 } 820 821 /* Verify the address, offset and length */ 822 /* offset must be a multiple of 8 */ 823 if (offset % 8) { 824 goto specification_error; 825 } 826 /* Length must be greater than 8, a multiple of 8 */ 827 /* and not greater than maxstbl */ 828 if ((len <= 8) || (len % 8) || 829 (len > pbdev->pci_group->zpci_group.maxstbl)) { 830 goto specification_error; 831 } 832 /* Do not cross a 4K-byte boundary */ 833 if (((offset & 0xfff) + len) > 0x1000) { 834 goto specification_error; 835 } 836 /* Guest address must be double word aligned */ 837 if (gaddr & 0x07UL) { 838 goto specification_error; 839 } 840 841 mr = pbdev->pdev->io_regions[pcias].memory; 842 mr = s390_get_subregion(mr, offset, len); 843 offset -= mr->addr; 844 845 for (i = 0; i < len; i += 8) { 846 if (!memory_region_access_valid(mr, offset + i, 8, true, 847 MEMTXATTRS_UNSPECIFIED)) { 848 s390_program_interrupt(env, PGM_OPERAND, ra); 849 return 0; 850 } 851 } 852 853 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) { 854 s390_cpu_virt_mem_handle_exc(cpu, ra); 855 return 0; 856 } 857 858 for (i = 0; i < len / 8; i++) { 859 result = memory_region_dispatch_write(mr, offset + i * 8, 860 ldq_p(buffer + i * 8), 861 MO_64, MEMTXATTRS_UNSPECIFIED); 862 if (result != MEMTX_OK) { 863 s390_program_interrupt(env, PGM_OPERAND, ra); 864 return 0; 865 } 866 } 867 868 pbdev->fmb.counter[ZPCI_FMB_CNT_STB]++; 869 870 setcc(cpu, ZPCI_PCI_LS_OK); 871 return 0; 872 873 specification_error: 874 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 875 return 0; 876 } 877 878 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib) 879 { 880 int ret, len; 881 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data)); 882 883 pbdev->routes.adapter.adapter_id = css_get_adapter_id( 884 CSS_IO_ADAPTER_PCI, isc); 885 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t)); 886 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long); 887 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len); 888 889 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 890 if (ret) { 891 goto out; 892 } 893 894 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator); 895 if (ret) { 896 goto out; 897 } 898 899 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb); 900 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data)); 901 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv); 902 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data)); 903 pbdev->isc = isc; 904 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data)); 905 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data)); 906 907 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 908 return 0; 909 out: 910 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 911 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 912 pbdev->summary_ind = NULL; 913 pbdev->indicator = NULL; 914 return ret; 915 } 916 917 int pci_dereg_irqs(S390PCIBusDevice *pbdev) 918 { 919 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 920 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 921 922 pbdev->summary_ind = NULL; 923 pbdev->indicator = NULL; 924 pbdev->routes.adapter.summary_addr = 0; 925 pbdev->routes.adapter.summary_offset = 0; 926 pbdev->routes.adapter.ind_addr = 0; 927 pbdev->routes.adapter.ind_offset = 0; 928 pbdev->isc = 0; 929 pbdev->noi = 0; 930 pbdev->sum = 0; 931 932 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 933 return 0; 934 } 935 936 static int reg_ioat(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib, 937 uintptr_t ra) 938 { 939 S390PCIIOMMU *iommu = pbdev->iommu; 940 uint64_t pba = ldq_p(&fib.pba); 941 uint64_t pal = ldq_p(&fib.pal); 942 uint64_t g_iota = ldq_p(&fib.iota); 943 uint8_t dt = (g_iota >> 2) & 0x7; 944 uint8_t t = (g_iota >> 11) & 0x1; 945 946 pba &= ~0xfff; 947 pal |= 0xfff; 948 if (pba > pal || pba < pbdev->zpci_fn.sdma || pal > pbdev->zpci_fn.edma) { 949 s390_program_interrupt(env, PGM_OPERAND, ra); 950 return -EINVAL; 951 } 952 953 /* currently we only support designation type 1 with translation */ 954 if (!(dt == ZPCI_IOTA_RTTO && t)) { 955 error_report("unsupported ioat dt %d t %d", dt, t); 956 s390_program_interrupt(env, PGM_OPERAND, ra); 957 return -EINVAL; 958 } 959 960 iommu->pba = pba; 961 iommu->pal = pal; 962 iommu->g_iota = g_iota; 963 964 s390_pci_iommu_enable(iommu); 965 966 return 0; 967 } 968 969 void pci_dereg_ioat(S390PCIIOMMU *iommu) 970 { 971 s390_pci_iommu_disable(iommu); 972 iommu->pba = 0; 973 iommu->pal = 0; 974 iommu->g_iota = 0; 975 } 976 977 void fmb_timer_free(S390PCIBusDevice *pbdev) 978 { 979 if (pbdev->fmb_timer) { 980 timer_free(pbdev->fmb_timer); 981 pbdev->fmb_timer = NULL; 982 } 983 pbdev->fmb_addr = 0; 984 memset(&pbdev->fmb, 0, sizeof(ZpciFmb)); 985 } 986 987 static int fmb_do_update(S390PCIBusDevice *pbdev, int offset, uint64_t val, 988 int len) 989 { 990 MemTxResult ret; 991 uint64_t dst = pbdev->fmb_addr + offset; 992 993 switch (len) { 994 case 8: 995 address_space_stq_be(&address_space_memory, dst, val, 996 MEMTXATTRS_UNSPECIFIED, 997 &ret); 998 break; 999 case 4: 1000 address_space_stl_be(&address_space_memory, dst, val, 1001 MEMTXATTRS_UNSPECIFIED, 1002 &ret); 1003 break; 1004 case 2: 1005 address_space_stw_be(&address_space_memory, dst, val, 1006 MEMTXATTRS_UNSPECIFIED, 1007 &ret); 1008 break; 1009 case 1: 1010 address_space_stb(&address_space_memory, dst, val, 1011 MEMTXATTRS_UNSPECIFIED, 1012 &ret); 1013 break; 1014 default: 1015 ret = MEMTX_ERROR; 1016 break; 1017 } 1018 if (ret != MEMTX_OK) { 1019 s390_pci_generate_error_event(ERR_EVENT_FMBA, pbdev->fh, pbdev->fid, 1020 pbdev->fmb_addr, 0); 1021 fmb_timer_free(pbdev); 1022 } 1023 1024 return ret; 1025 } 1026 1027 static void fmb_update(void *opaque) 1028 { 1029 S390PCIBusDevice *pbdev = opaque; 1030 int64_t t = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); 1031 int i; 1032 1033 /* Update U bit */ 1034 pbdev->fmb.last_update *= 2; 1035 pbdev->fmb.last_update |= UPDATE_U_BIT; 1036 if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update), 1037 pbdev->fmb.last_update, 1038 sizeof(pbdev->fmb.last_update))) { 1039 return; 1040 } 1041 1042 /* Update FMB sample count */ 1043 if (fmb_do_update(pbdev, offsetof(ZpciFmb, sample), 1044 pbdev->fmb.sample++, 1045 sizeof(pbdev->fmb.sample))) { 1046 return; 1047 } 1048 1049 /* Update FMB counters */ 1050 for (i = 0; i < ZPCI_FMB_CNT_MAX; i++) { 1051 if (fmb_do_update(pbdev, offsetof(ZpciFmb, counter[i]), 1052 pbdev->fmb.counter[i], 1053 sizeof(pbdev->fmb.counter[0]))) { 1054 return; 1055 } 1056 } 1057 1058 /* Clear U bit and update the time */ 1059 pbdev->fmb.last_update = time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 1060 pbdev->fmb.last_update *= 2; 1061 if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update), 1062 pbdev->fmb.last_update, 1063 sizeof(pbdev->fmb.last_update))) { 1064 return; 1065 } 1066 timer_mod(pbdev->fmb_timer, t + pbdev->pci_group->zpci_group.mui); 1067 } 1068 1069 static int mpcifc_reg_int_interp(S390PCIBusDevice *pbdev, ZpciFib *fib) 1070 { 1071 int rc; 1072 1073 rc = s390_pci_kvm_aif_enable(pbdev, fib, pbdev->forwarding_assist); 1074 if (rc) { 1075 DPRINTF("Failed to enable interrupt forwarding\n"); 1076 return rc; 1077 } 1078 1079 return 0; 1080 } 1081 1082 static int mpcifc_dereg_int_interp(S390PCIBusDevice *pbdev, ZpciFib *fib) 1083 { 1084 int rc; 1085 1086 rc = s390_pci_kvm_aif_disable(pbdev); 1087 if (rc) { 1088 DPRINTF("Failed to disable interrupt forwarding\n"); 1089 return rc; 1090 } 1091 1092 return 0; 1093 } 1094 1095 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 1096 uintptr_t ra) 1097 { 1098 CPUS390XState *env = &cpu->env; 1099 uint8_t oc, dmaas; 1100 uint32_t fh; 1101 ZpciFib fib; 1102 S390PCIBusDevice *pbdev; 1103 uint64_t cc = ZPCI_PCI_LS_OK; 1104 1105 if (env->psw.mask & PSW_MASK_PSTATE) { 1106 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 1107 return 0; 1108 } 1109 1110 oc = env->regs[r1] & 0xff; 1111 dmaas = (env->regs[r1] >> 16) & 0xff; 1112 fh = env->regs[r1] >> 32; 1113 1114 if (fiba & 0x7) { 1115 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 1116 return 0; 1117 } 1118 1119 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 1120 if (!pbdev) { 1121 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh); 1122 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1123 return 0; 1124 } 1125 1126 switch (pbdev->state) { 1127 case ZPCI_FS_RESERVED: 1128 case ZPCI_FS_STANDBY: 1129 case ZPCI_FS_DISABLED: 1130 case ZPCI_FS_PERMANENT_ERROR: 1131 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1132 return 0; 1133 default: 1134 break; 1135 } 1136 1137 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 1138 s390_cpu_virt_mem_handle_exc(cpu, ra); 1139 return 0; 1140 } 1141 1142 if (fib.fmt != 0) { 1143 s390_program_interrupt(env, PGM_OPERAND, ra); 1144 return 0; 1145 } 1146 1147 switch (oc) { 1148 case ZPCI_MOD_FC_REG_INT: 1149 if (pbdev->interp) { 1150 if (mpcifc_reg_int_interp(pbdev, &fib)) { 1151 cc = ZPCI_PCI_LS_ERR; 1152 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1153 } 1154 } else if (pbdev->summary_ind) { 1155 cc = ZPCI_PCI_LS_ERR; 1156 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1157 } else if (reg_irqs(env, pbdev, fib)) { 1158 cc = ZPCI_PCI_LS_ERR; 1159 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL); 1160 } 1161 break; 1162 case ZPCI_MOD_FC_DEREG_INT: 1163 if (pbdev->interp) { 1164 if (mpcifc_dereg_int_interp(pbdev, &fib)) { 1165 cc = ZPCI_PCI_LS_ERR; 1166 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1167 } 1168 } else if (!pbdev->summary_ind) { 1169 cc = ZPCI_PCI_LS_ERR; 1170 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1171 } else { 1172 pci_dereg_irqs(pbdev); 1173 } 1174 break; 1175 case ZPCI_MOD_FC_REG_IOAT: 1176 if (dmaas != 0) { 1177 cc = ZPCI_PCI_LS_ERR; 1178 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 1179 } else if (pbdev->iommu->enabled) { 1180 cc = ZPCI_PCI_LS_ERR; 1181 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1182 } else if (reg_ioat(env, pbdev, fib, ra)) { 1183 cc = ZPCI_PCI_LS_ERR; 1184 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 1185 } 1186 break; 1187 case ZPCI_MOD_FC_DEREG_IOAT: 1188 if (dmaas != 0) { 1189 cc = ZPCI_PCI_LS_ERR; 1190 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 1191 } else if (!pbdev->iommu->enabled) { 1192 cc = ZPCI_PCI_LS_ERR; 1193 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1194 } else { 1195 pci_dereg_ioat(pbdev->iommu); 1196 } 1197 break; 1198 case ZPCI_MOD_FC_REREG_IOAT: 1199 if (dmaas != 0) { 1200 cc = ZPCI_PCI_LS_ERR; 1201 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 1202 } else if (!pbdev->iommu->enabled) { 1203 cc = ZPCI_PCI_LS_ERR; 1204 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1205 } else { 1206 pci_dereg_ioat(pbdev->iommu); 1207 if (reg_ioat(env, pbdev, fib, ra)) { 1208 cc = ZPCI_PCI_LS_ERR; 1209 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 1210 } 1211 } 1212 break; 1213 case ZPCI_MOD_FC_RESET_ERROR: 1214 switch (pbdev->state) { 1215 case ZPCI_FS_BLOCKED: 1216 case ZPCI_FS_ERROR: 1217 pbdev->state = ZPCI_FS_ENABLED; 1218 break; 1219 default: 1220 cc = ZPCI_PCI_LS_ERR; 1221 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1222 } 1223 break; 1224 case ZPCI_MOD_FC_RESET_BLOCK: 1225 switch (pbdev->state) { 1226 case ZPCI_FS_ERROR: 1227 pbdev->state = ZPCI_FS_BLOCKED; 1228 break; 1229 default: 1230 cc = ZPCI_PCI_LS_ERR; 1231 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1232 } 1233 break; 1234 case ZPCI_MOD_FC_SET_MEASURE: { 1235 uint64_t fmb_addr = ldq_p(&fib.fmb_addr); 1236 1237 if (fmb_addr & FMBK_MASK) { 1238 cc = ZPCI_PCI_LS_ERR; 1239 s390_pci_generate_error_event(ERR_EVENT_FMBPRO, pbdev->fh, 1240 pbdev->fid, fmb_addr, 0); 1241 fmb_timer_free(pbdev); 1242 break; 1243 } 1244 1245 if (!fmb_addr) { 1246 /* Stop updating FMB. */ 1247 fmb_timer_free(pbdev); 1248 break; 1249 } 1250 1251 if (!pbdev->fmb_timer) { 1252 pbdev->fmb_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 1253 fmb_update, pbdev); 1254 } else if (timer_pending(pbdev->fmb_timer)) { 1255 /* Remove pending timer to update FMB address. */ 1256 timer_del(pbdev->fmb_timer); 1257 } 1258 pbdev->fmb_addr = fmb_addr; 1259 timer_mod(pbdev->fmb_timer, 1260 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1261 pbdev->pci_group->zpci_group.mui); 1262 break; 1263 } 1264 default: 1265 s390_program_interrupt(&cpu->env, PGM_OPERAND, ra); 1266 cc = ZPCI_PCI_LS_ERR; 1267 } 1268 1269 setcc(cpu, cc); 1270 return 0; 1271 } 1272 1273 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 1274 uintptr_t ra) 1275 { 1276 CPUS390XState *env = &cpu->env; 1277 uint8_t dmaas; 1278 uint32_t fh; 1279 ZpciFib fib; 1280 S390PCIBusDevice *pbdev; 1281 uint32_t data; 1282 uint64_t cc = ZPCI_PCI_LS_OK; 1283 1284 if (env->psw.mask & PSW_MASK_PSTATE) { 1285 s390_program_interrupt(env, PGM_PRIVILEGED, ra); 1286 return 0; 1287 } 1288 1289 fh = env->regs[r1] >> 32; 1290 dmaas = (env->regs[r1] >> 16) & 0xff; 1291 1292 if (dmaas) { 1293 setcc(cpu, ZPCI_PCI_LS_ERR); 1294 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS); 1295 return 0; 1296 } 1297 1298 if (fiba & 0x7) { 1299 s390_program_interrupt(env, PGM_SPECIFICATION, ra); 1300 return 0; 1301 } 1302 1303 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX); 1304 if (!pbdev) { 1305 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1306 return 0; 1307 } 1308 1309 memset(&fib, 0, sizeof(fib)); 1310 1311 switch (pbdev->state) { 1312 case ZPCI_FS_RESERVED: 1313 case ZPCI_FS_STANDBY: 1314 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1315 return 0; 1316 case ZPCI_FS_DISABLED: 1317 if (fh & FH_MASK_ENABLE) { 1318 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1319 return 0; 1320 } 1321 goto out; 1322 /* BLOCKED bit is set to one coincident with the setting of ERROR bit. 1323 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */ 1324 case ZPCI_FS_ERROR: 1325 fib.fc |= 0x20; 1326 /* fallthrough */ 1327 case ZPCI_FS_BLOCKED: 1328 fib.fc |= 0x40; 1329 /* fallthrough */ 1330 case ZPCI_FS_ENABLED: 1331 fib.fc |= 0x80; 1332 if (pbdev->iommu->enabled) { 1333 fib.fc |= 0x10; 1334 } 1335 if (!(fh & FH_MASK_ENABLE)) { 1336 env->regs[r1] |= 1ULL << 63; 1337 } 1338 break; 1339 case ZPCI_FS_PERMANENT_ERROR: 1340 setcc(cpu, ZPCI_PCI_LS_ERR); 1341 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR); 1342 return 0; 1343 } 1344 1345 stq_p(&fib.pba, pbdev->iommu->pba); 1346 stq_p(&fib.pal, pbdev->iommu->pal); 1347 stq_p(&fib.iota, pbdev->iommu->g_iota); 1348 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr); 1349 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr); 1350 stq_p(&fib.fmb_addr, pbdev->fmb_addr); 1351 1352 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) | 1353 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) | 1354 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset; 1355 stl_p(&fib.data, data); 1356 1357 out: 1358 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 1359 s390_cpu_virt_mem_handle_exc(cpu, ra); 1360 return 0; 1361 } 1362 1363 setcc(cpu, cc); 1364 return 0; 1365 } 1366