1 /* 2 * s390 PCI instructions 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu-common.h" 16 #include "cpu.h" 17 #include "s390-pci-inst.h" 18 #include "s390-pci-bus.h" 19 #include "exec/memory-internal.h" 20 #include "qemu/error-report.h" 21 #include "sysemu/hw_accel.h" 22 23 #ifndef DEBUG_S390PCI_INST 24 #define DEBUG_S390PCI_INST 0 25 #endif 26 27 #define DPRINTF(fmt, ...) \ 28 do { \ 29 if (DEBUG_S390PCI_INST) { \ 30 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \ 31 } \ 32 } while (0) 33 34 static void s390_set_status_code(CPUS390XState *env, 35 uint8_t r, uint64_t status_code) 36 { 37 env->regs[r] &= ~0xff000000ULL; 38 env->regs[r] |= (status_code & 0xff) << 24; 39 } 40 41 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) 42 { 43 S390PCIBusDevice *pbdev = NULL; 44 S390pciState *s = s390_get_phb(); 45 uint32_t res_code, initial_l2, g_l2; 46 int rc, i; 47 uint64_t resume_token; 48 49 rc = 0; 50 if (lduw_p(&rrb->request.hdr.len) != 32) { 51 res_code = CLP_RC_LEN; 52 rc = -EINVAL; 53 goto out; 54 } 55 56 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) { 57 res_code = CLP_RC_FMT; 58 rc = -EINVAL; 59 goto out; 60 } 61 62 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 || 63 ldq_p(&rrb->request.reserved1) != 0) { 64 res_code = CLP_RC_RESNOT0; 65 rc = -EINVAL; 66 goto out; 67 } 68 69 resume_token = ldq_p(&rrb->request.resume_token); 70 71 if (resume_token) { 72 pbdev = s390_pci_find_dev_by_idx(s, resume_token); 73 if (!pbdev) { 74 res_code = CLP_RC_LISTPCI_BADRT; 75 rc = -EINVAL; 76 goto out; 77 } 78 } else { 79 pbdev = s390_pci_find_next_avail_dev(s, NULL); 80 } 81 82 if (lduw_p(&rrb->response.hdr.len) < 48) { 83 res_code = CLP_RC_8K; 84 rc = -EINVAL; 85 goto out; 86 } 87 88 initial_l2 = lduw_p(&rrb->response.hdr.len); 89 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry) 90 != 0) { 91 res_code = CLP_RC_LEN; 92 rc = -EINVAL; 93 *cc = 3; 94 goto out; 95 } 96 97 stl_p(&rrb->response.fmt, 0); 98 stq_p(&rrb->response.reserved1, 0); 99 stl_p(&rrb->response.mdd, FH_MASK_SHM); 100 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS); 101 rrb->response.flags = UID_CHECKING_ENABLED; 102 rrb->response.entry_size = sizeof(ClpFhListEntry); 103 104 i = 0; 105 g_l2 = LIST_PCI_HDR_LEN; 106 while (g_l2 < initial_l2 && pbdev) { 107 stw_p(&rrb->response.fh_list[i].device_id, 108 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID)); 109 stw_p(&rrb->response.fh_list[i].vendor_id, 110 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID)); 111 /* Ignore RESERVED devices. */ 112 stl_p(&rrb->response.fh_list[i].config, 113 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31); 114 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid); 115 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh); 116 117 g_l2 += sizeof(ClpFhListEntry); 118 /* Add endian check for DPRINTF? */ 119 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n", 120 g_l2, 121 lduw_p(&rrb->response.fh_list[i].vendor_id), 122 lduw_p(&rrb->response.fh_list[i].device_id), 123 ldl_p(&rrb->response.fh_list[i].fid), 124 ldl_p(&rrb->response.fh_list[i].fh)); 125 pbdev = s390_pci_find_next_avail_dev(s, pbdev); 126 i++; 127 } 128 129 if (!pbdev) { 130 resume_token = 0; 131 } else { 132 resume_token = pbdev->fh & FH_MASK_INDEX; 133 } 134 stq_p(&rrb->response.resume_token, resume_token); 135 stw_p(&rrb->response.hdr.len, g_l2); 136 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK); 137 out: 138 if (rc) { 139 DPRINTF("list pci failed rc 0x%x\n", rc); 140 stw_p(&rrb->response.hdr.rsp, res_code); 141 } 142 return rc; 143 } 144 145 int clp_service_call(S390CPU *cpu, uint8_t r2) 146 { 147 ClpReqHdr *reqh; 148 ClpRspHdr *resh; 149 S390PCIBusDevice *pbdev; 150 uint32_t req_len; 151 uint32_t res_len; 152 uint8_t buffer[4096 * 2]; 153 uint8_t cc = 0; 154 CPUS390XState *env = &cpu->env; 155 S390pciState *s = s390_get_phb(); 156 int i; 157 158 cpu_synchronize_state(CPU(cpu)); 159 160 if (env->psw.mask & PSW_MASK_PSTATE) { 161 program_interrupt(env, PGM_PRIVILEGED, 4); 162 return 0; 163 } 164 165 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) { 166 return 0; 167 } 168 reqh = (ClpReqHdr *)buffer; 169 req_len = lduw_p(&reqh->len); 170 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) { 171 program_interrupt(env, PGM_OPERAND, 4); 172 return 0; 173 } 174 175 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 176 req_len + sizeof(*resh))) { 177 return 0; 178 } 179 resh = (ClpRspHdr *)(buffer + req_len); 180 res_len = lduw_p(&resh->len); 181 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) { 182 program_interrupt(env, PGM_OPERAND, 4); 183 return 0; 184 } 185 if ((req_len + res_len) > 8192) { 186 program_interrupt(env, PGM_OPERAND, 4); 187 return 0; 188 } 189 190 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 191 req_len + res_len)) { 192 return 0; 193 } 194 195 if (req_len != 32) { 196 stw_p(&resh->rsp, CLP_RC_LEN); 197 goto out; 198 } 199 200 switch (lduw_p(&reqh->cmd)) { 201 case CLP_LIST_PCI: { 202 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer; 203 list_pci(rrb, &cc); 204 break; 205 } 206 case CLP_SET_PCI_FN: { 207 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh; 208 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh; 209 210 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh)); 211 if (!pbdev) { 212 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); 213 goto out; 214 } 215 216 switch (reqsetpci->oc) { 217 case CLP_SET_ENABLE_PCI_FN: 218 switch (reqsetpci->ndas) { 219 case 0: 220 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS); 221 goto out; 222 case 1: 223 break; 224 default: 225 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES); 226 goto out; 227 } 228 229 if (pbdev->fh & FH_MASK_ENABLE) { 230 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 231 goto out; 232 } 233 234 pbdev->fh |= FH_MASK_ENABLE; 235 pbdev->state = ZPCI_FS_ENABLED; 236 stl_p(&ressetpci->fh, pbdev->fh); 237 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 238 break; 239 case CLP_SET_DISABLE_PCI_FN: 240 if (!(pbdev->fh & FH_MASK_ENABLE)) { 241 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 242 goto out; 243 } 244 device_reset(DEVICE(pbdev)); 245 pbdev->fh &= ~FH_MASK_ENABLE; 246 pbdev->state = ZPCI_FS_DISABLED; 247 stl_p(&ressetpci->fh, pbdev->fh); 248 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 249 break; 250 default: 251 DPRINTF("unknown set pci command\n"); 252 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 253 break; 254 } 255 break; 256 } 257 case CLP_QUERY_PCI_FN: { 258 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh; 259 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh; 260 261 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh)); 262 if (!pbdev) { 263 DPRINTF("query pci no pci dev\n"); 264 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH); 265 goto out; 266 } 267 268 for (i = 0; i < PCI_BAR_COUNT; i++) { 269 uint32_t data = pci_get_long(pbdev->pdev->config + 270 PCI_BASE_ADDRESS_0 + (i * 4)); 271 272 stl_p(&resquery->bar[i], data); 273 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ? 274 ctz64(pbdev->pdev->io_regions[i].size) : 0; 275 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i, 276 ldl_p(&resquery->bar[i]), 277 pbdev->pdev->io_regions[i].size, 278 resquery->bar_size[i]); 279 } 280 281 stq_p(&resquery->sdma, ZPCI_SDMA_ADDR); 282 stq_p(&resquery->edma, ZPCI_EDMA_ADDR); 283 stl_p(&resquery->fid, pbdev->fid); 284 stw_p(&resquery->pchid, 0); 285 stw_p(&resquery->ug, 1); 286 stl_p(&resquery->uid, pbdev->uid); 287 stw_p(&resquery->hdr.rsp, CLP_RC_OK); 288 break; 289 } 290 case CLP_QUERY_PCI_FNGRP: { 291 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh; 292 resgrp->fr = 1; 293 stq_p(&resgrp->dasm, 0); 294 stq_p(&resgrp->msia, ZPCI_MSI_ADDR); 295 stw_p(&resgrp->mui, 0); 296 stw_p(&resgrp->i, 128); 297 resgrp->version = 0; 298 299 stw_p(&resgrp->hdr.rsp, CLP_RC_OK); 300 break; 301 } 302 default: 303 DPRINTF("unknown clp command\n"); 304 stw_p(&resh->rsp, CLP_RC_CMD); 305 break; 306 } 307 308 out: 309 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer, 310 req_len + res_len)) { 311 return 0; 312 } 313 setcc(cpu, cc); 314 return 0; 315 } 316 317 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2) 318 { 319 CPUS390XState *env = &cpu->env; 320 S390PCIBusDevice *pbdev; 321 uint64_t offset; 322 uint64_t data; 323 MemoryRegion *mr; 324 MemTxResult result; 325 uint8_t len; 326 uint32_t fh; 327 uint8_t pcias; 328 329 cpu_synchronize_state(CPU(cpu)); 330 331 if (env->psw.mask & PSW_MASK_PSTATE) { 332 program_interrupt(env, PGM_PRIVILEGED, 4); 333 return 0; 334 } 335 336 if (r2 & 0x1) { 337 program_interrupt(env, PGM_SPECIFICATION, 4); 338 return 0; 339 } 340 341 fh = env->regs[r2] >> 32; 342 pcias = (env->regs[r2] >> 16) & 0xf; 343 len = env->regs[r2] & 0xf; 344 offset = env->regs[r2 + 1]; 345 346 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 347 if (!pbdev) { 348 DPRINTF("pcilg no pci dev\n"); 349 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 350 return 0; 351 } 352 353 switch (pbdev->state) { 354 case ZPCI_FS_RESERVED: 355 case ZPCI_FS_STANDBY: 356 case ZPCI_FS_DISABLED: 357 case ZPCI_FS_PERMANENT_ERROR: 358 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 359 return 0; 360 case ZPCI_FS_ERROR: 361 setcc(cpu, ZPCI_PCI_LS_ERR); 362 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 363 return 0; 364 default: 365 break; 366 } 367 368 if (pcias < 6) { 369 if ((8 - (offset & 0x7)) < len) { 370 program_interrupt(env, PGM_OPERAND, 4); 371 return 0; 372 } 373 mr = pbdev->pdev->io_regions[pcias].memory; 374 result = memory_region_dispatch_read(mr, offset, &data, len, 375 MEMTXATTRS_UNSPECIFIED); 376 if (result != MEMTX_OK) { 377 program_interrupt(env, PGM_OPERAND, 4); 378 return 0; 379 } 380 } else if (pcias == 15) { 381 if ((4 - (offset & 0x3)) < len) { 382 program_interrupt(env, PGM_OPERAND, 4); 383 return 0; 384 } 385 data = pci_host_config_read_common( 386 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len); 387 388 switch (len) { 389 case 1: 390 break; 391 case 2: 392 data = bswap16(data); 393 break; 394 case 4: 395 data = bswap32(data); 396 break; 397 case 8: 398 data = bswap64(data); 399 break; 400 default: 401 program_interrupt(env, PGM_OPERAND, 4); 402 return 0; 403 } 404 } else { 405 DPRINTF("invalid space\n"); 406 setcc(cpu, ZPCI_PCI_LS_ERR); 407 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 408 return 0; 409 } 410 411 env->regs[r1] = data; 412 setcc(cpu, ZPCI_PCI_LS_OK); 413 return 0; 414 } 415 416 static void update_msix_table_msg_data(S390PCIBusDevice *pbdev, uint64_t offset, 417 uint64_t *data, uint8_t len) 418 { 419 uint32_t val; 420 uint8_t *msg_data; 421 422 if (offset % PCI_MSIX_ENTRY_SIZE != 8) { 423 return; 424 } 425 426 if (len != 4) { 427 DPRINTF("access msix table msg data but len is %d\n", len); 428 return; 429 } 430 431 msg_data = (uint8_t *)data - offset % PCI_MSIX_ENTRY_SIZE + 432 PCI_MSIX_ENTRY_VECTOR_CTRL; 433 val = pci_get_long(msg_data) | 434 ((pbdev->fh & FH_MASK_INDEX) << ZPCI_MSI_VEC_BITS); 435 pci_set_long(msg_data, val); 436 DPRINTF("update msix msg_data to 0x%" PRIx64 "\n", *data); 437 } 438 439 static int trap_msix(S390PCIBusDevice *pbdev, uint64_t offset, uint8_t pcias) 440 { 441 if (pbdev->msix.available && pbdev->msix.table_bar == pcias && 442 offset >= pbdev->msix.table_offset && 443 offset <= pbdev->msix.table_offset + 444 (pbdev->msix.entries - 1) * PCI_MSIX_ENTRY_SIZE) { 445 return 1; 446 } else { 447 return 0; 448 } 449 } 450 451 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2) 452 { 453 CPUS390XState *env = &cpu->env; 454 uint64_t offset, data; 455 S390PCIBusDevice *pbdev; 456 MemoryRegion *mr; 457 MemTxResult result; 458 uint8_t len; 459 uint32_t fh; 460 uint8_t pcias; 461 462 cpu_synchronize_state(CPU(cpu)); 463 464 if (env->psw.mask & PSW_MASK_PSTATE) { 465 program_interrupt(env, PGM_PRIVILEGED, 4); 466 return 0; 467 } 468 469 if (r2 & 0x1) { 470 program_interrupt(env, PGM_SPECIFICATION, 4); 471 return 0; 472 } 473 474 fh = env->regs[r2] >> 32; 475 pcias = (env->regs[r2] >> 16) & 0xf; 476 len = env->regs[r2] & 0xf; 477 offset = env->regs[r2 + 1]; 478 479 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 480 if (!pbdev) { 481 DPRINTF("pcistg no pci dev\n"); 482 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 483 return 0; 484 } 485 486 switch (pbdev->state) { 487 case ZPCI_FS_RESERVED: 488 case ZPCI_FS_STANDBY: 489 case ZPCI_FS_DISABLED: 490 case ZPCI_FS_PERMANENT_ERROR: 491 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 492 return 0; 493 case ZPCI_FS_ERROR: 494 setcc(cpu, ZPCI_PCI_LS_ERR); 495 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 496 return 0; 497 default: 498 break; 499 } 500 501 data = env->regs[r1]; 502 if (pcias < 6) { 503 if ((8 - (offset & 0x7)) < len) { 504 program_interrupt(env, PGM_OPERAND, 4); 505 return 0; 506 } 507 508 if (trap_msix(pbdev, offset, pcias)) { 509 offset = offset - pbdev->msix.table_offset; 510 mr = &pbdev->pdev->msix_table_mmio; 511 update_msix_table_msg_data(pbdev, offset, &data, len); 512 } else { 513 mr = pbdev->pdev->io_regions[pcias].memory; 514 } 515 516 result = memory_region_dispatch_write(mr, offset, data, len, 517 MEMTXATTRS_UNSPECIFIED); 518 if (result != MEMTX_OK) { 519 program_interrupt(env, PGM_OPERAND, 4); 520 return 0; 521 } 522 } else if (pcias == 15) { 523 if ((4 - (offset & 0x3)) < len) { 524 program_interrupt(env, PGM_OPERAND, 4); 525 return 0; 526 } 527 switch (len) { 528 case 1: 529 break; 530 case 2: 531 data = bswap16(data); 532 break; 533 case 4: 534 data = bswap32(data); 535 break; 536 case 8: 537 data = bswap64(data); 538 break; 539 default: 540 program_interrupt(env, PGM_OPERAND, 4); 541 return 0; 542 } 543 544 pci_host_config_write_common(pbdev->pdev, offset, 545 pci_config_size(pbdev->pdev), 546 data, len); 547 } else { 548 DPRINTF("pcistg invalid space\n"); 549 setcc(cpu, ZPCI_PCI_LS_ERR); 550 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 551 return 0; 552 } 553 554 setcc(cpu, ZPCI_PCI_LS_OK); 555 return 0; 556 } 557 558 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2) 559 { 560 CPUS390XState *env = &cpu->env; 561 uint32_t fh; 562 S390PCIBusDevice *pbdev; 563 S390PCIIOMMU *iommu; 564 hwaddr start, end; 565 IOMMUTLBEntry entry; 566 MemoryRegion *mr; 567 568 cpu_synchronize_state(CPU(cpu)); 569 570 if (env->psw.mask & PSW_MASK_PSTATE) { 571 program_interrupt(env, PGM_PRIVILEGED, 4); 572 goto out; 573 } 574 575 if (r2 & 0x1) { 576 program_interrupt(env, PGM_SPECIFICATION, 4); 577 goto out; 578 } 579 580 fh = env->regs[r1] >> 32; 581 start = env->regs[r2]; 582 end = start + env->regs[r2 + 1]; 583 584 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 585 if (!pbdev) { 586 DPRINTF("rpcit no pci dev\n"); 587 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 588 goto out; 589 } 590 591 switch (pbdev->state) { 592 case ZPCI_FS_RESERVED: 593 case ZPCI_FS_STANDBY: 594 case ZPCI_FS_DISABLED: 595 case ZPCI_FS_PERMANENT_ERROR: 596 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 597 return 0; 598 case ZPCI_FS_ERROR: 599 setcc(cpu, ZPCI_PCI_LS_ERR); 600 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER); 601 return 0; 602 default: 603 break; 604 } 605 606 iommu = pbdev->iommu; 607 if (!iommu->g_iota) { 608 pbdev->state = ZPCI_FS_ERROR; 609 setcc(cpu, ZPCI_PCI_LS_ERR); 610 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 611 s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid, 612 start, 0); 613 goto out; 614 } 615 616 if (end < iommu->pba || start > iommu->pal) { 617 pbdev->state = ZPCI_FS_ERROR; 618 setcc(cpu, ZPCI_PCI_LS_ERR); 619 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 620 s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid, 621 start, 0); 622 goto out; 623 } 624 625 mr = &iommu->iommu_mr; 626 while (start < end) { 627 entry = mr->iommu_ops->translate(mr, start, 0); 628 629 if (!entry.translated_addr) { 630 pbdev->state = ZPCI_FS_ERROR; 631 setcc(cpu, ZPCI_PCI_LS_ERR); 632 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 633 s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid, 634 start, ERR_EVENT_Q_BIT); 635 goto out; 636 } 637 638 memory_region_notify_iommu(mr, entry); 639 start += entry.addr_mask + 1; 640 } 641 642 setcc(cpu, ZPCI_PCI_LS_OK); 643 out: 644 return 0; 645 } 646 647 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, 648 uint8_t ar) 649 { 650 CPUS390XState *env = &cpu->env; 651 S390PCIBusDevice *pbdev; 652 MemoryRegion *mr; 653 MemTxResult result; 654 int i; 655 uint32_t fh; 656 uint8_t pcias; 657 uint8_t len; 658 uint8_t buffer[128]; 659 660 if (env->psw.mask & PSW_MASK_PSTATE) { 661 program_interrupt(env, PGM_PRIVILEGED, 6); 662 return 0; 663 } 664 665 fh = env->regs[r1] >> 32; 666 pcias = (env->regs[r1] >> 16) & 0xf; 667 len = env->regs[r1] & 0xff; 668 669 if (pcias > 5) { 670 DPRINTF("pcistb invalid space\n"); 671 setcc(cpu, ZPCI_PCI_LS_ERR); 672 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS); 673 return 0; 674 } 675 676 switch (len) { 677 case 16: 678 case 32: 679 case 64: 680 case 128: 681 break; 682 default: 683 program_interrupt(env, PGM_SPECIFICATION, 6); 684 return 0; 685 } 686 687 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 688 if (!pbdev) { 689 DPRINTF("pcistb no pci dev fh 0x%x\n", fh); 690 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 691 return 0; 692 } 693 694 switch (pbdev->state) { 695 case ZPCI_FS_RESERVED: 696 case ZPCI_FS_STANDBY: 697 case ZPCI_FS_DISABLED: 698 case ZPCI_FS_PERMANENT_ERROR: 699 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 700 return 0; 701 case ZPCI_FS_ERROR: 702 setcc(cpu, ZPCI_PCI_LS_ERR); 703 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED); 704 return 0; 705 default: 706 break; 707 } 708 709 mr = pbdev->pdev->io_regions[pcias].memory; 710 if (!memory_region_access_valid(mr, env->regs[r3], len, true)) { 711 program_interrupt(env, PGM_OPERAND, 6); 712 return 0; 713 } 714 715 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) { 716 return 0; 717 } 718 719 for (i = 0; i < len / 8; i++) { 720 result = memory_region_dispatch_write(mr, env->regs[r3] + i * 8, 721 ldq_p(buffer + i * 8), 8, 722 MEMTXATTRS_UNSPECIFIED); 723 if (result != MEMTX_OK) { 724 program_interrupt(env, PGM_OPERAND, 6); 725 return 0; 726 } 727 } 728 729 setcc(cpu, ZPCI_PCI_LS_OK); 730 return 0; 731 } 732 733 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib) 734 { 735 int ret, len; 736 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data)); 737 738 pbdev->routes.adapter.adapter_id = css_get_adapter_id( 739 CSS_IO_ADAPTER_PCI, isc); 740 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t)); 741 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long); 742 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len); 743 744 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 745 if (ret) { 746 goto out; 747 } 748 749 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator); 750 if (ret) { 751 goto out; 752 } 753 754 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb); 755 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data)); 756 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv); 757 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data)); 758 pbdev->isc = isc; 759 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data)); 760 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data)); 761 762 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 763 return 0; 764 out: 765 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 766 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 767 pbdev->summary_ind = NULL; 768 pbdev->indicator = NULL; 769 return ret; 770 } 771 772 int pci_dereg_irqs(S390PCIBusDevice *pbdev) 773 { 774 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 775 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 776 777 pbdev->summary_ind = NULL; 778 pbdev->indicator = NULL; 779 pbdev->routes.adapter.summary_addr = 0; 780 pbdev->routes.adapter.summary_offset = 0; 781 pbdev->routes.adapter.ind_addr = 0; 782 pbdev->routes.adapter.ind_offset = 0; 783 pbdev->isc = 0; 784 pbdev->noi = 0; 785 pbdev->sum = 0; 786 787 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 788 return 0; 789 } 790 791 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib) 792 { 793 uint64_t pba = ldq_p(&fib.pba); 794 uint64_t pal = ldq_p(&fib.pal); 795 uint64_t g_iota = ldq_p(&fib.iota); 796 uint8_t dt = (g_iota >> 2) & 0x7; 797 uint8_t t = (g_iota >> 11) & 0x1; 798 799 if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) { 800 program_interrupt(env, PGM_OPERAND, 6); 801 return -EINVAL; 802 } 803 804 /* currently we only support designation type 1 with translation */ 805 if (!(dt == ZPCI_IOTA_RTTO && t)) { 806 error_report("unsupported ioat dt %d t %d", dt, t); 807 program_interrupt(env, PGM_OPERAND, 6); 808 return -EINVAL; 809 } 810 811 iommu->pba = pba; 812 iommu->pal = pal; 813 iommu->g_iota = g_iota; 814 815 s390_pci_iommu_enable(iommu); 816 817 return 0; 818 } 819 820 void pci_dereg_ioat(S390PCIIOMMU *iommu) 821 { 822 s390_pci_iommu_disable(iommu); 823 iommu->pba = 0; 824 iommu->pal = 0; 825 iommu->g_iota = 0; 826 } 827 828 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar) 829 { 830 CPUS390XState *env = &cpu->env; 831 uint8_t oc, dmaas; 832 uint32_t fh; 833 ZpciFib fib; 834 S390PCIBusDevice *pbdev; 835 uint64_t cc = ZPCI_PCI_LS_OK; 836 837 if (env->psw.mask & PSW_MASK_PSTATE) { 838 program_interrupt(env, PGM_PRIVILEGED, 6); 839 return 0; 840 } 841 842 oc = env->regs[r1] & 0xff; 843 dmaas = (env->regs[r1] >> 16) & 0xff; 844 fh = env->regs[r1] >> 32; 845 846 if (fiba & 0x7) { 847 program_interrupt(env, PGM_SPECIFICATION, 6); 848 return 0; 849 } 850 851 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 852 if (!pbdev) { 853 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh); 854 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 855 return 0; 856 } 857 858 switch (pbdev->state) { 859 case ZPCI_FS_RESERVED: 860 case ZPCI_FS_STANDBY: 861 case ZPCI_FS_DISABLED: 862 case ZPCI_FS_PERMANENT_ERROR: 863 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 864 return 0; 865 default: 866 break; 867 } 868 869 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 870 return 0; 871 } 872 873 if (fib.fmt != 0) { 874 program_interrupt(env, PGM_OPERAND, 6); 875 return 0; 876 } 877 878 switch (oc) { 879 case ZPCI_MOD_FC_REG_INT: 880 if (pbdev->summary_ind) { 881 cc = ZPCI_PCI_LS_ERR; 882 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 883 } else if (reg_irqs(env, pbdev, fib)) { 884 cc = ZPCI_PCI_LS_ERR; 885 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL); 886 } 887 break; 888 case ZPCI_MOD_FC_DEREG_INT: 889 if (!pbdev->summary_ind) { 890 cc = ZPCI_PCI_LS_ERR; 891 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 892 } else { 893 pci_dereg_irqs(pbdev); 894 } 895 break; 896 case ZPCI_MOD_FC_REG_IOAT: 897 if (dmaas != 0) { 898 cc = ZPCI_PCI_LS_ERR; 899 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 900 } else if (pbdev->iommu->enabled) { 901 cc = ZPCI_PCI_LS_ERR; 902 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 903 } else if (reg_ioat(env, pbdev->iommu, fib)) { 904 cc = ZPCI_PCI_LS_ERR; 905 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 906 } 907 break; 908 case ZPCI_MOD_FC_DEREG_IOAT: 909 if (dmaas != 0) { 910 cc = ZPCI_PCI_LS_ERR; 911 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 912 } else if (!pbdev->iommu->enabled) { 913 cc = ZPCI_PCI_LS_ERR; 914 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 915 } else { 916 pci_dereg_ioat(pbdev->iommu); 917 } 918 break; 919 case ZPCI_MOD_FC_REREG_IOAT: 920 if (dmaas != 0) { 921 cc = ZPCI_PCI_LS_ERR; 922 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 923 } else if (!pbdev->iommu->enabled) { 924 cc = ZPCI_PCI_LS_ERR; 925 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 926 } else { 927 pci_dereg_ioat(pbdev->iommu); 928 if (reg_ioat(env, pbdev->iommu, fib)) { 929 cc = ZPCI_PCI_LS_ERR; 930 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 931 } 932 } 933 break; 934 case ZPCI_MOD_FC_RESET_ERROR: 935 switch (pbdev->state) { 936 case ZPCI_FS_BLOCKED: 937 case ZPCI_FS_ERROR: 938 pbdev->state = ZPCI_FS_ENABLED; 939 break; 940 default: 941 cc = ZPCI_PCI_LS_ERR; 942 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 943 } 944 break; 945 case ZPCI_MOD_FC_RESET_BLOCK: 946 switch (pbdev->state) { 947 case ZPCI_FS_ERROR: 948 pbdev->state = ZPCI_FS_BLOCKED; 949 break; 950 default: 951 cc = ZPCI_PCI_LS_ERR; 952 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 953 } 954 break; 955 case ZPCI_MOD_FC_SET_MEASURE: 956 pbdev->fmb_addr = ldq_p(&fib.fmb_addr); 957 break; 958 default: 959 program_interrupt(&cpu->env, PGM_OPERAND, 6); 960 cc = ZPCI_PCI_LS_ERR; 961 } 962 963 setcc(cpu, cc); 964 return 0; 965 } 966 967 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar) 968 { 969 CPUS390XState *env = &cpu->env; 970 uint8_t dmaas; 971 uint32_t fh; 972 ZpciFib fib; 973 S390PCIBusDevice *pbdev; 974 uint32_t data; 975 uint64_t cc = ZPCI_PCI_LS_OK; 976 977 if (env->psw.mask & PSW_MASK_PSTATE) { 978 program_interrupt(env, PGM_PRIVILEGED, 6); 979 return 0; 980 } 981 982 fh = env->regs[r1] >> 32; 983 dmaas = (env->regs[r1] >> 16) & 0xff; 984 985 if (dmaas) { 986 setcc(cpu, ZPCI_PCI_LS_ERR); 987 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS); 988 return 0; 989 } 990 991 if (fiba & 0x7) { 992 program_interrupt(env, PGM_SPECIFICATION, 6); 993 return 0; 994 } 995 996 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX); 997 if (!pbdev) { 998 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 999 return 0; 1000 } 1001 1002 memset(&fib, 0, sizeof(fib)); 1003 1004 switch (pbdev->state) { 1005 case ZPCI_FS_RESERVED: 1006 case ZPCI_FS_STANDBY: 1007 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1008 return 0; 1009 case ZPCI_FS_DISABLED: 1010 if (fh & FH_MASK_ENABLE) { 1011 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1012 return 0; 1013 } 1014 goto out; 1015 /* BLOCKED bit is set to one coincident with the setting of ERROR bit. 1016 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */ 1017 case ZPCI_FS_ERROR: 1018 fib.fc |= 0x20; 1019 case ZPCI_FS_BLOCKED: 1020 fib.fc |= 0x40; 1021 case ZPCI_FS_ENABLED: 1022 fib.fc |= 0x80; 1023 if (pbdev->iommu->enabled) { 1024 fib.fc |= 0x10; 1025 } 1026 if (!(fh & FH_MASK_ENABLE)) { 1027 env->regs[r1] |= 1ULL << 63; 1028 } 1029 break; 1030 case ZPCI_FS_PERMANENT_ERROR: 1031 setcc(cpu, ZPCI_PCI_LS_ERR); 1032 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR); 1033 return 0; 1034 } 1035 1036 stq_p(&fib.pba, pbdev->iommu->pba); 1037 stq_p(&fib.pal, pbdev->iommu->pal); 1038 stq_p(&fib.iota, pbdev->iommu->g_iota); 1039 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr); 1040 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr); 1041 stq_p(&fib.fmb_addr, pbdev->fmb_addr); 1042 1043 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) | 1044 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) | 1045 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset; 1046 stl_p(&fib.data, data); 1047 1048 out: 1049 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 1050 return 0; 1051 } 1052 1053 setcc(cpu, cc); 1054 return 0; 1055 } 1056