1 /* 2 * s390 PCI instructions 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "cpu.h" 16 #include "s390-pci-inst.h" 17 #include "s390-pci-bus.h" 18 #include "exec/memop.h" 19 #include "exec/memory-internal.h" 20 #include "qemu/error-report.h" 21 #include "sysemu/hw_accel.h" 22 #include "hw/s390x/tod.h" 23 24 #ifndef DEBUG_S390PCI_INST 25 #define DEBUG_S390PCI_INST 0 26 #endif 27 28 #define DPRINTF(fmt, ...) \ 29 do { \ 30 if (DEBUG_S390PCI_INST) { \ 31 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \ 32 } \ 33 } while (0) 34 35 static void s390_set_status_code(CPUS390XState *env, 36 uint8_t r, uint64_t status_code) 37 { 38 env->regs[r] &= ~0xff000000ULL; 39 env->regs[r] |= (status_code & 0xff) << 24; 40 } 41 42 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) 43 { 44 S390PCIBusDevice *pbdev = NULL; 45 S390pciState *s = s390_get_phb(); 46 uint32_t res_code, initial_l2, g_l2; 47 int rc, i; 48 uint64_t resume_token; 49 50 rc = 0; 51 if (lduw_p(&rrb->request.hdr.len) != 32) { 52 res_code = CLP_RC_LEN; 53 rc = -EINVAL; 54 goto out; 55 } 56 57 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) { 58 res_code = CLP_RC_FMT; 59 rc = -EINVAL; 60 goto out; 61 } 62 63 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 || 64 ldq_p(&rrb->request.reserved1) != 0) { 65 res_code = CLP_RC_RESNOT0; 66 rc = -EINVAL; 67 goto out; 68 } 69 70 resume_token = ldq_p(&rrb->request.resume_token); 71 72 if (resume_token) { 73 pbdev = s390_pci_find_dev_by_idx(s, resume_token); 74 if (!pbdev) { 75 res_code = CLP_RC_LISTPCI_BADRT; 76 rc = -EINVAL; 77 goto out; 78 } 79 } else { 80 pbdev = s390_pci_find_next_avail_dev(s, NULL); 81 } 82 83 if (lduw_p(&rrb->response.hdr.len) < 48) { 84 res_code = CLP_RC_8K; 85 rc = -EINVAL; 86 goto out; 87 } 88 89 initial_l2 = lduw_p(&rrb->response.hdr.len); 90 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry) 91 != 0) { 92 res_code = CLP_RC_LEN; 93 rc = -EINVAL; 94 *cc = 3; 95 goto out; 96 } 97 98 stl_p(&rrb->response.fmt, 0); 99 stq_p(&rrb->response.reserved1, 0); 100 stl_p(&rrb->response.mdd, FH_MASK_SHM); 101 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS); 102 rrb->response.flags = UID_CHECKING_ENABLED; 103 rrb->response.entry_size = sizeof(ClpFhListEntry); 104 105 i = 0; 106 g_l2 = LIST_PCI_HDR_LEN; 107 while (g_l2 < initial_l2 && pbdev) { 108 stw_p(&rrb->response.fh_list[i].device_id, 109 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID)); 110 stw_p(&rrb->response.fh_list[i].vendor_id, 111 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID)); 112 /* Ignore RESERVED devices. */ 113 stl_p(&rrb->response.fh_list[i].config, 114 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31); 115 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid); 116 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh); 117 118 g_l2 += sizeof(ClpFhListEntry); 119 /* Add endian check for DPRINTF? */ 120 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n", 121 g_l2, 122 lduw_p(&rrb->response.fh_list[i].vendor_id), 123 lduw_p(&rrb->response.fh_list[i].device_id), 124 ldl_p(&rrb->response.fh_list[i].fid), 125 ldl_p(&rrb->response.fh_list[i].fh)); 126 pbdev = s390_pci_find_next_avail_dev(s, pbdev); 127 i++; 128 } 129 130 if (!pbdev) { 131 resume_token = 0; 132 } else { 133 resume_token = pbdev->fh & FH_MASK_INDEX; 134 } 135 stq_p(&rrb->response.resume_token, resume_token); 136 stw_p(&rrb->response.hdr.len, g_l2); 137 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK); 138 out: 139 if (rc) { 140 DPRINTF("list pci failed rc 0x%x\n", rc); 141 stw_p(&rrb->response.hdr.rsp, res_code); 142 } 143 return rc; 144 } 145 146 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) 147 { 148 ClpReqHdr *reqh; 149 ClpRspHdr *resh; 150 S390PCIBusDevice *pbdev; 151 uint32_t req_len; 152 uint32_t res_len; 153 uint8_t buffer[4096 * 2]; 154 uint8_t cc = 0; 155 CPUS390XState *env = &cpu->env; 156 S390pciState *s = s390_get_phb(); 157 int i; 158 159 if (env->psw.mask & PSW_MASK_PSTATE) { 160 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 161 return 0; 162 } 163 164 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) { 165 s390_cpu_virt_mem_handle_exc(cpu, ra); 166 return 0; 167 } 168 reqh = (ClpReqHdr *)buffer; 169 req_len = lduw_p(&reqh->len); 170 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) { 171 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 172 return 0; 173 } 174 175 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 176 req_len + sizeof(*resh))) { 177 s390_cpu_virt_mem_handle_exc(cpu, ra); 178 return 0; 179 } 180 resh = (ClpRspHdr *)(buffer + req_len); 181 res_len = lduw_p(&resh->len); 182 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) { 183 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 184 return 0; 185 } 186 if ((req_len + res_len) > 8192) { 187 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 188 return 0; 189 } 190 191 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 192 req_len + res_len)) { 193 s390_cpu_virt_mem_handle_exc(cpu, ra); 194 return 0; 195 } 196 197 if (req_len != 32) { 198 stw_p(&resh->rsp, CLP_RC_LEN); 199 goto out; 200 } 201 202 switch (lduw_p(&reqh->cmd)) { 203 case CLP_LIST_PCI: { 204 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer; 205 list_pci(rrb, &cc); 206 break; 207 } 208 case CLP_SET_PCI_FN: { 209 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh; 210 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh; 211 212 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh)); 213 if (!pbdev) { 214 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); 215 goto out; 216 } 217 218 switch (reqsetpci->oc) { 219 case CLP_SET_ENABLE_PCI_FN: 220 switch (reqsetpci->ndas) { 221 case 0: 222 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS); 223 goto out; 224 case 1: 225 break; 226 default: 227 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES); 228 goto out; 229 } 230 231 if (pbdev->fh & FH_MASK_ENABLE) { 232 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 233 goto out; 234 } 235 236 pbdev->fh |= FH_MASK_ENABLE; 237 pbdev->state = ZPCI_FS_ENABLED; 238 stl_p(&ressetpci->fh, pbdev->fh); 239 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 240 break; 241 case CLP_SET_DISABLE_PCI_FN: 242 if (!(pbdev->fh & FH_MASK_ENABLE)) { 243 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 244 goto out; 245 } 246 device_reset(DEVICE(pbdev)); 247 pbdev->fh &= ~FH_MASK_ENABLE; 248 pbdev->state = ZPCI_FS_DISABLED; 249 stl_p(&ressetpci->fh, pbdev->fh); 250 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 251 break; 252 default: 253 DPRINTF("unknown set pci command\n"); 254 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 255 break; 256 } 257 break; 258 } 259 case CLP_QUERY_PCI_FN: { 260 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh; 261 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh; 262 263 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh)); 264 if (!pbdev) { 265 DPRINTF("query pci no pci dev\n"); 266 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH); 267 goto out; 268 } 269 270 for (i = 0; i < PCI_BAR_COUNT; i++) { 271 uint32_t data = pci_get_long(pbdev->pdev->config + 272 PCI_BASE_ADDRESS_0 + (i * 4)); 273 274 stl_p(&resquery->bar[i], data); 275 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ? 276 ctz64(pbdev->pdev->io_regions[i].size) : 0; 277 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i, 278 ldl_p(&resquery->bar[i]), 279 pbdev->pdev->io_regions[i].size, 280 resquery->bar_size[i]); 281 } 282 283 stq_p(&resquery->sdma, ZPCI_SDMA_ADDR); 284 stq_p(&resquery->edma, ZPCI_EDMA_ADDR); 285 stl_p(&resquery->fid, pbdev->fid); 286 stw_p(&resquery->pchid, 0); 287 stw_p(&resquery->ug, 1); 288 stl_p(&resquery->uid, pbdev->uid); 289 stw_p(&resquery->hdr.rsp, CLP_RC_OK); 290 break; 291 } 292 case CLP_QUERY_PCI_FNGRP: { 293 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh; 294 resgrp->fr = 1; 295 stq_p(&resgrp->dasm, 0); 296 stq_p(&resgrp->msia, ZPCI_MSI_ADDR); 297 stw_p(&resgrp->mui, DEFAULT_MUI); 298 stw_p(&resgrp->i, 128); 299 stw_p(&resgrp->maxstbl, 128); 300 resgrp->version = 0; 301 302 stw_p(&resgrp->hdr.rsp, CLP_RC_OK); 303 break; 304 } 305 default: 306 DPRINTF("unknown clp command\n"); 307 stw_p(&resh->rsp, CLP_RC_CMD); 308 break; 309 } 310 311 out: 312 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer, 313 req_len + res_len)) { 314 s390_cpu_virt_mem_handle_exc(cpu, ra); 315 return 0; 316 } 317 setcc(cpu, cc); 318 return 0; 319 } 320 321 /** 322 * Swap data contained in s390x big endian registers to little endian 323 * PCI bars. 324 * 325 * @ptr: a pointer to a uint64_t data field 326 * @len: the length of the valid data, must be 1,2,4 or 8 327 */ 328 static int zpci_endian_swap(uint64_t *ptr, uint8_t len) 329 { 330 uint64_t data = *ptr; 331 332 switch (len) { 333 case 1: 334 break; 335 case 2: 336 data = bswap16(data); 337 break; 338 case 4: 339 data = bswap32(data); 340 break; 341 case 8: 342 data = bswap64(data); 343 break; 344 default: 345 return -EINVAL; 346 } 347 *ptr = data; 348 return 0; 349 } 350 351 static MemoryRegion *s390_get_subregion(MemoryRegion *mr, uint64_t offset, 352 uint8_t len) 353 { 354 MemoryRegion *subregion; 355 uint64_t subregion_size; 356 357 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) { 358 subregion_size = int128_get64(subregion->size); 359 if ((offset >= subregion->addr) && 360 (offset + len) <= (subregion->addr + subregion_size)) { 361 mr = subregion; 362 break; 363 } 364 } 365 return mr; 366 } 367 368 static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias, 369 uint64_t offset, uint64_t *data, uint8_t len) 370 { 371 MemoryRegion *mr; 372 373 mr = pbdev->pdev->io_regions[pcias].memory; 374 mr = s390_get_subregion(mr, offset, len); 375 offset -= mr->addr; 376 return memory_region_dispatch_read(mr, offset, data, size_memop(len), 377 MEMTXATTRS_UNSPECIFIED); 378 } 379 380 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 381 { 382 CPUS390XState *env = &cpu->env; 383 S390PCIBusDevice *pbdev; 384 uint64_t offset; 385 uint64_t data; 386 MemTxResult result; 387 uint8_t len; 388 uint32_t fh; 389 uint8_t pcias; 390 391 if (env->psw.mask & PSW_MASK_PSTATE) { 392 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 393 return 0; 394 } 395 396 if (r2 & 0x1) { 397 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 398 return 0; 399 } 400 401 fh = env->regs[r2] >> 32; 402 pcias = (env->regs[r2] >> 16) & 0xf; 403 len = env->regs[r2] & 0xf; 404 offset = env->regs[r2 + 1]; 405 406 if (!(fh & FH_MASK_ENABLE)) { 407 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 408 return 0; 409 } 410 411 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 412 if (!pbdev) { 413 DPRINTF("pcilg no pci dev\n"); 414 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 415 return 0; 416 } 417 418 switch (pbdev->state) { 419 case ZPCI_FS_PERMANENT_ERROR: 420 case ZPCI_FS_ERROR: 421 setcc(cpu, ZPCI_PCI_LS_ERR); 422 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 423 return 0; 424 default: 425 break; 426 } 427 428 switch (pcias) { 429 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 430 if (!len || (len > (8 - (offset & 0x7)))) { 431 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 432 return 0; 433 } 434 result = zpci_read_bar(pbdev, pcias, offset, &data, len); 435 if (result != MEMTX_OK) { 436 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 437 return 0; 438 } 439 break; 440 case ZPCI_CONFIG_BAR: 441 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 442 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 443 return 0; 444 } 445 data = pci_host_config_read_common( 446 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len); 447 448 if (zpci_endian_swap(&data, len)) { 449 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 450 return 0; 451 } 452 break; 453 default: 454 DPRINTF("pcilg invalid space\n"); 455 setcc(cpu, ZPCI_PCI_LS_ERR); 456 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 457 return 0; 458 } 459 460 pbdev->fmb.counter[ZPCI_FMB_CNT_LD]++; 461 462 env->regs[r1] = data; 463 setcc(cpu, ZPCI_PCI_LS_OK); 464 return 0; 465 } 466 467 static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias, 468 uint64_t offset, uint64_t data, uint8_t len) 469 { 470 MemoryRegion *mr; 471 472 mr = pbdev->pdev->io_regions[pcias].memory; 473 mr = s390_get_subregion(mr, offset, len); 474 offset -= mr->addr; 475 return memory_region_dispatch_write(mr, offset, data, size_memop(len), 476 MEMTXATTRS_UNSPECIFIED); 477 } 478 479 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 480 { 481 CPUS390XState *env = &cpu->env; 482 uint64_t offset, data; 483 S390PCIBusDevice *pbdev; 484 MemTxResult result; 485 uint8_t len; 486 uint32_t fh; 487 uint8_t pcias; 488 489 if (env->psw.mask & PSW_MASK_PSTATE) { 490 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 491 return 0; 492 } 493 494 if (r2 & 0x1) { 495 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 496 return 0; 497 } 498 499 fh = env->regs[r2] >> 32; 500 pcias = (env->regs[r2] >> 16) & 0xf; 501 len = env->regs[r2] & 0xf; 502 offset = env->regs[r2 + 1]; 503 data = env->regs[r1]; 504 505 if (!(fh & FH_MASK_ENABLE)) { 506 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 507 return 0; 508 } 509 510 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 511 if (!pbdev) { 512 DPRINTF("pcistg no pci dev\n"); 513 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 514 return 0; 515 } 516 517 switch (pbdev->state) { 518 /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED 519 * are already covered by the FH_MASK_ENABLE check above 520 */ 521 case ZPCI_FS_PERMANENT_ERROR: 522 case ZPCI_FS_ERROR: 523 setcc(cpu, ZPCI_PCI_LS_ERR); 524 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 525 return 0; 526 default: 527 break; 528 } 529 530 switch (pcias) { 531 /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */ 532 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 533 /* Check length: 534 * A length of 0 is invalid and length should not cross a double word 535 */ 536 if (!len || (len > (8 - (offset & 0x7)))) { 537 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 538 return 0; 539 } 540 541 result = zpci_write_bar(pbdev, pcias, offset, data, len); 542 if (result != MEMTX_OK) { 543 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 544 return 0; 545 } 546 break; 547 case ZPCI_CONFIG_BAR: 548 /* ZPCI uses the pseudo BAR number 15 as configuration space */ 549 /* possible access lengths are 1,2,4 and must not cross a word */ 550 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 551 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 552 return 0; 553 } 554 /* len = 1,2,4 so we do not need to test */ 555 zpci_endian_swap(&data, len); 556 pci_host_config_write_common(pbdev->pdev, offset, 557 pci_config_size(pbdev->pdev), 558 data, len); 559 break; 560 default: 561 DPRINTF("pcistg invalid space\n"); 562 setcc(cpu, ZPCI_PCI_LS_ERR); 563 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 564 return 0; 565 } 566 567 pbdev->fmb.counter[ZPCI_FMB_CNT_ST]++; 568 569 setcc(cpu, ZPCI_PCI_LS_OK); 570 return 0; 571 } 572 573 static void s390_pci_update_iotlb(S390PCIIOMMU *iommu, S390IOTLBEntry *entry) 574 { 575 S390IOTLBEntry *cache = g_hash_table_lookup(iommu->iotlb, &entry->iova); 576 IOMMUTLBEntry notify = { 577 .target_as = &address_space_memory, 578 .iova = entry->iova, 579 .translated_addr = entry->translated_addr, 580 .perm = entry->perm, 581 .addr_mask = ~PAGE_MASK, 582 }; 583 584 if (entry->perm == IOMMU_NONE) { 585 if (!cache) { 586 return; 587 } 588 g_hash_table_remove(iommu->iotlb, &entry->iova); 589 } else { 590 if (cache) { 591 if (cache->perm == entry->perm && 592 cache->translated_addr == entry->translated_addr) { 593 return; 594 } 595 596 notify.perm = IOMMU_NONE; 597 memory_region_notify_iommu(&iommu->iommu_mr, 0, notify); 598 notify.perm = entry->perm; 599 } 600 601 cache = g_new(S390IOTLBEntry, 1); 602 cache->iova = entry->iova; 603 cache->translated_addr = entry->translated_addr; 604 cache->len = PAGE_SIZE; 605 cache->perm = entry->perm; 606 g_hash_table_replace(iommu->iotlb, &cache->iova, cache); 607 } 608 609 memory_region_notify_iommu(&iommu->iommu_mr, 0, notify); 610 } 611 612 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 613 { 614 CPUS390XState *env = &cpu->env; 615 uint32_t fh; 616 uint16_t error = 0; 617 S390PCIBusDevice *pbdev; 618 S390PCIIOMMU *iommu; 619 S390IOTLBEntry entry; 620 hwaddr start, end; 621 622 if (env->psw.mask & PSW_MASK_PSTATE) { 623 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 624 return 0; 625 } 626 627 if (r2 & 0x1) { 628 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 629 return 0; 630 } 631 632 fh = env->regs[r1] >> 32; 633 start = env->regs[r2]; 634 end = start + env->regs[r2 + 1]; 635 636 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 637 if (!pbdev) { 638 DPRINTF("rpcit no pci dev\n"); 639 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 640 return 0; 641 } 642 643 switch (pbdev->state) { 644 case ZPCI_FS_RESERVED: 645 case ZPCI_FS_STANDBY: 646 case ZPCI_FS_DISABLED: 647 case ZPCI_FS_PERMANENT_ERROR: 648 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 649 return 0; 650 case ZPCI_FS_ERROR: 651 setcc(cpu, ZPCI_PCI_LS_ERR); 652 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER); 653 return 0; 654 default: 655 break; 656 } 657 658 iommu = pbdev->iommu; 659 if (!iommu->g_iota) { 660 error = ERR_EVENT_INVALAS; 661 goto err; 662 } 663 664 if (end < iommu->pba || start > iommu->pal) { 665 error = ERR_EVENT_OORANGE; 666 goto err; 667 } 668 669 while (start < end) { 670 error = s390_guest_io_table_walk(iommu->g_iota, start, &entry); 671 if (error) { 672 break; 673 } 674 675 start += entry.len; 676 while (entry.iova < start && entry.iova < end) { 677 s390_pci_update_iotlb(iommu, &entry); 678 entry.iova += PAGE_SIZE; 679 entry.translated_addr += PAGE_SIZE; 680 } 681 } 682 err: 683 if (error) { 684 pbdev->state = ZPCI_FS_ERROR; 685 setcc(cpu, ZPCI_PCI_LS_ERR); 686 s390_set_status_code(env, r1, ZPCI_PCI_ST_FUNC_IN_ERR); 687 s390_pci_generate_error_event(error, pbdev->fh, pbdev->fid, start, 0); 688 } else { 689 pbdev->fmb.counter[ZPCI_FMB_CNT_RPCIT]++; 690 setcc(cpu, ZPCI_PCI_LS_OK); 691 } 692 return 0; 693 } 694 695 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, 696 uint8_t ar, uintptr_t ra) 697 { 698 CPUS390XState *env = &cpu->env; 699 S390PCIBusDevice *pbdev; 700 MemoryRegion *mr; 701 MemTxResult result; 702 uint64_t offset; 703 int i; 704 uint32_t fh; 705 uint8_t pcias; 706 uint8_t len; 707 uint8_t buffer[128]; 708 709 if (env->psw.mask & PSW_MASK_PSTATE) { 710 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 711 return 0; 712 } 713 714 fh = env->regs[r1] >> 32; 715 pcias = (env->regs[r1] >> 16) & 0xf; 716 len = env->regs[r1] & 0xff; 717 offset = env->regs[r3]; 718 719 if (!(fh & FH_MASK_ENABLE)) { 720 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 721 return 0; 722 } 723 724 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 725 if (!pbdev) { 726 DPRINTF("pcistb no pci dev fh 0x%x\n", fh); 727 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 728 return 0; 729 } 730 731 switch (pbdev->state) { 732 case ZPCI_FS_PERMANENT_ERROR: 733 case ZPCI_FS_ERROR: 734 setcc(cpu, ZPCI_PCI_LS_ERR); 735 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED); 736 return 0; 737 default: 738 break; 739 } 740 741 if (pcias > ZPCI_IO_BAR_MAX) { 742 DPRINTF("pcistb invalid space\n"); 743 setcc(cpu, ZPCI_PCI_LS_ERR); 744 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS); 745 return 0; 746 } 747 748 /* Verify the address, offset and length */ 749 /* offset must be a multiple of 8 */ 750 if (offset % 8) { 751 goto specification_error; 752 } 753 /* Length must be greater than 8, a multiple of 8 */ 754 /* and not greater than maxstbl */ 755 if ((len <= 8) || (len % 8) || (len > pbdev->maxstbl)) { 756 goto specification_error; 757 } 758 /* Do not cross a 4K-byte boundary */ 759 if (((offset & 0xfff) + len) > 0x1000) { 760 goto specification_error; 761 } 762 /* Guest address must be double word aligned */ 763 if (gaddr & 0x07UL) { 764 goto specification_error; 765 } 766 767 mr = pbdev->pdev->io_regions[pcias].memory; 768 mr = s390_get_subregion(mr, offset, len); 769 offset -= mr->addr; 770 771 if (!memory_region_access_valid(mr, offset, len, true, 772 MEMTXATTRS_UNSPECIFIED)) { 773 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 774 return 0; 775 } 776 777 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) { 778 s390_cpu_virt_mem_handle_exc(cpu, ra); 779 return 0; 780 } 781 782 for (i = 0; i < len / 8; i++) { 783 result = memory_region_dispatch_write(mr, offset + i * 8, 784 ldq_p(buffer + i * 8), 785 size_memop(8), 786 MEMTXATTRS_UNSPECIFIED); 787 if (result != MEMTX_OK) { 788 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 789 return 0; 790 } 791 } 792 793 pbdev->fmb.counter[ZPCI_FMB_CNT_STB]++; 794 795 setcc(cpu, ZPCI_PCI_LS_OK); 796 return 0; 797 798 specification_error: 799 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 800 return 0; 801 } 802 803 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib) 804 { 805 int ret, len; 806 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data)); 807 808 pbdev->routes.adapter.adapter_id = css_get_adapter_id( 809 CSS_IO_ADAPTER_PCI, isc); 810 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t)); 811 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long); 812 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len); 813 814 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 815 if (ret) { 816 goto out; 817 } 818 819 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator); 820 if (ret) { 821 goto out; 822 } 823 824 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb); 825 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data)); 826 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv); 827 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data)); 828 pbdev->isc = isc; 829 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data)); 830 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data)); 831 832 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 833 return 0; 834 out: 835 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 836 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 837 pbdev->summary_ind = NULL; 838 pbdev->indicator = NULL; 839 return ret; 840 } 841 842 int pci_dereg_irqs(S390PCIBusDevice *pbdev) 843 { 844 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 845 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 846 847 pbdev->summary_ind = NULL; 848 pbdev->indicator = NULL; 849 pbdev->routes.adapter.summary_addr = 0; 850 pbdev->routes.adapter.summary_offset = 0; 851 pbdev->routes.adapter.ind_addr = 0; 852 pbdev->routes.adapter.ind_offset = 0; 853 pbdev->isc = 0; 854 pbdev->noi = 0; 855 pbdev->sum = 0; 856 857 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 858 return 0; 859 } 860 861 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib, 862 uintptr_t ra) 863 { 864 uint64_t pba = ldq_p(&fib.pba); 865 uint64_t pal = ldq_p(&fib.pal); 866 uint64_t g_iota = ldq_p(&fib.iota); 867 uint8_t dt = (g_iota >> 2) & 0x7; 868 uint8_t t = (g_iota >> 11) & 0x1; 869 870 pba &= ~0xfff; 871 pal |= 0xfff; 872 if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) { 873 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 874 return -EINVAL; 875 } 876 877 /* currently we only support designation type 1 with translation */ 878 if (!(dt == ZPCI_IOTA_RTTO && t)) { 879 error_report("unsupported ioat dt %d t %d", dt, t); 880 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 881 return -EINVAL; 882 } 883 884 iommu->pba = pba; 885 iommu->pal = pal; 886 iommu->g_iota = g_iota; 887 888 s390_pci_iommu_enable(iommu); 889 890 return 0; 891 } 892 893 void pci_dereg_ioat(S390PCIIOMMU *iommu) 894 { 895 s390_pci_iommu_disable(iommu); 896 iommu->pba = 0; 897 iommu->pal = 0; 898 iommu->g_iota = 0; 899 } 900 901 void fmb_timer_free(S390PCIBusDevice *pbdev) 902 { 903 if (pbdev->fmb_timer) { 904 timer_del(pbdev->fmb_timer); 905 timer_free(pbdev->fmb_timer); 906 pbdev->fmb_timer = NULL; 907 } 908 pbdev->fmb_addr = 0; 909 memset(&pbdev->fmb, 0, sizeof(ZpciFmb)); 910 } 911 912 static int fmb_do_update(S390PCIBusDevice *pbdev, int offset, uint64_t val, 913 int len) 914 { 915 MemTxResult ret; 916 uint64_t dst = pbdev->fmb_addr + offset; 917 918 switch (len) { 919 case 8: 920 address_space_stq_be(&address_space_memory, dst, val, 921 MEMTXATTRS_UNSPECIFIED, 922 &ret); 923 break; 924 case 4: 925 address_space_stl_be(&address_space_memory, dst, val, 926 MEMTXATTRS_UNSPECIFIED, 927 &ret); 928 break; 929 case 2: 930 address_space_stw_be(&address_space_memory, dst, val, 931 MEMTXATTRS_UNSPECIFIED, 932 &ret); 933 break; 934 case 1: 935 address_space_stb(&address_space_memory, dst, val, 936 MEMTXATTRS_UNSPECIFIED, 937 &ret); 938 break; 939 default: 940 ret = MEMTX_ERROR; 941 break; 942 } 943 if (ret != MEMTX_OK) { 944 s390_pci_generate_error_event(ERR_EVENT_FMBA, pbdev->fh, pbdev->fid, 945 pbdev->fmb_addr, 0); 946 fmb_timer_free(pbdev); 947 } 948 949 return ret; 950 } 951 952 static void fmb_update(void *opaque) 953 { 954 S390PCIBusDevice *pbdev = opaque; 955 int64_t t = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); 956 int i; 957 958 /* Update U bit */ 959 pbdev->fmb.last_update *= 2; 960 pbdev->fmb.last_update |= UPDATE_U_BIT; 961 if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update), 962 pbdev->fmb.last_update, 963 sizeof(pbdev->fmb.last_update))) { 964 return; 965 } 966 967 /* Update FMB sample count */ 968 if (fmb_do_update(pbdev, offsetof(ZpciFmb, sample), 969 pbdev->fmb.sample++, 970 sizeof(pbdev->fmb.sample))) { 971 return; 972 } 973 974 /* Update FMB counters */ 975 for (i = 0; i < ZPCI_FMB_CNT_MAX; i++) { 976 if (fmb_do_update(pbdev, offsetof(ZpciFmb, counter[i]), 977 pbdev->fmb.counter[i], 978 sizeof(pbdev->fmb.counter[0]))) { 979 return; 980 } 981 } 982 983 /* Clear U bit and update the time */ 984 pbdev->fmb.last_update = time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 985 pbdev->fmb.last_update *= 2; 986 if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update), 987 pbdev->fmb.last_update, 988 sizeof(pbdev->fmb.last_update))) { 989 return; 990 } 991 timer_mod(pbdev->fmb_timer, t + DEFAULT_MUI); 992 } 993 994 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 995 uintptr_t ra) 996 { 997 CPUS390XState *env = &cpu->env; 998 uint8_t oc, dmaas; 999 uint32_t fh; 1000 ZpciFib fib; 1001 S390PCIBusDevice *pbdev; 1002 uint64_t cc = ZPCI_PCI_LS_OK; 1003 1004 if (env->psw.mask & PSW_MASK_PSTATE) { 1005 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 1006 return 0; 1007 } 1008 1009 oc = env->regs[r1] & 0xff; 1010 dmaas = (env->regs[r1] >> 16) & 0xff; 1011 fh = env->regs[r1] >> 32; 1012 1013 if (fiba & 0x7) { 1014 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 1015 return 0; 1016 } 1017 1018 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 1019 if (!pbdev) { 1020 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh); 1021 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1022 return 0; 1023 } 1024 1025 switch (pbdev->state) { 1026 case ZPCI_FS_RESERVED: 1027 case ZPCI_FS_STANDBY: 1028 case ZPCI_FS_DISABLED: 1029 case ZPCI_FS_PERMANENT_ERROR: 1030 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1031 return 0; 1032 default: 1033 break; 1034 } 1035 1036 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 1037 s390_cpu_virt_mem_handle_exc(cpu, ra); 1038 return 0; 1039 } 1040 1041 if (fib.fmt != 0) { 1042 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 1043 return 0; 1044 } 1045 1046 switch (oc) { 1047 case ZPCI_MOD_FC_REG_INT: 1048 if (pbdev->summary_ind) { 1049 cc = ZPCI_PCI_LS_ERR; 1050 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1051 } else if (reg_irqs(env, pbdev, fib)) { 1052 cc = ZPCI_PCI_LS_ERR; 1053 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL); 1054 } 1055 break; 1056 case ZPCI_MOD_FC_DEREG_INT: 1057 if (!pbdev->summary_ind) { 1058 cc = ZPCI_PCI_LS_ERR; 1059 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1060 } else { 1061 pci_dereg_irqs(pbdev); 1062 } 1063 break; 1064 case ZPCI_MOD_FC_REG_IOAT: 1065 if (dmaas != 0) { 1066 cc = ZPCI_PCI_LS_ERR; 1067 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 1068 } else if (pbdev->iommu->enabled) { 1069 cc = ZPCI_PCI_LS_ERR; 1070 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1071 } else if (reg_ioat(env, pbdev->iommu, fib, ra)) { 1072 cc = ZPCI_PCI_LS_ERR; 1073 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 1074 } 1075 break; 1076 case ZPCI_MOD_FC_DEREG_IOAT: 1077 if (dmaas != 0) { 1078 cc = ZPCI_PCI_LS_ERR; 1079 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 1080 } else if (!pbdev->iommu->enabled) { 1081 cc = ZPCI_PCI_LS_ERR; 1082 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1083 } else { 1084 pci_dereg_ioat(pbdev->iommu); 1085 } 1086 break; 1087 case ZPCI_MOD_FC_REREG_IOAT: 1088 if (dmaas != 0) { 1089 cc = ZPCI_PCI_LS_ERR; 1090 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 1091 } else if (!pbdev->iommu->enabled) { 1092 cc = ZPCI_PCI_LS_ERR; 1093 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1094 } else { 1095 pci_dereg_ioat(pbdev->iommu); 1096 if (reg_ioat(env, pbdev->iommu, fib, ra)) { 1097 cc = ZPCI_PCI_LS_ERR; 1098 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 1099 } 1100 } 1101 break; 1102 case ZPCI_MOD_FC_RESET_ERROR: 1103 switch (pbdev->state) { 1104 case ZPCI_FS_BLOCKED: 1105 case ZPCI_FS_ERROR: 1106 pbdev->state = ZPCI_FS_ENABLED; 1107 break; 1108 default: 1109 cc = ZPCI_PCI_LS_ERR; 1110 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1111 } 1112 break; 1113 case ZPCI_MOD_FC_RESET_BLOCK: 1114 switch (pbdev->state) { 1115 case ZPCI_FS_ERROR: 1116 pbdev->state = ZPCI_FS_BLOCKED; 1117 break; 1118 default: 1119 cc = ZPCI_PCI_LS_ERR; 1120 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1121 } 1122 break; 1123 case ZPCI_MOD_FC_SET_MEASURE: { 1124 uint64_t fmb_addr = ldq_p(&fib.fmb_addr); 1125 1126 if (fmb_addr & FMBK_MASK) { 1127 cc = ZPCI_PCI_LS_ERR; 1128 s390_pci_generate_error_event(ERR_EVENT_FMBPRO, pbdev->fh, 1129 pbdev->fid, fmb_addr, 0); 1130 fmb_timer_free(pbdev); 1131 break; 1132 } 1133 1134 if (!fmb_addr) { 1135 /* Stop updating FMB. */ 1136 fmb_timer_free(pbdev); 1137 break; 1138 } 1139 1140 if (!pbdev->fmb_timer) { 1141 pbdev->fmb_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 1142 fmb_update, pbdev); 1143 } else if (timer_pending(pbdev->fmb_timer)) { 1144 /* Remove pending timer to update FMB address. */ 1145 timer_del(pbdev->fmb_timer); 1146 } 1147 pbdev->fmb_addr = fmb_addr; 1148 timer_mod(pbdev->fmb_timer, 1149 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + DEFAULT_MUI); 1150 break; 1151 } 1152 default: 1153 s390_program_interrupt(&cpu->env, PGM_OPERAND, 6, ra); 1154 cc = ZPCI_PCI_LS_ERR; 1155 } 1156 1157 setcc(cpu, cc); 1158 return 0; 1159 } 1160 1161 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 1162 uintptr_t ra) 1163 { 1164 CPUS390XState *env = &cpu->env; 1165 uint8_t dmaas; 1166 uint32_t fh; 1167 ZpciFib fib; 1168 S390PCIBusDevice *pbdev; 1169 uint32_t data; 1170 uint64_t cc = ZPCI_PCI_LS_OK; 1171 1172 if (env->psw.mask & PSW_MASK_PSTATE) { 1173 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 1174 return 0; 1175 } 1176 1177 fh = env->regs[r1] >> 32; 1178 dmaas = (env->regs[r1] >> 16) & 0xff; 1179 1180 if (dmaas) { 1181 setcc(cpu, ZPCI_PCI_LS_ERR); 1182 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS); 1183 return 0; 1184 } 1185 1186 if (fiba & 0x7) { 1187 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 1188 return 0; 1189 } 1190 1191 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX); 1192 if (!pbdev) { 1193 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1194 return 0; 1195 } 1196 1197 memset(&fib, 0, sizeof(fib)); 1198 1199 switch (pbdev->state) { 1200 case ZPCI_FS_RESERVED: 1201 case ZPCI_FS_STANDBY: 1202 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1203 return 0; 1204 case ZPCI_FS_DISABLED: 1205 if (fh & FH_MASK_ENABLE) { 1206 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1207 return 0; 1208 } 1209 goto out; 1210 /* BLOCKED bit is set to one coincident with the setting of ERROR bit. 1211 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */ 1212 case ZPCI_FS_ERROR: 1213 fib.fc |= 0x20; 1214 /* fallthrough */ 1215 case ZPCI_FS_BLOCKED: 1216 fib.fc |= 0x40; 1217 /* fallthrough */ 1218 case ZPCI_FS_ENABLED: 1219 fib.fc |= 0x80; 1220 if (pbdev->iommu->enabled) { 1221 fib.fc |= 0x10; 1222 } 1223 if (!(fh & FH_MASK_ENABLE)) { 1224 env->regs[r1] |= 1ULL << 63; 1225 } 1226 break; 1227 case ZPCI_FS_PERMANENT_ERROR: 1228 setcc(cpu, ZPCI_PCI_LS_ERR); 1229 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR); 1230 return 0; 1231 } 1232 1233 stq_p(&fib.pba, pbdev->iommu->pba); 1234 stq_p(&fib.pal, pbdev->iommu->pal); 1235 stq_p(&fib.iota, pbdev->iommu->g_iota); 1236 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr); 1237 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr); 1238 stq_p(&fib.fmb_addr, pbdev->fmb_addr); 1239 1240 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) | 1241 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) | 1242 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset; 1243 stl_p(&fib.data, data); 1244 1245 out: 1246 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 1247 s390_cpu_virt_mem_handle_exc(cpu, ra); 1248 return 0; 1249 } 1250 1251 setcc(cpu, cc); 1252 return 0; 1253 } 1254