1 /* 2 * s390 PCI BUS 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qapi/error.h" 16 #include "qapi/visitor.h" 17 #include "qemu-common.h" 18 #include "cpu.h" 19 #include "s390-pci-bus.h" 20 #include "s390-pci-inst.h" 21 #include "hw/pci/pci_bus.h" 22 #include "hw/pci/pci_bridge.h" 23 #include "hw/pci/msi.h" 24 #include "qemu/error-report.h" 25 26 /* #define DEBUG_S390PCI_BUS */ 27 #ifdef DEBUG_S390PCI_BUS 28 #define DPRINTF(fmt, ...) \ 29 do { fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); } while (0) 30 #else 31 #define DPRINTF(fmt, ...) \ 32 do { } while (0) 33 #endif 34 35 S390pciState *s390_get_phb(void) 36 { 37 static S390pciState *phb; 38 39 if (!phb) { 40 phb = S390_PCI_HOST_BRIDGE( 41 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL)); 42 assert(phb != NULL); 43 } 44 45 return phb; 46 } 47 48 int chsc_sei_nt2_get_event(void *res) 49 { 50 ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res; 51 PciCcdfAvail *accdf; 52 PciCcdfErr *eccdf; 53 int rc = 1; 54 SeiContainer *sei_cont; 55 S390pciState *s = s390_get_phb(); 56 57 sei_cont = QTAILQ_FIRST(&s->pending_sei); 58 if (sei_cont) { 59 QTAILQ_REMOVE(&s->pending_sei, sei_cont, link); 60 nt2_res->nt = 2; 61 nt2_res->cc = sei_cont->cc; 62 nt2_res->length = cpu_to_be16(sizeof(ChscSeiNt2Res)); 63 switch (sei_cont->cc) { 64 case 1: /* error event */ 65 eccdf = (PciCcdfErr *)nt2_res->ccdf; 66 eccdf->fid = cpu_to_be32(sei_cont->fid); 67 eccdf->fh = cpu_to_be32(sei_cont->fh); 68 eccdf->e = cpu_to_be32(sei_cont->e); 69 eccdf->faddr = cpu_to_be64(sei_cont->faddr); 70 eccdf->pec = cpu_to_be16(sei_cont->pec); 71 break; 72 case 2: /* availability event */ 73 accdf = (PciCcdfAvail *)nt2_res->ccdf; 74 accdf->fid = cpu_to_be32(sei_cont->fid); 75 accdf->fh = cpu_to_be32(sei_cont->fh); 76 accdf->pec = cpu_to_be16(sei_cont->pec); 77 break; 78 default: 79 abort(); 80 } 81 g_free(sei_cont); 82 rc = 0; 83 } 84 85 return rc; 86 } 87 88 int chsc_sei_nt2_have_event(void) 89 { 90 S390pciState *s = s390_get_phb(); 91 92 return !QTAILQ_EMPTY(&s->pending_sei); 93 } 94 95 S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s, 96 S390PCIBusDevice *pbdev) 97 { 98 S390PCIBusDevice *ret = pbdev ? QTAILQ_NEXT(pbdev, link) : 99 QTAILQ_FIRST(&s->zpci_devs); 100 101 while (ret && ret->state == ZPCI_FS_RESERVED) { 102 ret = QTAILQ_NEXT(ret, link); 103 } 104 105 return ret; 106 } 107 108 S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid) 109 { 110 S390PCIBusDevice *pbdev; 111 112 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) { 113 if (pbdev->fid == fid) { 114 return pbdev; 115 } 116 } 117 118 return NULL; 119 } 120 121 void s390_pci_sclp_configure(SCCB *sccb) 122 { 123 PciCfgSccb *psccb = (PciCfgSccb *)sccb; 124 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(s390_get_phb(), 125 be32_to_cpu(psccb->aid)); 126 uint16_t rc; 127 128 if (be16_to_cpu(sccb->h.length) < 16) { 129 rc = SCLP_RC_INSUFFICIENT_SCCB_LENGTH; 130 goto out; 131 } 132 133 if (!pbdev) { 134 DPRINTF("sclp config no dev found\n"); 135 rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED; 136 goto out; 137 } 138 139 switch (pbdev->state) { 140 case ZPCI_FS_RESERVED: 141 rc = SCLP_RC_ADAPTER_IN_RESERVED_STATE; 142 break; 143 case ZPCI_FS_STANDBY: 144 pbdev->state = ZPCI_FS_DISABLED; 145 rc = SCLP_RC_NORMAL_COMPLETION; 146 break; 147 default: 148 rc = SCLP_RC_NO_ACTION_REQUIRED; 149 } 150 out: 151 psccb->header.response_code = cpu_to_be16(rc); 152 } 153 154 void s390_pci_sclp_deconfigure(SCCB *sccb) 155 { 156 PciCfgSccb *psccb = (PciCfgSccb *)sccb; 157 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(s390_get_phb(), 158 be32_to_cpu(psccb->aid)); 159 uint16_t rc; 160 161 if (be16_to_cpu(sccb->h.length) < 16) { 162 rc = SCLP_RC_INSUFFICIENT_SCCB_LENGTH; 163 goto out; 164 } 165 166 if (!pbdev) { 167 DPRINTF("sclp deconfig no dev found\n"); 168 rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED; 169 goto out; 170 } 171 172 switch (pbdev->state) { 173 case ZPCI_FS_RESERVED: 174 rc = SCLP_RC_ADAPTER_IN_RESERVED_STATE; 175 break; 176 case ZPCI_FS_STANDBY: 177 rc = SCLP_RC_NO_ACTION_REQUIRED; 178 break; 179 default: 180 if (pbdev->summary_ind) { 181 pci_dereg_irqs(pbdev); 182 } 183 if (pbdev->iommu->enabled) { 184 pci_dereg_ioat(pbdev->iommu); 185 } 186 pbdev->state = ZPCI_FS_STANDBY; 187 rc = SCLP_RC_NORMAL_COMPLETION; 188 189 if (pbdev->release_timer) { 190 qdev_unplug(DEVICE(pbdev->pdev), NULL); 191 } 192 } 193 out: 194 psccb->header.response_code = cpu_to_be16(rc); 195 } 196 197 static S390PCIBusDevice *s390_pci_find_dev_by_uid(S390pciState *s, uint16_t uid) 198 { 199 S390PCIBusDevice *pbdev; 200 201 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) { 202 if (pbdev->uid == uid) { 203 return pbdev; 204 } 205 } 206 207 return NULL; 208 } 209 210 static S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s, 211 const char *target) 212 { 213 S390PCIBusDevice *pbdev; 214 215 if (!target) { 216 return NULL; 217 } 218 219 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) { 220 if (!strcmp(pbdev->target, target)) { 221 return pbdev; 222 } 223 } 224 225 return NULL; 226 } 227 228 S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx) 229 { 230 return g_hash_table_lookup(s->zpci_table, &idx); 231 } 232 233 S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh) 234 { 235 uint32_t idx = FH_MASK_INDEX & fh; 236 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_idx(s, idx); 237 238 if (pbdev && pbdev->fh == fh) { 239 return pbdev; 240 } 241 242 return NULL; 243 } 244 245 static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh, 246 uint32_t fid, uint64_t faddr, uint32_t e) 247 { 248 SeiContainer *sei_cont; 249 S390pciState *s = s390_get_phb(); 250 251 sei_cont = g_malloc0(sizeof(SeiContainer)); 252 sei_cont->fh = fh; 253 sei_cont->fid = fid; 254 sei_cont->cc = cc; 255 sei_cont->pec = pec; 256 sei_cont->faddr = faddr; 257 sei_cont->e = e; 258 259 QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link); 260 css_generate_css_crws(0); 261 } 262 263 static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh, 264 uint32_t fid) 265 { 266 s390_pci_generate_event(2, pec, fh, fid, 0, 0); 267 } 268 269 void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid, 270 uint64_t faddr, uint32_t e) 271 { 272 s390_pci_generate_event(1, pec, fh, fid, faddr, e); 273 } 274 275 static void s390_pci_set_irq(void *opaque, int irq, int level) 276 { 277 /* nothing to do */ 278 } 279 280 static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num) 281 { 282 /* nothing to do */ 283 return 0; 284 } 285 286 static uint64_t s390_pci_get_table_origin(uint64_t iota) 287 { 288 return iota & ~ZPCI_IOTA_RTTO_FLAG; 289 } 290 291 static unsigned int calc_rtx(dma_addr_t ptr) 292 { 293 return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK; 294 } 295 296 static unsigned int calc_sx(dma_addr_t ptr) 297 { 298 return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK; 299 } 300 301 static unsigned int calc_px(dma_addr_t ptr) 302 { 303 return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK; 304 } 305 306 static uint64_t get_rt_sto(uint64_t entry) 307 { 308 return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX) 309 ? (entry & ZPCI_RTE_ADDR_MASK) 310 : 0; 311 } 312 313 static uint64_t get_st_pto(uint64_t entry) 314 { 315 return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX) 316 ? (entry & ZPCI_STE_ADDR_MASK) 317 : 0; 318 } 319 320 static uint64_t s390_guest_io_table_walk(uint64_t guest_iota, 321 uint64_t guest_dma_address) 322 { 323 uint64_t sto_a, pto_a, px_a; 324 uint64_t sto, pto, pte; 325 uint32_t rtx, sx, px; 326 327 rtx = calc_rtx(guest_dma_address); 328 sx = calc_sx(guest_dma_address); 329 px = calc_px(guest_dma_address); 330 331 sto_a = guest_iota + rtx * sizeof(uint64_t); 332 sto = address_space_ldq(&address_space_memory, sto_a, 333 MEMTXATTRS_UNSPECIFIED, NULL); 334 sto = get_rt_sto(sto); 335 if (!sto) { 336 pte = 0; 337 goto out; 338 } 339 340 pto_a = sto + sx * sizeof(uint64_t); 341 pto = address_space_ldq(&address_space_memory, pto_a, 342 MEMTXATTRS_UNSPECIFIED, NULL); 343 pto = get_st_pto(pto); 344 if (!pto) { 345 pte = 0; 346 goto out; 347 } 348 349 px_a = pto + px * sizeof(uint64_t); 350 pte = address_space_ldq(&address_space_memory, px_a, 351 MEMTXATTRS_UNSPECIFIED, NULL); 352 353 out: 354 return pte; 355 } 356 357 static IOMMUTLBEntry s390_translate_iommu(MemoryRegion *mr, hwaddr addr, 358 bool is_write) 359 { 360 uint64_t pte; 361 uint32_t flags; 362 S390PCIIOMMU *iommu = container_of(mr, S390PCIIOMMU, iommu_mr); 363 IOMMUTLBEntry ret = { 364 .target_as = &address_space_memory, 365 .iova = 0, 366 .translated_addr = 0, 367 .addr_mask = ~(hwaddr)0, 368 .perm = IOMMU_NONE, 369 }; 370 371 switch (iommu->pbdev->state) { 372 case ZPCI_FS_ENABLED: 373 case ZPCI_FS_BLOCKED: 374 if (!iommu->enabled) { 375 return ret; 376 } 377 break; 378 default: 379 return ret; 380 } 381 382 DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr); 383 384 if (addr < iommu->pba || addr > iommu->pal) { 385 return ret; 386 } 387 388 pte = s390_guest_io_table_walk(s390_pci_get_table_origin(iommu->g_iota), 389 addr); 390 if (!pte) { 391 return ret; 392 } 393 394 flags = pte & ZPCI_PTE_FLAG_MASK; 395 ret.iova = addr; 396 ret.translated_addr = pte & ZPCI_PTE_ADDR_MASK; 397 ret.addr_mask = 0xfff; 398 399 if (flags & ZPCI_PTE_INVALID) { 400 ret.perm = IOMMU_NONE; 401 } else { 402 ret.perm = IOMMU_RW; 403 } 404 405 return ret; 406 } 407 408 static const MemoryRegionIOMMUOps s390_iommu_ops = { 409 .translate = s390_translate_iommu, 410 }; 411 412 static S390PCIIOMMU *s390_pci_get_iommu(S390pciState *s, PCIBus *bus, 413 int devfn) 414 { 415 uint64_t key = (uintptr_t)bus; 416 S390PCIIOMMUTable *table = g_hash_table_lookup(s->iommu_table, &key); 417 S390PCIIOMMU *iommu; 418 419 if (!table) { 420 table = g_malloc0(sizeof(S390PCIIOMMUTable)); 421 table->key = key; 422 g_hash_table_insert(s->iommu_table, &table->key, table); 423 } 424 425 iommu = table->iommu[PCI_SLOT(devfn)]; 426 if (!iommu) { 427 iommu = S390_PCI_IOMMU(object_new(TYPE_S390_PCI_IOMMU)); 428 429 char *mr_name = g_strdup_printf("iommu-root-%02x:%02x.%01x", 430 pci_bus_num(bus), 431 PCI_SLOT(devfn), 432 PCI_FUNC(devfn)); 433 char *as_name = g_strdup_printf("iommu-pci-%02x:%02x.%01x", 434 pci_bus_num(bus), 435 PCI_SLOT(devfn), 436 PCI_FUNC(devfn)); 437 memory_region_init(&iommu->mr, OBJECT(iommu), mr_name, UINT64_MAX); 438 address_space_init(&iommu->as, &iommu->mr, as_name); 439 table->iommu[PCI_SLOT(devfn)] = iommu; 440 441 g_free(mr_name); 442 g_free(as_name); 443 } 444 445 return iommu; 446 } 447 448 static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 449 { 450 S390pciState *s = opaque; 451 S390PCIIOMMU *iommu = s390_pci_get_iommu(s, bus, devfn); 452 453 return &iommu->as; 454 } 455 456 static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set) 457 { 458 uint8_t ind_old, ind_new; 459 hwaddr len = 1; 460 uint8_t *ind_addr; 461 462 ind_addr = cpu_physical_memory_map(ind_loc, &len, 1); 463 if (!ind_addr) { 464 s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0); 465 return -1; 466 } 467 do { 468 ind_old = *ind_addr; 469 ind_new = ind_old | to_be_set; 470 } while (atomic_cmpxchg(ind_addr, ind_old, ind_new) != ind_old); 471 cpu_physical_memory_unmap(ind_addr, len, 1, len); 472 473 return ind_old; 474 } 475 476 static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data, 477 unsigned int size) 478 { 479 S390PCIBusDevice *pbdev = opaque; 480 uint32_t idx = data >> ZPCI_MSI_VEC_BITS; 481 uint32_t vec = data & ZPCI_MSI_VEC_MASK; 482 uint64_t ind_bit; 483 uint32_t sum_bit; 484 uint32_t e = 0; 485 486 DPRINTF("write_msix data 0x%" PRIx64 " idx %d vec 0x%x\n", data, idx, vec); 487 488 if (!pbdev) { 489 e |= (vec << ERR_EVENT_MVN_OFFSET); 490 s390_pci_generate_error_event(ERR_EVENT_NOMSI, idx, 0, addr, e); 491 return; 492 } 493 494 if (pbdev->state != ZPCI_FS_ENABLED) { 495 return; 496 } 497 498 ind_bit = pbdev->routes.adapter.ind_offset; 499 sum_bit = pbdev->routes.adapter.summary_offset; 500 501 set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8, 502 0x80 >> ((ind_bit + vec) % 8)); 503 if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8, 504 0x80 >> (sum_bit % 8))) { 505 css_adapter_interrupt(pbdev->isc); 506 } 507 } 508 509 static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size) 510 { 511 return 0xffffffff; 512 } 513 514 static const MemoryRegionOps s390_msi_ctrl_ops = { 515 .write = s390_msi_ctrl_write, 516 .read = s390_msi_ctrl_read, 517 .endianness = DEVICE_LITTLE_ENDIAN, 518 }; 519 520 void s390_pci_iommu_enable(S390PCIIOMMU *iommu) 521 { 522 char *name = g_strdup_printf("iommu-s390-%04x", iommu->pbdev->uid); 523 memory_region_init_iommu(&iommu->iommu_mr, OBJECT(&iommu->mr), 524 &s390_iommu_ops, name, iommu->pal + 1); 525 iommu->enabled = true; 526 memory_region_add_subregion(&iommu->mr, 0, &iommu->iommu_mr); 527 g_free(name); 528 } 529 530 void s390_pci_iommu_disable(S390PCIIOMMU *iommu) 531 { 532 iommu->enabled = false; 533 memory_region_del_subregion(&iommu->mr, &iommu->iommu_mr); 534 object_unparent(OBJECT(&iommu->iommu_mr)); 535 } 536 537 static void s390_pci_iommu_free(S390pciState *s, PCIBus *bus, int32_t devfn) 538 { 539 uint64_t key = (uintptr_t)bus; 540 S390PCIIOMMUTable *table = g_hash_table_lookup(s->iommu_table, &key); 541 S390PCIIOMMU *iommu = table ? table->iommu[PCI_SLOT(devfn)] : NULL; 542 543 if (!table || !iommu) { 544 return; 545 } 546 547 table->iommu[PCI_SLOT(devfn)] = NULL; 548 address_space_destroy(&iommu->as); 549 object_unparent(OBJECT(&iommu->mr)); 550 object_unparent(OBJECT(iommu)); 551 object_unref(OBJECT(iommu)); 552 } 553 554 static int s390_pcihost_init(SysBusDevice *dev) 555 { 556 PCIBus *b; 557 BusState *bus; 558 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 559 S390pciState *s = S390_PCI_HOST_BRIDGE(dev); 560 561 DPRINTF("host_init\n"); 562 563 b = pci_register_bus(DEVICE(dev), NULL, 564 s390_pci_set_irq, s390_pci_map_irq, NULL, 565 get_system_memory(), get_system_io(), 0, 64, 566 TYPE_PCI_BUS); 567 pci_setup_iommu(b, s390_pci_dma_iommu, s); 568 569 bus = BUS(b); 570 qbus_set_hotplug_handler(bus, DEVICE(dev), NULL); 571 phb->bus = b; 572 573 s->bus = S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, DEVICE(s), NULL)); 574 qbus_set_hotplug_handler(BUS(s->bus), DEVICE(s), NULL); 575 576 s->iommu_table = g_hash_table_new_full(g_int64_hash, g_int64_equal, 577 NULL, g_free); 578 s->zpci_table = g_hash_table_new_full(g_int_hash, g_int_equal, NULL, NULL); 579 s->bus_no = 0; 580 QTAILQ_INIT(&s->pending_sei); 581 QTAILQ_INIT(&s->zpci_devs); 582 return 0; 583 } 584 585 static int s390_pci_msix_init(S390PCIBusDevice *pbdev) 586 { 587 char *name; 588 uint8_t pos; 589 uint16_t ctrl; 590 uint32_t table, pba; 591 592 pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX); 593 if (!pos) { 594 pbdev->msix.available = false; 595 return -1; 596 } 597 598 ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_FLAGS, 599 pci_config_size(pbdev->pdev), sizeof(ctrl)); 600 table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE, 601 pci_config_size(pbdev->pdev), sizeof(table)); 602 pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA, 603 pci_config_size(pbdev->pdev), sizeof(pba)); 604 605 pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK; 606 pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK; 607 pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK; 608 pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK; 609 pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 610 pbdev->msix.available = true; 611 612 name = g_strdup_printf("msix-s390-%04x", pbdev->uid); 613 memory_region_init_io(&pbdev->msix_notify_mr, OBJECT(pbdev), 614 &s390_msi_ctrl_ops, pbdev, name, PAGE_SIZE); 615 memory_region_add_subregion(&pbdev->iommu->mr, ZPCI_MSI_ADDR, 616 &pbdev->msix_notify_mr); 617 g_free(name); 618 619 return 0; 620 } 621 622 static void s390_pci_msix_free(S390PCIBusDevice *pbdev) 623 { 624 memory_region_del_subregion(&pbdev->iommu->mr, &pbdev->msix_notify_mr); 625 object_unparent(OBJECT(&pbdev->msix_notify_mr)); 626 } 627 628 static S390PCIBusDevice *s390_pci_device_new(S390pciState *s, 629 const char *target) 630 { 631 DeviceState *dev = NULL; 632 633 dev = qdev_try_create(BUS(s->bus), TYPE_S390_PCI_DEVICE); 634 if (!dev) { 635 return NULL; 636 } 637 638 qdev_prop_set_string(dev, "target", target); 639 qdev_init_nofail(dev); 640 641 return S390_PCI_DEVICE(dev); 642 } 643 644 static bool s390_pci_alloc_idx(S390pciState *s, S390PCIBusDevice *pbdev) 645 { 646 uint32_t idx; 647 648 idx = s->next_idx; 649 while (s390_pci_find_dev_by_idx(s, idx)) { 650 idx = (idx + 1) & FH_MASK_INDEX; 651 if (idx == s->next_idx) { 652 return false; 653 } 654 } 655 656 pbdev->idx = idx; 657 s->next_idx = (idx + 1) & FH_MASK_INDEX; 658 659 return true; 660 } 661 662 static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev, 663 DeviceState *dev, Error **errp) 664 { 665 PCIDevice *pdev = NULL; 666 S390PCIBusDevice *pbdev = NULL; 667 S390pciState *s = s390_get_phb(); 668 669 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 670 BusState *bus; 671 PCIBridge *pb = PCI_BRIDGE(dev); 672 PCIDevice *pdev = PCI_DEVICE(dev); 673 674 pci_bridge_map_irq(pb, dev->id, s390_pci_map_irq); 675 pci_setup_iommu(&pb->sec_bus, s390_pci_dma_iommu, s); 676 677 bus = BUS(&pb->sec_bus); 678 qbus_set_hotplug_handler(bus, DEVICE(s), errp); 679 680 if (dev->hotplugged) { 681 pci_default_write_config(pdev, PCI_PRIMARY_BUS, s->bus_no, 1); 682 s->bus_no += 1; 683 pci_default_write_config(pdev, PCI_SECONDARY_BUS, s->bus_no, 1); 684 do { 685 pdev = pdev->bus->parent_dev; 686 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, 687 s->bus_no, 1); 688 } while (pdev->bus && pci_bus_num(pdev->bus)); 689 } 690 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 691 pdev = PCI_DEVICE(dev); 692 693 if (!dev->id) { 694 /* In the case the PCI device does not define an id */ 695 /* we generate one based on the PCI address */ 696 dev->id = g_strdup_printf("auto_%02x:%02x.%01x", 697 pci_bus_num(pdev->bus), 698 PCI_SLOT(pdev->devfn), 699 PCI_FUNC(pdev->devfn)); 700 } 701 702 pbdev = s390_pci_find_dev_by_target(s, dev->id); 703 if (!pbdev) { 704 pbdev = s390_pci_device_new(s, dev->id); 705 if (!pbdev) { 706 error_setg(errp, "create zpci device failed"); 707 return; 708 } 709 } 710 711 if (object_dynamic_cast(OBJECT(dev), "vfio-pci")) { 712 pbdev->fh |= FH_SHM_VFIO; 713 } else { 714 pbdev->fh |= FH_SHM_EMUL; 715 } 716 717 pbdev->pdev = pdev; 718 pbdev->iommu = s390_pci_get_iommu(s, pdev->bus, pdev->devfn); 719 pbdev->iommu->pbdev = pbdev; 720 pbdev->state = ZPCI_FS_STANDBY; 721 722 if (s390_pci_msix_init(pbdev)) { 723 error_setg(errp, "MSI-X support is mandatory " 724 "in the S390 architecture"); 725 return; 726 } 727 728 if (dev->hotplugged) { 729 s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY, 730 pbdev->fh, pbdev->fid); 731 } 732 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) { 733 pbdev = S390_PCI_DEVICE(dev); 734 735 if (!s390_pci_alloc_idx(s, pbdev)) { 736 error_setg(errp, "no slot for plugging zpci device"); 737 return; 738 } 739 pbdev->fh = pbdev->idx; 740 QTAILQ_INSERT_TAIL(&s->zpci_devs, pbdev, link); 741 g_hash_table_insert(s->zpci_table, &pbdev->idx, pbdev); 742 } 743 } 744 745 static void s390_pcihost_timer_cb(void *opaque) 746 { 747 S390PCIBusDevice *pbdev = opaque; 748 749 if (pbdev->summary_ind) { 750 pci_dereg_irqs(pbdev); 751 } 752 if (pbdev->iommu->enabled) { 753 pci_dereg_ioat(pbdev->iommu); 754 } 755 756 pbdev->state = ZPCI_FS_STANDBY; 757 s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES, 758 pbdev->fh, pbdev->fid); 759 qdev_unplug(DEVICE(pbdev), NULL); 760 } 761 762 static void s390_pcihost_hot_unplug(HotplugHandler *hotplug_dev, 763 DeviceState *dev, Error **errp) 764 { 765 PCIDevice *pci_dev = NULL; 766 PCIBus *bus; 767 int32_t devfn; 768 S390PCIBusDevice *pbdev = NULL; 769 S390pciState *s = s390_get_phb(); 770 771 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 772 error_setg(errp, "PCI bridge hot unplug currently not supported"); 773 return; 774 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 775 pci_dev = PCI_DEVICE(dev); 776 777 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) { 778 if (pbdev->pdev == pci_dev) { 779 break; 780 } 781 } 782 assert(pbdev != NULL); 783 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) { 784 pbdev = S390_PCI_DEVICE(dev); 785 pci_dev = pbdev->pdev; 786 } 787 788 switch (pbdev->state) { 789 case ZPCI_FS_RESERVED: 790 goto out; 791 case ZPCI_FS_STANDBY: 792 break; 793 default: 794 s390_pci_generate_plug_event(HP_EVENT_DECONFIGURE_REQUEST, 795 pbdev->fh, pbdev->fid); 796 pbdev->release_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 797 s390_pcihost_timer_cb, 798 pbdev); 799 timer_mod(pbdev->release_timer, 800 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + HOT_UNPLUG_TIMEOUT); 801 return; 802 } 803 804 if (pbdev->release_timer && timer_pending(pbdev->release_timer)) { 805 timer_del(pbdev->release_timer); 806 timer_free(pbdev->release_timer); 807 pbdev->release_timer = NULL; 808 } 809 810 s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED, 811 pbdev->fh, pbdev->fid); 812 bus = pci_dev->bus; 813 devfn = pci_dev->devfn; 814 object_unparent(OBJECT(pci_dev)); 815 s390_pci_msix_free(pbdev); 816 s390_pci_iommu_free(s, bus, devfn); 817 pbdev->pdev = NULL; 818 pbdev->state = ZPCI_FS_RESERVED; 819 out: 820 pbdev->fid = 0; 821 QTAILQ_REMOVE(&s->zpci_devs, pbdev, link); 822 g_hash_table_remove(s->zpci_table, &pbdev->idx); 823 object_unparent(OBJECT(pbdev)); 824 } 825 826 static void s390_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 827 void *opaque) 828 { 829 S390pciState *s = opaque; 830 unsigned int primary = s->bus_no; 831 unsigned int subordinate = 0xff; 832 PCIBus *sec_bus = NULL; 833 834 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 835 PCI_HEADER_TYPE_BRIDGE)) { 836 return; 837 } 838 839 (s->bus_no)++; 840 pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); 841 pci_default_write_config(pdev, PCI_SECONDARY_BUS, s->bus_no, 1); 842 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, s->bus_no, 1); 843 844 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 845 if (!sec_bus) { 846 return; 847 } 848 849 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); 850 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 851 s390_pci_enumerate_bridge, s); 852 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, s->bus_no, 1); 853 } 854 855 static void s390_pcihost_reset(DeviceState *dev) 856 { 857 S390pciState *s = S390_PCI_HOST_BRIDGE(dev); 858 PCIBus *bus = s->parent_obj.bus; 859 860 s->bus_no = 0; 861 pci_for_each_device(bus, pci_bus_num(bus), s390_pci_enumerate_bridge, s); 862 } 863 864 static void s390_pcihost_class_init(ObjectClass *klass, void *data) 865 { 866 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 867 DeviceClass *dc = DEVICE_CLASS(klass); 868 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 869 870 dc->cannot_instantiate_with_device_add_yet = true; 871 dc->reset = s390_pcihost_reset; 872 k->init = s390_pcihost_init; 873 hc->plug = s390_pcihost_hot_plug; 874 hc->unplug = s390_pcihost_hot_unplug; 875 msi_nonbroken = true; 876 } 877 878 static const TypeInfo s390_pcihost_info = { 879 .name = TYPE_S390_PCI_HOST_BRIDGE, 880 .parent = TYPE_PCI_HOST_BRIDGE, 881 .instance_size = sizeof(S390pciState), 882 .class_init = s390_pcihost_class_init, 883 .interfaces = (InterfaceInfo[]) { 884 { TYPE_HOTPLUG_HANDLER }, 885 { } 886 } 887 }; 888 889 static const TypeInfo s390_pcibus_info = { 890 .name = TYPE_S390_PCI_BUS, 891 .parent = TYPE_BUS, 892 .instance_size = sizeof(S390PCIBus), 893 }; 894 895 static uint16_t s390_pci_generate_uid(S390pciState *s) 896 { 897 uint16_t uid = 0; 898 899 do { 900 uid++; 901 if (!s390_pci_find_dev_by_uid(s, uid)) { 902 return uid; 903 } 904 } while (uid < ZPCI_MAX_UID); 905 906 return UID_UNDEFINED; 907 } 908 909 static uint32_t s390_pci_generate_fid(S390pciState *s, Error **errp) 910 { 911 uint32_t fid = 0; 912 913 do { 914 if (!s390_pci_find_dev_by_fid(s, fid)) { 915 return fid; 916 } 917 } while (fid++ != ZPCI_MAX_FID); 918 919 error_setg(errp, "no free fid could be found"); 920 return 0; 921 } 922 923 static void s390_pci_device_realize(DeviceState *dev, Error **errp) 924 { 925 S390PCIBusDevice *zpci = S390_PCI_DEVICE(dev); 926 S390pciState *s = s390_get_phb(); 927 928 if (!zpci->target) { 929 error_setg(errp, "target must be defined"); 930 return; 931 } 932 933 if (s390_pci_find_dev_by_target(s, zpci->target)) { 934 error_setg(errp, "target %s already has an associated zpci device", 935 zpci->target); 936 return; 937 } 938 939 if (zpci->uid == UID_UNDEFINED) { 940 zpci->uid = s390_pci_generate_uid(s); 941 if (!zpci->uid) { 942 error_setg(errp, "no free uid could be found"); 943 return; 944 } 945 } else if (s390_pci_find_dev_by_uid(s, zpci->uid)) { 946 error_setg(errp, "uid %u already in use", zpci->uid); 947 return; 948 } 949 950 if (!zpci->fid_defined) { 951 Error *local_error = NULL; 952 953 zpci->fid = s390_pci_generate_fid(s, &local_error); 954 if (local_error) { 955 error_propagate(errp, local_error); 956 return; 957 } 958 } else if (s390_pci_find_dev_by_fid(s, zpci->fid)) { 959 error_setg(errp, "fid %u already in use", zpci->fid); 960 return; 961 } 962 963 zpci->state = ZPCI_FS_RESERVED; 964 } 965 966 static void s390_pci_device_reset(DeviceState *dev) 967 { 968 S390PCIBusDevice *pbdev = S390_PCI_DEVICE(dev); 969 970 switch (pbdev->state) { 971 case ZPCI_FS_RESERVED: 972 return; 973 case ZPCI_FS_STANDBY: 974 break; 975 default: 976 pbdev->fh &= ~FH_MASK_ENABLE; 977 pbdev->state = ZPCI_FS_DISABLED; 978 break; 979 } 980 981 if (pbdev->summary_ind) { 982 pci_dereg_irqs(pbdev); 983 } 984 if (pbdev->iommu->enabled) { 985 pci_dereg_ioat(pbdev->iommu); 986 } 987 988 pbdev->fmb_addr = 0; 989 } 990 991 static void s390_pci_get_fid(Object *obj, Visitor *v, const char *name, 992 void *opaque, Error **errp) 993 { 994 Property *prop = opaque; 995 uint32_t *ptr = qdev_get_prop_ptr(DEVICE(obj), prop); 996 997 visit_type_uint32(v, name, ptr, errp); 998 } 999 1000 static void s390_pci_set_fid(Object *obj, Visitor *v, const char *name, 1001 void *opaque, Error **errp) 1002 { 1003 DeviceState *dev = DEVICE(obj); 1004 S390PCIBusDevice *zpci = S390_PCI_DEVICE(obj); 1005 Property *prop = opaque; 1006 uint32_t *ptr = qdev_get_prop_ptr(dev, prop); 1007 1008 if (dev->realized) { 1009 qdev_prop_set_after_realize(dev, name, errp); 1010 return; 1011 } 1012 1013 visit_type_uint32(v, name, ptr, errp); 1014 zpci->fid_defined = true; 1015 } 1016 1017 static PropertyInfo s390_pci_fid_propinfo = { 1018 .name = "zpci_fid", 1019 .get = s390_pci_get_fid, 1020 .set = s390_pci_set_fid, 1021 }; 1022 1023 #define DEFINE_PROP_S390_PCI_FID(_n, _s, _f) \ 1024 DEFINE_PROP(_n, _s, _f, s390_pci_fid_propinfo, uint32_t) 1025 1026 static Property s390_pci_device_properties[] = { 1027 DEFINE_PROP_UINT16("uid", S390PCIBusDevice, uid, UID_UNDEFINED), 1028 DEFINE_PROP_S390_PCI_FID("fid", S390PCIBusDevice, fid), 1029 DEFINE_PROP_STRING("target", S390PCIBusDevice, target), 1030 DEFINE_PROP_END_OF_LIST(), 1031 }; 1032 1033 static void s390_pci_device_class_init(ObjectClass *klass, void *data) 1034 { 1035 DeviceClass *dc = DEVICE_CLASS(klass); 1036 1037 dc->desc = "zpci device"; 1038 dc->reset = s390_pci_device_reset; 1039 dc->bus_type = TYPE_S390_PCI_BUS; 1040 dc->realize = s390_pci_device_realize; 1041 dc->props = s390_pci_device_properties; 1042 } 1043 1044 static const TypeInfo s390_pci_device_info = { 1045 .name = TYPE_S390_PCI_DEVICE, 1046 .parent = TYPE_DEVICE, 1047 .instance_size = sizeof(S390PCIBusDevice), 1048 .class_init = s390_pci_device_class_init, 1049 }; 1050 1051 static TypeInfo s390_pci_iommu_info = { 1052 .name = TYPE_S390_PCI_IOMMU, 1053 .parent = TYPE_OBJECT, 1054 .instance_size = sizeof(S390PCIIOMMU), 1055 }; 1056 1057 static void s390_pci_register_types(void) 1058 { 1059 type_register_static(&s390_pcihost_info); 1060 type_register_static(&s390_pcibus_info); 1061 type_register_static(&s390_pci_device_info); 1062 type_register_static(&s390_pci_iommu_info); 1063 } 1064 1065 type_init(s390_pci_register_types) 1066