1 /* 2 * s390 PCI BUS 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qapi/error.h" 16 #include "qapi/visitor.h" 17 #include "qemu-common.h" 18 #include "cpu.h" 19 #include "s390-pci-bus.h" 20 #include "s390-pci-inst.h" 21 #include "hw/pci/pci_bus.h" 22 #include "hw/pci/pci_bridge.h" 23 #include "hw/pci/msi.h" 24 #include "qemu/error-report.h" 25 26 #ifndef DEBUG_S390PCI_BUS 27 #define DEBUG_S390PCI_BUS 0 28 #endif 29 30 #define DPRINTF(fmt, ...) \ 31 do { \ 32 if (DEBUG_S390PCI_BUS) { \ 33 fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); \ 34 } \ 35 } while (0) 36 37 S390pciState *s390_get_phb(void) 38 { 39 static S390pciState *phb; 40 41 if (!phb) { 42 phb = S390_PCI_HOST_BRIDGE( 43 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL)); 44 assert(phb != NULL); 45 } 46 47 return phb; 48 } 49 50 int pci_chsc_sei_nt2_get_event(void *res) 51 { 52 ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res; 53 PciCcdfAvail *accdf; 54 PciCcdfErr *eccdf; 55 int rc = 1; 56 SeiContainer *sei_cont; 57 S390pciState *s = s390_get_phb(); 58 59 sei_cont = QTAILQ_FIRST(&s->pending_sei); 60 if (sei_cont) { 61 QTAILQ_REMOVE(&s->pending_sei, sei_cont, link); 62 nt2_res->nt = 2; 63 nt2_res->cc = sei_cont->cc; 64 nt2_res->length = cpu_to_be16(sizeof(ChscSeiNt2Res)); 65 switch (sei_cont->cc) { 66 case 1: /* error event */ 67 eccdf = (PciCcdfErr *)nt2_res->ccdf; 68 eccdf->fid = cpu_to_be32(sei_cont->fid); 69 eccdf->fh = cpu_to_be32(sei_cont->fh); 70 eccdf->e = cpu_to_be32(sei_cont->e); 71 eccdf->faddr = cpu_to_be64(sei_cont->faddr); 72 eccdf->pec = cpu_to_be16(sei_cont->pec); 73 break; 74 case 2: /* availability event */ 75 accdf = (PciCcdfAvail *)nt2_res->ccdf; 76 accdf->fid = cpu_to_be32(sei_cont->fid); 77 accdf->fh = cpu_to_be32(sei_cont->fh); 78 accdf->pec = cpu_to_be16(sei_cont->pec); 79 break; 80 default: 81 abort(); 82 } 83 g_free(sei_cont); 84 rc = 0; 85 } 86 87 return rc; 88 } 89 90 int pci_chsc_sei_nt2_have_event(void) 91 { 92 S390pciState *s = s390_get_phb(); 93 94 return !QTAILQ_EMPTY(&s->pending_sei); 95 } 96 97 S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s, 98 S390PCIBusDevice *pbdev) 99 { 100 S390PCIBusDevice *ret = pbdev ? QTAILQ_NEXT(pbdev, link) : 101 QTAILQ_FIRST(&s->zpci_devs); 102 103 while (ret && ret->state == ZPCI_FS_RESERVED) { 104 ret = QTAILQ_NEXT(ret, link); 105 } 106 107 return ret; 108 } 109 110 S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid) 111 { 112 S390PCIBusDevice *pbdev; 113 114 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) { 115 if (pbdev->fid == fid) { 116 return pbdev; 117 } 118 } 119 120 return NULL; 121 } 122 123 void s390_pci_sclp_configure(SCCB *sccb) 124 { 125 IoaCfgSccb *psccb = (IoaCfgSccb *)sccb; 126 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(s390_get_phb(), 127 be32_to_cpu(psccb->aid)); 128 uint16_t rc; 129 130 if (!pbdev) { 131 DPRINTF("sclp config no dev found\n"); 132 rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED; 133 goto out; 134 } 135 136 switch (pbdev->state) { 137 case ZPCI_FS_RESERVED: 138 rc = SCLP_RC_ADAPTER_IN_RESERVED_STATE; 139 break; 140 case ZPCI_FS_STANDBY: 141 pbdev->state = ZPCI_FS_DISABLED; 142 rc = SCLP_RC_NORMAL_COMPLETION; 143 break; 144 default: 145 rc = SCLP_RC_NO_ACTION_REQUIRED; 146 } 147 out: 148 psccb->header.response_code = cpu_to_be16(rc); 149 } 150 151 void s390_pci_sclp_deconfigure(SCCB *sccb) 152 { 153 IoaCfgSccb *psccb = (IoaCfgSccb *)sccb; 154 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(s390_get_phb(), 155 be32_to_cpu(psccb->aid)); 156 uint16_t rc; 157 158 if (!pbdev) { 159 DPRINTF("sclp deconfig no dev found\n"); 160 rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED; 161 goto out; 162 } 163 164 switch (pbdev->state) { 165 case ZPCI_FS_RESERVED: 166 rc = SCLP_RC_ADAPTER_IN_RESERVED_STATE; 167 break; 168 case ZPCI_FS_STANDBY: 169 rc = SCLP_RC_NO_ACTION_REQUIRED; 170 break; 171 default: 172 if (pbdev->summary_ind) { 173 pci_dereg_irqs(pbdev); 174 } 175 if (pbdev->iommu->enabled) { 176 pci_dereg_ioat(pbdev->iommu); 177 } 178 pbdev->state = ZPCI_FS_STANDBY; 179 rc = SCLP_RC_NORMAL_COMPLETION; 180 181 if (pbdev->release_timer) { 182 qdev_unplug(DEVICE(pbdev->pdev), NULL); 183 } 184 } 185 out: 186 psccb->header.response_code = cpu_to_be16(rc); 187 } 188 189 static S390PCIBusDevice *s390_pci_find_dev_by_uid(S390pciState *s, uint16_t uid) 190 { 191 S390PCIBusDevice *pbdev; 192 193 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) { 194 if (pbdev->uid == uid) { 195 return pbdev; 196 } 197 } 198 199 return NULL; 200 } 201 202 static S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s, 203 const char *target) 204 { 205 S390PCIBusDevice *pbdev; 206 207 if (!target) { 208 return NULL; 209 } 210 211 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) { 212 if (!strcmp(pbdev->target, target)) { 213 return pbdev; 214 } 215 } 216 217 return NULL; 218 } 219 220 S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx) 221 { 222 return g_hash_table_lookup(s->zpci_table, &idx); 223 } 224 225 S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh) 226 { 227 uint32_t idx = FH_MASK_INDEX & fh; 228 S390PCIBusDevice *pbdev = s390_pci_find_dev_by_idx(s, idx); 229 230 if (pbdev && pbdev->fh == fh) { 231 return pbdev; 232 } 233 234 return NULL; 235 } 236 237 static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh, 238 uint32_t fid, uint64_t faddr, uint32_t e) 239 { 240 SeiContainer *sei_cont; 241 S390pciState *s = s390_get_phb(); 242 243 sei_cont = g_malloc0(sizeof(SeiContainer)); 244 sei_cont->fh = fh; 245 sei_cont->fid = fid; 246 sei_cont->cc = cc; 247 sei_cont->pec = pec; 248 sei_cont->faddr = faddr; 249 sei_cont->e = e; 250 251 QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link); 252 css_generate_css_crws(0); 253 } 254 255 static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh, 256 uint32_t fid) 257 { 258 s390_pci_generate_event(2, pec, fh, fid, 0, 0); 259 } 260 261 void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid, 262 uint64_t faddr, uint32_t e) 263 { 264 s390_pci_generate_event(1, pec, fh, fid, faddr, e); 265 } 266 267 static void s390_pci_set_irq(void *opaque, int irq, int level) 268 { 269 /* nothing to do */ 270 } 271 272 static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num) 273 { 274 /* nothing to do */ 275 return 0; 276 } 277 278 static uint64_t s390_pci_get_table_origin(uint64_t iota) 279 { 280 return iota & ~ZPCI_IOTA_RTTO_FLAG; 281 } 282 283 static unsigned int calc_rtx(dma_addr_t ptr) 284 { 285 return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK; 286 } 287 288 static unsigned int calc_sx(dma_addr_t ptr) 289 { 290 return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK; 291 } 292 293 static unsigned int calc_px(dma_addr_t ptr) 294 { 295 return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK; 296 } 297 298 static uint64_t get_rt_sto(uint64_t entry) 299 { 300 return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX) 301 ? (entry & ZPCI_RTE_ADDR_MASK) 302 : 0; 303 } 304 305 static uint64_t get_st_pto(uint64_t entry) 306 { 307 return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX) 308 ? (entry & ZPCI_STE_ADDR_MASK) 309 : 0; 310 } 311 312 static uint64_t s390_guest_io_table_walk(uint64_t guest_iota, 313 uint64_t guest_dma_address) 314 { 315 uint64_t sto_a, pto_a, px_a; 316 uint64_t sto, pto, pte; 317 uint32_t rtx, sx, px; 318 319 rtx = calc_rtx(guest_dma_address); 320 sx = calc_sx(guest_dma_address); 321 px = calc_px(guest_dma_address); 322 323 sto_a = guest_iota + rtx * sizeof(uint64_t); 324 sto = address_space_ldq(&address_space_memory, sto_a, 325 MEMTXATTRS_UNSPECIFIED, NULL); 326 sto = get_rt_sto(sto); 327 if (!sto) { 328 pte = 0; 329 goto out; 330 } 331 332 pto_a = sto + sx * sizeof(uint64_t); 333 pto = address_space_ldq(&address_space_memory, pto_a, 334 MEMTXATTRS_UNSPECIFIED, NULL); 335 pto = get_st_pto(pto); 336 if (!pto) { 337 pte = 0; 338 goto out; 339 } 340 341 px_a = pto + px * sizeof(uint64_t); 342 pte = address_space_ldq(&address_space_memory, px_a, 343 MEMTXATTRS_UNSPECIFIED, NULL); 344 345 out: 346 return pte; 347 } 348 349 static IOMMUTLBEntry s390_translate_iommu(IOMMUMemoryRegion *mr, hwaddr addr, 350 IOMMUAccessFlags flag) 351 { 352 uint64_t pte; 353 uint32_t flags; 354 S390PCIIOMMU *iommu = container_of(mr, S390PCIIOMMU, iommu_mr); 355 IOMMUTLBEntry ret = { 356 .target_as = &address_space_memory, 357 .iova = 0, 358 .translated_addr = 0, 359 .addr_mask = ~(hwaddr)0, 360 .perm = IOMMU_NONE, 361 }; 362 363 switch (iommu->pbdev->state) { 364 case ZPCI_FS_ENABLED: 365 case ZPCI_FS_BLOCKED: 366 if (!iommu->enabled) { 367 return ret; 368 } 369 break; 370 default: 371 return ret; 372 } 373 374 DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr); 375 376 if (addr < iommu->pba || addr > iommu->pal) { 377 return ret; 378 } 379 380 pte = s390_guest_io_table_walk(s390_pci_get_table_origin(iommu->g_iota), 381 addr); 382 if (!pte) { 383 return ret; 384 } 385 386 flags = pte & ZPCI_PTE_FLAG_MASK; 387 ret.iova = addr; 388 ret.translated_addr = pte & ZPCI_PTE_ADDR_MASK; 389 ret.addr_mask = 0xfff; 390 391 if (flags & ZPCI_PTE_INVALID) { 392 ret.perm = IOMMU_NONE; 393 } else { 394 ret.perm = IOMMU_RW; 395 } 396 397 return ret; 398 } 399 400 static S390PCIIOMMU *s390_pci_get_iommu(S390pciState *s, PCIBus *bus, 401 int devfn) 402 { 403 uint64_t key = (uintptr_t)bus; 404 S390PCIIOMMUTable *table = g_hash_table_lookup(s->iommu_table, &key); 405 S390PCIIOMMU *iommu; 406 407 if (!table) { 408 table = g_malloc0(sizeof(S390PCIIOMMUTable)); 409 table->key = key; 410 g_hash_table_insert(s->iommu_table, &table->key, table); 411 } 412 413 iommu = table->iommu[PCI_SLOT(devfn)]; 414 if (!iommu) { 415 iommu = S390_PCI_IOMMU(object_new(TYPE_S390_PCI_IOMMU)); 416 417 char *mr_name = g_strdup_printf("iommu-root-%02x:%02x.%01x", 418 pci_bus_num(bus), 419 PCI_SLOT(devfn), 420 PCI_FUNC(devfn)); 421 char *as_name = g_strdup_printf("iommu-pci-%02x:%02x.%01x", 422 pci_bus_num(bus), 423 PCI_SLOT(devfn), 424 PCI_FUNC(devfn)); 425 memory_region_init(&iommu->mr, OBJECT(iommu), mr_name, UINT64_MAX); 426 address_space_init(&iommu->as, &iommu->mr, as_name); 427 table->iommu[PCI_SLOT(devfn)] = iommu; 428 429 g_free(mr_name); 430 g_free(as_name); 431 } 432 433 return iommu; 434 } 435 436 static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 437 { 438 S390pciState *s = opaque; 439 S390PCIIOMMU *iommu = s390_pci_get_iommu(s, bus, devfn); 440 441 return &iommu->as; 442 } 443 444 static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set) 445 { 446 uint8_t ind_old, ind_new; 447 hwaddr len = 1; 448 uint8_t *ind_addr; 449 450 ind_addr = cpu_physical_memory_map(ind_loc, &len, 1); 451 if (!ind_addr) { 452 s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0); 453 return -1; 454 } 455 do { 456 ind_old = *ind_addr; 457 ind_new = ind_old | to_be_set; 458 } while (atomic_cmpxchg(ind_addr, ind_old, ind_new) != ind_old); 459 cpu_physical_memory_unmap(ind_addr, len, 1, len); 460 461 return ind_old; 462 } 463 464 static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data, 465 unsigned int size) 466 { 467 S390PCIBusDevice *pbdev = opaque; 468 uint32_t idx = data >> ZPCI_MSI_VEC_BITS; 469 uint32_t vec = data & ZPCI_MSI_VEC_MASK; 470 uint64_t ind_bit; 471 uint32_t sum_bit; 472 uint32_t e = 0; 473 474 DPRINTF("write_msix data 0x%" PRIx64 " idx %d vec 0x%x\n", data, idx, vec); 475 476 if (!pbdev) { 477 e |= (vec << ERR_EVENT_MVN_OFFSET); 478 s390_pci_generate_error_event(ERR_EVENT_NOMSI, idx, 0, addr, e); 479 return; 480 } 481 482 if (pbdev->state != ZPCI_FS_ENABLED) { 483 return; 484 } 485 486 ind_bit = pbdev->routes.adapter.ind_offset; 487 sum_bit = pbdev->routes.adapter.summary_offset; 488 489 set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8, 490 0x80 >> ((ind_bit + vec) % 8)); 491 if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8, 492 0x80 >> (sum_bit % 8))) { 493 css_adapter_interrupt(CSS_IO_ADAPTER_PCI, pbdev->isc); 494 } 495 } 496 497 static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size) 498 { 499 return 0xffffffff; 500 } 501 502 static const MemoryRegionOps s390_msi_ctrl_ops = { 503 .write = s390_msi_ctrl_write, 504 .read = s390_msi_ctrl_read, 505 .endianness = DEVICE_LITTLE_ENDIAN, 506 }; 507 508 void s390_pci_iommu_enable(S390PCIIOMMU *iommu) 509 { 510 char *name = g_strdup_printf("iommu-s390-%04x", iommu->pbdev->uid); 511 memory_region_init_iommu(&iommu->iommu_mr, sizeof(iommu->iommu_mr), 512 TYPE_S390_IOMMU_MEMORY_REGION, OBJECT(&iommu->mr), 513 name, iommu->pal + 1); 514 iommu->enabled = true; 515 memory_region_add_subregion(&iommu->mr, 0, MEMORY_REGION(&iommu->iommu_mr)); 516 g_free(name); 517 } 518 519 void s390_pci_iommu_disable(S390PCIIOMMU *iommu) 520 { 521 iommu->enabled = false; 522 memory_region_del_subregion(&iommu->mr, MEMORY_REGION(&iommu->iommu_mr)); 523 object_unparent(OBJECT(&iommu->iommu_mr)); 524 } 525 526 static void s390_pci_iommu_free(S390pciState *s, PCIBus *bus, int32_t devfn) 527 { 528 uint64_t key = (uintptr_t)bus; 529 S390PCIIOMMUTable *table = g_hash_table_lookup(s->iommu_table, &key); 530 S390PCIIOMMU *iommu = table ? table->iommu[PCI_SLOT(devfn)] : NULL; 531 532 if (!table || !iommu) { 533 return; 534 } 535 536 table->iommu[PCI_SLOT(devfn)] = NULL; 537 address_space_destroy(&iommu->as); 538 object_unparent(OBJECT(&iommu->mr)); 539 object_unparent(OBJECT(iommu)); 540 object_unref(OBJECT(iommu)); 541 } 542 543 static int s390_pcihost_init(SysBusDevice *dev) 544 { 545 PCIBus *b; 546 BusState *bus; 547 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 548 S390pciState *s = S390_PCI_HOST_BRIDGE(dev); 549 550 DPRINTF("host_init\n"); 551 552 b = pci_register_bus(DEVICE(dev), NULL, 553 s390_pci_set_irq, s390_pci_map_irq, NULL, 554 get_system_memory(), get_system_io(), 0, 64, 555 TYPE_PCI_BUS); 556 pci_setup_iommu(b, s390_pci_dma_iommu, s); 557 558 bus = BUS(b); 559 qbus_set_hotplug_handler(bus, DEVICE(dev), NULL); 560 phb->bus = b; 561 562 s->bus = S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, DEVICE(s), NULL)); 563 qbus_set_hotplug_handler(BUS(s->bus), DEVICE(s), NULL); 564 565 s->iommu_table = g_hash_table_new_full(g_int64_hash, g_int64_equal, 566 NULL, g_free); 567 s->zpci_table = g_hash_table_new_full(g_int_hash, g_int_equal, NULL, NULL); 568 s->bus_no = 0; 569 QTAILQ_INIT(&s->pending_sei); 570 QTAILQ_INIT(&s->zpci_devs); 571 572 css_register_io_adapters(CSS_IO_ADAPTER_PCI, true, false, 573 S390_ADAPTER_SUPPRESSIBLE, &error_abort); 574 575 return 0; 576 } 577 578 static int s390_pci_msix_init(S390PCIBusDevice *pbdev) 579 { 580 char *name; 581 uint8_t pos; 582 uint16_t ctrl; 583 uint32_t table, pba; 584 585 pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX); 586 if (!pos) { 587 pbdev->msix.available = false; 588 return -1; 589 } 590 591 ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_FLAGS, 592 pci_config_size(pbdev->pdev), sizeof(ctrl)); 593 table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE, 594 pci_config_size(pbdev->pdev), sizeof(table)); 595 pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA, 596 pci_config_size(pbdev->pdev), sizeof(pba)); 597 598 pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK; 599 pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK; 600 pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK; 601 pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK; 602 pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 603 pbdev->msix.available = true; 604 605 name = g_strdup_printf("msix-s390-%04x", pbdev->uid); 606 memory_region_init_io(&pbdev->msix_notify_mr, OBJECT(pbdev), 607 &s390_msi_ctrl_ops, pbdev, name, PAGE_SIZE); 608 memory_region_add_subregion(&pbdev->iommu->mr, ZPCI_MSI_ADDR, 609 &pbdev->msix_notify_mr); 610 g_free(name); 611 612 return 0; 613 } 614 615 static void s390_pci_msix_free(S390PCIBusDevice *pbdev) 616 { 617 memory_region_del_subregion(&pbdev->iommu->mr, &pbdev->msix_notify_mr); 618 object_unparent(OBJECT(&pbdev->msix_notify_mr)); 619 } 620 621 static S390PCIBusDevice *s390_pci_device_new(S390pciState *s, 622 const char *target) 623 { 624 DeviceState *dev = NULL; 625 626 dev = qdev_try_create(BUS(s->bus), TYPE_S390_PCI_DEVICE); 627 if (!dev) { 628 return NULL; 629 } 630 631 qdev_prop_set_string(dev, "target", target); 632 qdev_init_nofail(dev); 633 634 return S390_PCI_DEVICE(dev); 635 } 636 637 static bool s390_pci_alloc_idx(S390pciState *s, S390PCIBusDevice *pbdev) 638 { 639 uint32_t idx; 640 641 idx = s->next_idx; 642 while (s390_pci_find_dev_by_idx(s, idx)) { 643 idx = (idx + 1) & FH_MASK_INDEX; 644 if (idx == s->next_idx) { 645 return false; 646 } 647 } 648 649 pbdev->idx = idx; 650 s->next_idx = (idx + 1) & FH_MASK_INDEX; 651 652 return true; 653 } 654 655 static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev, 656 DeviceState *dev, Error **errp) 657 { 658 PCIDevice *pdev = NULL; 659 S390PCIBusDevice *pbdev = NULL; 660 S390pciState *s = s390_get_phb(); 661 662 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 663 BusState *bus; 664 PCIBridge *pb = PCI_BRIDGE(dev); 665 PCIDevice *pdev = PCI_DEVICE(dev); 666 667 pci_bridge_map_irq(pb, dev->id, s390_pci_map_irq); 668 pci_setup_iommu(&pb->sec_bus, s390_pci_dma_iommu, s); 669 670 bus = BUS(&pb->sec_bus); 671 qbus_set_hotplug_handler(bus, DEVICE(s), errp); 672 673 if (dev->hotplugged) { 674 pci_default_write_config(pdev, PCI_PRIMARY_BUS, s->bus_no, 1); 675 s->bus_no += 1; 676 pci_default_write_config(pdev, PCI_SECONDARY_BUS, s->bus_no, 1); 677 do { 678 pdev = pdev->bus->parent_dev; 679 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, 680 s->bus_no, 1); 681 } while (pdev->bus && pci_bus_num(pdev->bus)); 682 } 683 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 684 pdev = PCI_DEVICE(dev); 685 686 if (!dev->id) { 687 /* In the case the PCI device does not define an id */ 688 /* we generate one based on the PCI address */ 689 dev->id = g_strdup_printf("auto_%02x:%02x.%01x", 690 pci_bus_num(pdev->bus), 691 PCI_SLOT(pdev->devfn), 692 PCI_FUNC(pdev->devfn)); 693 } 694 695 pbdev = s390_pci_find_dev_by_target(s, dev->id); 696 if (!pbdev) { 697 pbdev = s390_pci_device_new(s, dev->id); 698 if (!pbdev) { 699 error_setg(errp, "create zpci device failed"); 700 return; 701 } 702 } 703 704 if (object_dynamic_cast(OBJECT(dev), "vfio-pci")) { 705 pbdev->fh |= FH_SHM_VFIO; 706 } else { 707 pbdev->fh |= FH_SHM_EMUL; 708 } 709 710 pbdev->pdev = pdev; 711 pbdev->iommu = s390_pci_get_iommu(s, pdev->bus, pdev->devfn); 712 pbdev->iommu->pbdev = pbdev; 713 pbdev->state = ZPCI_FS_STANDBY; 714 715 if (s390_pci_msix_init(pbdev)) { 716 error_setg(errp, "MSI-X support is mandatory " 717 "in the S390 architecture"); 718 return; 719 } 720 721 if (dev->hotplugged) { 722 s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY, 723 pbdev->fh, pbdev->fid); 724 } 725 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) { 726 pbdev = S390_PCI_DEVICE(dev); 727 728 if (!s390_pci_alloc_idx(s, pbdev)) { 729 error_setg(errp, "no slot for plugging zpci device"); 730 return; 731 } 732 pbdev->fh = pbdev->idx; 733 QTAILQ_INSERT_TAIL(&s->zpci_devs, pbdev, link); 734 g_hash_table_insert(s->zpci_table, &pbdev->idx, pbdev); 735 } 736 } 737 738 static void s390_pcihost_timer_cb(void *opaque) 739 { 740 S390PCIBusDevice *pbdev = opaque; 741 742 if (pbdev->summary_ind) { 743 pci_dereg_irqs(pbdev); 744 } 745 if (pbdev->iommu->enabled) { 746 pci_dereg_ioat(pbdev->iommu); 747 } 748 749 pbdev->state = ZPCI_FS_STANDBY; 750 s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES, 751 pbdev->fh, pbdev->fid); 752 qdev_unplug(DEVICE(pbdev), NULL); 753 } 754 755 static void s390_pcihost_hot_unplug(HotplugHandler *hotplug_dev, 756 DeviceState *dev, Error **errp) 757 { 758 PCIDevice *pci_dev = NULL; 759 PCIBus *bus; 760 int32_t devfn; 761 S390PCIBusDevice *pbdev = NULL; 762 S390pciState *s = s390_get_phb(); 763 764 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { 765 error_setg(errp, "PCI bridge hot unplug currently not supported"); 766 return; 767 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 768 pci_dev = PCI_DEVICE(dev); 769 770 QTAILQ_FOREACH(pbdev, &s->zpci_devs, link) { 771 if (pbdev->pdev == pci_dev) { 772 break; 773 } 774 } 775 assert(pbdev != NULL); 776 } else if (object_dynamic_cast(OBJECT(dev), TYPE_S390_PCI_DEVICE)) { 777 pbdev = S390_PCI_DEVICE(dev); 778 pci_dev = pbdev->pdev; 779 } 780 781 switch (pbdev->state) { 782 case ZPCI_FS_RESERVED: 783 goto out; 784 case ZPCI_FS_STANDBY: 785 break; 786 default: 787 s390_pci_generate_plug_event(HP_EVENT_DECONFIGURE_REQUEST, 788 pbdev->fh, pbdev->fid); 789 pbdev->release_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 790 s390_pcihost_timer_cb, 791 pbdev); 792 timer_mod(pbdev->release_timer, 793 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + HOT_UNPLUG_TIMEOUT); 794 return; 795 } 796 797 if (pbdev->release_timer && timer_pending(pbdev->release_timer)) { 798 timer_del(pbdev->release_timer); 799 timer_free(pbdev->release_timer); 800 pbdev->release_timer = NULL; 801 } 802 803 s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED, 804 pbdev->fh, pbdev->fid); 805 bus = pci_dev->bus; 806 devfn = pci_dev->devfn; 807 object_unparent(OBJECT(pci_dev)); 808 s390_pci_msix_free(pbdev); 809 s390_pci_iommu_free(s, bus, devfn); 810 pbdev->pdev = NULL; 811 pbdev->state = ZPCI_FS_RESERVED; 812 out: 813 pbdev->fid = 0; 814 QTAILQ_REMOVE(&s->zpci_devs, pbdev, link); 815 g_hash_table_remove(s->zpci_table, &pbdev->idx); 816 object_unparent(OBJECT(pbdev)); 817 } 818 819 static void s390_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 820 void *opaque) 821 { 822 S390pciState *s = opaque; 823 unsigned int primary = s->bus_no; 824 unsigned int subordinate = 0xff; 825 PCIBus *sec_bus = NULL; 826 827 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 828 PCI_HEADER_TYPE_BRIDGE)) { 829 return; 830 } 831 832 (s->bus_no)++; 833 pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1); 834 pci_default_write_config(pdev, PCI_SECONDARY_BUS, s->bus_no, 1); 835 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, s->bus_no, 1); 836 837 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 838 if (!sec_bus) { 839 return; 840 } 841 842 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1); 843 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 844 s390_pci_enumerate_bridge, s); 845 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, s->bus_no, 1); 846 } 847 848 static void s390_pcihost_reset(DeviceState *dev) 849 { 850 S390pciState *s = S390_PCI_HOST_BRIDGE(dev); 851 PCIBus *bus = s->parent_obj.bus; 852 853 s->bus_no = 0; 854 pci_for_each_device(bus, pci_bus_num(bus), s390_pci_enumerate_bridge, s); 855 } 856 857 static void s390_pcihost_class_init(ObjectClass *klass, void *data) 858 { 859 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 860 DeviceClass *dc = DEVICE_CLASS(klass); 861 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 862 863 dc->reset = s390_pcihost_reset; 864 k->init = s390_pcihost_init; 865 hc->plug = s390_pcihost_hot_plug; 866 hc->unplug = s390_pcihost_hot_unplug; 867 msi_nonbroken = true; 868 } 869 870 static const TypeInfo s390_pcihost_info = { 871 .name = TYPE_S390_PCI_HOST_BRIDGE, 872 .parent = TYPE_PCI_HOST_BRIDGE, 873 .instance_size = sizeof(S390pciState), 874 .class_init = s390_pcihost_class_init, 875 .interfaces = (InterfaceInfo[]) { 876 { TYPE_HOTPLUG_HANDLER }, 877 { } 878 } 879 }; 880 881 static const TypeInfo s390_pcibus_info = { 882 .name = TYPE_S390_PCI_BUS, 883 .parent = TYPE_BUS, 884 .instance_size = sizeof(S390PCIBus), 885 }; 886 887 static uint16_t s390_pci_generate_uid(S390pciState *s) 888 { 889 uint16_t uid = 0; 890 891 do { 892 uid++; 893 if (!s390_pci_find_dev_by_uid(s, uid)) { 894 return uid; 895 } 896 } while (uid < ZPCI_MAX_UID); 897 898 return UID_UNDEFINED; 899 } 900 901 static uint32_t s390_pci_generate_fid(S390pciState *s, Error **errp) 902 { 903 uint32_t fid = 0; 904 905 do { 906 if (!s390_pci_find_dev_by_fid(s, fid)) { 907 return fid; 908 } 909 } while (fid++ != ZPCI_MAX_FID); 910 911 error_setg(errp, "no free fid could be found"); 912 return 0; 913 } 914 915 static void s390_pci_device_realize(DeviceState *dev, Error **errp) 916 { 917 S390PCIBusDevice *zpci = S390_PCI_DEVICE(dev); 918 S390pciState *s = s390_get_phb(); 919 920 if (!zpci->target) { 921 error_setg(errp, "target must be defined"); 922 return; 923 } 924 925 if (s390_pci_find_dev_by_target(s, zpci->target)) { 926 error_setg(errp, "target %s already has an associated zpci device", 927 zpci->target); 928 return; 929 } 930 931 if (zpci->uid == UID_UNDEFINED) { 932 zpci->uid = s390_pci_generate_uid(s); 933 if (!zpci->uid) { 934 error_setg(errp, "no free uid could be found"); 935 return; 936 } 937 } else if (s390_pci_find_dev_by_uid(s, zpci->uid)) { 938 error_setg(errp, "uid %u already in use", zpci->uid); 939 return; 940 } 941 942 if (!zpci->fid_defined) { 943 Error *local_error = NULL; 944 945 zpci->fid = s390_pci_generate_fid(s, &local_error); 946 if (local_error) { 947 error_propagate(errp, local_error); 948 return; 949 } 950 } else if (s390_pci_find_dev_by_fid(s, zpci->fid)) { 951 error_setg(errp, "fid %u already in use", zpci->fid); 952 return; 953 } 954 955 zpci->state = ZPCI_FS_RESERVED; 956 } 957 958 static void s390_pci_device_reset(DeviceState *dev) 959 { 960 S390PCIBusDevice *pbdev = S390_PCI_DEVICE(dev); 961 962 switch (pbdev->state) { 963 case ZPCI_FS_RESERVED: 964 return; 965 case ZPCI_FS_STANDBY: 966 break; 967 default: 968 pbdev->fh &= ~FH_MASK_ENABLE; 969 pbdev->state = ZPCI_FS_DISABLED; 970 break; 971 } 972 973 if (pbdev->summary_ind) { 974 pci_dereg_irqs(pbdev); 975 } 976 if (pbdev->iommu->enabled) { 977 pci_dereg_ioat(pbdev->iommu); 978 } 979 980 pbdev->fmb_addr = 0; 981 } 982 983 static void s390_pci_get_fid(Object *obj, Visitor *v, const char *name, 984 void *opaque, Error **errp) 985 { 986 Property *prop = opaque; 987 uint32_t *ptr = qdev_get_prop_ptr(DEVICE(obj), prop); 988 989 visit_type_uint32(v, name, ptr, errp); 990 } 991 992 static void s390_pci_set_fid(Object *obj, Visitor *v, const char *name, 993 void *opaque, Error **errp) 994 { 995 DeviceState *dev = DEVICE(obj); 996 S390PCIBusDevice *zpci = S390_PCI_DEVICE(obj); 997 Property *prop = opaque; 998 uint32_t *ptr = qdev_get_prop_ptr(dev, prop); 999 1000 if (dev->realized) { 1001 qdev_prop_set_after_realize(dev, name, errp); 1002 return; 1003 } 1004 1005 visit_type_uint32(v, name, ptr, errp); 1006 zpci->fid_defined = true; 1007 } 1008 1009 static const PropertyInfo s390_pci_fid_propinfo = { 1010 .name = "zpci_fid", 1011 .get = s390_pci_get_fid, 1012 .set = s390_pci_set_fid, 1013 }; 1014 1015 #define DEFINE_PROP_S390_PCI_FID(_n, _s, _f) \ 1016 DEFINE_PROP(_n, _s, _f, s390_pci_fid_propinfo, uint32_t) 1017 1018 static Property s390_pci_device_properties[] = { 1019 DEFINE_PROP_UINT16("uid", S390PCIBusDevice, uid, UID_UNDEFINED), 1020 DEFINE_PROP_S390_PCI_FID("fid", S390PCIBusDevice, fid), 1021 DEFINE_PROP_STRING("target", S390PCIBusDevice, target), 1022 DEFINE_PROP_END_OF_LIST(), 1023 }; 1024 1025 static void s390_pci_device_class_init(ObjectClass *klass, void *data) 1026 { 1027 DeviceClass *dc = DEVICE_CLASS(klass); 1028 1029 dc->desc = "zpci device"; 1030 dc->reset = s390_pci_device_reset; 1031 dc->bus_type = TYPE_S390_PCI_BUS; 1032 dc->realize = s390_pci_device_realize; 1033 dc->props = s390_pci_device_properties; 1034 } 1035 1036 static const TypeInfo s390_pci_device_info = { 1037 .name = TYPE_S390_PCI_DEVICE, 1038 .parent = TYPE_DEVICE, 1039 .instance_size = sizeof(S390PCIBusDevice), 1040 .class_init = s390_pci_device_class_init, 1041 }; 1042 1043 static TypeInfo s390_pci_iommu_info = { 1044 .name = TYPE_S390_PCI_IOMMU, 1045 .parent = TYPE_OBJECT, 1046 .instance_size = sizeof(S390PCIIOMMU), 1047 }; 1048 1049 static void s390_iommu_memory_region_class_init(ObjectClass *klass, void *data) 1050 { 1051 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); 1052 1053 imrc->translate = s390_translate_iommu; 1054 } 1055 1056 static const TypeInfo s390_iommu_memory_region_info = { 1057 .parent = TYPE_IOMMU_MEMORY_REGION, 1058 .name = TYPE_S390_IOMMU_MEMORY_REGION, 1059 .class_init = s390_iommu_memory_region_class_init, 1060 }; 1061 1062 static void s390_pci_register_types(void) 1063 { 1064 type_register_static(&s390_pcihost_info); 1065 type_register_static(&s390_pcibus_info); 1066 type_register_static(&s390_pci_device_info); 1067 type_register_static(&s390_pci_iommu_info); 1068 type_register_static(&s390_iommu_memory_region_info); 1069 } 1070 1071 type_init(s390_pci_register_types) 1072