1 /* 2 * s390 IPL device 3 * 4 * Copyright 2015, 2020 IBM Corp. 5 * Author(s): Zhang Fan <bjfanzh@cn.ibm.com> 6 * Janosch Frank <frankja@linux.ibm.com> 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or (at 9 * your option) any later version. See the COPYING file in the top-level 10 * directory. 11 */ 12 13 #ifndef HW_S390_IPL_H 14 #define HW_S390_IPL_H 15 16 #include "cpu.h" 17 #include "system/address-spaces.h" 18 #include "system/memory.h" 19 #include "hw/qdev-core.h" 20 #include "hw/s390x/ipl/qipl.h" 21 #include "qom/object.h" 22 23 #define DIAG308_FLAGS_LP_VALID 0x80 24 #define MAX_BOOT_DEVS 8 /* Max number of devices that may have a bootindex */ 25 26 void s390_ipl_convert_loadparm(char *ascii_lp, uint8_t *ebcdic_lp); 27 void s390_ipl_fmt_loadparm(uint8_t *loadparm, char *str, Error **errp); 28 void s390_rebuild_iplb(uint16_t index, IplParameterBlock *iplb); 29 void s390_ipl_update_diag308(IplParameterBlock *iplb); 30 int s390_ipl_prepare_pv_header(Error **errp); 31 int s390_ipl_pv_unpack(void); 32 void s390_ipl_prepare_cpu(S390CPU *cpu); 33 IplParameterBlock *s390_ipl_get_iplb(void); 34 IplParameterBlock *s390_ipl_get_iplb_pv(void); 35 36 enum s390_reset { 37 /* default is a reset not triggered by a CPU e.g. issued by QMP */ 38 S390_RESET_EXTERNAL = 0, 39 S390_RESET_REIPL, 40 S390_RESET_MODIFIED_CLEAR, 41 S390_RESET_LOAD_NORMAL, 42 S390_RESET_PV, 43 }; 44 void s390_ipl_reset_request(CPUState *cs, enum s390_reset reset_type); 45 void s390_ipl_get_reset_request(CPUState **cs, enum s390_reset *reset_type); 46 void s390_ipl_clear_reset_request(void); 47 48 #define QIPL_ADDRESS 0xcc 49 50 /* Boot Menu flags */ 51 #define QIPL_FLAG_BM_OPTS_CMD 0x80 52 #define QIPL_FLAG_BM_OPTS_ZIPL 0x40 53 54 #define TYPE_S390_IPL "s390-ipl" 55 OBJECT_DECLARE_SIMPLE_TYPE(S390IPLState, S390_IPL) 56 57 struct S390IPLState { 58 /*< private >*/ 59 DeviceState parent_obj; 60 IplParameterBlock iplb; 61 IplParameterBlock iplb_pv; 62 QemuIplParameters qipl; 63 uint64_t start_addr; 64 uint64_t compat_start_addr; 65 uint64_t bios_start_addr; 66 uint64_t compat_bios_start_addr; 67 bool enforce_bios; 68 bool iplb_valid; 69 bool iplb_valid_pv; 70 bool rebuilt_iplb; 71 uint16_t iplb_index; 72 /* reset related properties don't have to be migrated or reset */ 73 enum s390_reset reset_type; 74 int reset_cpu_index; 75 76 /*< public >*/ 77 char *kernel; 78 char *initrd; 79 char *cmdline; 80 char *firmware; 81 uint8_t cssid; 82 uint8_t ssid; 83 uint16_t devno; 84 }; 85 QEMU_BUILD_BUG_MSG(offsetof(S390IPLState, iplb) & 3, "alignment of iplb wrong"); 86 87 #define DIAG_308_RC_OK 0x0001 88 #define DIAG_308_RC_NO_CONF 0x0102 89 #define DIAG_308_RC_INVALID 0x0402 90 #define DIAG_308_RC_NO_PV_CONF 0x0902 91 #define DIAG_308_RC_INVAL_FOR_PV 0x0a02 92 93 #define DIAG308_RESET_MOD_CLR 0 94 #define DIAG308_RESET_LOAD_NORM 1 95 #define DIAG308_LOAD_CLEAR 3 96 #define DIAG308_LOAD_NORMAL_DUMP 4 97 #define DIAG308_SET 5 98 #define DIAG308_STORE 6 99 #define DIAG308_PV_SET 8 100 #define DIAG308_PV_STORE 9 101 #define DIAG308_PV_START 10 102 103 #define S390_IPL_TYPE_FCP 0x00 104 #define S390_IPL_TYPE_CCW 0x02 105 #define S390_IPL_TYPE_PV 0x05 106 #define S390_IPL_TYPE_QEMU_SCSI 0xff 107 108 #define S390_IPLB_HEADER_LEN 8 109 #define S390_IPLB_MIN_PV_LEN 148 110 #define S390_IPLB_MIN_CCW_LEN 200 111 #define S390_IPLB_MIN_FCP_LEN 384 112 #define S390_IPLB_MIN_QEMU_SCSI_LEN 200 113 114 static inline bool iplb_valid_len(IplParameterBlock *iplb) 115 { 116 return be32_to_cpu(iplb->len) <= sizeof(IplParameterBlock); 117 } 118 119 static inline bool ipl_valid_pv_components(IplParameterBlock *iplb) 120 { 121 IPLBlockPV *ipib_pv = &iplb->pv; 122 int i; 123 124 if (ipib_pv->num_comp == 0) { 125 return false; 126 } 127 128 for (i = 0; i < ipib_pv->num_comp; i++) { 129 /* Addr must be 4k aligned */ 130 if (ipib_pv->components[i].addr & ~TARGET_PAGE_MASK) { 131 return false; 132 } 133 134 /* Tweak prefix is monotonically increasing with each component */ 135 if (i < ipib_pv->num_comp - 1 && 136 ipib_pv->components[i].tweak_pref >= 137 ipib_pv->components[i + 1].tweak_pref) { 138 return false; 139 } 140 } 141 return true; 142 } 143 144 static inline bool ipl_valid_pv_header(IplParameterBlock *iplb) 145 { 146 IPLBlockPV *ipib_pv = &iplb->pv; 147 148 if (ipib_pv->pv_header_len > 2 * TARGET_PAGE_SIZE) { 149 return false; 150 } 151 152 if (!address_space_access_valid(&address_space_memory, 153 ipib_pv->pv_header_addr, 154 ipib_pv->pv_header_len, 155 false, 156 MEMTXATTRS_UNSPECIFIED)) { 157 return false; 158 } 159 160 return true; 161 } 162 163 static inline bool iplb_valid_pv(IplParameterBlock *iplb) 164 { 165 if (iplb->pbt != S390_IPL_TYPE_PV || 166 be32_to_cpu(iplb->len) < S390_IPLB_MIN_PV_LEN) { 167 return false; 168 } 169 if (!ipl_valid_pv_header(iplb)) { 170 return false; 171 } 172 return ipl_valid_pv_components(iplb); 173 } 174 175 static inline bool iplb_valid(IplParameterBlock *iplb) 176 { 177 uint32_t len = be32_to_cpu(iplb->len); 178 179 switch (iplb->pbt) { 180 case S390_IPL_TYPE_FCP: 181 return len >= S390_IPLB_MIN_FCP_LEN; 182 case S390_IPL_TYPE_CCW: 183 return len >= S390_IPLB_MIN_CCW_LEN; 184 case S390_IPL_TYPE_QEMU_SCSI: 185 default: 186 return false; 187 } 188 } 189 190 #endif 191