1 /* 2 * Channel subsystem base support. 3 * 4 * Copyright 2012 IBM Corp. 5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or (at 8 * your option) any later version. See the COPYING file in the top-level 9 * directory. 10 */ 11 12 #include <hw/qdev.h> 13 #include "qemu/bitops.h" 14 #include "exec/address-spaces.h" 15 #include "cpu.h" 16 #include "ioinst.h" 17 #include "css.h" 18 #include "trace.h" 19 #include "hw/s390x/s390_flic.h" 20 21 typedef struct CrwContainer { 22 CRW crw; 23 QTAILQ_ENTRY(CrwContainer) sibling; 24 } CrwContainer; 25 26 typedef struct ChpInfo { 27 uint8_t in_use; 28 uint8_t type; 29 uint8_t is_virtual; 30 } ChpInfo; 31 32 typedef struct SubchSet { 33 SubchDev *sch[MAX_SCHID + 1]; 34 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 35 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 36 } SubchSet; 37 38 typedef struct CssImage { 39 SubchSet *sch_set[MAX_SSID + 1]; 40 ChpInfo chpids[MAX_CHPID + 1]; 41 } CssImage; 42 43 typedef struct IoAdapter { 44 uint32_t id; 45 uint8_t type; 46 uint8_t isc; 47 QTAILQ_ENTRY(IoAdapter) sibling; 48 } IoAdapter; 49 50 typedef struct ChannelSubSys { 51 QTAILQ_HEAD(, CrwContainer) pending_crws; 52 bool do_crw_mchk; 53 bool crws_lost; 54 uint8_t max_cssid; 55 uint8_t max_ssid; 56 bool chnmon_active; 57 uint64_t chnmon_area; 58 CssImage *css[MAX_CSSID + 1]; 59 uint8_t default_cssid; 60 QTAILQ_HEAD(, IoAdapter) io_adapters; 61 } ChannelSubSys; 62 63 static ChannelSubSys *channel_subsys; 64 65 int css_create_css_image(uint8_t cssid, bool default_image) 66 { 67 trace_css_new_image(cssid, default_image ? "(default)" : ""); 68 if (cssid > MAX_CSSID) { 69 return -EINVAL; 70 } 71 if (channel_subsys->css[cssid]) { 72 return -EBUSY; 73 } 74 channel_subsys->css[cssid] = g_malloc0(sizeof(CssImage)); 75 if (default_image) { 76 channel_subsys->default_cssid = cssid; 77 } 78 return 0; 79 } 80 81 int css_register_io_adapter(uint8_t type, uint8_t isc, bool swap, 82 bool maskable, uint32_t *id) 83 { 84 IoAdapter *adapter; 85 bool found = false; 86 int ret; 87 S390FLICState *fs = s390_get_flic(); 88 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs); 89 90 *id = 0; 91 QTAILQ_FOREACH(adapter, &channel_subsys->io_adapters, sibling) { 92 if ((adapter->type == type) && (adapter->isc == isc)) { 93 *id = adapter->id; 94 found = true; 95 ret = 0; 96 break; 97 } 98 if (adapter->id >= *id) { 99 *id = adapter->id + 1; 100 } 101 } 102 if (found) { 103 goto out; 104 } 105 adapter = g_new0(IoAdapter, 1); 106 ret = fsc->register_io_adapter(fs, *id, isc, swap, maskable); 107 if (ret == 0) { 108 adapter->id = *id; 109 adapter->isc = isc; 110 adapter->type = type; 111 QTAILQ_INSERT_TAIL(&channel_subsys->io_adapters, adapter, sibling); 112 } else { 113 g_free(adapter); 114 fprintf(stderr, "Unexpected error %d when registering adapter %d\n", 115 ret, *id); 116 } 117 out: 118 return ret; 119 } 120 121 uint16_t css_build_subchannel_id(SubchDev *sch) 122 { 123 if (channel_subsys->max_cssid > 0) { 124 return (sch->cssid << 8) | (1 << 3) | (sch->ssid << 1) | 1; 125 } 126 return (sch->ssid << 1) | 1; 127 } 128 129 static void css_inject_io_interrupt(SubchDev *sch) 130 { 131 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 132 133 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 134 sch->curr_status.pmcw.intparm, isc, ""); 135 s390_io_interrupt(css_build_subchannel_id(sch), 136 sch->schid, 137 sch->curr_status.pmcw.intparm, 138 isc << 27); 139 } 140 141 void css_conditional_io_interrupt(SubchDev *sch) 142 { 143 /* 144 * If the subchannel is not currently status pending, make it pending 145 * with alert status. 146 */ 147 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) { 148 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 149 150 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 151 sch->curr_status.pmcw.intparm, isc, 152 "(unsolicited)"); 153 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 154 sch->curr_status.scsw.ctrl |= 155 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 156 /* Inject an I/O interrupt. */ 157 s390_io_interrupt(css_build_subchannel_id(sch), 158 sch->schid, 159 sch->curr_status.pmcw.intparm, 160 isc << 27); 161 } 162 } 163 164 void css_adapter_interrupt(uint8_t isc) 165 { 166 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI; 167 168 trace_css_adapter_interrupt(isc); 169 s390_io_interrupt(0, 0, 0, io_int_word); 170 } 171 172 static void sch_handle_clear_func(SubchDev *sch) 173 { 174 PMCW *p = &sch->curr_status.pmcw; 175 SCSW *s = &sch->curr_status.scsw; 176 int path; 177 178 /* Path management: In our simple css, we always choose the only path. */ 179 path = 0x80; 180 181 /* Reset values prior to 'issuing the clear signal'. */ 182 p->lpum = 0; 183 p->pom = 0xff; 184 s->flags &= ~SCSW_FLAGS_MASK_PNO; 185 186 /* We always 'attempt to issue the clear signal', and we always succeed. */ 187 sch->channel_prog = 0x0; 188 sch->last_cmd_valid = false; 189 s->ctrl &= ~SCSW_ACTL_CLEAR_PEND; 190 s->ctrl |= SCSW_STCTL_STATUS_PEND; 191 192 s->dstat = 0; 193 s->cstat = 0; 194 p->lpum = path; 195 196 } 197 198 static void sch_handle_halt_func(SubchDev *sch) 199 { 200 201 PMCW *p = &sch->curr_status.pmcw; 202 SCSW *s = &sch->curr_status.scsw; 203 hwaddr curr_ccw = sch->channel_prog; 204 int path; 205 206 /* Path management: In our simple css, we always choose the only path. */ 207 path = 0x80; 208 209 /* We always 'attempt to issue the halt signal', and we always succeed. */ 210 sch->channel_prog = 0x0; 211 sch->last_cmd_valid = false; 212 s->ctrl &= ~SCSW_ACTL_HALT_PEND; 213 s->ctrl |= SCSW_STCTL_STATUS_PEND; 214 215 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) || 216 !((s->ctrl & SCSW_ACTL_START_PEND) || 217 (s->ctrl & SCSW_ACTL_SUSP))) { 218 s->dstat = SCSW_DSTAT_DEVICE_END; 219 } 220 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) || 221 (s->ctrl & SCSW_ACTL_SUSP)) { 222 s->cpa = curr_ccw + 8; 223 } 224 s->cstat = 0; 225 p->lpum = path; 226 227 } 228 229 static void copy_sense_id_to_guest(SenseId *dest, SenseId *src) 230 { 231 int i; 232 233 dest->reserved = src->reserved; 234 dest->cu_type = cpu_to_be16(src->cu_type); 235 dest->cu_model = src->cu_model; 236 dest->dev_type = cpu_to_be16(src->dev_type); 237 dest->dev_model = src->dev_model; 238 dest->unused = src->unused; 239 for (i = 0; i < ARRAY_SIZE(dest->ciw); i++) { 240 dest->ciw[i].type = src->ciw[i].type; 241 dest->ciw[i].command = src->ciw[i].command; 242 dest->ciw[i].count = cpu_to_be16(src->ciw[i].count); 243 } 244 } 245 246 static CCW1 copy_ccw_from_guest(hwaddr addr) 247 { 248 CCW1 tmp; 249 CCW1 ret; 250 251 cpu_physical_memory_read(addr, &tmp, sizeof(tmp)); 252 ret.cmd_code = tmp.cmd_code; 253 ret.flags = tmp.flags; 254 ret.count = be16_to_cpu(tmp.count); 255 ret.cda = be32_to_cpu(tmp.cda); 256 257 return ret; 258 } 259 260 static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr) 261 { 262 int ret; 263 bool check_len; 264 int len; 265 CCW1 ccw; 266 267 if (!ccw_addr) { 268 return -EIO; 269 } 270 271 ccw = copy_ccw_from_guest(ccw_addr); 272 273 /* Check for invalid command codes. */ 274 if ((ccw.cmd_code & 0x0f) == 0) { 275 return -EINVAL; 276 } 277 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) && 278 ((ccw.cmd_code & 0xf0) != 0)) { 279 return -EINVAL; 280 } 281 282 if (ccw.flags & CCW_FLAG_SUSPEND) { 283 return -EINPROGRESS; 284 } 285 286 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC)); 287 288 /* Look at the command. */ 289 switch (ccw.cmd_code) { 290 case CCW_CMD_NOOP: 291 /* Nothing to do. */ 292 ret = 0; 293 break; 294 case CCW_CMD_BASIC_SENSE: 295 if (check_len) { 296 if (ccw.count != sizeof(sch->sense_data)) { 297 ret = -EINVAL; 298 break; 299 } 300 } 301 len = MIN(ccw.count, sizeof(sch->sense_data)); 302 cpu_physical_memory_write(ccw.cda, sch->sense_data, len); 303 sch->curr_status.scsw.count = ccw.count - len; 304 memset(sch->sense_data, 0, sizeof(sch->sense_data)); 305 ret = 0; 306 break; 307 case CCW_CMD_SENSE_ID: 308 { 309 SenseId sense_id; 310 311 copy_sense_id_to_guest(&sense_id, &sch->id); 312 /* Sense ID information is device specific. */ 313 if (check_len) { 314 if (ccw.count != sizeof(sense_id)) { 315 ret = -EINVAL; 316 break; 317 } 318 } 319 len = MIN(ccw.count, sizeof(sense_id)); 320 /* 321 * Only indicate 0xff in the first sense byte if we actually 322 * have enough place to store at least bytes 0-3. 323 */ 324 if (len >= 4) { 325 sense_id.reserved = 0xff; 326 } else { 327 sense_id.reserved = 0; 328 } 329 cpu_physical_memory_write(ccw.cda, &sense_id, len); 330 sch->curr_status.scsw.count = ccw.count - len; 331 ret = 0; 332 break; 333 } 334 case CCW_CMD_TIC: 335 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) { 336 ret = -EINVAL; 337 break; 338 } 339 if (ccw.flags & (CCW_FLAG_CC | CCW_FLAG_DC)) { 340 ret = -EINVAL; 341 break; 342 } 343 sch->channel_prog = ccw.cda; 344 ret = -EAGAIN; 345 break; 346 default: 347 if (sch->ccw_cb) { 348 /* Handle device specific commands. */ 349 ret = sch->ccw_cb(sch, ccw); 350 } else { 351 ret = -ENOSYS; 352 } 353 break; 354 } 355 sch->last_cmd = ccw; 356 sch->last_cmd_valid = true; 357 if (ret == 0) { 358 if (ccw.flags & CCW_FLAG_CC) { 359 sch->channel_prog += 8; 360 ret = -EAGAIN; 361 } 362 } 363 364 return ret; 365 } 366 367 static void sch_handle_start_func(SubchDev *sch, ORB *orb) 368 { 369 370 PMCW *p = &sch->curr_status.pmcw; 371 SCSW *s = &sch->curr_status.scsw; 372 int path; 373 int ret; 374 375 /* Path management: In our simple css, we always choose the only path. */ 376 path = 0x80; 377 378 if (!(s->ctrl & SCSW_ACTL_SUSP)) { 379 /* Look at the orb and try to execute the channel program. */ 380 assert(orb != NULL); /* resume does not pass an orb */ 381 p->intparm = orb->intparm; 382 if (!(orb->lpm & path)) { 383 /* Generate a deferred cc 3 condition. */ 384 s->flags |= SCSW_FLAGS_MASK_CC; 385 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 386 s->ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND); 387 return; 388 } 389 } else { 390 s->ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND); 391 } 392 sch->last_cmd_valid = false; 393 do { 394 ret = css_interpret_ccw(sch, sch->channel_prog); 395 switch (ret) { 396 case -EAGAIN: 397 /* ccw chain, continue processing */ 398 break; 399 case 0: 400 /* success */ 401 s->ctrl &= ~SCSW_ACTL_START_PEND; 402 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 403 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 404 SCSW_STCTL_STATUS_PEND; 405 s->dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END; 406 s->cpa = sch->channel_prog + 8; 407 break; 408 case -ENOSYS: 409 /* unsupported command, generate unit check (command reject) */ 410 s->ctrl &= ~SCSW_ACTL_START_PEND; 411 s->dstat = SCSW_DSTAT_UNIT_CHECK; 412 /* Set sense bit 0 in ecw0. */ 413 sch->sense_data[0] = 0x80; 414 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 415 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 416 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 417 s->cpa = sch->channel_prog + 8; 418 break; 419 case -EFAULT: 420 /* memory problem, generate channel data check */ 421 s->ctrl &= ~SCSW_ACTL_START_PEND; 422 s->cstat = SCSW_CSTAT_DATA_CHECK; 423 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 424 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 425 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 426 s->cpa = sch->channel_prog + 8; 427 break; 428 case -EBUSY: 429 /* subchannel busy, generate deferred cc 1 */ 430 s->flags &= ~SCSW_FLAGS_MASK_CC; 431 s->flags |= (1 << 8); 432 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 433 s->ctrl |= SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 434 break; 435 case -EINPROGRESS: 436 /* channel program has been suspended */ 437 s->ctrl &= ~SCSW_ACTL_START_PEND; 438 s->ctrl |= SCSW_ACTL_SUSP; 439 break; 440 default: 441 /* error, generate channel program check */ 442 s->ctrl &= ~SCSW_ACTL_START_PEND; 443 s->cstat = SCSW_CSTAT_PROG_CHECK; 444 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 445 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 446 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 447 s->cpa = sch->channel_prog + 8; 448 break; 449 } 450 } while (ret == -EAGAIN); 451 452 } 453 454 /* 455 * On real machines, this would run asynchronously to the main vcpus. 456 * We might want to make some parts of the ssch handling (interpreting 457 * read/writes) asynchronous later on if we start supporting more than 458 * our current very simple devices. 459 */ 460 static void do_subchannel_work(SubchDev *sch, ORB *orb) 461 { 462 463 SCSW *s = &sch->curr_status.scsw; 464 465 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) { 466 sch_handle_clear_func(sch); 467 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) { 468 sch_handle_halt_func(sch); 469 } else if (s->ctrl & SCSW_FCTL_START_FUNC) { 470 sch_handle_start_func(sch, orb); 471 } else { 472 /* Cannot happen. */ 473 return; 474 } 475 css_inject_io_interrupt(sch); 476 } 477 478 static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src) 479 { 480 int i; 481 482 dest->intparm = cpu_to_be32(src->intparm); 483 dest->flags = cpu_to_be16(src->flags); 484 dest->devno = cpu_to_be16(src->devno); 485 dest->lpm = src->lpm; 486 dest->pnom = src->pnom; 487 dest->lpum = src->lpum; 488 dest->pim = src->pim; 489 dest->mbi = cpu_to_be16(src->mbi); 490 dest->pom = src->pom; 491 dest->pam = src->pam; 492 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 493 dest->chpid[i] = src->chpid[i]; 494 } 495 dest->chars = cpu_to_be32(src->chars); 496 } 497 498 static void copy_scsw_to_guest(SCSW *dest, const SCSW *src) 499 { 500 dest->flags = cpu_to_be16(src->flags); 501 dest->ctrl = cpu_to_be16(src->ctrl); 502 dest->cpa = cpu_to_be32(src->cpa); 503 dest->dstat = src->dstat; 504 dest->cstat = src->cstat; 505 dest->count = cpu_to_be16(src->count); 506 } 507 508 static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src) 509 { 510 int i; 511 512 copy_pmcw_to_guest(&dest->pmcw, &src->pmcw); 513 copy_scsw_to_guest(&dest->scsw, &src->scsw); 514 dest->mba = cpu_to_be64(src->mba); 515 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 516 dest->mda[i] = src->mda[i]; 517 } 518 } 519 520 int css_do_stsch(SubchDev *sch, SCHIB *schib) 521 { 522 /* Use current status. */ 523 copy_schib_to_guest(schib, &sch->curr_status); 524 return 0; 525 } 526 527 static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src) 528 { 529 int i; 530 531 dest->intparm = be32_to_cpu(src->intparm); 532 dest->flags = be16_to_cpu(src->flags); 533 dest->devno = be16_to_cpu(src->devno); 534 dest->lpm = src->lpm; 535 dest->pnom = src->pnom; 536 dest->lpum = src->lpum; 537 dest->pim = src->pim; 538 dest->mbi = be16_to_cpu(src->mbi); 539 dest->pom = src->pom; 540 dest->pam = src->pam; 541 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 542 dest->chpid[i] = src->chpid[i]; 543 } 544 dest->chars = be32_to_cpu(src->chars); 545 } 546 547 static void copy_scsw_from_guest(SCSW *dest, const SCSW *src) 548 { 549 dest->flags = be16_to_cpu(src->flags); 550 dest->ctrl = be16_to_cpu(src->ctrl); 551 dest->cpa = be32_to_cpu(src->cpa); 552 dest->dstat = src->dstat; 553 dest->cstat = src->cstat; 554 dest->count = be16_to_cpu(src->count); 555 } 556 557 static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src) 558 { 559 int i; 560 561 copy_pmcw_from_guest(&dest->pmcw, &src->pmcw); 562 copy_scsw_from_guest(&dest->scsw, &src->scsw); 563 dest->mba = be64_to_cpu(src->mba); 564 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 565 dest->mda[i] = src->mda[i]; 566 } 567 } 568 569 int css_do_msch(SubchDev *sch, SCHIB *orig_schib) 570 { 571 SCSW *s = &sch->curr_status.scsw; 572 PMCW *p = &sch->curr_status.pmcw; 573 int ret; 574 SCHIB schib; 575 576 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_DNV)) { 577 ret = 0; 578 goto out; 579 } 580 581 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 582 ret = -EINPROGRESS; 583 goto out; 584 } 585 586 if (s->ctrl & 587 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) { 588 ret = -EBUSY; 589 goto out; 590 } 591 592 copy_schib_from_guest(&schib, orig_schib); 593 /* Only update the program-modifiable fields. */ 594 p->intparm = schib.pmcw.intparm; 595 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 596 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 597 PMCW_FLAGS_MASK_MP); 598 p->flags |= schib.pmcw.flags & 599 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 600 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 601 PMCW_FLAGS_MASK_MP); 602 p->lpm = schib.pmcw.lpm; 603 p->mbi = schib.pmcw.mbi; 604 p->pom = schib.pmcw.pom; 605 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 606 p->chars |= schib.pmcw.chars & 607 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 608 sch->curr_status.mba = schib.mba; 609 610 ret = 0; 611 612 out: 613 return ret; 614 } 615 616 int css_do_xsch(SubchDev *sch) 617 { 618 SCSW *s = &sch->curr_status.scsw; 619 PMCW *p = &sch->curr_status.pmcw; 620 int ret; 621 622 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 623 ret = -ENODEV; 624 goto out; 625 } 626 627 if (!(s->ctrl & SCSW_CTRL_MASK_FCTL) || 628 ((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 629 (!(s->ctrl & 630 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) || 631 (s->ctrl & SCSW_ACTL_SUBCH_ACTIVE)) { 632 ret = -EINPROGRESS; 633 goto out; 634 } 635 636 if (s->ctrl & SCSW_CTRL_MASK_STCTL) { 637 ret = -EBUSY; 638 goto out; 639 } 640 641 /* Cancel the current operation. */ 642 s->ctrl &= ~(SCSW_FCTL_START_FUNC | 643 SCSW_ACTL_RESUME_PEND | 644 SCSW_ACTL_START_PEND | 645 SCSW_ACTL_SUSP); 646 sch->channel_prog = 0x0; 647 sch->last_cmd_valid = false; 648 s->dstat = 0; 649 s->cstat = 0; 650 ret = 0; 651 652 out: 653 return ret; 654 } 655 656 int css_do_csch(SubchDev *sch) 657 { 658 SCSW *s = &sch->curr_status.scsw; 659 PMCW *p = &sch->curr_status.pmcw; 660 int ret; 661 662 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 663 ret = -ENODEV; 664 goto out; 665 } 666 667 /* Trigger the clear function. */ 668 s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL); 669 s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_FCTL_CLEAR_FUNC; 670 671 do_subchannel_work(sch, NULL); 672 ret = 0; 673 674 out: 675 return ret; 676 } 677 678 int css_do_hsch(SubchDev *sch) 679 { 680 SCSW *s = &sch->curr_status.scsw; 681 PMCW *p = &sch->curr_status.pmcw; 682 int ret; 683 684 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 685 ret = -ENODEV; 686 goto out; 687 } 688 689 if (((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) || 690 (s->ctrl & (SCSW_STCTL_PRIMARY | 691 SCSW_STCTL_SECONDARY | 692 SCSW_STCTL_ALERT))) { 693 ret = -EINPROGRESS; 694 goto out; 695 } 696 697 if (s->ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) { 698 ret = -EBUSY; 699 goto out; 700 } 701 702 /* Trigger the halt function. */ 703 s->ctrl |= SCSW_FCTL_HALT_FUNC; 704 s->ctrl &= ~SCSW_FCTL_START_FUNC; 705 if (((s->ctrl & SCSW_CTRL_MASK_ACTL) == 706 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) && 707 ((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_INTERMEDIATE)) { 708 s->ctrl &= ~SCSW_STCTL_STATUS_PEND; 709 } 710 s->ctrl |= SCSW_ACTL_HALT_PEND; 711 712 do_subchannel_work(sch, NULL); 713 ret = 0; 714 715 out: 716 return ret; 717 } 718 719 static void css_update_chnmon(SubchDev *sch) 720 { 721 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) { 722 /* Not active. */ 723 return; 724 } 725 /* The counter is conveniently located at the beginning of the struct. */ 726 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) { 727 /* Format 1, per-subchannel area. */ 728 uint32_t count; 729 730 count = ldl_phys(&address_space_memory, sch->curr_status.mba); 731 count++; 732 stl_phys(&address_space_memory, sch->curr_status.mba, count); 733 } else { 734 /* Format 0, global area. */ 735 uint32_t offset; 736 uint16_t count; 737 738 offset = sch->curr_status.pmcw.mbi << 5; 739 count = lduw_phys(&address_space_memory, 740 channel_subsys->chnmon_area + offset); 741 count++; 742 stw_phys(&address_space_memory, 743 channel_subsys->chnmon_area + offset, count); 744 } 745 } 746 747 int css_do_ssch(SubchDev *sch, ORB *orb) 748 { 749 SCSW *s = &sch->curr_status.scsw; 750 PMCW *p = &sch->curr_status.pmcw; 751 int ret; 752 753 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 754 ret = -ENODEV; 755 goto out; 756 } 757 758 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 759 ret = -EINPROGRESS; 760 goto out; 761 } 762 763 if (s->ctrl & (SCSW_FCTL_START_FUNC | 764 SCSW_FCTL_HALT_FUNC | 765 SCSW_FCTL_CLEAR_FUNC)) { 766 ret = -EBUSY; 767 goto out; 768 } 769 770 /* If monitoring is active, update counter. */ 771 if (channel_subsys->chnmon_active) { 772 css_update_chnmon(sch); 773 } 774 sch->channel_prog = orb->cpa; 775 /* Trigger the start function. */ 776 s->ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND); 777 s->flags &= ~SCSW_FLAGS_MASK_PNO; 778 779 do_subchannel_work(sch, orb); 780 ret = 0; 781 782 out: 783 return ret; 784 } 785 786 static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw) 787 { 788 int i; 789 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 790 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 791 792 copy_scsw_to_guest(&dest->scsw, &src->scsw); 793 794 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) { 795 dest->esw[i] = cpu_to_be32(src->esw[i]); 796 } 797 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) { 798 dest->ecw[i] = cpu_to_be32(src->ecw[i]); 799 } 800 /* extended measurements enabled? */ 801 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) || 802 !(pmcw->flags & PMCW_FLAGS_MASK_TF) || 803 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) { 804 return; 805 } 806 /* extended measurements pending? */ 807 if (!(stctl & SCSW_STCTL_STATUS_PEND)) { 808 return; 809 } 810 if ((stctl & SCSW_STCTL_PRIMARY) || 811 (stctl == SCSW_STCTL_SECONDARY) || 812 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) { 813 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) { 814 dest->emw[i] = cpu_to_be32(src->emw[i]); 815 } 816 } 817 } 818 819 int css_do_tsch(SubchDev *sch, IRB *target_irb) 820 { 821 SCSW *s = &sch->curr_status.scsw; 822 PMCW *p = &sch->curr_status.pmcw; 823 uint16_t stctl; 824 uint16_t fctl; 825 uint16_t actl; 826 IRB irb; 827 int ret; 828 829 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 830 ret = 3; 831 goto out; 832 } 833 834 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL; 835 fctl = s->ctrl & SCSW_CTRL_MASK_FCTL; 836 actl = s->ctrl & SCSW_CTRL_MASK_ACTL; 837 838 /* Prepare the irb for the guest. */ 839 memset(&irb, 0, sizeof(IRB)); 840 841 /* Copy scsw from current status. */ 842 memcpy(&irb.scsw, s, sizeof(SCSW)); 843 if (stctl & SCSW_STCTL_STATUS_PEND) { 844 if (s->cstat & (SCSW_CSTAT_DATA_CHECK | 845 SCSW_CSTAT_CHN_CTRL_CHK | 846 SCSW_CSTAT_INTF_CTRL_CHK)) { 847 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF; 848 irb.esw[0] = 0x04804000; 849 } else { 850 irb.esw[0] = 0x00800000; 851 } 852 /* If a unit check is pending, copy sense data. */ 853 if ((s->dstat & SCSW_DSTAT_UNIT_CHECK) && 854 (p->chars & PMCW_CHARS_MASK_CSENSE)) { 855 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL; 856 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data)); 857 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8); 858 } 859 } 860 /* Store the irb to the guest. */ 861 copy_irb_to_guest(target_irb, &irb, p); 862 863 /* Clear conditions on subchannel, if applicable. */ 864 if (stctl & SCSW_STCTL_STATUS_PEND) { 865 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 866 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) || 867 ((fctl & SCSW_FCTL_HALT_FUNC) && 868 (actl & SCSW_ACTL_SUSP))) { 869 s->ctrl &= ~SCSW_CTRL_MASK_FCTL; 870 } 871 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) { 872 s->flags &= ~SCSW_FLAGS_MASK_PNO; 873 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 874 SCSW_ACTL_START_PEND | 875 SCSW_ACTL_HALT_PEND | 876 SCSW_ACTL_CLEAR_PEND | 877 SCSW_ACTL_SUSP); 878 } else { 879 if ((actl & SCSW_ACTL_SUSP) && 880 (fctl & SCSW_FCTL_START_FUNC)) { 881 s->flags &= ~SCSW_FLAGS_MASK_PNO; 882 if (fctl & SCSW_FCTL_HALT_FUNC) { 883 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 884 SCSW_ACTL_START_PEND | 885 SCSW_ACTL_HALT_PEND | 886 SCSW_ACTL_CLEAR_PEND | 887 SCSW_ACTL_SUSP); 888 } else { 889 s->ctrl &= ~SCSW_ACTL_RESUME_PEND; 890 } 891 } 892 } 893 /* Clear pending sense data. */ 894 if (p->chars & PMCW_CHARS_MASK_CSENSE) { 895 memset(sch->sense_data, 0 , sizeof(sch->sense_data)); 896 } 897 } 898 899 ret = ((stctl & SCSW_STCTL_STATUS_PEND) == 0); 900 901 out: 902 return ret; 903 } 904 905 static void copy_crw_to_guest(CRW *dest, const CRW *src) 906 { 907 dest->flags = cpu_to_be16(src->flags); 908 dest->rsid = cpu_to_be16(src->rsid); 909 } 910 911 int css_do_stcrw(CRW *crw) 912 { 913 CrwContainer *crw_cont; 914 int ret; 915 916 crw_cont = QTAILQ_FIRST(&channel_subsys->pending_crws); 917 if (crw_cont) { 918 QTAILQ_REMOVE(&channel_subsys->pending_crws, crw_cont, sibling); 919 copy_crw_to_guest(crw, &crw_cont->crw); 920 g_free(crw_cont); 921 ret = 0; 922 } else { 923 /* List was empty, turn crw machine checks on again. */ 924 memset(crw, 0, sizeof(*crw)); 925 channel_subsys->do_crw_mchk = true; 926 ret = 1; 927 } 928 929 return ret; 930 } 931 932 int css_do_tpi(IOIntCode *int_code, int lowcore) 933 { 934 /* No pending interrupts for !KVM. */ 935 return 0; 936 } 937 938 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, 939 int rfmt, void *buf) 940 { 941 int i, desc_size; 942 uint32_t words[8]; 943 uint32_t chpid_type_word; 944 CssImage *css; 945 946 if (!m && !cssid) { 947 css = channel_subsys->css[channel_subsys->default_cssid]; 948 } else { 949 css = channel_subsys->css[cssid]; 950 } 951 if (!css) { 952 return 0; 953 } 954 desc_size = 0; 955 for (i = f_chpid; i <= l_chpid; i++) { 956 if (css->chpids[i].in_use) { 957 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i; 958 if (rfmt == 0) { 959 words[0] = cpu_to_be32(chpid_type_word); 960 words[1] = 0; 961 memcpy(buf + desc_size, words, 8); 962 desc_size += 8; 963 } else if (rfmt == 1) { 964 words[0] = cpu_to_be32(chpid_type_word); 965 words[1] = 0; 966 words[2] = 0; 967 words[3] = 0; 968 words[4] = 0; 969 words[5] = 0; 970 words[6] = 0; 971 words[7] = 0; 972 memcpy(buf + desc_size, words, 32); 973 desc_size += 32; 974 } 975 } 976 } 977 return desc_size; 978 } 979 980 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo) 981 { 982 /* dct is currently ignored (not really meaningful for our devices) */ 983 /* TODO: Don't ignore mbk. */ 984 if (update && !channel_subsys->chnmon_active) { 985 /* Enable measuring. */ 986 channel_subsys->chnmon_area = mbo; 987 channel_subsys->chnmon_active = true; 988 } 989 if (!update && channel_subsys->chnmon_active) { 990 /* Disable measuring. */ 991 channel_subsys->chnmon_area = 0; 992 channel_subsys->chnmon_active = false; 993 } 994 } 995 996 int css_do_rsch(SubchDev *sch) 997 { 998 SCSW *s = &sch->curr_status.scsw; 999 PMCW *p = &sch->curr_status.pmcw; 1000 int ret; 1001 1002 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 1003 ret = -ENODEV; 1004 goto out; 1005 } 1006 1007 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 1008 ret = -EINPROGRESS; 1009 goto out; 1010 } 1011 1012 if (((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1013 (s->ctrl & SCSW_ACTL_RESUME_PEND) || 1014 (!(s->ctrl & SCSW_ACTL_SUSP))) { 1015 ret = -EINVAL; 1016 goto out; 1017 } 1018 1019 /* If monitoring is active, update counter. */ 1020 if (channel_subsys->chnmon_active) { 1021 css_update_chnmon(sch); 1022 } 1023 1024 s->ctrl |= SCSW_ACTL_RESUME_PEND; 1025 do_subchannel_work(sch, NULL); 1026 ret = 0; 1027 1028 out: 1029 return ret; 1030 } 1031 1032 int css_do_rchp(uint8_t cssid, uint8_t chpid) 1033 { 1034 uint8_t real_cssid; 1035 1036 if (cssid > channel_subsys->max_cssid) { 1037 return -EINVAL; 1038 } 1039 if (channel_subsys->max_cssid == 0) { 1040 real_cssid = channel_subsys->default_cssid; 1041 } else { 1042 real_cssid = cssid; 1043 } 1044 if (!channel_subsys->css[real_cssid]) { 1045 return -EINVAL; 1046 } 1047 1048 if (!channel_subsys->css[real_cssid]->chpids[chpid].in_use) { 1049 return -ENODEV; 1050 } 1051 1052 if (!channel_subsys->css[real_cssid]->chpids[chpid].is_virtual) { 1053 fprintf(stderr, 1054 "rchp unsupported for non-virtual chpid %x.%02x!\n", 1055 real_cssid, chpid); 1056 return -ENODEV; 1057 } 1058 1059 /* We don't really use a channel path, so we're done here. */ 1060 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1061 channel_subsys->max_cssid > 0 ? 1 : 0, chpid); 1062 if (channel_subsys->max_cssid > 0) { 1063 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 0, real_cssid << 8); 1064 } 1065 return 0; 1066 } 1067 1068 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1069 { 1070 SubchSet *set; 1071 uint8_t real_cssid; 1072 1073 real_cssid = (!m && (cssid == 0)) ? channel_subsys->default_cssid : cssid; 1074 if (real_cssid > MAX_CSSID || ssid > MAX_SSID || 1075 !channel_subsys->css[real_cssid] || 1076 !channel_subsys->css[real_cssid]->sch_set[ssid]) { 1077 return true; 1078 } 1079 set = channel_subsys->css[real_cssid]->sch_set[ssid]; 1080 return schid > find_last_bit(set->schids_used, 1081 (MAX_SCHID + 1) / sizeof(unsigned long)); 1082 } 1083 1084 static int css_add_virtual_chpid(uint8_t cssid, uint8_t chpid, uint8_t type) 1085 { 1086 CssImage *css; 1087 1088 trace_css_chpid_add(cssid, chpid, type); 1089 if (cssid > MAX_CSSID) { 1090 return -EINVAL; 1091 } 1092 css = channel_subsys->css[cssid]; 1093 if (!css) { 1094 return -EINVAL; 1095 } 1096 if (css->chpids[chpid].in_use) { 1097 return -EEXIST; 1098 } 1099 css->chpids[chpid].in_use = 1; 1100 css->chpids[chpid].type = type; 1101 css->chpids[chpid].is_virtual = 1; 1102 1103 css_generate_chp_crws(cssid, chpid); 1104 1105 return 0; 1106 } 1107 1108 void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type) 1109 { 1110 PMCW *p = &sch->curr_status.pmcw; 1111 SCSW *s = &sch->curr_status.scsw; 1112 int i; 1113 CssImage *css = channel_subsys->css[sch->cssid]; 1114 1115 assert(css != NULL); 1116 memset(p, 0, sizeof(PMCW)); 1117 p->flags |= PMCW_FLAGS_MASK_DNV; 1118 p->devno = sch->devno; 1119 /* single path */ 1120 p->pim = 0x80; 1121 p->pom = 0xff; 1122 p->pam = 0x80; 1123 p->chpid[0] = chpid; 1124 if (!css->chpids[chpid].in_use) { 1125 css_add_virtual_chpid(sch->cssid, chpid, type); 1126 } 1127 1128 memset(s, 0, sizeof(SCSW)); 1129 sch->curr_status.mba = 0; 1130 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) { 1131 sch->curr_status.mda[i] = 0; 1132 } 1133 } 1134 1135 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1136 { 1137 uint8_t real_cssid; 1138 1139 real_cssid = (!m && (cssid == 0)) ? channel_subsys->default_cssid : cssid; 1140 1141 if (!channel_subsys->css[real_cssid]) { 1142 return NULL; 1143 } 1144 1145 if (!channel_subsys->css[real_cssid]->sch_set[ssid]) { 1146 return NULL; 1147 } 1148 1149 return channel_subsys->css[real_cssid]->sch_set[ssid]->sch[schid]; 1150 } 1151 1152 bool css_subch_visible(SubchDev *sch) 1153 { 1154 if (sch->ssid > channel_subsys->max_ssid) { 1155 return false; 1156 } 1157 1158 if (sch->cssid != channel_subsys->default_cssid) { 1159 return (channel_subsys->max_cssid > 0); 1160 } 1161 1162 return true; 1163 } 1164 1165 bool css_present(uint8_t cssid) 1166 { 1167 return (channel_subsys->css[cssid] != NULL); 1168 } 1169 1170 bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno) 1171 { 1172 if (!channel_subsys->css[cssid]) { 1173 return false; 1174 } 1175 if (!channel_subsys->css[cssid]->sch_set[ssid]) { 1176 return false; 1177 } 1178 1179 return !!test_bit(devno, 1180 channel_subsys->css[cssid]->sch_set[ssid]->devnos_used); 1181 } 1182 1183 void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid, 1184 uint16_t devno, SubchDev *sch) 1185 { 1186 CssImage *css; 1187 SubchSet *s_set; 1188 1189 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid, 1190 devno); 1191 if (!channel_subsys->css[cssid]) { 1192 fprintf(stderr, 1193 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n", 1194 __func__, cssid, ssid, schid); 1195 return; 1196 } 1197 css = channel_subsys->css[cssid]; 1198 1199 if (!css->sch_set[ssid]) { 1200 css->sch_set[ssid] = g_malloc0(sizeof(SubchSet)); 1201 } 1202 s_set = css->sch_set[ssid]; 1203 1204 s_set->sch[schid] = sch; 1205 if (sch) { 1206 set_bit(schid, s_set->schids_used); 1207 set_bit(devno, s_set->devnos_used); 1208 } else { 1209 clear_bit(schid, s_set->schids_used); 1210 clear_bit(devno, s_set->devnos_used); 1211 } 1212 } 1213 1214 void css_queue_crw(uint8_t rsc, uint8_t erc, int chain, uint16_t rsid) 1215 { 1216 CrwContainer *crw_cont; 1217 1218 trace_css_crw(rsc, erc, rsid, chain ? "(chained)" : ""); 1219 /* TODO: Maybe use a static crw pool? */ 1220 crw_cont = g_try_malloc0(sizeof(CrwContainer)); 1221 if (!crw_cont) { 1222 channel_subsys->crws_lost = true; 1223 return; 1224 } 1225 crw_cont->crw.flags = (rsc << 8) | erc; 1226 if (chain) { 1227 crw_cont->crw.flags |= CRW_FLAGS_MASK_C; 1228 } 1229 crw_cont->crw.rsid = rsid; 1230 if (channel_subsys->crws_lost) { 1231 crw_cont->crw.flags |= CRW_FLAGS_MASK_R; 1232 channel_subsys->crws_lost = false; 1233 } 1234 1235 QTAILQ_INSERT_TAIL(&channel_subsys->pending_crws, crw_cont, sibling); 1236 1237 if (channel_subsys->do_crw_mchk) { 1238 channel_subsys->do_crw_mchk = false; 1239 /* Inject crw pending machine check. */ 1240 s390_crw_mchk(); 1241 } 1242 } 1243 1244 void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid, 1245 int hotplugged, int add) 1246 { 1247 uint8_t guest_cssid; 1248 bool chain_crw; 1249 1250 if (add && !hotplugged) { 1251 return; 1252 } 1253 if (channel_subsys->max_cssid == 0) { 1254 /* Default cssid shows up as 0. */ 1255 guest_cssid = (cssid == channel_subsys->default_cssid) ? 0 : cssid; 1256 } else { 1257 /* Show real cssid to the guest. */ 1258 guest_cssid = cssid; 1259 } 1260 /* 1261 * Only notify for higher subchannel sets/channel subsystems if the 1262 * guest has enabled it. 1263 */ 1264 if ((ssid > channel_subsys->max_ssid) || 1265 (guest_cssid > channel_subsys->max_cssid) || 1266 ((channel_subsys->max_cssid == 0) && 1267 (cssid != channel_subsys->default_cssid))) { 1268 return; 1269 } 1270 chain_crw = (channel_subsys->max_ssid > 0) || 1271 (channel_subsys->max_cssid > 0); 1272 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, chain_crw ? 1 : 0, schid); 1273 if (chain_crw) { 1274 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 1275 (guest_cssid << 8) | (ssid << 4)); 1276 } 1277 } 1278 1279 void css_generate_chp_crws(uint8_t cssid, uint8_t chpid) 1280 { 1281 /* TODO */ 1282 } 1283 1284 int css_enable_mcsse(void) 1285 { 1286 trace_css_enable_facility("mcsse"); 1287 channel_subsys->max_cssid = MAX_CSSID; 1288 return 0; 1289 } 1290 1291 int css_enable_mss(void) 1292 { 1293 trace_css_enable_facility("mss"); 1294 channel_subsys->max_ssid = MAX_SSID; 1295 return 0; 1296 } 1297 1298 void subch_device_save(SubchDev *s, QEMUFile *f) 1299 { 1300 int i; 1301 1302 qemu_put_byte(f, s->cssid); 1303 qemu_put_byte(f, s->ssid); 1304 qemu_put_be16(f, s->schid); 1305 qemu_put_be16(f, s->devno); 1306 qemu_put_byte(f, s->thinint_active); 1307 /* SCHIB */ 1308 /* PMCW */ 1309 qemu_put_be32(f, s->curr_status.pmcw.intparm); 1310 qemu_put_be16(f, s->curr_status.pmcw.flags); 1311 qemu_put_be16(f, s->curr_status.pmcw.devno); 1312 qemu_put_byte(f, s->curr_status.pmcw.lpm); 1313 qemu_put_byte(f, s->curr_status.pmcw.pnom); 1314 qemu_put_byte(f, s->curr_status.pmcw.lpum); 1315 qemu_put_byte(f, s->curr_status.pmcw.pim); 1316 qemu_put_be16(f, s->curr_status.pmcw.mbi); 1317 qemu_put_byte(f, s->curr_status.pmcw.pom); 1318 qemu_put_byte(f, s->curr_status.pmcw.pam); 1319 qemu_put_buffer(f, s->curr_status.pmcw.chpid, 8); 1320 qemu_put_be32(f, s->curr_status.pmcw.chars); 1321 /* SCSW */ 1322 qemu_put_be16(f, s->curr_status.scsw.flags); 1323 qemu_put_be16(f, s->curr_status.scsw.ctrl); 1324 qemu_put_be32(f, s->curr_status.scsw.cpa); 1325 qemu_put_byte(f, s->curr_status.scsw.dstat); 1326 qemu_put_byte(f, s->curr_status.scsw.cstat); 1327 qemu_put_be16(f, s->curr_status.scsw.count); 1328 qemu_put_be64(f, s->curr_status.mba); 1329 qemu_put_buffer(f, s->curr_status.mda, 4); 1330 /* end SCHIB */ 1331 qemu_put_buffer(f, s->sense_data, 32); 1332 qemu_put_be64(f, s->channel_prog); 1333 /* last cmd */ 1334 qemu_put_byte(f, s->last_cmd.cmd_code); 1335 qemu_put_byte(f, s->last_cmd.flags); 1336 qemu_put_be16(f, s->last_cmd.count); 1337 qemu_put_be32(f, s->last_cmd.cda); 1338 qemu_put_byte(f, s->last_cmd_valid); 1339 qemu_put_byte(f, s->id.reserved); 1340 qemu_put_be16(f, s->id.cu_type); 1341 qemu_put_byte(f, s->id.cu_model); 1342 qemu_put_be16(f, s->id.dev_type); 1343 qemu_put_byte(f, s->id.dev_model); 1344 qemu_put_byte(f, s->id.unused); 1345 for (i = 0; i < ARRAY_SIZE(s->id.ciw); i++) { 1346 qemu_put_byte(f, s->id.ciw[i].type); 1347 qemu_put_byte(f, s->id.ciw[i].command); 1348 qemu_put_be16(f, s->id.ciw[i].count); 1349 } 1350 return; 1351 } 1352 1353 int subch_device_load(SubchDev *s, QEMUFile *f) 1354 { 1355 int i; 1356 1357 s->cssid = qemu_get_byte(f); 1358 s->ssid = qemu_get_byte(f); 1359 s->schid = qemu_get_be16(f); 1360 s->devno = qemu_get_be16(f); 1361 s->thinint_active = qemu_get_byte(f); 1362 /* SCHIB */ 1363 /* PMCW */ 1364 s->curr_status.pmcw.intparm = qemu_get_be32(f); 1365 s->curr_status.pmcw.flags = qemu_get_be16(f); 1366 s->curr_status.pmcw.devno = qemu_get_be16(f); 1367 s->curr_status.pmcw.lpm = qemu_get_byte(f); 1368 s->curr_status.pmcw.pnom = qemu_get_byte(f); 1369 s->curr_status.pmcw.lpum = qemu_get_byte(f); 1370 s->curr_status.pmcw.pim = qemu_get_byte(f); 1371 s->curr_status.pmcw.mbi = qemu_get_be16(f); 1372 s->curr_status.pmcw.pom = qemu_get_byte(f); 1373 s->curr_status.pmcw.pam = qemu_get_byte(f); 1374 qemu_get_buffer(f, s->curr_status.pmcw.chpid, 8); 1375 s->curr_status.pmcw.chars = qemu_get_be32(f); 1376 /* SCSW */ 1377 s->curr_status.scsw.flags = qemu_get_be16(f); 1378 s->curr_status.scsw.ctrl = qemu_get_be16(f); 1379 s->curr_status.scsw.cpa = qemu_get_be32(f); 1380 s->curr_status.scsw.dstat = qemu_get_byte(f); 1381 s->curr_status.scsw.cstat = qemu_get_byte(f); 1382 s->curr_status.scsw.count = qemu_get_be16(f); 1383 s->curr_status.mba = qemu_get_be64(f); 1384 qemu_get_buffer(f, s->curr_status.mda, 4); 1385 /* end SCHIB */ 1386 qemu_get_buffer(f, s->sense_data, 32); 1387 s->channel_prog = qemu_get_be64(f); 1388 /* last cmd */ 1389 s->last_cmd.cmd_code = qemu_get_byte(f); 1390 s->last_cmd.flags = qemu_get_byte(f); 1391 s->last_cmd.count = qemu_get_be16(f); 1392 s->last_cmd.cda = qemu_get_be32(f); 1393 s->last_cmd_valid = qemu_get_byte(f); 1394 s->id.reserved = qemu_get_byte(f); 1395 s->id.cu_type = qemu_get_be16(f); 1396 s->id.cu_model = qemu_get_byte(f); 1397 s->id.dev_type = qemu_get_be16(f); 1398 s->id.dev_model = qemu_get_byte(f); 1399 s->id.unused = qemu_get_byte(f); 1400 for (i = 0; i < ARRAY_SIZE(s->id.ciw); i++) { 1401 s->id.ciw[i].type = qemu_get_byte(f); 1402 s->id.ciw[i].command = qemu_get_byte(f); 1403 s->id.ciw[i].count = qemu_get_be16(f); 1404 } 1405 return 0; 1406 } 1407 1408 1409 static void css_init(void) 1410 { 1411 channel_subsys = g_malloc0(sizeof(*channel_subsys)); 1412 QTAILQ_INIT(&channel_subsys->pending_crws); 1413 channel_subsys->do_crw_mchk = true; 1414 channel_subsys->crws_lost = false; 1415 channel_subsys->chnmon_active = false; 1416 QTAILQ_INIT(&channel_subsys->io_adapters); 1417 } 1418 machine_init(css_init); 1419 1420 void css_reset_sch(SubchDev *sch) 1421 { 1422 PMCW *p = &sch->curr_status.pmcw; 1423 1424 p->intparm = 0; 1425 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1426 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1427 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF); 1428 p->flags |= PMCW_FLAGS_MASK_DNV; 1429 p->devno = sch->devno; 1430 p->pim = 0x80; 1431 p->lpm = p->pim; 1432 p->pnom = 0; 1433 p->lpum = 0; 1434 p->mbi = 0; 1435 p->pom = 0xff; 1436 p->pam = 0x80; 1437 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME | 1438 PMCW_CHARS_MASK_CSENSE); 1439 1440 memset(&sch->curr_status.scsw, 0, sizeof(sch->curr_status.scsw)); 1441 sch->curr_status.mba = 0; 1442 1443 sch->channel_prog = 0x0; 1444 sch->last_cmd_valid = false; 1445 sch->thinint_active = false; 1446 } 1447 1448 void css_reset(void) 1449 { 1450 CrwContainer *crw_cont; 1451 1452 /* Clean up monitoring. */ 1453 channel_subsys->chnmon_active = false; 1454 channel_subsys->chnmon_area = 0; 1455 1456 /* Clear pending CRWs. */ 1457 while ((crw_cont = QTAILQ_FIRST(&channel_subsys->pending_crws))) { 1458 QTAILQ_REMOVE(&channel_subsys->pending_crws, crw_cont, sibling); 1459 g_free(crw_cont); 1460 } 1461 channel_subsys->do_crw_mchk = true; 1462 channel_subsys->crws_lost = false; 1463 1464 /* Reset maximum ids. */ 1465 channel_subsys->max_cssid = 0; 1466 channel_subsys->max_ssid = 0; 1467 } 1468