1 /* 2 * Channel subsystem base support. 3 * 4 * Copyright 2012 IBM Corp. 5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or (at 8 * your option) any later version. See the COPYING file in the top-level 9 * directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qapi/visitor.h" 15 #include "hw/qdev.h" 16 #include "qemu/error-report.h" 17 #include "qemu/bitops.h" 18 #include "qemu/error-report.h" 19 #include "exec/address-spaces.h" 20 #include "cpu.h" 21 #include "hw/s390x/ioinst.h" 22 #include "hw/s390x/css.h" 23 #include "trace.h" 24 #include "hw/s390x/s390_flic.h" 25 #include "hw/s390x/s390-virtio-ccw.h" 26 27 typedef struct CrwContainer { 28 CRW crw; 29 QTAILQ_ENTRY(CrwContainer) sibling; 30 } CrwContainer; 31 32 static const VMStateDescription vmstate_crw = { 33 .name = "s390_crw", 34 .version_id = 1, 35 .minimum_version_id = 1, 36 .fields = (VMStateField[]) { 37 VMSTATE_UINT16(flags, CRW), 38 VMSTATE_UINT16(rsid, CRW), 39 VMSTATE_END_OF_LIST() 40 }, 41 }; 42 43 static const VMStateDescription vmstate_crw_container = { 44 .name = "s390_crw_container", 45 .version_id = 1, 46 .minimum_version_id = 1, 47 .fields = (VMStateField[]) { 48 VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW), 49 VMSTATE_END_OF_LIST() 50 }, 51 }; 52 53 typedef struct ChpInfo { 54 uint8_t in_use; 55 uint8_t type; 56 uint8_t is_virtual; 57 } ChpInfo; 58 59 static const VMStateDescription vmstate_chp_info = { 60 .name = "s390_chp_info", 61 .version_id = 1, 62 .minimum_version_id = 1, 63 .fields = (VMStateField[]) { 64 VMSTATE_UINT8(in_use, ChpInfo), 65 VMSTATE_UINT8(type, ChpInfo), 66 VMSTATE_UINT8(is_virtual, ChpInfo), 67 VMSTATE_END_OF_LIST() 68 } 69 }; 70 71 typedef struct SubchSet { 72 SubchDev *sch[MAX_SCHID + 1]; 73 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 74 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 75 } SubchSet; 76 77 static const VMStateDescription vmstate_scsw = { 78 .name = "s390_scsw", 79 .version_id = 1, 80 .minimum_version_id = 1, 81 .fields = (VMStateField[]) { 82 VMSTATE_UINT16(flags, SCSW), 83 VMSTATE_UINT16(ctrl, SCSW), 84 VMSTATE_UINT32(cpa, SCSW), 85 VMSTATE_UINT8(dstat, SCSW), 86 VMSTATE_UINT8(cstat, SCSW), 87 VMSTATE_UINT16(count, SCSW), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 static const VMStateDescription vmstate_pmcw = { 93 .name = "s390_pmcw", 94 .version_id = 1, 95 .minimum_version_id = 1, 96 .fields = (VMStateField[]) { 97 VMSTATE_UINT32(intparm, PMCW), 98 VMSTATE_UINT16(flags, PMCW), 99 VMSTATE_UINT16(devno, PMCW), 100 VMSTATE_UINT8(lpm, PMCW), 101 VMSTATE_UINT8(pnom, PMCW), 102 VMSTATE_UINT8(lpum, PMCW), 103 VMSTATE_UINT8(pim, PMCW), 104 VMSTATE_UINT16(mbi, PMCW), 105 VMSTATE_UINT8(pom, PMCW), 106 VMSTATE_UINT8(pam, PMCW), 107 VMSTATE_UINT8_ARRAY(chpid, PMCW, 8), 108 VMSTATE_UINT32(chars, PMCW), 109 VMSTATE_END_OF_LIST() 110 } 111 }; 112 113 static const VMStateDescription vmstate_schib = { 114 .name = "s390_schib", 115 .version_id = 1, 116 .minimum_version_id = 1, 117 .fields = (VMStateField[]) { 118 VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW), 119 VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW), 120 VMSTATE_UINT64(mba, SCHIB), 121 VMSTATE_UINT8_ARRAY(mda, SCHIB, 4), 122 VMSTATE_END_OF_LIST() 123 } 124 }; 125 126 127 static const VMStateDescription vmstate_ccw1 = { 128 .name = "s390_ccw1", 129 .version_id = 1, 130 .minimum_version_id = 1, 131 .fields = (VMStateField[]) { 132 VMSTATE_UINT8(cmd_code, CCW1), 133 VMSTATE_UINT8(flags, CCW1), 134 VMSTATE_UINT16(count, CCW1), 135 VMSTATE_UINT32(cda, CCW1), 136 VMSTATE_END_OF_LIST() 137 } 138 }; 139 140 static const VMStateDescription vmstate_ciw = { 141 .name = "s390_ciw", 142 .version_id = 1, 143 .minimum_version_id = 1, 144 .fields = (VMStateField[]) { 145 VMSTATE_UINT8(type, CIW), 146 VMSTATE_UINT8(command, CIW), 147 VMSTATE_UINT16(count, CIW), 148 VMSTATE_END_OF_LIST() 149 } 150 }; 151 152 static const VMStateDescription vmstate_sense_id = { 153 .name = "s390_sense_id", 154 .version_id = 1, 155 .minimum_version_id = 1, 156 .fields = (VMStateField[]) { 157 VMSTATE_UINT8(reserved, SenseId), 158 VMSTATE_UINT16(cu_type, SenseId), 159 VMSTATE_UINT8(cu_model, SenseId), 160 VMSTATE_UINT16(dev_type, SenseId), 161 VMSTATE_UINT8(dev_model, SenseId), 162 VMSTATE_UINT8(unused, SenseId), 163 VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW), 164 VMSTATE_END_OF_LIST() 165 } 166 }; 167 168 static const VMStateDescription vmstate_orb = { 169 .name = "s390_orb", 170 .version_id = 1, 171 .minimum_version_id = 1, 172 .fields = (VMStateField[]) { 173 VMSTATE_UINT32(intparm, ORB), 174 VMSTATE_UINT16(ctrl0, ORB), 175 VMSTATE_UINT8(lpm, ORB), 176 VMSTATE_UINT8(ctrl1, ORB), 177 VMSTATE_UINT32(cpa, ORB), 178 VMSTATE_END_OF_LIST() 179 } 180 }; 181 182 static bool vmstate_schdev_orb_needed(void *opaque) 183 { 184 return css_migration_enabled(); 185 } 186 187 static const VMStateDescription vmstate_schdev_orb = { 188 .name = "s390_subch_dev/orb", 189 .version_id = 1, 190 .minimum_version_id = 1, 191 .needed = vmstate_schdev_orb_needed, 192 .fields = (VMStateField[]) { 193 VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB), 194 VMSTATE_END_OF_LIST() 195 } 196 }; 197 198 static int subch_dev_post_load(void *opaque, int version_id); 199 static int subch_dev_pre_save(void *opaque); 200 201 const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!" 202 " Likely reason: some sequences of plug and unplug can break" 203 " migration for machine versions prior to 2.7 (known design flaw)."; 204 205 const VMStateDescription vmstate_subch_dev = { 206 .name = "s390_subch_dev", 207 .version_id = 1, 208 .minimum_version_id = 1, 209 .post_load = subch_dev_post_load, 210 .pre_save = subch_dev_pre_save, 211 .fields = (VMStateField[]) { 212 VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"), 213 VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"), 214 VMSTATE_UINT16(migrated_schid, SubchDev), 215 VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno), 216 VMSTATE_BOOL(thinint_active, SubchDev), 217 VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB), 218 VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32), 219 VMSTATE_UINT64(channel_prog, SubchDev), 220 VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1), 221 VMSTATE_BOOL(last_cmd_valid, SubchDev), 222 VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId), 223 VMSTATE_BOOL(ccw_fmt_1, SubchDev), 224 VMSTATE_UINT8(ccw_no_data_cnt, SubchDev), 225 VMSTATE_END_OF_LIST() 226 }, 227 .subsections = (const VMStateDescription * []) { 228 &vmstate_schdev_orb, 229 NULL 230 } 231 }; 232 233 typedef struct IndAddrPtrTmp { 234 IndAddr **parent; 235 uint64_t addr; 236 int32_t len; 237 } IndAddrPtrTmp; 238 239 static int post_load_ind_addr(void *opaque, int version_id) 240 { 241 IndAddrPtrTmp *ptmp = opaque; 242 IndAddr **ind_addr = ptmp->parent; 243 244 if (ptmp->len != 0) { 245 *ind_addr = get_indicator(ptmp->addr, ptmp->len); 246 } else { 247 *ind_addr = NULL; 248 } 249 return 0; 250 } 251 252 static int pre_save_ind_addr(void *opaque) 253 { 254 IndAddrPtrTmp *ptmp = opaque; 255 IndAddr *ind_addr = *(ptmp->parent); 256 257 if (ind_addr != NULL) { 258 ptmp->len = ind_addr->len; 259 ptmp->addr = ind_addr->addr; 260 } else { 261 ptmp->len = 0; 262 ptmp->addr = 0L; 263 } 264 265 return 0; 266 } 267 268 const VMStateDescription vmstate_ind_addr_tmp = { 269 .name = "s390_ind_addr_tmp", 270 .pre_save = pre_save_ind_addr, 271 .post_load = post_load_ind_addr, 272 273 .fields = (VMStateField[]) { 274 VMSTATE_INT32(len, IndAddrPtrTmp), 275 VMSTATE_UINT64(addr, IndAddrPtrTmp), 276 VMSTATE_END_OF_LIST() 277 } 278 }; 279 280 const VMStateDescription vmstate_ind_addr = { 281 .name = "s390_ind_addr_tmp", 282 .fields = (VMStateField[]) { 283 VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp), 284 VMSTATE_END_OF_LIST() 285 } 286 }; 287 288 typedef struct CssImage { 289 SubchSet *sch_set[MAX_SSID + 1]; 290 ChpInfo chpids[MAX_CHPID + 1]; 291 } CssImage; 292 293 static const VMStateDescription vmstate_css_img = { 294 .name = "s390_css_img", 295 .version_id = 1, 296 .minimum_version_id = 1, 297 .fields = (VMStateField[]) { 298 /* Subchannel sets have no relevant state. */ 299 VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0, 300 vmstate_chp_info, ChpInfo), 301 VMSTATE_END_OF_LIST() 302 } 303 304 }; 305 306 typedef struct IoAdapter { 307 uint32_t id; 308 uint8_t type; 309 uint8_t isc; 310 uint8_t flags; 311 } IoAdapter; 312 313 typedef struct ChannelSubSys { 314 QTAILQ_HEAD(, CrwContainer) pending_crws; 315 bool sei_pending; 316 bool do_crw_mchk; 317 bool crws_lost; 318 uint8_t max_cssid; 319 uint8_t max_ssid; 320 bool chnmon_active; 321 uint64_t chnmon_area; 322 CssImage *css[MAX_CSSID + 1]; 323 uint8_t default_cssid; 324 /* don't migrate, see css_register_io_adapters */ 325 IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1]; 326 /* don't migrate, see get_indicator and IndAddrPtrTmp */ 327 QTAILQ_HEAD(, IndAddr) indicator_addresses; 328 } ChannelSubSys; 329 330 static const VMStateDescription vmstate_css = { 331 .name = "s390_css", 332 .version_id = 1, 333 .minimum_version_id = 1, 334 .fields = (VMStateField[]) { 335 VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container, 336 CrwContainer, sibling), 337 VMSTATE_BOOL(sei_pending, ChannelSubSys), 338 VMSTATE_BOOL(do_crw_mchk, ChannelSubSys), 339 VMSTATE_BOOL(crws_lost, ChannelSubSys), 340 /* These were kind of migrated by virtio */ 341 VMSTATE_UINT8(max_cssid, ChannelSubSys), 342 VMSTATE_UINT8(max_ssid, ChannelSubSys), 343 VMSTATE_BOOL(chnmon_active, ChannelSubSys), 344 VMSTATE_UINT64(chnmon_area, ChannelSubSys), 345 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1, 346 0, vmstate_css_img, CssImage), 347 VMSTATE_UINT8(default_cssid, ChannelSubSys), 348 VMSTATE_END_OF_LIST() 349 } 350 }; 351 352 static ChannelSubSys channel_subsys = { 353 .pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws), 354 .do_crw_mchk = true, 355 .sei_pending = false, 356 .do_crw_mchk = true, 357 .crws_lost = false, 358 .chnmon_active = false, 359 .indicator_addresses = 360 QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses), 361 }; 362 363 static int subch_dev_pre_save(void *opaque) 364 { 365 SubchDev *s = opaque; 366 367 /* Prepare remote_schid for save */ 368 s->migrated_schid = s->schid; 369 370 return 0; 371 } 372 373 static int subch_dev_post_load(void *opaque, int version_id) 374 { 375 376 SubchDev *s = opaque; 377 378 /* Re-assign the subchannel to remote_schid if necessary */ 379 if (s->migrated_schid != s->schid) { 380 if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) { 381 /* 382 * Cleanup the slot before moving to s->migrated_schid provided 383 * it still belongs to us, i.e. it was not changed by previous 384 * invocation of this function. 385 */ 386 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL); 387 } 388 /* It's OK to re-assign without a prior de-assign. */ 389 s->schid = s->migrated_schid; 390 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s); 391 } 392 393 if (css_migration_enabled()) { 394 /* No compat voodoo to do ;) */ 395 return 0; 396 } 397 /* 398 * Hack alert. If we don't migrate the channel subsystem status 399 * we still need to find out if the guest enabled mss/mcss-e. 400 * If the subchannel is enabled, it certainly was able to access it, 401 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid 402 * values. This is not watertight, but better than nothing. 403 */ 404 if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) { 405 if (s->ssid) { 406 channel_subsys.max_ssid = MAX_SSID; 407 } 408 if (s->cssid != channel_subsys.default_cssid) { 409 channel_subsys.max_cssid = MAX_CSSID; 410 } 411 } 412 return 0; 413 } 414 415 void css_register_vmstate(void) 416 { 417 vmstate_register(NULL, 0, &vmstate_css, &channel_subsys); 418 } 419 420 IndAddr *get_indicator(hwaddr ind_addr, int len) 421 { 422 IndAddr *indicator; 423 424 QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) { 425 if (indicator->addr == ind_addr) { 426 indicator->refcnt++; 427 return indicator; 428 } 429 } 430 indicator = g_new0(IndAddr, 1); 431 indicator->addr = ind_addr; 432 indicator->len = len; 433 indicator->refcnt = 1; 434 QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses, 435 indicator, sibling); 436 return indicator; 437 } 438 439 static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr, 440 bool do_map) 441 { 442 S390FLICState *fs = s390_get_flic(); 443 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs); 444 445 return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map); 446 } 447 448 void release_indicator(AdapterInfo *adapter, IndAddr *indicator) 449 { 450 assert(indicator->refcnt > 0); 451 indicator->refcnt--; 452 if (indicator->refcnt > 0) { 453 return; 454 } 455 QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling); 456 if (indicator->map) { 457 s390_io_adapter_map(adapter, indicator->map, false); 458 } 459 g_free(indicator); 460 } 461 462 int map_indicator(AdapterInfo *adapter, IndAddr *indicator) 463 { 464 int ret; 465 466 if (indicator->map) { 467 return 0; /* already mapped is not an error */ 468 } 469 indicator->map = indicator->addr; 470 ret = s390_io_adapter_map(adapter, indicator->map, true); 471 if ((ret != 0) && (ret != -ENOSYS)) { 472 goto out_err; 473 } 474 return 0; 475 476 out_err: 477 indicator->map = 0; 478 return ret; 479 } 480 481 int css_create_css_image(uint8_t cssid, bool default_image) 482 { 483 trace_css_new_image(cssid, default_image ? "(default)" : ""); 484 /* 255 is reserved */ 485 if (cssid == 255) { 486 return -EINVAL; 487 } 488 if (channel_subsys.css[cssid]) { 489 return -EBUSY; 490 } 491 channel_subsys.css[cssid] = g_new0(CssImage, 1); 492 if (default_image) { 493 channel_subsys.default_cssid = cssid; 494 } 495 return 0; 496 } 497 498 uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc) 499 { 500 if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC || 501 !channel_subsys.io_adapters[type][isc]) { 502 return -1; 503 } 504 505 return channel_subsys.io_adapters[type][isc]->id; 506 } 507 508 /** 509 * css_register_io_adapters: Register I/O adapters per ISC during init 510 * 511 * @swap: an indication if byte swap is needed. 512 * @maskable: an indication if the adapter is subject to the mask operation. 513 * @flags: further characteristics of the adapter. 514 * e.g. suppressible, an indication if the adapter is subject to AIS. 515 * @errp: location to store error information. 516 */ 517 void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable, 518 uint8_t flags, Error **errp) 519 { 520 uint32_t id; 521 int ret, isc; 522 IoAdapter *adapter; 523 S390FLICState *fs = s390_get_flic(); 524 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs); 525 526 /* 527 * Disallow multiple registrations for the same device type. 528 * Report an error if registering for an already registered type. 529 */ 530 if (channel_subsys.io_adapters[type][0]) { 531 error_setg(errp, "Adapters for type %d already registered", type); 532 } 533 534 for (isc = 0; isc <= MAX_ISC; isc++) { 535 id = (type << 3) | isc; 536 ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags); 537 if (ret == 0) { 538 adapter = g_new0(IoAdapter, 1); 539 adapter->id = id; 540 adapter->isc = isc; 541 adapter->type = type; 542 adapter->flags = flags; 543 channel_subsys.io_adapters[type][isc] = adapter; 544 } else { 545 error_setg_errno(errp, -ret, "Unexpected error %d when " 546 "registering adapter %d", ret, id); 547 break; 548 } 549 } 550 551 /* 552 * No need to free registered adapters in kvm: kvm will clean up 553 * when the machine goes away. 554 */ 555 if (ret) { 556 for (isc--; isc >= 0; isc--) { 557 g_free(channel_subsys.io_adapters[type][isc]); 558 channel_subsys.io_adapters[type][isc] = NULL; 559 } 560 } 561 562 } 563 564 static void css_clear_io_interrupt(uint16_t subchannel_id, 565 uint16_t subchannel_nr) 566 { 567 Error *err = NULL; 568 static bool no_clear_irq; 569 S390FLICState *fs = s390_get_flic(); 570 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs); 571 int r; 572 573 if (unlikely(no_clear_irq)) { 574 return; 575 } 576 r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr); 577 switch (r) { 578 case 0: 579 break; 580 case -ENOSYS: 581 no_clear_irq = true; 582 /* 583 * Ignore unavailability, as the user can't do anything 584 * about it anyway. 585 */ 586 break; 587 default: 588 error_setg_errno(&err, -r, "unexpected error condition"); 589 error_propagate(&error_abort, err); 590 } 591 } 592 593 static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid) 594 { 595 if (channel_subsys.max_cssid > 0) { 596 return (cssid << 8) | (1 << 3) | (ssid << 1) | 1; 597 } 598 return (ssid << 1) | 1; 599 } 600 601 uint16_t css_build_subchannel_id(SubchDev *sch) 602 { 603 return css_do_build_subchannel_id(sch->cssid, sch->ssid); 604 } 605 606 void css_inject_io_interrupt(SubchDev *sch) 607 { 608 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 609 610 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 611 sch->curr_status.pmcw.intparm, isc, ""); 612 s390_io_interrupt(css_build_subchannel_id(sch), 613 sch->schid, 614 sch->curr_status.pmcw.intparm, 615 isc << 27); 616 } 617 618 void css_conditional_io_interrupt(SubchDev *sch) 619 { 620 /* 621 * If the subchannel is not currently status pending, make it pending 622 * with alert status. 623 */ 624 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) { 625 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 626 627 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 628 sch->curr_status.pmcw.intparm, isc, 629 "(unsolicited)"); 630 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 631 sch->curr_status.scsw.ctrl |= 632 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 633 /* Inject an I/O interrupt. */ 634 s390_io_interrupt(css_build_subchannel_id(sch), 635 sch->schid, 636 sch->curr_status.pmcw.intparm, 637 isc << 27); 638 } 639 } 640 641 int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode) 642 { 643 S390FLICState *fs = s390_get_flic(); 644 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs); 645 int r; 646 647 if (env->psw.mask & PSW_MASK_PSTATE) { 648 r = -PGM_PRIVILEGED; 649 goto out; 650 } 651 652 trace_css_do_sic(mode, isc); 653 switch (mode) { 654 case SIC_IRQ_MODE_ALL: 655 case SIC_IRQ_MODE_SINGLE: 656 break; 657 default: 658 r = -PGM_OPERAND; 659 goto out; 660 } 661 662 r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0; 663 out: 664 return r; 665 } 666 667 void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc) 668 { 669 S390FLICState *fs = s390_get_flic(); 670 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs); 671 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI; 672 IoAdapter *adapter = channel_subsys.io_adapters[type][isc]; 673 674 if (!adapter) { 675 return; 676 } 677 678 trace_css_adapter_interrupt(isc); 679 if (fs->ais_supported) { 680 if (fsc->inject_airq(fs, type, isc, adapter->flags)) { 681 error_report("Failed to inject airq with AIS supported"); 682 exit(1); 683 } 684 } else { 685 s390_io_interrupt(0, 0, 0, io_int_word); 686 } 687 } 688 689 static void sch_handle_clear_func(SubchDev *sch) 690 { 691 PMCW *p = &sch->curr_status.pmcw; 692 SCSW *s = &sch->curr_status.scsw; 693 int path; 694 695 /* Path management: In our simple css, we always choose the only path. */ 696 path = 0x80; 697 698 /* Reset values prior to 'issuing the clear signal'. */ 699 p->lpum = 0; 700 p->pom = 0xff; 701 s->flags &= ~SCSW_FLAGS_MASK_PNO; 702 703 /* We always 'attempt to issue the clear signal', and we always succeed. */ 704 sch->channel_prog = 0x0; 705 sch->last_cmd_valid = false; 706 s->ctrl &= ~SCSW_ACTL_CLEAR_PEND; 707 s->ctrl |= SCSW_STCTL_STATUS_PEND; 708 709 s->dstat = 0; 710 s->cstat = 0; 711 p->lpum = path; 712 713 } 714 715 static void sch_handle_halt_func(SubchDev *sch) 716 { 717 718 PMCW *p = &sch->curr_status.pmcw; 719 SCSW *s = &sch->curr_status.scsw; 720 hwaddr curr_ccw = sch->channel_prog; 721 int path; 722 723 /* Path management: In our simple css, we always choose the only path. */ 724 path = 0x80; 725 726 /* We always 'attempt to issue the halt signal', and we always succeed. */ 727 sch->channel_prog = 0x0; 728 sch->last_cmd_valid = false; 729 s->ctrl &= ~SCSW_ACTL_HALT_PEND; 730 s->ctrl |= SCSW_STCTL_STATUS_PEND; 731 732 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) || 733 !((s->ctrl & SCSW_ACTL_START_PEND) || 734 (s->ctrl & SCSW_ACTL_SUSP))) { 735 s->dstat = SCSW_DSTAT_DEVICE_END; 736 } 737 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) || 738 (s->ctrl & SCSW_ACTL_SUSP)) { 739 s->cpa = curr_ccw + 8; 740 } 741 s->cstat = 0; 742 p->lpum = path; 743 744 } 745 746 static void copy_sense_id_to_guest(SenseId *dest, SenseId *src) 747 { 748 int i; 749 750 dest->reserved = src->reserved; 751 dest->cu_type = cpu_to_be16(src->cu_type); 752 dest->cu_model = src->cu_model; 753 dest->dev_type = cpu_to_be16(src->dev_type); 754 dest->dev_model = src->dev_model; 755 dest->unused = src->unused; 756 for (i = 0; i < ARRAY_SIZE(dest->ciw); i++) { 757 dest->ciw[i].type = src->ciw[i].type; 758 dest->ciw[i].command = src->ciw[i].command; 759 dest->ciw[i].count = cpu_to_be16(src->ciw[i].count); 760 } 761 } 762 763 static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1) 764 { 765 CCW0 tmp0; 766 CCW1 tmp1; 767 CCW1 ret; 768 769 if (fmt1) { 770 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1)); 771 ret.cmd_code = tmp1.cmd_code; 772 ret.flags = tmp1.flags; 773 ret.count = be16_to_cpu(tmp1.count); 774 ret.cda = be32_to_cpu(tmp1.cda); 775 } else { 776 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0)); 777 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) { 778 ret.cmd_code = CCW_CMD_TIC; 779 ret.flags = 0; 780 ret.count = 0; 781 } else { 782 ret.cmd_code = tmp0.cmd_code; 783 ret.flags = tmp0.flags; 784 ret.count = be16_to_cpu(tmp0.count); 785 } 786 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16); 787 } 788 return ret; 789 } 790 /** 791 * If out of bounds marks the stream broken. If broken returns -EINVAL, 792 * otherwise the requested length (may be zero) 793 */ 794 static inline int cds_check_len(CcwDataStream *cds, int len) 795 { 796 if (cds->at_byte + len > cds->count) { 797 cds->flags |= CDS_F_STREAM_BROKEN; 798 } 799 return cds->flags & CDS_F_STREAM_BROKEN ? -EINVAL : len; 800 } 801 802 static inline bool cds_ccw_addrs_ok(hwaddr addr, int len, bool ccw_fmt1) 803 { 804 return (addr + len) < (ccw_fmt1 ? (1UL << 31) : (1UL << 24)); 805 } 806 807 static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len, 808 CcwDataStreamOp op) 809 { 810 int ret; 811 812 ret = cds_check_len(cds, len); 813 if (ret <= 0) { 814 return ret; 815 } 816 if (!cds_ccw_addrs_ok(cds->cda, len, cds->flags & CDS_F_FMT)) { 817 return -EINVAL; /* channel program check */ 818 } 819 if (op == CDS_OP_A) { 820 goto incr; 821 } 822 ret = address_space_rw(&address_space_memory, cds->cda, 823 MEMTXATTRS_UNSPECIFIED, buff, len, op); 824 if (ret != MEMTX_OK) { 825 cds->flags |= CDS_F_STREAM_BROKEN; 826 return -EINVAL; 827 } 828 incr: 829 cds->at_byte += len; 830 cds->cda += len; 831 return 0; 832 } 833 834 /* returns values between 1 and bsz, where bsz is a power of 2 */ 835 static inline uint16_t ida_continuous_left(hwaddr cda, uint64_t bsz) 836 { 837 return bsz - (cda & (bsz - 1)); 838 } 839 840 static inline uint64_t ccw_ida_block_size(uint8_t flags) 841 { 842 if ((flags & CDS_F_C64) && !(flags & CDS_F_I2K)) { 843 return 1ULL << 12; 844 } 845 return 1ULL << 11; 846 } 847 848 static inline int ida_read_next_idaw(CcwDataStream *cds) 849 { 850 union {uint64_t fmt2; uint32_t fmt1; } idaw; 851 int ret; 852 hwaddr idaw_addr; 853 bool idaw_fmt2 = cds->flags & CDS_F_C64; 854 bool ccw_fmt1 = cds->flags & CDS_F_FMT; 855 856 if (idaw_fmt2) { 857 idaw_addr = cds->cda_orig + sizeof(idaw.fmt2) * cds->at_idaw; 858 if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { 859 return -EINVAL; /* channel program check */ 860 } 861 ret = address_space_rw(&address_space_memory, idaw_addr, 862 MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt2, 863 sizeof(idaw.fmt2), false); 864 cds->cda = be64_to_cpu(idaw.fmt2); 865 } else { 866 idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw; 867 if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { 868 return -EINVAL; /* channel program check */ 869 } 870 ret = address_space_rw(&address_space_memory, idaw_addr, 871 MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt1, 872 sizeof(idaw.fmt1), false); 873 cds->cda = be64_to_cpu(idaw.fmt1); 874 if (cds->cda & 0x80000000) { 875 return -EINVAL; /* channel program check */ 876 } 877 } 878 ++(cds->at_idaw); 879 if (ret != MEMTX_OK) { 880 /* assume inaccessible address */ 881 return -EINVAL; /* channel program check */ 882 } 883 return 0; 884 } 885 886 static int ccw_dstream_rw_ida(CcwDataStream *cds, void *buff, int len, 887 CcwDataStreamOp op) 888 { 889 uint64_t bsz = ccw_ida_block_size(cds->flags); 890 int ret = 0; 891 uint16_t cont_left, iter_len; 892 893 ret = cds_check_len(cds, len); 894 if (ret <= 0) { 895 return ret; 896 } 897 if (!cds->at_idaw) { 898 /* read first idaw */ 899 ret = ida_read_next_idaw(cds); 900 if (ret) { 901 goto err; 902 } 903 cont_left = ida_continuous_left(cds->cda, bsz); 904 } else { 905 cont_left = ida_continuous_left(cds->cda, bsz); 906 if (cont_left == bsz) { 907 ret = ida_read_next_idaw(cds); 908 if (ret) { 909 goto err; 910 } 911 if (cds->cda & (bsz - 1)) { 912 ret = -EINVAL; /* channel program check */ 913 goto err; 914 } 915 } 916 } 917 do { 918 iter_len = MIN(len, cont_left); 919 if (op != CDS_OP_A) { 920 ret = address_space_rw(&address_space_memory, cds->cda, 921 MEMTXATTRS_UNSPECIFIED, buff, iter_len, op); 922 if (ret != MEMTX_OK) { 923 /* assume inaccessible address */ 924 ret = -EINVAL; /* channel program check */ 925 goto err; 926 } 927 } 928 cds->at_byte += iter_len; 929 cds->cda += iter_len; 930 len -= iter_len; 931 if (!len) { 932 break; 933 } 934 ret = ida_read_next_idaw(cds); 935 if (ret) { 936 goto err; 937 } 938 cont_left = bsz; 939 } while (true); 940 return ret; 941 err: 942 cds->flags |= CDS_F_STREAM_BROKEN; 943 return ret; 944 } 945 946 void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb) 947 { 948 /* 949 * We don't support MIDA (an optional facility) yet and we 950 * catch this earlier. Just for expressing the precondition. 951 */ 952 g_assert(!(orb->ctrl1 & ORB_CTRL1_MASK_MIDAW)); 953 cds->flags = (orb->ctrl0 & ORB_CTRL0_MASK_I2K ? CDS_F_I2K : 0) | 954 (orb->ctrl0 & ORB_CTRL0_MASK_C64 ? CDS_F_C64 : 0) | 955 (orb->ctrl0 & ORB_CTRL0_MASK_FMT ? CDS_F_FMT : 0) | 956 (ccw->flags & CCW_FLAG_IDA ? CDS_F_IDA : 0); 957 958 cds->count = ccw->count; 959 cds->cda_orig = ccw->cda; 960 ccw_dstream_rewind(cds); 961 if (!(cds->flags & CDS_F_IDA)) { 962 cds->op_handler = ccw_dstream_rw_noflags; 963 } else { 964 cds->op_handler = ccw_dstream_rw_ida; 965 } 966 } 967 968 static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr, 969 bool suspend_allowed) 970 { 971 int ret; 972 bool check_len; 973 int len; 974 CCW1 ccw; 975 976 if (!ccw_addr) { 977 return -EINVAL; /* channel-program check */ 978 } 979 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */ 980 if (ccw_addr & (sch->ccw_fmt_1 ? 0x80000007 : 0xff000007)) { 981 return -EINVAL; 982 } 983 984 /* Translate everything to format-1 ccws - the information is the same. */ 985 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1); 986 987 /* Check for invalid command codes. */ 988 if ((ccw.cmd_code & 0x0f) == 0) { 989 return -EINVAL; 990 } 991 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) && 992 ((ccw.cmd_code & 0xf0) != 0)) { 993 return -EINVAL; 994 } 995 if (!sch->ccw_fmt_1 && (ccw.count == 0) && 996 (ccw.cmd_code != CCW_CMD_TIC)) { 997 return -EINVAL; 998 } 999 1000 /* We don't support MIDA. */ 1001 if (ccw.flags & CCW_FLAG_MIDA) { 1002 return -EINVAL; 1003 } 1004 1005 if (ccw.flags & CCW_FLAG_SUSPEND) { 1006 return suspend_allowed ? -EINPROGRESS : -EINVAL; 1007 } 1008 1009 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC)); 1010 1011 if (!ccw.cda) { 1012 if (sch->ccw_no_data_cnt == 255) { 1013 return -EINVAL; 1014 } 1015 sch->ccw_no_data_cnt++; 1016 } 1017 1018 /* Look at the command. */ 1019 ccw_dstream_init(&sch->cds, &ccw, &(sch->orb)); 1020 switch (ccw.cmd_code) { 1021 case CCW_CMD_NOOP: 1022 /* Nothing to do. */ 1023 ret = 0; 1024 break; 1025 case CCW_CMD_BASIC_SENSE: 1026 if (check_len) { 1027 if (ccw.count != sizeof(sch->sense_data)) { 1028 ret = -EINVAL; 1029 break; 1030 } 1031 } 1032 len = MIN(ccw.count, sizeof(sch->sense_data)); 1033 ccw_dstream_write_buf(&sch->cds, sch->sense_data, len); 1034 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds); 1035 memset(sch->sense_data, 0, sizeof(sch->sense_data)); 1036 ret = 0; 1037 break; 1038 case CCW_CMD_SENSE_ID: 1039 { 1040 SenseId sense_id; 1041 1042 copy_sense_id_to_guest(&sense_id, &sch->id); 1043 /* Sense ID information is device specific. */ 1044 if (check_len) { 1045 if (ccw.count != sizeof(sense_id)) { 1046 ret = -EINVAL; 1047 break; 1048 } 1049 } 1050 len = MIN(ccw.count, sizeof(sense_id)); 1051 /* 1052 * Only indicate 0xff in the first sense byte if we actually 1053 * have enough place to store at least bytes 0-3. 1054 */ 1055 if (len >= 4) { 1056 sense_id.reserved = 0xff; 1057 } else { 1058 sense_id.reserved = 0; 1059 } 1060 ccw_dstream_write_buf(&sch->cds, &sense_id, len); 1061 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds); 1062 ret = 0; 1063 break; 1064 } 1065 case CCW_CMD_TIC: 1066 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) { 1067 ret = -EINVAL; 1068 break; 1069 } 1070 if (ccw.flags || ccw.count) { 1071 /* We have already sanitized these if converted from fmt 0. */ 1072 ret = -EINVAL; 1073 break; 1074 } 1075 sch->channel_prog = ccw.cda; 1076 ret = -EAGAIN; 1077 break; 1078 default: 1079 if (sch->ccw_cb) { 1080 /* Handle device specific commands. */ 1081 ret = sch->ccw_cb(sch, ccw); 1082 } else { 1083 ret = -ENOSYS; 1084 } 1085 break; 1086 } 1087 sch->last_cmd = ccw; 1088 sch->last_cmd_valid = true; 1089 if (ret == 0) { 1090 if (ccw.flags & CCW_FLAG_CC) { 1091 sch->channel_prog += 8; 1092 ret = -EAGAIN; 1093 } 1094 } 1095 1096 return ret; 1097 } 1098 1099 static void sch_handle_start_func_virtual(SubchDev *sch) 1100 { 1101 1102 PMCW *p = &sch->curr_status.pmcw; 1103 SCSW *s = &sch->curr_status.scsw; 1104 int path; 1105 int ret; 1106 bool suspend_allowed; 1107 1108 /* Path management: In our simple css, we always choose the only path. */ 1109 path = 0x80; 1110 1111 if (!(s->ctrl & SCSW_ACTL_SUSP)) { 1112 /* Start Function triggered via ssch, i.e. we have an ORB */ 1113 ORB *orb = &sch->orb; 1114 s->cstat = 0; 1115 s->dstat = 0; 1116 /* Look at the orb and try to execute the channel program. */ 1117 p->intparm = orb->intparm; 1118 if (!(orb->lpm & path)) { 1119 /* Generate a deferred cc 3 condition. */ 1120 s->flags |= SCSW_FLAGS_MASK_CC; 1121 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 1122 s->ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND); 1123 return; 1124 } 1125 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT); 1126 s->flags |= (sch->ccw_fmt_1) ? SCSW_FLAGS_MASK_FMT : 0; 1127 sch->ccw_no_data_cnt = 0; 1128 suspend_allowed = !!(orb->ctrl0 & ORB_CTRL0_MASK_SPND); 1129 } else { 1130 /* Start Function resumed via rsch */ 1131 s->ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND); 1132 /* The channel program had been suspended before. */ 1133 suspend_allowed = true; 1134 } 1135 sch->last_cmd_valid = false; 1136 do { 1137 ret = css_interpret_ccw(sch, sch->channel_prog, suspend_allowed); 1138 switch (ret) { 1139 case -EAGAIN: 1140 /* ccw chain, continue processing */ 1141 break; 1142 case 0: 1143 /* success */ 1144 s->ctrl &= ~SCSW_ACTL_START_PEND; 1145 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 1146 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1147 SCSW_STCTL_STATUS_PEND; 1148 s->dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END; 1149 s->cpa = sch->channel_prog + 8; 1150 break; 1151 case -EIO: 1152 /* I/O errors, status depends on specific devices */ 1153 break; 1154 case -ENOSYS: 1155 /* unsupported command, generate unit check (command reject) */ 1156 s->ctrl &= ~SCSW_ACTL_START_PEND; 1157 s->dstat = SCSW_DSTAT_UNIT_CHECK; 1158 /* Set sense bit 0 in ecw0. */ 1159 sch->sense_data[0] = 0x80; 1160 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 1161 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1162 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 1163 s->cpa = sch->channel_prog + 8; 1164 break; 1165 case -EINPROGRESS: 1166 /* channel program has been suspended */ 1167 s->ctrl &= ~SCSW_ACTL_START_PEND; 1168 s->ctrl |= SCSW_ACTL_SUSP; 1169 break; 1170 default: 1171 /* error, generate channel program check */ 1172 s->ctrl &= ~SCSW_ACTL_START_PEND; 1173 s->cstat = SCSW_CSTAT_PROG_CHECK; 1174 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 1175 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1176 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 1177 s->cpa = sch->channel_prog + 8; 1178 break; 1179 } 1180 } while (ret == -EAGAIN); 1181 1182 } 1183 1184 static IOInstEnding sch_handle_start_func_passthrough(SubchDev *sch) 1185 { 1186 1187 PMCW *p = &sch->curr_status.pmcw; 1188 SCSW *s = &sch->curr_status.scsw; 1189 1190 ORB *orb = &sch->orb; 1191 if (!(s->ctrl & SCSW_ACTL_SUSP)) { 1192 assert(orb != NULL); 1193 p->intparm = orb->intparm; 1194 } 1195 1196 /* 1197 * Only support prefetch enable mode. 1198 * Only support 64bit addressing idal. 1199 */ 1200 if (!(orb->ctrl0 & ORB_CTRL0_MASK_PFCH) || 1201 !(orb->ctrl0 & ORB_CTRL0_MASK_C64)) { 1202 warn_report("vfio-ccw requires PFCH and C64 flags set"); 1203 sch_gen_unit_exception(sch); 1204 css_inject_io_interrupt(sch); 1205 return IOINST_CC_EXPECTED; 1206 } 1207 return s390_ccw_cmd_request(sch); 1208 } 1209 1210 /* 1211 * On real machines, this would run asynchronously to the main vcpus. 1212 * We might want to make some parts of the ssch handling (interpreting 1213 * read/writes) asynchronous later on if we start supporting more than 1214 * our current very simple devices. 1215 */ 1216 IOInstEnding do_subchannel_work_virtual(SubchDev *sch) 1217 { 1218 1219 SCSW *s = &sch->curr_status.scsw; 1220 1221 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) { 1222 sch_handle_clear_func(sch); 1223 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) { 1224 sch_handle_halt_func(sch); 1225 } else if (s->ctrl & SCSW_FCTL_START_FUNC) { 1226 /* Triggered by both ssch and rsch. */ 1227 sch_handle_start_func_virtual(sch); 1228 } 1229 css_inject_io_interrupt(sch); 1230 /* inst must succeed if this func is called */ 1231 return IOINST_CC_EXPECTED; 1232 } 1233 1234 IOInstEnding do_subchannel_work_passthrough(SubchDev *sch) 1235 { 1236 SCSW *s = &sch->curr_status.scsw; 1237 1238 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) { 1239 /* TODO: Clear handling */ 1240 sch_handle_clear_func(sch); 1241 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) { 1242 /* TODO: Halt handling */ 1243 sch_handle_halt_func(sch); 1244 } else if (s->ctrl & SCSW_FCTL_START_FUNC) { 1245 return sch_handle_start_func_passthrough(sch); 1246 } 1247 return IOINST_CC_EXPECTED; 1248 } 1249 1250 static IOInstEnding do_subchannel_work(SubchDev *sch) 1251 { 1252 if (!sch->do_subchannel_work) { 1253 return IOINST_CC_STATUS_PRESENT; 1254 } 1255 g_assert(sch->curr_status.scsw.ctrl & SCSW_CTRL_MASK_FCTL); 1256 return sch->do_subchannel_work(sch); 1257 } 1258 1259 static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src) 1260 { 1261 int i; 1262 1263 dest->intparm = cpu_to_be32(src->intparm); 1264 dest->flags = cpu_to_be16(src->flags); 1265 dest->devno = cpu_to_be16(src->devno); 1266 dest->lpm = src->lpm; 1267 dest->pnom = src->pnom; 1268 dest->lpum = src->lpum; 1269 dest->pim = src->pim; 1270 dest->mbi = cpu_to_be16(src->mbi); 1271 dest->pom = src->pom; 1272 dest->pam = src->pam; 1273 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 1274 dest->chpid[i] = src->chpid[i]; 1275 } 1276 dest->chars = cpu_to_be32(src->chars); 1277 } 1278 1279 void copy_scsw_to_guest(SCSW *dest, const SCSW *src) 1280 { 1281 dest->flags = cpu_to_be16(src->flags); 1282 dest->ctrl = cpu_to_be16(src->ctrl); 1283 dest->cpa = cpu_to_be32(src->cpa); 1284 dest->dstat = src->dstat; 1285 dest->cstat = src->cstat; 1286 dest->count = cpu_to_be16(src->count); 1287 } 1288 1289 static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src) 1290 { 1291 int i; 1292 1293 copy_pmcw_to_guest(&dest->pmcw, &src->pmcw); 1294 copy_scsw_to_guest(&dest->scsw, &src->scsw); 1295 dest->mba = cpu_to_be64(src->mba); 1296 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 1297 dest->mda[i] = src->mda[i]; 1298 } 1299 } 1300 1301 int css_do_stsch(SubchDev *sch, SCHIB *schib) 1302 { 1303 /* Use current status. */ 1304 copy_schib_to_guest(schib, &sch->curr_status); 1305 return 0; 1306 } 1307 1308 static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src) 1309 { 1310 int i; 1311 1312 dest->intparm = be32_to_cpu(src->intparm); 1313 dest->flags = be16_to_cpu(src->flags); 1314 dest->devno = be16_to_cpu(src->devno); 1315 dest->lpm = src->lpm; 1316 dest->pnom = src->pnom; 1317 dest->lpum = src->lpum; 1318 dest->pim = src->pim; 1319 dest->mbi = be16_to_cpu(src->mbi); 1320 dest->pom = src->pom; 1321 dest->pam = src->pam; 1322 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 1323 dest->chpid[i] = src->chpid[i]; 1324 } 1325 dest->chars = be32_to_cpu(src->chars); 1326 } 1327 1328 static void copy_scsw_from_guest(SCSW *dest, const SCSW *src) 1329 { 1330 dest->flags = be16_to_cpu(src->flags); 1331 dest->ctrl = be16_to_cpu(src->ctrl); 1332 dest->cpa = be32_to_cpu(src->cpa); 1333 dest->dstat = src->dstat; 1334 dest->cstat = src->cstat; 1335 dest->count = be16_to_cpu(src->count); 1336 } 1337 1338 static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src) 1339 { 1340 int i; 1341 1342 copy_pmcw_from_guest(&dest->pmcw, &src->pmcw); 1343 copy_scsw_from_guest(&dest->scsw, &src->scsw); 1344 dest->mba = be64_to_cpu(src->mba); 1345 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 1346 dest->mda[i] = src->mda[i]; 1347 } 1348 } 1349 1350 IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *orig_schib) 1351 { 1352 SCSW *s = &sch->curr_status.scsw; 1353 PMCW *p = &sch->curr_status.pmcw; 1354 uint16_t oldflags; 1355 SCHIB schib; 1356 1357 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_DNV)) { 1358 return IOINST_CC_EXPECTED; 1359 } 1360 1361 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 1362 return IOINST_CC_STATUS_PRESENT; 1363 } 1364 1365 if (s->ctrl & 1366 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) { 1367 return IOINST_CC_BUSY; 1368 } 1369 1370 copy_schib_from_guest(&schib, orig_schib); 1371 /* Only update the program-modifiable fields. */ 1372 p->intparm = schib.pmcw.intparm; 1373 oldflags = p->flags; 1374 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1375 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1376 PMCW_FLAGS_MASK_MP); 1377 p->flags |= schib.pmcw.flags & 1378 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1379 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1380 PMCW_FLAGS_MASK_MP); 1381 p->lpm = schib.pmcw.lpm; 1382 p->mbi = schib.pmcw.mbi; 1383 p->pom = schib.pmcw.pom; 1384 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 1385 p->chars |= schib.pmcw.chars & 1386 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 1387 sch->curr_status.mba = schib.mba; 1388 1389 /* Has the channel been disabled? */ 1390 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0 1391 && (p->flags & PMCW_FLAGS_MASK_ENA) == 0) { 1392 sch->disable_cb(sch); 1393 } 1394 return IOINST_CC_EXPECTED; 1395 } 1396 1397 IOInstEnding css_do_xsch(SubchDev *sch) 1398 { 1399 SCSW *s = &sch->curr_status.scsw; 1400 PMCW *p = &sch->curr_status.pmcw; 1401 1402 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1403 return IOINST_CC_NOT_OPERATIONAL; 1404 } 1405 1406 if (s->ctrl & SCSW_CTRL_MASK_STCTL) { 1407 return IOINST_CC_STATUS_PRESENT; 1408 } 1409 1410 if (!(s->ctrl & SCSW_CTRL_MASK_FCTL) || 1411 ((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1412 (!(s->ctrl & 1413 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) || 1414 (s->ctrl & SCSW_ACTL_SUBCH_ACTIVE)) { 1415 return IOINST_CC_BUSY; 1416 } 1417 1418 /* Cancel the current operation. */ 1419 s->ctrl &= ~(SCSW_FCTL_START_FUNC | 1420 SCSW_ACTL_RESUME_PEND | 1421 SCSW_ACTL_START_PEND | 1422 SCSW_ACTL_SUSP); 1423 sch->channel_prog = 0x0; 1424 sch->last_cmd_valid = false; 1425 s->dstat = 0; 1426 s->cstat = 0; 1427 return IOINST_CC_EXPECTED; 1428 } 1429 1430 IOInstEnding css_do_csch(SubchDev *sch) 1431 { 1432 SCSW *s = &sch->curr_status.scsw; 1433 PMCW *p = &sch->curr_status.pmcw; 1434 1435 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1436 return IOINST_CC_NOT_OPERATIONAL; 1437 } 1438 1439 /* Trigger the clear function. */ 1440 s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL); 1441 s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND; 1442 1443 return do_subchannel_work(sch); 1444 } 1445 1446 IOInstEnding css_do_hsch(SubchDev *sch) 1447 { 1448 SCSW *s = &sch->curr_status.scsw; 1449 PMCW *p = &sch->curr_status.pmcw; 1450 1451 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1452 return IOINST_CC_NOT_OPERATIONAL; 1453 } 1454 1455 if (((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) || 1456 (s->ctrl & (SCSW_STCTL_PRIMARY | 1457 SCSW_STCTL_SECONDARY | 1458 SCSW_STCTL_ALERT))) { 1459 return IOINST_CC_STATUS_PRESENT; 1460 } 1461 1462 if (s->ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) { 1463 return IOINST_CC_BUSY; 1464 } 1465 1466 /* Trigger the halt function. */ 1467 s->ctrl |= SCSW_FCTL_HALT_FUNC; 1468 s->ctrl &= ~SCSW_FCTL_START_FUNC; 1469 if (((s->ctrl & SCSW_CTRL_MASK_ACTL) == 1470 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) && 1471 ((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_INTERMEDIATE)) { 1472 s->ctrl &= ~SCSW_STCTL_STATUS_PEND; 1473 } 1474 s->ctrl |= SCSW_ACTL_HALT_PEND; 1475 1476 return do_subchannel_work(sch); 1477 } 1478 1479 static void css_update_chnmon(SubchDev *sch) 1480 { 1481 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) { 1482 /* Not active. */ 1483 return; 1484 } 1485 /* The counter is conveniently located at the beginning of the struct. */ 1486 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) { 1487 /* Format 1, per-subchannel area. */ 1488 uint32_t count; 1489 1490 count = address_space_ldl(&address_space_memory, 1491 sch->curr_status.mba, 1492 MEMTXATTRS_UNSPECIFIED, 1493 NULL); 1494 count++; 1495 address_space_stl(&address_space_memory, sch->curr_status.mba, count, 1496 MEMTXATTRS_UNSPECIFIED, NULL); 1497 } else { 1498 /* Format 0, global area. */ 1499 uint32_t offset; 1500 uint16_t count; 1501 1502 offset = sch->curr_status.pmcw.mbi << 5; 1503 count = address_space_lduw(&address_space_memory, 1504 channel_subsys.chnmon_area + offset, 1505 MEMTXATTRS_UNSPECIFIED, 1506 NULL); 1507 count++; 1508 address_space_stw(&address_space_memory, 1509 channel_subsys.chnmon_area + offset, count, 1510 MEMTXATTRS_UNSPECIFIED, NULL); 1511 } 1512 } 1513 1514 IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb) 1515 { 1516 SCSW *s = &sch->curr_status.scsw; 1517 PMCW *p = &sch->curr_status.pmcw; 1518 1519 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1520 return IOINST_CC_NOT_OPERATIONAL; 1521 } 1522 1523 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 1524 return IOINST_CC_STATUS_PRESENT; 1525 } 1526 1527 if (s->ctrl & (SCSW_FCTL_START_FUNC | 1528 SCSW_FCTL_HALT_FUNC | 1529 SCSW_FCTL_CLEAR_FUNC)) { 1530 return IOINST_CC_BUSY; 1531 } 1532 1533 /* If monitoring is active, update counter. */ 1534 if (channel_subsys.chnmon_active) { 1535 css_update_chnmon(sch); 1536 } 1537 sch->orb = *orb; 1538 sch->channel_prog = orb->cpa; 1539 /* Trigger the start function. */ 1540 s->ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND); 1541 s->flags &= ~SCSW_FLAGS_MASK_PNO; 1542 1543 return do_subchannel_work(sch); 1544 } 1545 1546 static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw, 1547 int *irb_len) 1548 { 1549 int i; 1550 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1551 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 1552 1553 copy_scsw_to_guest(&dest->scsw, &src->scsw); 1554 1555 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) { 1556 dest->esw[i] = cpu_to_be32(src->esw[i]); 1557 } 1558 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) { 1559 dest->ecw[i] = cpu_to_be32(src->ecw[i]); 1560 } 1561 *irb_len = sizeof(*dest) - sizeof(dest->emw); 1562 1563 /* extended measurements enabled? */ 1564 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) || 1565 !(pmcw->flags & PMCW_FLAGS_MASK_TF) || 1566 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) { 1567 return; 1568 } 1569 /* extended measurements pending? */ 1570 if (!(stctl & SCSW_STCTL_STATUS_PEND)) { 1571 return; 1572 } 1573 if ((stctl & SCSW_STCTL_PRIMARY) || 1574 (stctl == SCSW_STCTL_SECONDARY) || 1575 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) { 1576 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) { 1577 dest->emw[i] = cpu_to_be32(src->emw[i]); 1578 } 1579 } 1580 *irb_len = sizeof(*dest); 1581 } 1582 1583 int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len) 1584 { 1585 SCSW *s = &sch->curr_status.scsw; 1586 PMCW *p = &sch->curr_status.pmcw; 1587 uint16_t stctl; 1588 IRB irb; 1589 1590 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1591 return 3; 1592 } 1593 1594 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL; 1595 1596 /* Prepare the irb for the guest. */ 1597 memset(&irb, 0, sizeof(IRB)); 1598 1599 /* Copy scsw from current status. */ 1600 memcpy(&irb.scsw, s, sizeof(SCSW)); 1601 if (stctl & SCSW_STCTL_STATUS_PEND) { 1602 if (s->cstat & (SCSW_CSTAT_DATA_CHECK | 1603 SCSW_CSTAT_CHN_CTRL_CHK | 1604 SCSW_CSTAT_INTF_CTRL_CHK)) { 1605 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF; 1606 irb.esw[0] = 0x04804000; 1607 } else { 1608 irb.esw[0] = 0x00800000; 1609 } 1610 /* If a unit check is pending, copy sense data. */ 1611 if ((s->dstat & SCSW_DSTAT_UNIT_CHECK) && 1612 (p->chars & PMCW_CHARS_MASK_CSENSE)) { 1613 int i; 1614 1615 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL; 1616 /* Attention: sense_data is already BE! */ 1617 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data)); 1618 for (i = 0; i < ARRAY_SIZE(irb.ecw); i++) { 1619 irb.ecw[i] = be32_to_cpu(irb.ecw[i]); 1620 } 1621 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8); 1622 } 1623 } 1624 /* Store the irb to the guest. */ 1625 copy_irb_to_guest(target_irb, &irb, p, irb_len); 1626 1627 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0); 1628 } 1629 1630 void css_do_tsch_update_subch(SubchDev *sch) 1631 { 1632 SCSW *s = &sch->curr_status.scsw; 1633 PMCW *p = &sch->curr_status.pmcw; 1634 uint16_t stctl; 1635 uint16_t fctl; 1636 uint16_t actl; 1637 1638 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL; 1639 fctl = s->ctrl & SCSW_CTRL_MASK_FCTL; 1640 actl = s->ctrl & SCSW_CTRL_MASK_ACTL; 1641 1642 /* Clear conditions on subchannel, if applicable. */ 1643 if (stctl & SCSW_STCTL_STATUS_PEND) { 1644 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 1645 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) || 1646 ((fctl & SCSW_FCTL_HALT_FUNC) && 1647 (actl & SCSW_ACTL_SUSP))) { 1648 s->ctrl &= ~SCSW_CTRL_MASK_FCTL; 1649 } 1650 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) { 1651 s->flags &= ~SCSW_FLAGS_MASK_PNO; 1652 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 1653 SCSW_ACTL_START_PEND | 1654 SCSW_ACTL_HALT_PEND | 1655 SCSW_ACTL_CLEAR_PEND | 1656 SCSW_ACTL_SUSP); 1657 } else { 1658 if ((actl & SCSW_ACTL_SUSP) && 1659 (fctl & SCSW_FCTL_START_FUNC)) { 1660 s->flags &= ~SCSW_FLAGS_MASK_PNO; 1661 if (fctl & SCSW_FCTL_HALT_FUNC) { 1662 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 1663 SCSW_ACTL_START_PEND | 1664 SCSW_ACTL_HALT_PEND | 1665 SCSW_ACTL_CLEAR_PEND | 1666 SCSW_ACTL_SUSP); 1667 } else { 1668 s->ctrl &= ~SCSW_ACTL_RESUME_PEND; 1669 } 1670 } 1671 } 1672 /* Clear pending sense data. */ 1673 if (p->chars & PMCW_CHARS_MASK_CSENSE) { 1674 memset(sch->sense_data, 0 , sizeof(sch->sense_data)); 1675 } 1676 } 1677 } 1678 1679 static void copy_crw_to_guest(CRW *dest, const CRW *src) 1680 { 1681 dest->flags = cpu_to_be16(src->flags); 1682 dest->rsid = cpu_to_be16(src->rsid); 1683 } 1684 1685 int css_do_stcrw(CRW *crw) 1686 { 1687 CrwContainer *crw_cont; 1688 int ret; 1689 1690 crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws); 1691 if (crw_cont) { 1692 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling); 1693 copy_crw_to_guest(crw, &crw_cont->crw); 1694 g_free(crw_cont); 1695 ret = 0; 1696 } else { 1697 /* List was empty, turn crw machine checks on again. */ 1698 memset(crw, 0, sizeof(*crw)); 1699 channel_subsys.do_crw_mchk = true; 1700 ret = 1; 1701 } 1702 1703 return ret; 1704 } 1705 1706 static void copy_crw_from_guest(CRW *dest, const CRW *src) 1707 { 1708 dest->flags = be16_to_cpu(src->flags); 1709 dest->rsid = be16_to_cpu(src->rsid); 1710 } 1711 1712 void css_undo_stcrw(CRW *crw) 1713 { 1714 CrwContainer *crw_cont; 1715 1716 crw_cont = g_try_new0(CrwContainer, 1); 1717 if (!crw_cont) { 1718 channel_subsys.crws_lost = true; 1719 return; 1720 } 1721 copy_crw_from_guest(&crw_cont->crw, crw); 1722 1723 QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling); 1724 } 1725 1726 int css_do_tpi(IOIntCode *int_code, int lowcore) 1727 { 1728 /* No pending interrupts for !KVM. */ 1729 return 0; 1730 } 1731 1732 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, 1733 int rfmt, void *buf) 1734 { 1735 int i, desc_size; 1736 uint32_t words[8]; 1737 uint32_t chpid_type_word; 1738 CssImage *css; 1739 1740 if (!m && !cssid) { 1741 css = channel_subsys.css[channel_subsys.default_cssid]; 1742 } else { 1743 css = channel_subsys.css[cssid]; 1744 } 1745 if (!css) { 1746 return 0; 1747 } 1748 desc_size = 0; 1749 for (i = f_chpid; i <= l_chpid; i++) { 1750 if (css->chpids[i].in_use) { 1751 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i; 1752 if (rfmt == 0) { 1753 words[0] = cpu_to_be32(chpid_type_word); 1754 words[1] = 0; 1755 memcpy(buf + desc_size, words, 8); 1756 desc_size += 8; 1757 } else if (rfmt == 1) { 1758 words[0] = cpu_to_be32(chpid_type_word); 1759 words[1] = 0; 1760 words[2] = 0; 1761 words[3] = 0; 1762 words[4] = 0; 1763 words[5] = 0; 1764 words[6] = 0; 1765 words[7] = 0; 1766 memcpy(buf + desc_size, words, 32); 1767 desc_size += 32; 1768 } 1769 } 1770 } 1771 return desc_size; 1772 } 1773 1774 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo) 1775 { 1776 /* dct is currently ignored (not really meaningful for our devices) */ 1777 /* TODO: Don't ignore mbk. */ 1778 if (update && !channel_subsys.chnmon_active) { 1779 /* Enable measuring. */ 1780 channel_subsys.chnmon_area = mbo; 1781 channel_subsys.chnmon_active = true; 1782 } 1783 if (!update && channel_subsys.chnmon_active) { 1784 /* Disable measuring. */ 1785 channel_subsys.chnmon_area = 0; 1786 channel_subsys.chnmon_active = false; 1787 } 1788 } 1789 1790 IOInstEnding css_do_rsch(SubchDev *sch) 1791 { 1792 SCSW *s = &sch->curr_status.scsw; 1793 PMCW *p = &sch->curr_status.pmcw; 1794 1795 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1796 return IOINST_CC_NOT_OPERATIONAL; 1797 } 1798 1799 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 1800 return IOINST_CC_STATUS_PRESENT; 1801 } 1802 1803 if (((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1804 (s->ctrl & SCSW_ACTL_RESUME_PEND) || 1805 (!(s->ctrl & SCSW_ACTL_SUSP))) { 1806 return IOINST_CC_BUSY; 1807 } 1808 1809 /* If monitoring is active, update counter. */ 1810 if (channel_subsys.chnmon_active) { 1811 css_update_chnmon(sch); 1812 } 1813 1814 s->ctrl |= SCSW_ACTL_RESUME_PEND; 1815 return do_subchannel_work(sch); 1816 } 1817 1818 int css_do_rchp(uint8_t cssid, uint8_t chpid) 1819 { 1820 uint8_t real_cssid; 1821 1822 if (cssid > channel_subsys.max_cssid) { 1823 return -EINVAL; 1824 } 1825 if (channel_subsys.max_cssid == 0) { 1826 real_cssid = channel_subsys.default_cssid; 1827 } else { 1828 real_cssid = cssid; 1829 } 1830 if (!channel_subsys.css[real_cssid]) { 1831 return -EINVAL; 1832 } 1833 1834 if (!channel_subsys.css[real_cssid]->chpids[chpid].in_use) { 1835 return -ENODEV; 1836 } 1837 1838 if (!channel_subsys.css[real_cssid]->chpids[chpid].is_virtual) { 1839 fprintf(stderr, 1840 "rchp unsupported for non-virtual chpid %x.%02x!\n", 1841 real_cssid, chpid); 1842 return -ENODEV; 1843 } 1844 1845 /* We don't really use a channel path, so we're done here. */ 1846 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 1847 channel_subsys.max_cssid > 0 ? 1 : 0, chpid); 1848 if (channel_subsys.max_cssid > 0) { 1849 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 0, real_cssid << 8); 1850 } 1851 return 0; 1852 } 1853 1854 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1855 { 1856 SubchSet *set; 1857 uint8_t real_cssid; 1858 1859 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid; 1860 if (ssid > MAX_SSID || 1861 !channel_subsys.css[real_cssid] || 1862 !channel_subsys.css[real_cssid]->sch_set[ssid]) { 1863 return true; 1864 } 1865 set = channel_subsys.css[real_cssid]->sch_set[ssid]; 1866 return schid > find_last_bit(set->schids_used, 1867 (MAX_SCHID + 1) / sizeof(unsigned long)); 1868 } 1869 1870 unsigned int css_find_free_chpid(uint8_t cssid) 1871 { 1872 CssImage *css = channel_subsys.css[cssid]; 1873 unsigned int chpid; 1874 1875 if (!css) { 1876 return MAX_CHPID + 1; 1877 } 1878 1879 for (chpid = 0; chpid <= MAX_CHPID; chpid++) { 1880 /* skip reserved chpid */ 1881 if (chpid == VIRTIO_CCW_CHPID) { 1882 continue; 1883 } 1884 if (!css->chpids[chpid].in_use) { 1885 return chpid; 1886 } 1887 } 1888 return MAX_CHPID + 1; 1889 } 1890 1891 static int css_add_chpid(uint8_t cssid, uint8_t chpid, uint8_t type, 1892 bool is_virt) 1893 { 1894 CssImage *css; 1895 1896 trace_css_chpid_add(cssid, chpid, type); 1897 css = channel_subsys.css[cssid]; 1898 if (!css) { 1899 return -EINVAL; 1900 } 1901 if (css->chpids[chpid].in_use) { 1902 return -EEXIST; 1903 } 1904 css->chpids[chpid].in_use = 1; 1905 css->chpids[chpid].type = type; 1906 css->chpids[chpid].is_virtual = is_virt; 1907 1908 css_generate_chp_crws(cssid, chpid); 1909 1910 return 0; 1911 } 1912 1913 void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type) 1914 { 1915 PMCW *p = &sch->curr_status.pmcw; 1916 SCSW *s = &sch->curr_status.scsw; 1917 int i; 1918 CssImage *css = channel_subsys.css[sch->cssid]; 1919 1920 assert(css != NULL); 1921 memset(p, 0, sizeof(PMCW)); 1922 p->flags |= PMCW_FLAGS_MASK_DNV; 1923 p->devno = sch->devno; 1924 /* single path */ 1925 p->pim = 0x80; 1926 p->pom = 0xff; 1927 p->pam = 0x80; 1928 p->chpid[0] = chpid; 1929 if (!css->chpids[chpid].in_use) { 1930 css_add_chpid(sch->cssid, chpid, type, true); 1931 } 1932 1933 memset(s, 0, sizeof(SCSW)); 1934 sch->curr_status.mba = 0; 1935 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) { 1936 sch->curr_status.mda[i] = 0; 1937 } 1938 } 1939 1940 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1941 { 1942 uint8_t real_cssid; 1943 1944 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid; 1945 1946 if (!channel_subsys.css[real_cssid]) { 1947 return NULL; 1948 } 1949 1950 if (!channel_subsys.css[real_cssid]->sch_set[ssid]) { 1951 return NULL; 1952 } 1953 1954 return channel_subsys.css[real_cssid]->sch_set[ssid]->sch[schid]; 1955 } 1956 1957 /** 1958 * Return free device number in subchannel set. 1959 * 1960 * Return index of the first free device number in the subchannel set 1961 * identified by @p cssid and @p ssid, beginning the search at @p 1962 * start and wrapping around at MAX_DEVNO. Return a value exceeding 1963 * MAX_SCHID if there are no free device numbers in the subchannel 1964 * set. 1965 */ 1966 static uint32_t css_find_free_devno(uint8_t cssid, uint8_t ssid, 1967 uint16_t start) 1968 { 1969 uint32_t round; 1970 1971 for (round = 0; round <= MAX_DEVNO; round++) { 1972 uint16_t devno = (start + round) % MAX_DEVNO; 1973 1974 if (!css_devno_used(cssid, ssid, devno)) { 1975 return devno; 1976 } 1977 } 1978 return MAX_DEVNO + 1; 1979 } 1980 1981 /** 1982 * Return first free subchannel (id) in subchannel set. 1983 * 1984 * Return index of the first free subchannel in the subchannel set 1985 * identified by @p cssid and @p ssid, if there is any. Return a value 1986 * exceeding MAX_SCHID if there are no free subchannels in the 1987 * subchannel set. 1988 */ 1989 static uint32_t css_find_free_subch(uint8_t cssid, uint8_t ssid) 1990 { 1991 uint32_t schid; 1992 1993 for (schid = 0; schid <= MAX_SCHID; schid++) { 1994 if (!css_find_subch(1, cssid, ssid, schid)) { 1995 return schid; 1996 } 1997 } 1998 return MAX_SCHID + 1; 1999 } 2000 2001 /** 2002 * Return first free subchannel (id) in subchannel set for a device number 2003 * 2004 * Verify the device number @p devno is not used yet in the subchannel 2005 * set identified by @p cssid and @p ssid. Set @p schid to the index 2006 * of the first free subchannel in the subchannel set, if there is 2007 * any. Return true if everything succeeded and false otherwise. 2008 */ 2009 static bool css_find_free_subch_for_devno(uint8_t cssid, uint8_t ssid, 2010 uint16_t devno, uint16_t *schid, 2011 Error **errp) 2012 { 2013 uint32_t free_schid; 2014 2015 assert(schid); 2016 if (css_devno_used(cssid, ssid, devno)) { 2017 error_setg(errp, "Device %x.%x.%04x already exists", 2018 cssid, ssid, devno); 2019 return false; 2020 } 2021 free_schid = css_find_free_subch(cssid, ssid); 2022 if (free_schid > MAX_SCHID) { 2023 error_setg(errp, "No free subchannel found for %x.%x.%04x", 2024 cssid, ssid, devno); 2025 return false; 2026 } 2027 *schid = free_schid; 2028 return true; 2029 } 2030 2031 /** 2032 * Return first free subchannel (id) and device number 2033 * 2034 * Locate the first free subchannel and first free device number in 2035 * any of the subchannel sets of the channel subsystem identified by 2036 * @p cssid. Return false if no free subchannel / device number could 2037 * be found. Otherwise set @p ssid, @p devno and @p schid to identify 2038 * the available subchannel and device number and return true. 2039 * 2040 * May modify @p ssid, @p devno and / or @p schid even if no free 2041 * subchannel / device number could be found. 2042 */ 2043 static bool css_find_free_subch_and_devno(uint8_t cssid, uint8_t *ssid, 2044 uint16_t *devno, uint16_t *schid, 2045 Error **errp) 2046 { 2047 uint32_t free_schid, free_devno; 2048 2049 assert(ssid && devno && schid); 2050 for (*ssid = 0; *ssid <= MAX_SSID; (*ssid)++) { 2051 free_schid = css_find_free_subch(cssid, *ssid); 2052 if (free_schid > MAX_SCHID) { 2053 continue; 2054 } 2055 free_devno = css_find_free_devno(cssid, *ssid, free_schid); 2056 if (free_devno > MAX_DEVNO) { 2057 continue; 2058 } 2059 *schid = free_schid; 2060 *devno = free_devno; 2061 return true; 2062 } 2063 error_setg(errp, "Virtual channel subsystem is full!"); 2064 return false; 2065 } 2066 2067 bool css_subch_visible(SubchDev *sch) 2068 { 2069 if (sch->ssid > channel_subsys.max_ssid) { 2070 return false; 2071 } 2072 2073 if (sch->cssid != channel_subsys.default_cssid) { 2074 return (channel_subsys.max_cssid > 0); 2075 } 2076 2077 return true; 2078 } 2079 2080 bool css_present(uint8_t cssid) 2081 { 2082 return (channel_subsys.css[cssid] != NULL); 2083 } 2084 2085 bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno) 2086 { 2087 if (!channel_subsys.css[cssid]) { 2088 return false; 2089 } 2090 if (!channel_subsys.css[cssid]->sch_set[ssid]) { 2091 return false; 2092 } 2093 2094 return !!test_bit(devno, 2095 channel_subsys.css[cssid]->sch_set[ssid]->devnos_used); 2096 } 2097 2098 void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid, 2099 uint16_t devno, SubchDev *sch) 2100 { 2101 CssImage *css; 2102 SubchSet *s_set; 2103 2104 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid, 2105 devno); 2106 if (!channel_subsys.css[cssid]) { 2107 fprintf(stderr, 2108 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n", 2109 __func__, cssid, ssid, schid); 2110 return; 2111 } 2112 css = channel_subsys.css[cssid]; 2113 2114 if (!css->sch_set[ssid]) { 2115 css->sch_set[ssid] = g_new0(SubchSet, 1); 2116 } 2117 s_set = css->sch_set[ssid]; 2118 2119 s_set->sch[schid] = sch; 2120 if (sch) { 2121 set_bit(schid, s_set->schids_used); 2122 set_bit(devno, s_set->devnos_used); 2123 } else { 2124 clear_bit(schid, s_set->schids_used); 2125 clear_bit(devno, s_set->devnos_used); 2126 } 2127 } 2128 2129 void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited, 2130 int chain, uint16_t rsid) 2131 { 2132 CrwContainer *crw_cont; 2133 2134 trace_css_crw(rsc, erc, rsid, chain ? "(chained)" : ""); 2135 /* TODO: Maybe use a static crw pool? */ 2136 crw_cont = g_try_new0(CrwContainer, 1); 2137 if (!crw_cont) { 2138 channel_subsys.crws_lost = true; 2139 return; 2140 } 2141 crw_cont->crw.flags = (rsc << 8) | erc; 2142 if (solicited) { 2143 crw_cont->crw.flags |= CRW_FLAGS_MASK_S; 2144 } 2145 if (chain) { 2146 crw_cont->crw.flags |= CRW_FLAGS_MASK_C; 2147 } 2148 crw_cont->crw.rsid = rsid; 2149 if (channel_subsys.crws_lost) { 2150 crw_cont->crw.flags |= CRW_FLAGS_MASK_R; 2151 channel_subsys.crws_lost = false; 2152 } 2153 2154 QTAILQ_INSERT_TAIL(&channel_subsys.pending_crws, crw_cont, sibling); 2155 2156 if (channel_subsys.do_crw_mchk) { 2157 channel_subsys.do_crw_mchk = false; 2158 /* Inject crw pending machine check. */ 2159 s390_crw_mchk(); 2160 } 2161 } 2162 2163 void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid, 2164 int hotplugged, int add) 2165 { 2166 uint8_t guest_cssid; 2167 bool chain_crw; 2168 2169 if (add && !hotplugged) { 2170 return; 2171 } 2172 if (channel_subsys.max_cssid == 0) { 2173 /* Default cssid shows up as 0. */ 2174 guest_cssid = (cssid == channel_subsys.default_cssid) ? 0 : cssid; 2175 } else { 2176 /* Show real cssid to the guest. */ 2177 guest_cssid = cssid; 2178 } 2179 /* 2180 * Only notify for higher subchannel sets/channel subsystems if the 2181 * guest has enabled it. 2182 */ 2183 if ((ssid > channel_subsys.max_ssid) || 2184 (guest_cssid > channel_subsys.max_cssid) || 2185 ((channel_subsys.max_cssid == 0) && 2186 (cssid != channel_subsys.default_cssid))) { 2187 return; 2188 } 2189 chain_crw = (channel_subsys.max_ssid > 0) || 2190 (channel_subsys.max_cssid > 0); 2191 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, chain_crw ? 1 : 0, schid); 2192 if (chain_crw) { 2193 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 0, 2194 (guest_cssid << 8) | (ssid << 4)); 2195 } 2196 /* RW_ERC_IPI --> clear pending interrupts */ 2197 css_clear_io_interrupt(css_do_build_subchannel_id(cssid, ssid), schid); 2198 } 2199 2200 void css_generate_chp_crws(uint8_t cssid, uint8_t chpid) 2201 { 2202 /* TODO */ 2203 } 2204 2205 void css_generate_css_crws(uint8_t cssid) 2206 { 2207 if (!channel_subsys.sei_pending) { 2208 css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, 0, cssid); 2209 } 2210 channel_subsys.sei_pending = true; 2211 } 2212 2213 void css_clear_sei_pending(void) 2214 { 2215 channel_subsys.sei_pending = false; 2216 } 2217 2218 int css_enable_mcsse(void) 2219 { 2220 trace_css_enable_facility("mcsse"); 2221 channel_subsys.max_cssid = MAX_CSSID; 2222 return 0; 2223 } 2224 2225 int css_enable_mss(void) 2226 { 2227 trace_css_enable_facility("mss"); 2228 channel_subsys.max_ssid = MAX_SSID; 2229 return 0; 2230 } 2231 2232 void css_reset_sch(SubchDev *sch) 2233 { 2234 PMCW *p = &sch->curr_status.pmcw; 2235 2236 if ((p->flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) { 2237 sch->disable_cb(sch); 2238 } 2239 2240 p->intparm = 0; 2241 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 2242 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 2243 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF); 2244 p->flags |= PMCW_FLAGS_MASK_DNV; 2245 p->devno = sch->devno; 2246 p->pim = 0x80; 2247 p->lpm = p->pim; 2248 p->pnom = 0; 2249 p->lpum = 0; 2250 p->mbi = 0; 2251 p->pom = 0xff; 2252 p->pam = 0x80; 2253 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME | 2254 PMCW_CHARS_MASK_CSENSE); 2255 2256 memset(&sch->curr_status.scsw, 0, sizeof(sch->curr_status.scsw)); 2257 sch->curr_status.mba = 0; 2258 2259 sch->channel_prog = 0x0; 2260 sch->last_cmd_valid = false; 2261 sch->thinint_active = false; 2262 } 2263 2264 void css_reset(void) 2265 { 2266 CrwContainer *crw_cont; 2267 2268 /* Clean up monitoring. */ 2269 channel_subsys.chnmon_active = false; 2270 channel_subsys.chnmon_area = 0; 2271 2272 /* Clear pending CRWs. */ 2273 while ((crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws))) { 2274 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling); 2275 g_free(crw_cont); 2276 } 2277 channel_subsys.sei_pending = false; 2278 channel_subsys.do_crw_mchk = true; 2279 channel_subsys.crws_lost = false; 2280 2281 /* Reset maximum ids. */ 2282 channel_subsys.max_cssid = 0; 2283 channel_subsys.max_ssid = 0; 2284 } 2285 2286 static void get_css_devid(Object *obj, Visitor *v, const char *name, 2287 void *opaque, Error **errp) 2288 { 2289 DeviceState *dev = DEVICE(obj); 2290 Property *prop = opaque; 2291 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop); 2292 char buffer[] = "xx.x.xxxx"; 2293 char *p = buffer; 2294 int r; 2295 2296 if (dev_id->valid) { 2297 2298 r = snprintf(buffer, sizeof(buffer), "%02x.%1x.%04x", dev_id->cssid, 2299 dev_id->ssid, dev_id->devid); 2300 assert(r == sizeof(buffer) - 1); 2301 2302 /* drop leading zero */ 2303 if (dev_id->cssid <= 0xf) { 2304 p++; 2305 } 2306 } else { 2307 snprintf(buffer, sizeof(buffer), "<unset>"); 2308 } 2309 2310 visit_type_str(v, name, &p, errp); 2311 } 2312 2313 /* 2314 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid 2315 */ 2316 static void set_css_devid(Object *obj, Visitor *v, const char *name, 2317 void *opaque, Error **errp) 2318 { 2319 DeviceState *dev = DEVICE(obj); 2320 Property *prop = opaque; 2321 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop); 2322 Error *local_err = NULL; 2323 char *str; 2324 int num, n1, n2; 2325 unsigned int cssid, ssid, devid; 2326 2327 if (dev->realized) { 2328 qdev_prop_set_after_realize(dev, name, errp); 2329 return; 2330 } 2331 2332 visit_type_str(v, name, &str, &local_err); 2333 if (local_err) { 2334 error_propagate(errp, local_err); 2335 return; 2336 } 2337 2338 num = sscanf(str, "%2x.%1x%n.%4x%n", &cssid, &ssid, &n1, &devid, &n2); 2339 if (num != 3 || (n2 - n1) != 5 || strlen(str) != n2) { 2340 error_set_from_qdev_prop_error(errp, EINVAL, dev, prop, str); 2341 goto out; 2342 } 2343 if ((cssid > MAX_CSSID) || (ssid > MAX_SSID)) { 2344 error_setg(errp, "Invalid cssid or ssid: cssid %x, ssid %x", 2345 cssid, ssid); 2346 goto out; 2347 } 2348 2349 dev_id->cssid = cssid; 2350 dev_id->ssid = ssid; 2351 dev_id->devid = devid; 2352 dev_id->valid = true; 2353 2354 out: 2355 g_free(str); 2356 } 2357 2358 const PropertyInfo css_devid_propinfo = { 2359 .name = "str", 2360 .description = "Identifier of an I/O device in the channel " 2361 "subsystem, example: fe.1.23ab", 2362 .get = get_css_devid, 2363 .set = set_css_devid, 2364 }; 2365 2366 const PropertyInfo css_devid_ro_propinfo = { 2367 .name = "str", 2368 .description = "Read-only identifier of an I/O device in the channel " 2369 "subsystem, example: fe.1.23ab", 2370 .get = get_css_devid, 2371 }; 2372 2373 SubchDev *css_create_sch(CssDevId bus_id, bool is_virtual, bool squash_mcss, 2374 Error **errp) 2375 { 2376 uint16_t schid = 0; 2377 SubchDev *sch; 2378 2379 if (bus_id.valid) { 2380 if (is_virtual != (bus_id.cssid == VIRTUAL_CSSID)) { 2381 error_setg(errp, "cssid %hhx not valid for %s devices", 2382 bus_id.cssid, 2383 (is_virtual ? "virtual" : "non-virtual")); 2384 return NULL; 2385 } 2386 } 2387 2388 if (bus_id.valid) { 2389 if (squash_mcss) { 2390 bus_id.cssid = channel_subsys.default_cssid; 2391 } else if (!channel_subsys.css[bus_id.cssid]) { 2392 css_create_css_image(bus_id.cssid, false); 2393 } 2394 2395 if (!css_find_free_subch_for_devno(bus_id.cssid, bus_id.ssid, 2396 bus_id.devid, &schid, errp)) { 2397 return NULL; 2398 } 2399 } else if (squash_mcss || is_virtual) { 2400 bus_id.cssid = channel_subsys.default_cssid; 2401 2402 if (!css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid, 2403 &bus_id.devid, &schid, errp)) { 2404 return NULL; 2405 } 2406 } else { 2407 for (bus_id.cssid = 0; bus_id.cssid < MAX_CSSID; ++bus_id.cssid) { 2408 if (bus_id.cssid == VIRTUAL_CSSID) { 2409 continue; 2410 } 2411 2412 if (!channel_subsys.css[bus_id.cssid]) { 2413 css_create_css_image(bus_id.cssid, false); 2414 } 2415 2416 if (css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid, 2417 &bus_id.devid, &schid, 2418 NULL)) { 2419 break; 2420 } 2421 if (bus_id.cssid == MAX_CSSID) { 2422 error_setg(errp, "Virtual channel subsystem is full!"); 2423 return NULL; 2424 } 2425 } 2426 } 2427 2428 sch = g_new0(SubchDev, 1); 2429 sch->cssid = bus_id.cssid; 2430 sch->ssid = bus_id.ssid; 2431 sch->devno = bus_id.devid; 2432 sch->schid = schid; 2433 css_subch_assign(sch->cssid, sch->ssid, schid, sch->devno, sch); 2434 return sch; 2435 } 2436 2437 static int css_sch_get_chpids(SubchDev *sch, CssDevId *dev_id) 2438 { 2439 char *fid_path; 2440 FILE *fd; 2441 uint32_t chpid[8]; 2442 int i; 2443 PMCW *p = &sch->curr_status.pmcw; 2444 2445 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids", 2446 dev_id->cssid, dev_id->ssid, dev_id->devid); 2447 fd = fopen(fid_path, "r"); 2448 if (fd == NULL) { 2449 error_report("%s: open %s failed", __func__, fid_path); 2450 g_free(fid_path); 2451 return -EINVAL; 2452 } 2453 2454 if (fscanf(fd, "%x %x %x %x %x %x %x %x", 2455 &chpid[0], &chpid[1], &chpid[2], &chpid[3], 2456 &chpid[4], &chpid[5], &chpid[6], &chpid[7]) != 8) { 2457 fclose(fd); 2458 g_free(fid_path); 2459 return -EINVAL; 2460 } 2461 2462 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) { 2463 p->chpid[i] = chpid[i]; 2464 } 2465 2466 fclose(fd); 2467 g_free(fid_path); 2468 2469 return 0; 2470 } 2471 2472 static int css_sch_get_path_masks(SubchDev *sch, CssDevId *dev_id) 2473 { 2474 char *fid_path; 2475 FILE *fd; 2476 uint32_t pim, pam, pom; 2477 PMCW *p = &sch->curr_status.pmcw; 2478 2479 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom", 2480 dev_id->cssid, dev_id->ssid, dev_id->devid); 2481 fd = fopen(fid_path, "r"); 2482 if (fd == NULL) { 2483 error_report("%s: open %s failed", __func__, fid_path); 2484 g_free(fid_path); 2485 return -EINVAL; 2486 } 2487 2488 if (fscanf(fd, "%x %x %x", &pim, &pam, &pom) != 3) { 2489 fclose(fd); 2490 g_free(fid_path); 2491 return -EINVAL; 2492 } 2493 2494 p->pim = pim; 2495 p->pam = pam; 2496 p->pom = pom; 2497 fclose(fd); 2498 g_free(fid_path); 2499 2500 return 0; 2501 } 2502 2503 static int css_sch_get_chpid_type(uint8_t chpid, uint32_t *type, 2504 CssDevId *dev_id) 2505 { 2506 char *fid_path; 2507 FILE *fd; 2508 2509 fid_path = g_strdup_printf("/sys/devices/css%x/chp0.%02x/type", 2510 dev_id->cssid, chpid); 2511 fd = fopen(fid_path, "r"); 2512 if (fd == NULL) { 2513 error_report("%s: open %s failed", __func__, fid_path); 2514 g_free(fid_path); 2515 return -EINVAL; 2516 } 2517 2518 if (fscanf(fd, "%x", type) != 1) { 2519 fclose(fd); 2520 g_free(fid_path); 2521 return -EINVAL; 2522 } 2523 2524 fclose(fd); 2525 g_free(fid_path); 2526 2527 return 0; 2528 } 2529 2530 /* 2531 * We currently retrieve the real device information from sysfs to build the 2532 * guest subchannel information block without considering the migration feature. 2533 * We need to revisit this problem when we want to add migration support. 2534 */ 2535 int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id) 2536 { 2537 CssImage *css = channel_subsys.css[sch->cssid]; 2538 PMCW *p = &sch->curr_status.pmcw; 2539 SCSW *s = &sch->curr_status.scsw; 2540 uint32_t type; 2541 int i, ret; 2542 2543 assert(css != NULL); 2544 memset(p, 0, sizeof(PMCW)); 2545 p->flags |= PMCW_FLAGS_MASK_DNV; 2546 /* We are dealing with I/O subchannels only. */ 2547 p->devno = sch->devno; 2548 2549 /* Grab path mask from sysfs. */ 2550 ret = css_sch_get_path_masks(sch, dev_id); 2551 if (ret) { 2552 return ret; 2553 } 2554 2555 /* Grab chpids from sysfs. */ 2556 ret = css_sch_get_chpids(sch, dev_id); 2557 if (ret) { 2558 return ret; 2559 } 2560 2561 /* Build chpid type. */ 2562 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) { 2563 if (p->chpid[i] && !css->chpids[p->chpid[i]].in_use) { 2564 ret = css_sch_get_chpid_type(p->chpid[i], &type, dev_id); 2565 if (ret) { 2566 return ret; 2567 } 2568 css_add_chpid(sch->cssid, p->chpid[i], type, false); 2569 } 2570 } 2571 2572 memset(s, 0, sizeof(SCSW)); 2573 sch->curr_status.mba = 0; 2574 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) { 2575 sch->curr_status.mda[i] = 0; 2576 } 2577 2578 return 0; 2579 } 2580