1 /* 2 * Channel subsystem base support. 3 * 4 * Copyright 2012 IBM Corp. 5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or (at 8 * your option) any later version. See the COPYING file in the top-level 9 * directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qapi/visitor.h" 15 #include "hw/qdev.h" 16 #include "qemu/bitops.h" 17 #include "qemu/error-report.h" 18 #include "exec/address-spaces.h" 19 #include "cpu.h" 20 #include "hw/s390x/ioinst.h" 21 #include "hw/s390x/css.h" 22 #include "trace.h" 23 #include "hw/s390x/s390_flic.h" 24 #include "hw/s390x/s390-virtio-ccw.h" 25 26 typedef struct CrwContainer { 27 CRW crw; 28 QTAILQ_ENTRY(CrwContainer) sibling; 29 } CrwContainer; 30 31 static const VMStateDescription vmstate_crw = { 32 .name = "s390_crw", 33 .version_id = 1, 34 .minimum_version_id = 1, 35 .fields = (VMStateField[]) { 36 VMSTATE_UINT16(flags, CRW), 37 VMSTATE_UINT16(rsid, CRW), 38 VMSTATE_END_OF_LIST() 39 }, 40 }; 41 42 static const VMStateDescription vmstate_crw_container = { 43 .name = "s390_crw_container", 44 .version_id = 1, 45 .minimum_version_id = 1, 46 .fields = (VMStateField[]) { 47 VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW), 48 VMSTATE_END_OF_LIST() 49 }, 50 }; 51 52 typedef struct ChpInfo { 53 uint8_t in_use; 54 uint8_t type; 55 uint8_t is_virtual; 56 } ChpInfo; 57 58 static const VMStateDescription vmstate_chp_info = { 59 .name = "s390_chp_info", 60 .version_id = 1, 61 .minimum_version_id = 1, 62 .fields = (VMStateField[]) { 63 VMSTATE_UINT8(in_use, ChpInfo), 64 VMSTATE_UINT8(type, ChpInfo), 65 VMSTATE_UINT8(is_virtual, ChpInfo), 66 VMSTATE_END_OF_LIST() 67 } 68 }; 69 70 typedef struct SubchSet { 71 SubchDev *sch[MAX_SCHID + 1]; 72 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 73 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 74 } SubchSet; 75 76 static const VMStateDescription vmstate_scsw = { 77 .name = "s390_scsw", 78 .version_id = 1, 79 .minimum_version_id = 1, 80 .fields = (VMStateField[]) { 81 VMSTATE_UINT16(flags, SCSW), 82 VMSTATE_UINT16(ctrl, SCSW), 83 VMSTATE_UINT32(cpa, SCSW), 84 VMSTATE_UINT8(dstat, SCSW), 85 VMSTATE_UINT8(cstat, SCSW), 86 VMSTATE_UINT16(count, SCSW), 87 VMSTATE_END_OF_LIST() 88 } 89 }; 90 91 static const VMStateDescription vmstate_pmcw = { 92 .name = "s390_pmcw", 93 .version_id = 1, 94 .minimum_version_id = 1, 95 .fields = (VMStateField[]) { 96 VMSTATE_UINT32(intparm, PMCW), 97 VMSTATE_UINT16(flags, PMCW), 98 VMSTATE_UINT16(devno, PMCW), 99 VMSTATE_UINT8(lpm, PMCW), 100 VMSTATE_UINT8(pnom, PMCW), 101 VMSTATE_UINT8(lpum, PMCW), 102 VMSTATE_UINT8(pim, PMCW), 103 VMSTATE_UINT16(mbi, PMCW), 104 VMSTATE_UINT8(pom, PMCW), 105 VMSTATE_UINT8(pam, PMCW), 106 VMSTATE_UINT8_ARRAY(chpid, PMCW, 8), 107 VMSTATE_UINT32(chars, PMCW), 108 VMSTATE_END_OF_LIST() 109 } 110 }; 111 112 static const VMStateDescription vmstate_schib = { 113 .name = "s390_schib", 114 .version_id = 1, 115 .minimum_version_id = 1, 116 .fields = (VMStateField[]) { 117 VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW), 118 VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW), 119 VMSTATE_UINT64(mba, SCHIB), 120 VMSTATE_UINT8_ARRAY(mda, SCHIB, 4), 121 VMSTATE_END_OF_LIST() 122 } 123 }; 124 125 126 static const VMStateDescription vmstate_ccw1 = { 127 .name = "s390_ccw1", 128 .version_id = 1, 129 .minimum_version_id = 1, 130 .fields = (VMStateField[]) { 131 VMSTATE_UINT8(cmd_code, CCW1), 132 VMSTATE_UINT8(flags, CCW1), 133 VMSTATE_UINT16(count, CCW1), 134 VMSTATE_UINT32(cda, CCW1), 135 VMSTATE_END_OF_LIST() 136 } 137 }; 138 139 static const VMStateDescription vmstate_ciw = { 140 .name = "s390_ciw", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .fields = (VMStateField[]) { 144 VMSTATE_UINT8(type, CIW), 145 VMSTATE_UINT8(command, CIW), 146 VMSTATE_UINT16(count, CIW), 147 VMSTATE_END_OF_LIST() 148 } 149 }; 150 151 static const VMStateDescription vmstate_sense_id = { 152 .name = "s390_sense_id", 153 .version_id = 1, 154 .minimum_version_id = 1, 155 .fields = (VMStateField[]) { 156 VMSTATE_UINT8(reserved, SenseId), 157 VMSTATE_UINT16(cu_type, SenseId), 158 VMSTATE_UINT8(cu_model, SenseId), 159 VMSTATE_UINT16(dev_type, SenseId), 160 VMSTATE_UINT8(dev_model, SenseId), 161 VMSTATE_UINT8(unused, SenseId), 162 VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW), 163 VMSTATE_END_OF_LIST() 164 } 165 }; 166 167 static const VMStateDescription vmstate_orb = { 168 .name = "s390_orb", 169 .version_id = 1, 170 .minimum_version_id = 1, 171 .fields = (VMStateField[]) { 172 VMSTATE_UINT32(intparm, ORB), 173 VMSTATE_UINT16(ctrl0, ORB), 174 VMSTATE_UINT8(lpm, ORB), 175 VMSTATE_UINT8(ctrl1, ORB), 176 VMSTATE_UINT32(cpa, ORB), 177 VMSTATE_END_OF_LIST() 178 } 179 }; 180 181 static bool vmstate_schdev_orb_needed(void *opaque) 182 { 183 return css_migration_enabled(); 184 } 185 186 static const VMStateDescription vmstate_schdev_orb = { 187 .name = "s390_subch_dev/orb", 188 .version_id = 1, 189 .minimum_version_id = 1, 190 .needed = vmstate_schdev_orb_needed, 191 .fields = (VMStateField[]) { 192 VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB), 193 VMSTATE_END_OF_LIST() 194 } 195 }; 196 197 static int subch_dev_post_load(void *opaque, int version_id); 198 static int subch_dev_pre_save(void *opaque); 199 200 const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!" 201 " Likely reason: some sequences of plug and unplug can break" 202 " migration for machine versions prior to 2.7 (known design flaw)."; 203 204 const VMStateDescription vmstate_subch_dev = { 205 .name = "s390_subch_dev", 206 .version_id = 1, 207 .minimum_version_id = 1, 208 .post_load = subch_dev_post_load, 209 .pre_save = subch_dev_pre_save, 210 .fields = (VMStateField[]) { 211 VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"), 212 VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"), 213 VMSTATE_UINT16(migrated_schid, SubchDev), 214 VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno), 215 VMSTATE_BOOL(thinint_active, SubchDev), 216 VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB), 217 VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32), 218 VMSTATE_UINT64(channel_prog, SubchDev), 219 VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1), 220 VMSTATE_BOOL(last_cmd_valid, SubchDev), 221 VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId), 222 VMSTATE_BOOL(ccw_fmt_1, SubchDev), 223 VMSTATE_UINT8(ccw_no_data_cnt, SubchDev), 224 VMSTATE_END_OF_LIST() 225 }, 226 .subsections = (const VMStateDescription * []) { 227 &vmstate_schdev_orb, 228 NULL 229 } 230 }; 231 232 typedef struct IndAddrPtrTmp { 233 IndAddr **parent; 234 uint64_t addr; 235 int32_t len; 236 } IndAddrPtrTmp; 237 238 static int post_load_ind_addr(void *opaque, int version_id) 239 { 240 IndAddrPtrTmp *ptmp = opaque; 241 IndAddr **ind_addr = ptmp->parent; 242 243 if (ptmp->len != 0) { 244 *ind_addr = get_indicator(ptmp->addr, ptmp->len); 245 } else { 246 *ind_addr = NULL; 247 } 248 return 0; 249 } 250 251 static int pre_save_ind_addr(void *opaque) 252 { 253 IndAddrPtrTmp *ptmp = opaque; 254 IndAddr *ind_addr = *(ptmp->parent); 255 256 if (ind_addr != NULL) { 257 ptmp->len = ind_addr->len; 258 ptmp->addr = ind_addr->addr; 259 } else { 260 ptmp->len = 0; 261 ptmp->addr = 0L; 262 } 263 264 return 0; 265 } 266 267 const VMStateDescription vmstate_ind_addr_tmp = { 268 .name = "s390_ind_addr_tmp", 269 .pre_save = pre_save_ind_addr, 270 .post_load = post_load_ind_addr, 271 272 .fields = (VMStateField[]) { 273 VMSTATE_INT32(len, IndAddrPtrTmp), 274 VMSTATE_UINT64(addr, IndAddrPtrTmp), 275 VMSTATE_END_OF_LIST() 276 } 277 }; 278 279 const VMStateDescription vmstate_ind_addr = { 280 .name = "s390_ind_addr_tmp", 281 .fields = (VMStateField[]) { 282 VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp), 283 VMSTATE_END_OF_LIST() 284 } 285 }; 286 287 typedef struct CssImage { 288 SubchSet *sch_set[MAX_SSID + 1]; 289 ChpInfo chpids[MAX_CHPID + 1]; 290 } CssImage; 291 292 static const VMStateDescription vmstate_css_img = { 293 .name = "s390_css_img", 294 .version_id = 1, 295 .minimum_version_id = 1, 296 .fields = (VMStateField[]) { 297 /* Subchannel sets have no relevant state. */ 298 VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0, 299 vmstate_chp_info, ChpInfo), 300 VMSTATE_END_OF_LIST() 301 } 302 303 }; 304 305 typedef struct IoAdapter { 306 uint32_t id; 307 uint8_t type; 308 uint8_t isc; 309 uint8_t flags; 310 } IoAdapter; 311 312 typedef struct ChannelSubSys { 313 QTAILQ_HEAD(, CrwContainer) pending_crws; 314 bool sei_pending; 315 bool do_crw_mchk; 316 bool crws_lost; 317 uint8_t max_cssid; 318 uint8_t max_ssid; 319 bool chnmon_active; 320 uint64_t chnmon_area; 321 CssImage *css[MAX_CSSID + 1]; 322 uint8_t default_cssid; 323 /* don't migrate, see css_register_io_adapters */ 324 IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1]; 325 /* don't migrate, see get_indicator and IndAddrPtrTmp */ 326 QTAILQ_HEAD(, IndAddr) indicator_addresses; 327 } ChannelSubSys; 328 329 static const VMStateDescription vmstate_css = { 330 .name = "s390_css", 331 .version_id = 1, 332 .minimum_version_id = 1, 333 .fields = (VMStateField[]) { 334 VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container, 335 CrwContainer, sibling), 336 VMSTATE_BOOL(sei_pending, ChannelSubSys), 337 VMSTATE_BOOL(do_crw_mchk, ChannelSubSys), 338 VMSTATE_BOOL(crws_lost, ChannelSubSys), 339 /* These were kind of migrated by virtio */ 340 VMSTATE_UINT8(max_cssid, ChannelSubSys), 341 VMSTATE_UINT8(max_ssid, ChannelSubSys), 342 VMSTATE_BOOL(chnmon_active, ChannelSubSys), 343 VMSTATE_UINT64(chnmon_area, ChannelSubSys), 344 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1, 345 0, vmstate_css_img, CssImage), 346 VMSTATE_UINT8(default_cssid, ChannelSubSys), 347 VMSTATE_END_OF_LIST() 348 } 349 }; 350 351 static ChannelSubSys channel_subsys = { 352 .pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws), 353 .do_crw_mchk = true, 354 .sei_pending = false, 355 .do_crw_mchk = true, 356 .crws_lost = false, 357 .chnmon_active = false, 358 .indicator_addresses = 359 QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses), 360 }; 361 362 static int subch_dev_pre_save(void *opaque) 363 { 364 SubchDev *s = opaque; 365 366 /* Prepare remote_schid for save */ 367 s->migrated_schid = s->schid; 368 369 return 0; 370 } 371 372 static int subch_dev_post_load(void *opaque, int version_id) 373 { 374 375 SubchDev *s = opaque; 376 377 /* Re-assign the subchannel to remote_schid if necessary */ 378 if (s->migrated_schid != s->schid) { 379 if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) { 380 /* 381 * Cleanup the slot before moving to s->migrated_schid provided 382 * it still belongs to us, i.e. it was not changed by previous 383 * invocation of this function. 384 */ 385 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL); 386 } 387 /* It's OK to re-assign without a prior de-assign. */ 388 s->schid = s->migrated_schid; 389 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s); 390 } 391 392 if (css_migration_enabled()) { 393 /* No compat voodoo to do ;) */ 394 return 0; 395 } 396 /* 397 * Hack alert. If we don't migrate the channel subsystem status 398 * we still need to find out if the guest enabled mss/mcss-e. 399 * If the subchannel is enabled, it certainly was able to access it, 400 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid 401 * values. This is not watertight, but better than nothing. 402 */ 403 if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) { 404 if (s->ssid) { 405 channel_subsys.max_ssid = MAX_SSID; 406 } 407 if (s->cssid != channel_subsys.default_cssid) { 408 channel_subsys.max_cssid = MAX_CSSID; 409 } 410 } 411 return 0; 412 } 413 414 void css_register_vmstate(void) 415 { 416 vmstate_register(NULL, 0, &vmstate_css, &channel_subsys); 417 } 418 419 IndAddr *get_indicator(hwaddr ind_addr, int len) 420 { 421 IndAddr *indicator; 422 423 QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) { 424 if (indicator->addr == ind_addr) { 425 indicator->refcnt++; 426 return indicator; 427 } 428 } 429 indicator = g_new0(IndAddr, 1); 430 indicator->addr = ind_addr; 431 indicator->len = len; 432 indicator->refcnt = 1; 433 QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses, 434 indicator, sibling); 435 return indicator; 436 } 437 438 static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr, 439 bool do_map) 440 { 441 S390FLICState *fs = s390_get_flic(); 442 S390FLICStateClass *fsc = s390_get_flic_class(fs); 443 444 return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map); 445 } 446 447 void release_indicator(AdapterInfo *adapter, IndAddr *indicator) 448 { 449 assert(indicator->refcnt > 0); 450 indicator->refcnt--; 451 if (indicator->refcnt > 0) { 452 return; 453 } 454 QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling); 455 if (indicator->map) { 456 s390_io_adapter_map(adapter, indicator->map, false); 457 } 458 g_free(indicator); 459 } 460 461 int map_indicator(AdapterInfo *adapter, IndAddr *indicator) 462 { 463 int ret; 464 465 if (indicator->map) { 466 return 0; /* already mapped is not an error */ 467 } 468 indicator->map = indicator->addr; 469 ret = s390_io_adapter_map(adapter, indicator->map, true); 470 if ((ret != 0) && (ret != -ENOSYS)) { 471 goto out_err; 472 } 473 return 0; 474 475 out_err: 476 indicator->map = 0; 477 return ret; 478 } 479 480 int css_create_css_image(uint8_t cssid, bool default_image) 481 { 482 trace_css_new_image(cssid, default_image ? "(default)" : ""); 483 /* 255 is reserved */ 484 if (cssid == 255) { 485 return -EINVAL; 486 } 487 if (channel_subsys.css[cssid]) { 488 return -EBUSY; 489 } 490 channel_subsys.css[cssid] = g_new0(CssImage, 1); 491 if (default_image) { 492 channel_subsys.default_cssid = cssid; 493 } 494 return 0; 495 } 496 497 uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc) 498 { 499 if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC || 500 !channel_subsys.io_adapters[type][isc]) { 501 return -1; 502 } 503 504 return channel_subsys.io_adapters[type][isc]->id; 505 } 506 507 /** 508 * css_register_io_adapters: Register I/O adapters per ISC during init 509 * 510 * @swap: an indication if byte swap is needed. 511 * @maskable: an indication if the adapter is subject to the mask operation. 512 * @flags: further characteristics of the adapter. 513 * e.g. suppressible, an indication if the adapter is subject to AIS. 514 * @errp: location to store error information. 515 */ 516 void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable, 517 uint8_t flags, Error **errp) 518 { 519 uint32_t id; 520 int ret, isc; 521 IoAdapter *adapter; 522 S390FLICState *fs = s390_get_flic(); 523 S390FLICStateClass *fsc = s390_get_flic_class(fs); 524 525 /* 526 * Disallow multiple registrations for the same device type. 527 * Report an error if registering for an already registered type. 528 */ 529 if (channel_subsys.io_adapters[type][0]) { 530 error_setg(errp, "Adapters for type %d already registered", type); 531 } 532 533 for (isc = 0; isc <= MAX_ISC; isc++) { 534 id = (type << 3) | isc; 535 ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags); 536 if (ret == 0) { 537 adapter = g_new0(IoAdapter, 1); 538 adapter->id = id; 539 adapter->isc = isc; 540 adapter->type = type; 541 adapter->flags = flags; 542 channel_subsys.io_adapters[type][isc] = adapter; 543 } else { 544 error_setg_errno(errp, -ret, "Unexpected error %d when " 545 "registering adapter %d", ret, id); 546 break; 547 } 548 } 549 550 /* 551 * No need to free registered adapters in kvm: kvm will clean up 552 * when the machine goes away. 553 */ 554 if (ret) { 555 for (isc--; isc >= 0; isc--) { 556 g_free(channel_subsys.io_adapters[type][isc]); 557 channel_subsys.io_adapters[type][isc] = NULL; 558 } 559 } 560 561 } 562 563 static void css_clear_io_interrupt(uint16_t subchannel_id, 564 uint16_t subchannel_nr) 565 { 566 Error *err = NULL; 567 static bool no_clear_irq; 568 S390FLICState *fs = s390_get_flic(); 569 S390FLICStateClass *fsc = s390_get_flic_class(fs); 570 int r; 571 572 if (unlikely(no_clear_irq)) { 573 return; 574 } 575 r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr); 576 switch (r) { 577 case 0: 578 break; 579 case -ENOSYS: 580 no_clear_irq = true; 581 /* 582 * Ignore unavailability, as the user can't do anything 583 * about it anyway. 584 */ 585 break; 586 default: 587 error_setg_errno(&err, -r, "unexpected error condition"); 588 error_propagate(&error_abort, err); 589 } 590 } 591 592 static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid) 593 { 594 if (channel_subsys.max_cssid > 0) { 595 return (cssid << 8) | (1 << 3) | (ssid << 1) | 1; 596 } 597 return (ssid << 1) | 1; 598 } 599 600 uint16_t css_build_subchannel_id(SubchDev *sch) 601 { 602 return css_do_build_subchannel_id(sch->cssid, sch->ssid); 603 } 604 605 void css_inject_io_interrupt(SubchDev *sch) 606 { 607 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 608 609 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 610 sch->curr_status.pmcw.intparm, isc, ""); 611 s390_io_interrupt(css_build_subchannel_id(sch), 612 sch->schid, 613 sch->curr_status.pmcw.intparm, 614 isc << 27); 615 } 616 617 void css_conditional_io_interrupt(SubchDev *sch) 618 { 619 /* 620 * If the subchannel is not enabled, it is not made status pending 621 * (see PoP p. 16-17, "Status Control"). 622 */ 623 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA)) { 624 return; 625 } 626 627 /* 628 * If the subchannel is not currently status pending, make it pending 629 * with alert status. 630 */ 631 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) { 632 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 633 634 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 635 sch->curr_status.pmcw.intparm, isc, 636 "(unsolicited)"); 637 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 638 sch->curr_status.scsw.ctrl |= 639 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 640 /* Inject an I/O interrupt. */ 641 s390_io_interrupt(css_build_subchannel_id(sch), 642 sch->schid, 643 sch->curr_status.pmcw.intparm, 644 isc << 27); 645 } 646 } 647 648 int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode) 649 { 650 S390FLICState *fs = s390_get_flic(); 651 S390FLICStateClass *fsc = s390_get_flic_class(fs); 652 int r; 653 654 if (env->psw.mask & PSW_MASK_PSTATE) { 655 r = -PGM_PRIVILEGED; 656 goto out; 657 } 658 659 trace_css_do_sic(mode, isc); 660 switch (mode) { 661 case SIC_IRQ_MODE_ALL: 662 case SIC_IRQ_MODE_SINGLE: 663 break; 664 default: 665 r = -PGM_OPERAND; 666 goto out; 667 } 668 669 r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0; 670 out: 671 return r; 672 } 673 674 void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc) 675 { 676 S390FLICState *fs = s390_get_flic(); 677 S390FLICStateClass *fsc = s390_get_flic_class(fs); 678 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI; 679 IoAdapter *adapter = channel_subsys.io_adapters[type][isc]; 680 681 if (!adapter) { 682 return; 683 } 684 685 trace_css_adapter_interrupt(isc); 686 if (fs->ais_supported) { 687 if (fsc->inject_airq(fs, type, isc, adapter->flags)) { 688 error_report("Failed to inject airq with AIS supported"); 689 exit(1); 690 } 691 } else { 692 s390_io_interrupt(0, 0, 0, io_int_word); 693 } 694 } 695 696 static void sch_handle_clear_func(SubchDev *sch) 697 { 698 SCHIB *schib = &sch->curr_status; 699 int path; 700 701 /* Path management: In our simple css, we always choose the only path. */ 702 path = 0x80; 703 704 /* Reset values prior to 'issuing the clear signal'. */ 705 schib->pmcw.lpum = 0; 706 schib->pmcw.pom = 0xff; 707 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 708 709 /* We always 'attempt to issue the clear signal', and we always succeed. */ 710 sch->channel_prog = 0x0; 711 sch->last_cmd_valid = false; 712 schib->scsw.ctrl &= ~SCSW_ACTL_CLEAR_PEND; 713 schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND; 714 715 schib->scsw.dstat = 0; 716 schib->scsw.cstat = 0; 717 schib->pmcw.lpum = path; 718 719 } 720 721 static void sch_handle_halt_func(SubchDev *sch) 722 { 723 SCHIB *schib = &sch->curr_status; 724 hwaddr curr_ccw = sch->channel_prog; 725 int path; 726 727 /* Path management: In our simple css, we always choose the only path. */ 728 path = 0x80; 729 730 /* We always 'attempt to issue the halt signal', and we always succeed. */ 731 sch->channel_prog = 0x0; 732 sch->last_cmd_valid = false; 733 schib->scsw.ctrl &= ~SCSW_ACTL_HALT_PEND; 734 schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND; 735 736 if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE | 737 SCSW_ACTL_DEVICE_ACTIVE)) || 738 !((schib->scsw.ctrl & SCSW_ACTL_START_PEND) || 739 (schib->scsw.ctrl & SCSW_ACTL_SUSP))) { 740 schib->scsw.dstat = SCSW_DSTAT_DEVICE_END; 741 } 742 if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE | 743 SCSW_ACTL_DEVICE_ACTIVE)) || 744 (schib->scsw.ctrl & SCSW_ACTL_SUSP)) { 745 schib->scsw.cpa = curr_ccw + 8; 746 } 747 schib->scsw.cstat = 0; 748 schib->pmcw.lpum = path; 749 750 } 751 752 /* 753 * As the SenseId struct cannot be packed (would cause unaligned accesses), we 754 * have to copy the individual fields to an unstructured area using the correct 755 * layout (see SA22-7204-01 "Common I/O-Device Commands"). 756 */ 757 static void copy_sense_id_to_guest(uint8_t *dest, SenseId *src) 758 { 759 int i; 760 761 dest[0] = src->reserved; 762 stw_be_p(dest + 1, src->cu_type); 763 dest[3] = src->cu_model; 764 stw_be_p(dest + 4, src->dev_type); 765 dest[6] = src->dev_model; 766 dest[7] = src->unused; 767 for (i = 0; i < ARRAY_SIZE(src->ciw); i++) { 768 dest[8 + i * 4] = src->ciw[i].type; 769 dest[9 + i * 4] = src->ciw[i].command; 770 stw_be_p(dest + 10 + i * 4, src->ciw[i].count); 771 } 772 } 773 774 static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1) 775 { 776 CCW0 tmp0; 777 CCW1 tmp1; 778 CCW1 ret; 779 780 if (fmt1) { 781 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1)); 782 ret.cmd_code = tmp1.cmd_code; 783 ret.flags = tmp1.flags; 784 ret.count = be16_to_cpu(tmp1.count); 785 ret.cda = be32_to_cpu(tmp1.cda); 786 } else { 787 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0)); 788 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) { 789 ret.cmd_code = CCW_CMD_TIC; 790 ret.flags = 0; 791 ret.count = 0; 792 } else { 793 ret.cmd_code = tmp0.cmd_code; 794 ret.flags = tmp0.flags; 795 ret.count = be16_to_cpu(tmp0.count); 796 } 797 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16); 798 } 799 return ret; 800 } 801 /** 802 * If out of bounds marks the stream broken. If broken returns -EINVAL, 803 * otherwise the requested length (may be zero) 804 */ 805 static inline int cds_check_len(CcwDataStream *cds, int len) 806 { 807 if (cds->at_byte + len > cds->count) { 808 cds->flags |= CDS_F_STREAM_BROKEN; 809 } 810 return cds->flags & CDS_F_STREAM_BROKEN ? -EINVAL : len; 811 } 812 813 static inline bool cds_ccw_addrs_ok(hwaddr addr, int len, bool ccw_fmt1) 814 { 815 return (addr + len) < (ccw_fmt1 ? (1UL << 31) : (1UL << 24)); 816 } 817 818 static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len, 819 CcwDataStreamOp op) 820 { 821 int ret; 822 823 ret = cds_check_len(cds, len); 824 if (ret <= 0) { 825 return ret; 826 } 827 if (!cds_ccw_addrs_ok(cds->cda, len, cds->flags & CDS_F_FMT)) { 828 return -EINVAL; /* channel program check */ 829 } 830 if (op == CDS_OP_A) { 831 goto incr; 832 } 833 if (!cds->do_skip) { 834 ret = address_space_rw(&address_space_memory, cds->cda, 835 MEMTXATTRS_UNSPECIFIED, buff, len, op); 836 } else { 837 ret = MEMTX_OK; 838 } 839 if (ret != MEMTX_OK) { 840 cds->flags |= CDS_F_STREAM_BROKEN; 841 return -EINVAL; 842 } 843 incr: 844 cds->at_byte += len; 845 cds->cda += len; 846 return 0; 847 } 848 849 /* returns values between 1 and bsz, where bsz is a power of 2 */ 850 static inline uint16_t ida_continuous_left(hwaddr cda, uint64_t bsz) 851 { 852 return bsz - (cda & (bsz - 1)); 853 } 854 855 static inline uint64_t ccw_ida_block_size(uint8_t flags) 856 { 857 if ((flags & CDS_F_C64) && !(flags & CDS_F_I2K)) { 858 return 1ULL << 12; 859 } 860 return 1ULL << 11; 861 } 862 863 static inline int ida_read_next_idaw(CcwDataStream *cds) 864 { 865 union {uint64_t fmt2; uint32_t fmt1; } idaw; 866 int ret; 867 hwaddr idaw_addr; 868 bool idaw_fmt2 = cds->flags & CDS_F_C64; 869 bool ccw_fmt1 = cds->flags & CDS_F_FMT; 870 871 if (idaw_fmt2) { 872 idaw_addr = cds->cda_orig + sizeof(idaw.fmt2) * cds->at_idaw; 873 if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { 874 return -EINVAL; /* channel program check */ 875 } 876 ret = address_space_rw(&address_space_memory, idaw_addr, 877 MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt2, 878 sizeof(idaw.fmt2), false); 879 cds->cda = be64_to_cpu(idaw.fmt2); 880 } else { 881 idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw; 882 if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { 883 return -EINVAL; /* channel program check */ 884 } 885 ret = address_space_rw(&address_space_memory, idaw_addr, 886 MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt1, 887 sizeof(idaw.fmt1), false); 888 cds->cda = be64_to_cpu(idaw.fmt1); 889 if (cds->cda & 0x80000000) { 890 return -EINVAL; /* channel program check */ 891 } 892 } 893 ++(cds->at_idaw); 894 if (ret != MEMTX_OK) { 895 /* assume inaccessible address */ 896 return -EINVAL; /* channel program check */ 897 } 898 return 0; 899 } 900 901 static int ccw_dstream_rw_ida(CcwDataStream *cds, void *buff, int len, 902 CcwDataStreamOp op) 903 { 904 uint64_t bsz = ccw_ida_block_size(cds->flags); 905 int ret = 0; 906 uint16_t cont_left, iter_len; 907 908 ret = cds_check_len(cds, len); 909 if (ret <= 0) { 910 return ret; 911 } 912 if (!cds->at_idaw) { 913 /* read first idaw */ 914 ret = ida_read_next_idaw(cds); 915 if (ret) { 916 goto err; 917 } 918 cont_left = ida_continuous_left(cds->cda, bsz); 919 } else { 920 cont_left = ida_continuous_left(cds->cda, bsz); 921 if (cont_left == bsz) { 922 ret = ida_read_next_idaw(cds); 923 if (ret) { 924 goto err; 925 } 926 if (cds->cda & (bsz - 1)) { 927 ret = -EINVAL; /* channel program check */ 928 goto err; 929 } 930 } 931 } 932 do { 933 iter_len = MIN(len, cont_left); 934 if (op != CDS_OP_A) { 935 if (!cds->do_skip) { 936 ret = address_space_rw(&address_space_memory, cds->cda, 937 MEMTXATTRS_UNSPECIFIED, buff, iter_len, 938 op); 939 } else { 940 ret = MEMTX_OK; 941 } 942 if (ret != MEMTX_OK) { 943 /* assume inaccessible address */ 944 ret = -EINVAL; /* channel program check */ 945 goto err; 946 } 947 } 948 cds->at_byte += iter_len; 949 cds->cda += iter_len; 950 len -= iter_len; 951 if (!len) { 952 break; 953 } 954 ret = ida_read_next_idaw(cds); 955 if (ret) { 956 goto err; 957 } 958 cont_left = bsz; 959 } while (true); 960 return ret; 961 err: 962 cds->flags |= CDS_F_STREAM_BROKEN; 963 return ret; 964 } 965 966 void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb) 967 { 968 /* 969 * We don't support MIDA (an optional facility) yet and we 970 * catch this earlier. Just for expressing the precondition. 971 */ 972 g_assert(!(orb->ctrl1 & ORB_CTRL1_MASK_MIDAW)); 973 cds->flags = (orb->ctrl0 & ORB_CTRL0_MASK_I2K ? CDS_F_I2K : 0) | 974 (orb->ctrl0 & ORB_CTRL0_MASK_C64 ? CDS_F_C64 : 0) | 975 (orb->ctrl0 & ORB_CTRL0_MASK_FMT ? CDS_F_FMT : 0) | 976 (ccw->flags & CCW_FLAG_IDA ? CDS_F_IDA : 0); 977 978 cds->count = ccw->count; 979 cds->cda_orig = ccw->cda; 980 /* skip is only effective for read, read backwards, or sense commands */ 981 cds->do_skip = (ccw->flags & CCW_FLAG_SKIP) && 982 ((ccw->cmd_code & 0x0f) == CCW_CMD_BASIC_SENSE || 983 (ccw->cmd_code & 0x03) == 0x02 /* read */ || 984 (ccw->cmd_code & 0x0f) == 0x0c /* read backwards */); 985 ccw_dstream_rewind(cds); 986 if (!(cds->flags & CDS_F_IDA)) { 987 cds->op_handler = ccw_dstream_rw_noflags; 988 } else { 989 cds->op_handler = ccw_dstream_rw_ida; 990 } 991 } 992 993 static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr, 994 bool suspend_allowed) 995 { 996 int ret; 997 bool check_len; 998 int len; 999 CCW1 ccw; 1000 1001 if (!ccw_addr) { 1002 return -EINVAL; /* channel-program check */ 1003 } 1004 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */ 1005 if (ccw_addr & (sch->ccw_fmt_1 ? 0x80000007 : 0xff000007)) { 1006 return -EINVAL; 1007 } 1008 1009 /* Translate everything to format-1 ccws - the information is the same. */ 1010 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1); 1011 1012 /* Check for invalid command codes. */ 1013 if ((ccw.cmd_code & 0x0f) == 0) { 1014 return -EINVAL; 1015 } 1016 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) && 1017 ((ccw.cmd_code & 0xf0) != 0)) { 1018 return -EINVAL; 1019 } 1020 if (!sch->ccw_fmt_1 && (ccw.count == 0) && 1021 (ccw.cmd_code != CCW_CMD_TIC)) { 1022 return -EINVAL; 1023 } 1024 1025 /* We don't support MIDA. */ 1026 if (ccw.flags & CCW_FLAG_MIDA) { 1027 return -EINVAL; 1028 } 1029 1030 if (ccw.flags & CCW_FLAG_SUSPEND) { 1031 return suspend_allowed ? -EINPROGRESS : -EINVAL; 1032 } 1033 1034 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC)); 1035 1036 if (!ccw.cda) { 1037 if (sch->ccw_no_data_cnt == 255) { 1038 return -EINVAL; 1039 } 1040 sch->ccw_no_data_cnt++; 1041 } 1042 1043 /* Look at the command. */ 1044 ccw_dstream_init(&sch->cds, &ccw, &(sch->orb)); 1045 switch (ccw.cmd_code) { 1046 case CCW_CMD_NOOP: 1047 /* Nothing to do. */ 1048 ret = 0; 1049 break; 1050 case CCW_CMD_BASIC_SENSE: 1051 if (check_len) { 1052 if (ccw.count != sizeof(sch->sense_data)) { 1053 ret = -EINVAL; 1054 break; 1055 } 1056 } 1057 len = MIN(ccw.count, sizeof(sch->sense_data)); 1058 ccw_dstream_write_buf(&sch->cds, sch->sense_data, len); 1059 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds); 1060 memset(sch->sense_data, 0, sizeof(sch->sense_data)); 1061 ret = 0; 1062 break; 1063 case CCW_CMD_SENSE_ID: 1064 { 1065 /* According to SA22-7204-01, Sense-ID can store up to 256 bytes */ 1066 uint8_t sense_id[256]; 1067 1068 copy_sense_id_to_guest(sense_id, &sch->id); 1069 /* Sense ID information is device specific. */ 1070 if (check_len) { 1071 if (ccw.count != sizeof(sense_id)) { 1072 ret = -EINVAL; 1073 break; 1074 } 1075 } 1076 len = MIN(ccw.count, sizeof(sense_id)); 1077 /* 1078 * Only indicate 0xff in the first sense byte if we actually 1079 * have enough place to store at least bytes 0-3. 1080 */ 1081 if (len >= 4) { 1082 sense_id[0] = 0xff; 1083 } else { 1084 sense_id[0] = 0; 1085 } 1086 ccw_dstream_write_buf(&sch->cds, sense_id, len); 1087 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds); 1088 ret = 0; 1089 break; 1090 } 1091 case CCW_CMD_TIC: 1092 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) { 1093 ret = -EINVAL; 1094 break; 1095 } 1096 if (ccw.flags || ccw.count) { 1097 /* We have already sanitized these if converted from fmt 0. */ 1098 ret = -EINVAL; 1099 break; 1100 } 1101 sch->channel_prog = ccw.cda; 1102 ret = -EAGAIN; 1103 break; 1104 default: 1105 if (sch->ccw_cb) { 1106 /* Handle device specific commands. */ 1107 ret = sch->ccw_cb(sch, ccw); 1108 } else { 1109 ret = -ENOSYS; 1110 } 1111 break; 1112 } 1113 sch->last_cmd = ccw; 1114 sch->last_cmd_valid = true; 1115 if (ret == 0) { 1116 if (ccw.flags & CCW_FLAG_CC) { 1117 sch->channel_prog += 8; 1118 ret = -EAGAIN; 1119 } 1120 } 1121 1122 return ret; 1123 } 1124 1125 static void sch_handle_start_func_virtual(SubchDev *sch) 1126 { 1127 SCHIB *schib = &sch->curr_status; 1128 int path; 1129 int ret; 1130 bool suspend_allowed; 1131 1132 /* Path management: In our simple css, we always choose the only path. */ 1133 path = 0x80; 1134 1135 if (!(schib->scsw.ctrl & SCSW_ACTL_SUSP)) { 1136 /* Start Function triggered via ssch, i.e. we have an ORB */ 1137 ORB *orb = &sch->orb; 1138 schib->scsw.cstat = 0; 1139 schib->scsw.dstat = 0; 1140 /* Look at the orb and try to execute the channel program. */ 1141 schib->pmcw.intparm = orb->intparm; 1142 if (!(orb->lpm & path)) { 1143 /* Generate a deferred cc 3 condition. */ 1144 schib->scsw.flags |= SCSW_FLAGS_MASK_CC; 1145 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1146 schib->scsw.ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND); 1147 return; 1148 } 1149 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT); 1150 schib->scsw.flags |= (sch->ccw_fmt_1) ? SCSW_FLAGS_MASK_FMT : 0; 1151 sch->ccw_no_data_cnt = 0; 1152 suspend_allowed = !!(orb->ctrl0 & ORB_CTRL0_MASK_SPND); 1153 } else { 1154 /* Start Function resumed via rsch */ 1155 schib->scsw.ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND); 1156 /* The channel program had been suspended before. */ 1157 suspend_allowed = true; 1158 } 1159 sch->last_cmd_valid = false; 1160 do { 1161 ret = css_interpret_ccw(sch, sch->channel_prog, suspend_allowed); 1162 switch (ret) { 1163 case -EAGAIN: 1164 /* ccw chain, continue processing */ 1165 break; 1166 case 0: 1167 /* success */ 1168 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1169 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1170 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1171 SCSW_STCTL_STATUS_PEND; 1172 schib->scsw.dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END; 1173 schib->scsw.cpa = sch->channel_prog + 8; 1174 break; 1175 case -EIO: 1176 /* I/O errors, status depends on specific devices */ 1177 break; 1178 case -ENOSYS: 1179 /* unsupported command, generate unit check (command reject) */ 1180 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1181 schib->scsw.dstat = SCSW_DSTAT_UNIT_CHECK; 1182 /* Set sense bit 0 in ecw0. */ 1183 sch->sense_data[0] = 0x80; 1184 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1185 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1186 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 1187 schib->scsw.cpa = sch->channel_prog + 8; 1188 break; 1189 case -EINPROGRESS: 1190 /* channel program has been suspended */ 1191 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1192 schib->scsw.ctrl |= SCSW_ACTL_SUSP; 1193 break; 1194 default: 1195 /* error, generate channel program check */ 1196 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1197 schib->scsw.cstat = SCSW_CSTAT_PROG_CHECK; 1198 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1199 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1200 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 1201 schib->scsw.cpa = sch->channel_prog + 8; 1202 break; 1203 } 1204 } while (ret == -EAGAIN); 1205 1206 } 1207 1208 static IOInstEnding sch_handle_start_func_passthrough(SubchDev *sch) 1209 { 1210 SCHIB *schib = &sch->curr_status; 1211 ORB *orb = &sch->orb; 1212 if (!(schib->scsw.ctrl & SCSW_ACTL_SUSP)) { 1213 assert(orb != NULL); 1214 schib->pmcw.intparm = orb->intparm; 1215 } 1216 return s390_ccw_cmd_request(sch); 1217 } 1218 1219 /* 1220 * On real machines, this would run asynchronously to the main vcpus. 1221 * We might want to make some parts of the ssch handling (interpreting 1222 * read/writes) asynchronous later on if we start supporting more than 1223 * our current very simple devices. 1224 */ 1225 IOInstEnding do_subchannel_work_virtual(SubchDev *sch) 1226 { 1227 SCHIB *schib = &sch->curr_status; 1228 1229 if (schib->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) { 1230 sch_handle_clear_func(sch); 1231 } else if (schib->scsw.ctrl & SCSW_FCTL_HALT_FUNC) { 1232 sch_handle_halt_func(sch); 1233 } else if (schib->scsw.ctrl & SCSW_FCTL_START_FUNC) { 1234 /* Triggered by both ssch and rsch. */ 1235 sch_handle_start_func_virtual(sch); 1236 } 1237 css_inject_io_interrupt(sch); 1238 /* inst must succeed if this func is called */ 1239 return IOINST_CC_EXPECTED; 1240 } 1241 1242 IOInstEnding do_subchannel_work_passthrough(SubchDev *sch) 1243 { 1244 SCHIB *schib = &sch->curr_status; 1245 1246 if (schib->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) { 1247 /* TODO: Clear handling */ 1248 sch_handle_clear_func(sch); 1249 } else if (schib->scsw.ctrl & SCSW_FCTL_HALT_FUNC) { 1250 /* TODO: Halt handling */ 1251 sch_handle_halt_func(sch); 1252 } else if (schib->scsw.ctrl & SCSW_FCTL_START_FUNC) { 1253 return sch_handle_start_func_passthrough(sch); 1254 } 1255 return IOINST_CC_EXPECTED; 1256 } 1257 1258 static IOInstEnding do_subchannel_work(SubchDev *sch) 1259 { 1260 if (!sch->do_subchannel_work) { 1261 return IOINST_CC_STATUS_PRESENT; 1262 } 1263 g_assert(sch->curr_status.scsw.ctrl & SCSW_CTRL_MASK_FCTL); 1264 return sch->do_subchannel_work(sch); 1265 } 1266 1267 static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src) 1268 { 1269 int i; 1270 1271 dest->intparm = cpu_to_be32(src->intparm); 1272 dest->flags = cpu_to_be16(src->flags); 1273 dest->devno = cpu_to_be16(src->devno); 1274 dest->lpm = src->lpm; 1275 dest->pnom = src->pnom; 1276 dest->lpum = src->lpum; 1277 dest->pim = src->pim; 1278 dest->mbi = cpu_to_be16(src->mbi); 1279 dest->pom = src->pom; 1280 dest->pam = src->pam; 1281 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 1282 dest->chpid[i] = src->chpid[i]; 1283 } 1284 dest->chars = cpu_to_be32(src->chars); 1285 } 1286 1287 void copy_scsw_to_guest(SCSW *dest, const SCSW *src) 1288 { 1289 dest->flags = cpu_to_be16(src->flags); 1290 dest->ctrl = cpu_to_be16(src->ctrl); 1291 dest->cpa = cpu_to_be32(src->cpa); 1292 dest->dstat = src->dstat; 1293 dest->cstat = src->cstat; 1294 dest->count = cpu_to_be16(src->count); 1295 } 1296 1297 static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src) 1298 { 1299 int i; 1300 /* 1301 * We copy the PMCW and SCSW in and out of local variables to 1302 * avoid taking the address of members of a packed struct. 1303 */ 1304 PMCW src_pmcw, dest_pmcw; 1305 SCSW src_scsw, dest_scsw; 1306 1307 src_pmcw = src->pmcw; 1308 copy_pmcw_to_guest(&dest_pmcw, &src_pmcw); 1309 dest->pmcw = dest_pmcw; 1310 src_scsw = src->scsw; 1311 copy_scsw_to_guest(&dest_scsw, &src_scsw); 1312 dest->scsw = dest_scsw; 1313 dest->mba = cpu_to_be64(src->mba); 1314 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 1315 dest->mda[i] = src->mda[i]; 1316 } 1317 } 1318 1319 int css_do_stsch(SubchDev *sch, SCHIB *schib) 1320 { 1321 /* Use current status. */ 1322 copy_schib_to_guest(schib, &sch->curr_status); 1323 return 0; 1324 } 1325 1326 static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src) 1327 { 1328 int i; 1329 1330 dest->intparm = be32_to_cpu(src->intparm); 1331 dest->flags = be16_to_cpu(src->flags); 1332 dest->devno = be16_to_cpu(src->devno); 1333 dest->lpm = src->lpm; 1334 dest->pnom = src->pnom; 1335 dest->lpum = src->lpum; 1336 dest->pim = src->pim; 1337 dest->mbi = be16_to_cpu(src->mbi); 1338 dest->pom = src->pom; 1339 dest->pam = src->pam; 1340 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 1341 dest->chpid[i] = src->chpid[i]; 1342 } 1343 dest->chars = be32_to_cpu(src->chars); 1344 } 1345 1346 static void copy_scsw_from_guest(SCSW *dest, const SCSW *src) 1347 { 1348 dest->flags = be16_to_cpu(src->flags); 1349 dest->ctrl = be16_to_cpu(src->ctrl); 1350 dest->cpa = be32_to_cpu(src->cpa); 1351 dest->dstat = src->dstat; 1352 dest->cstat = src->cstat; 1353 dest->count = be16_to_cpu(src->count); 1354 } 1355 1356 static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src) 1357 { 1358 int i; 1359 /* 1360 * We copy the PMCW and SCSW in and out of local variables to 1361 * avoid taking the address of members of a packed struct. 1362 */ 1363 PMCW src_pmcw, dest_pmcw; 1364 SCSW src_scsw, dest_scsw; 1365 1366 src_pmcw = src->pmcw; 1367 copy_pmcw_from_guest(&dest_pmcw, &src_pmcw); 1368 dest->pmcw = dest_pmcw; 1369 src_scsw = src->scsw; 1370 copy_scsw_from_guest(&dest_scsw, &src_scsw); 1371 dest->scsw = dest_scsw; 1372 dest->mba = be64_to_cpu(src->mba); 1373 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 1374 dest->mda[i] = src->mda[i]; 1375 } 1376 } 1377 1378 IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *orig_schib) 1379 { 1380 SCHIB *schib = &sch->curr_status; 1381 uint16_t oldflags; 1382 SCHIB schib_copy; 1383 1384 if (!(schib->pmcw.flags & PMCW_FLAGS_MASK_DNV)) { 1385 return IOINST_CC_EXPECTED; 1386 } 1387 1388 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) { 1389 return IOINST_CC_STATUS_PRESENT; 1390 } 1391 1392 if (schib->scsw.ctrl & 1393 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) { 1394 return IOINST_CC_BUSY; 1395 } 1396 1397 copy_schib_from_guest(&schib_copy, orig_schib); 1398 /* Only update the program-modifiable fields. */ 1399 schib->pmcw.intparm = schib_copy.pmcw.intparm; 1400 oldflags = schib->pmcw.flags; 1401 schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1402 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1403 PMCW_FLAGS_MASK_MP); 1404 schib->pmcw.flags |= schib_copy.pmcw.flags & 1405 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1406 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1407 PMCW_FLAGS_MASK_MP); 1408 schib->pmcw.lpm = schib_copy.pmcw.lpm; 1409 schib->pmcw.mbi = schib_copy.pmcw.mbi; 1410 schib->pmcw.pom = schib_copy.pmcw.pom; 1411 schib->pmcw.chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 1412 schib->pmcw.chars |= schib_copy.pmcw.chars & 1413 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 1414 schib->mba = schib_copy.mba; 1415 1416 /* Has the channel been disabled? */ 1417 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0 1418 && (schib->pmcw.flags & PMCW_FLAGS_MASK_ENA) == 0) { 1419 sch->disable_cb(sch); 1420 } 1421 return IOINST_CC_EXPECTED; 1422 } 1423 1424 IOInstEnding css_do_xsch(SubchDev *sch) 1425 { 1426 SCHIB *schib = &sch->curr_status; 1427 1428 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1429 return IOINST_CC_NOT_OPERATIONAL; 1430 } 1431 1432 if (schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) { 1433 return IOINST_CC_STATUS_PRESENT; 1434 } 1435 1436 if (!(schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) || 1437 ((schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1438 (!(schib->scsw.ctrl & 1439 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) || 1440 (schib->scsw.ctrl & SCSW_ACTL_SUBCH_ACTIVE)) { 1441 return IOINST_CC_BUSY; 1442 } 1443 1444 /* Cancel the current operation. */ 1445 schib->scsw.ctrl &= ~(SCSW_FCTL_START_FUNC | 1446 SCSW_ACTL_RESUME_PEND | 1447 SCSW_ACTL_START_PEND | 1448 SCSW_ACTL_SUSP); 1449 sch->channel_prog = 0x0; 1450 sch->last_cmd_valid = false; 1451 schib->scsw.dstat = 0; 1452 schib->scsw.cstat = 0; 1453 return IOINST_CC_EXPECTED; 1454 } 1455 1456 IOInstEnding css_do_csch(SubchDev *sch) 1457 { 1458 SCHIB *schib = &sch->curr_status; 1459 1460 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1461 return IOINST_CC_NOT_OPERATIONAL; 1462 } 1463 1464 /* Trigger the clear function. */ 1465 schib->scsw.ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL); 1466 schib->scsw.ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND; 1467 1468 return do_subchannel_work(sch); 1469 } 1470 1471 IOInstEnding css_do_hsch(SubchDev *sch) 1472 { 1473 SCHIB *schib = &sch->curr_status; 1474 1475 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1476 return IOINST_CC_NOT_OPERATIONAL; 1477 } 1478 1479 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) || 1480 (schib->scsw.ctrl & (SCSW_STCTL_PRIMARY | 1481 SCSW_STCTL_SECONDARY | 1482 SCSW_STCTL_ALERT))) { 1483 return IOINST_CC_STATUS_PRESENT; 1484 } 1485 1486 if (schib->scsw.ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) { 1487 return IOINST_CC_BUSY; 1488 } 1489 1490 /* Trigger the halt function. */ 1491 schib->scsw.ctrl |= SCSW_FCTL_HALT_FUNC; 1492 schib->scsw.ctrl &= ~SCSW_FCTL_START_FUNC; 1493 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_ACTL) == 1494 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) && 1495 ((schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) == 1496 SCSW_STCTL_INTERMEDIATE)) { 1497 schib->scsw.ctrl &= ~SCSW_STCTL_STATUS_PEND; 1498 } 1499 schib->scsw.ctrl |= SCSW_ACTL_HALT_PEND; 1500 1501 return do_subchannel_work(sch); 1502 } 1503 1504 static void css_update_chnmon(SubchDev *sch) 1505 { 1506 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) { 1507 /* Not active. */ 1508 return; 1509 } 1510 /* The counter is conveniently located at the beginning of the struct. */ 1511 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) { 1512 /* Format 1, per-subchannel area. */ 1513 uint32_t count; 1514 1515 count = address_space_ldl(&address_space_memory, 1516 sch->curr_status.mba, 1517 MEMTXATTRS_UNSPECIFIED, 1518 NULL); 1519 count++; 1520 address_space_stl(&address_space_memory, sch->curr_status.mba, count, 1521 MEMTXATTRS_UNSPECIFIED, NULL); 1522 } else { 1523 /* Format 0, global area. */ 1524 uint32_t offset; 1525 uint16_t count; 1526 1527 offset = sch->curr_status.pmcw.mbi << 5; 1528 count = address_space_lduw(&address_space_memory, 1529 channel_subsys.chnmon_area + offset, 1530 MEMTXATTRS_UNSPECIFIED, 1531 NULL); 1532 count++; 1533 address_space_stw(&address_space_memory, 1534 channel_subsys.chnmon_area + offset, count, 1535 MEMTXATTRS_UNSPECIFIED, NULL); 1536 } 1537 } 1538 1539 IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb) 1540 { 1541 SCHIB *schib = &sch->curr_status; 1542 1543 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1544 return IOINST_CC_NOT_OPERATIONAL; 1545 } 1546 1547 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) { 1548 return IOINST_CC_STATUS_PRESENT; 1549 } 1550 1551 if (schib->scsw.ctrl & (SCSW_FCTL_START_FUNC | 1552 SCSW_FCTL_HALT_FUNC | 1553 SCSW_FCTL_CLEAR_FUNC)) { 1554 return IOINST_CC_BUSY; 1555 } 1556 1557 /* If monitoring is active, update counter. */ 1558 if (channel_subsys.chnmon_active) { 1559 css_update_chnmon(sch); 1560 } 1561 sch->orb = *orb; 1562 sch->channel_prog = orb->cpa; 1563 /* Trigger the start function. */ 1564 schib->scsw.ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND); 1565 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 1566 1567 return do_subchannel_work(sch); 1568 } 1569 1570 static void copy_irb_to_guest(IRB *dest, const IRB *src, const PMCW *pmcw, 1571 int *irb_len) 1572 { 1573 int i; 1574 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1575 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 1576 1577 copy_scsw_to_guest(&dest->scsw, &src->scsw); 1578 1579 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) { 1580 dest->esw[i] = cpu_to_be32(src->esw[i]); 1581 } 1582 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) { 1583 dest->ecw[i] = cpu_to_be32(src->ecw[i]); 1584 } 1585 *irb_len = sizeof(*dest) - sizeof(dest->emw); 1586 1587 /* extended measurements enabled? */ 1588 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) || 1589 !(pmcw->flags & PMCW_FLAGS_MASK_TF) || 1590 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) { 1591 return; 1592 } 1593 /* extended measurements pending? */ 1594 if (!(stctl & SCSW_STCTL_STATUS_PEND)) { 1595 return; 1596 } 1597 if ((stctl & SCSW_STCTL_PRIMARY) || 1598 (stctl == SCSW_STCTL_SECONDARY) || 1599 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) { 1600 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) { 1601 dest->emw[i] = cpu_to_be32(src->emw[i]); 1602 } 1603 } 1604 *irb_len = sizeof(*dest); 1605 } 1606 1607 int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len) 1608 { 1609 SCHIB *schib = &sch->curr_status; 1610 PMCW p; 1611 uint16_t stctl; 1612 IRB irb; 1613 1614 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1615 return 3; 1616 } 1617 1618 stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1619 1620 /* Prepare the irb for the guest. */ 1621 memset(&irb, 0, sizeof(IRB)); 1622 1623 /* Copy scsw from current status. */ 1624 irb.scsw = schib->scsw; 1625 if (stctl & SCSW_STCTL_STATUS_PEND) { 1626 if (schib->scsw.cstat & (SCSW_CSTAT_DATA_CHECK | 1627 SCSW_CSTAT_CHN_CTRL_CHK | 1628 SCSW_CSTAT_INTF_CTRL_CHK)) { 1629 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF; 1630 irb.esw[0] = 0x04804000; 1631 } else { 1632 irb.esw[0] = 0x00800000; 1633 } 1634 /* If a unit check is pending, copy sense data. */ 1635 if ((schib->scsw.dstat & SCSW_DSTAT_UNIT_CHECK) && 1636 (schib->pmcw.chars & PMCW_CHARS_MASK_CSENSE)) { 1637 int i; 1638 1639 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL; 1640 /* Attention: sense_data is already BE! */ 1641 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data)); 1642 for (i = 0; i < ARRAY_SIZE(irb.ecw); i++) { 1643 irb.ecw[i] = be32_to_cpu(irb.ecw[i]); 1644 } 1645 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8); 1646 } 1647 } 1648 /* Store the irb to the guest. */ 1649 p = schib->pmcw; 1650 copy_irb_to_guest(target_irb, &irb, &p, irb_len); 1651 1652 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0); 1653 } 1654 1655 void css_do_tsch_update_subch(SubchDev *sch) 1656 { 1657 SCHIB *schib = &sch->curr_status; 1658 uint16_t stctl; 1659 uint16_t fctl; 1660 uint16_t actl; 1661 1662 stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1663 fctl = schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL; 1664 actl = schib->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 1665 1666 /* Clear conditions on subchannel, if applicable. */ 1667 if (stctl & SCSW_STCTL_STATUS_PEND) { 1668 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1669 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) || 1670 ((fctl & SCSW_FCTL_HALT_FUNC) && 1671 (actl & SCSW_ACTL_SUSP))) { 1672 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_FCTL; 1673 } 1674 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) { 1675 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 1676 schib->scsw.ctrl &= ~(SCSW_ACTL_RESUME_PEND | 1677 SCSW_ACTL_START_PEND | 1678 SCSW_ACTL_HALT_PEND | 1679 SCSW_ACTL_CLEAR_PEND | 1680 SCSW_ACTL_SUSP); 1681 } else { 1682 if ((actl & SCSW_ACTL_SUSP) && 1683 (fctl & SCSW_FCTL_START_FUNC)) { 1684 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 1685 if (fctl & SCSW_FCTL_HALT_FUNC) { 1686 schib->scsw.ctrl &= ~(SCSW_ACTL_RESUME_PEND | 1687 SCSW_ACTL_START_PEND | 1688 SCSW_ACTL_HALT_PEND | 1689 SCSW_ACTL_CLEAR_PEND | 1690 SCSW_ACTL_SUSP); 1691 } else { 1692 schib->scsw.ctrl &= ~SCSW_ACTL_RESUME_PEND; 1693 } 1694 } 1695 } 1696 /* Clear pending sense data. */ 1697 if (schib->pmcw.chars & PMCW_CHARS_MASK_CSENSE) { 1698 memset(sch->sense_data, 0 , sizeof(sch->sense_data)); 1699 } 1700 } 1701 } 1702 1703 static void copy_crw_to_guest(CRW *dest, const CRW *src) 1704 { 1705 dest->flags = cpu_to_be16(src->flags); 1706 dest->rsid = cpu_to_be16(src->rsid); 1707 } 1708 1709 int css_do_stcrw(CRW *crw) 1710 { 1711 CrwContainer *crw_cont; 1712 int ret; 1713 1714 crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws); 1715 if (crw_cont) { 1716 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling); 1717 copy_crw_to_guest(crw, &crw_cont->crw); 1718 g_free(crw_cont); 1719 ret = 0; 1720 } else { 1721 /* List was empty, turn crw machine checks on again. */ 1722 memset(crw, 0, sizeof(*crw)); 1723 channel_subsys.do_crw_mchk = true; 1724 ret = 1; 1725 } 1726 1727 return ret; 1728 } 1729 1730 static void copy_crw_from_guest(CRW *dest, const CRW *src) 1731 { 1732 dest->flags = be16_to_cpu(src->flags); 1733 dest->rsid = be16_to_cpu(src->rsid); 1734 } 1735 1736 void css_undo_stcrw(CRW *crw) 1737 { 1738 CrwContainer *crw_cont; 1739 1740 crw_cont = g_try_new0(CrwContainer, 1); 1741 if (!crw_cont) { 1742 channel_subsys.crws_lost = true; 1743 return; 1744 } 1745 copy_crw_from_guest(&crw_cont->crw, crw); 1746 1747 QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling); 1748 } 1749 1750 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, 1751 int rfmt, void *buf) 1752 { 1753 int i, desc_size; 1754 uint32_t words[8]; 1755 uint32_t chpid_type_word; 1756 CssImage *css; 1757 1758 if (!m && !cssid) { 1759 css = channel_subsys.css[channel_subsys.default_cssid]; 1760 } else { 1761 css = channel_subsys.css[cssid]; 1762 } 1763 if (!css) { 1764 return 0; 1765 } 1766 desc_size = 0; 1767 for (i = f_chpid; i <= l_chpid; i++) { 1768 if (css->chpids[i].in_use) { 1769 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i; 1770 if (rfmt == 0) { 1771 words[0] = cpu_to_be32(chpid_type_word); 1772 words[1] = 0; 1773 memcpy(buf + desc_size, words, 8); 1774 desc_size += 8; 1775 } else if (rfmt == 1) { 1776 words[0] = cpu_to_be32(chpid_type_word); 1777 words[1] = 0; 1778 words[2] = 0; 1779 words[3] = 0; 1780 words[4] = 0; 1781 words[5] = 0; 1782 words[6] = 0; 1783 words[7] = 0; 1784 memcpy(buf + desc_size, words, 32); 1785 desc_size += 32; 1786 } 1787 } 1788 } 1789 return desc_size; 1790 } 1791 1792 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo) 1793 { 1794 /* dct is currently ignored (not really meaningful for our devices) */ 1795 /* TODO: Don't ignore mbk. */ 1796 if (update && !channel_subsys.chnmon_active) { 1797 /* Enable measuring. */ 1798 channel_subsys.chnmon_area = mbo; 1799 channel_subsys.chnmon_active = true; 1800 } 1801 if (!update && channel_subsys.chnmon_active) { 1802 /* Disable measuring. */ 1803 channel_subsys.chnmon_area = 0; 1804 channel_subsys.chnmon_active = false; 1805 } 1806 } 1807 1808 IOInstEnding css_do_rsch(SubchDev *sch) 1809 { 1810 SCHIB *schib = &sch->curr_status; 1811 1812 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1813 return IOINST_CC_NOT_OPERATIONAL; 1814 } 1815 1816 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) { 1817 return IOINST_CC_STATUS_PRESENT; 1818 } 1819 1820 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1821 (schib->scsw.ctrl & SCSW_ACTL_RESUME_PEND) || 1822 (!(schib->scsw.ctrl & SCSW_ACTL_SUSP))) { 1823 return IOINST_CC_BUSY; 1824 } 1825 1826 /* If monitoring is active, update counter. */ 1827 if (channel_subsys.chnmon_active) { 1828 css_update_chnmon(sch); 1829 } 1830 1831 schib->scsw.ctrl |= SCSW_ACTL_RESUME_PEND; 1832 return do_subchannel_work(sch); 1833 } 1834 1835 int css_do_rchp(uint8_t cssid, uint8_t chpid) 1836 { 1837 uint8_t real_cssid; 1838 1839 if (cssid > channel_subsys.max_cssid) { 1840 return -EINVAL; 1841 } 1842 if (channel_subsys.max_cssid == 0) { 1843 real_cssid = channel_subsys.default_cssid; 1844 } else { 1845 real_cssid = cssid; 1846 } 1847 if (!channel_subsys.css[real_cssid]) { 1848 return -EINVAL; 1849 } 1850 1851 if (!channel_subsys.css[real_cssid]->chpids[chpid].in_use) { 1852 return -ENODEV; 1853 } 1854 1855 if (!channel_subsys.css[real_cssid]->chpids[chpid].is_virtual) { 1856 fprintf(stderr, 1857 "rchp unsupported for non-virtual chpid %x.%02x!\n", 1858 real_cssid, chpid); 1859 return -ENODEV; 1860 } 1861 1862 /* We don't really use a channel path, so we're done here. */ 1863 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 1864 channel_subsys.max_cssid > 0 ? 1 : 0, chpid); 1865 if (channel_subsys.max_cssid > 0) { 1866 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 0, real_cssid << 8); 1867 } 1868 return 0; 1869 } 1870 1871 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1872 { 1873 SubchSet *set; 1874 uint8_t real_cssid; 1875 1876 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid; 1877 if (ssid > MAX_SSID || 1878 !channel_subsys.css[real_cssid] || 1879 !channel_subsys.css[real_cssid]->sch_set[ssid]) { 1880 return true; 1881 } 1882 set = channel_subsys.css[real_cssid]->sch_set[ssid]; 1883 return schid > find_last_bit(set->schids_used, 1884 (MAX_SCHID + 1) / sizeof(unsigned long)); 1885 } 1886 1887 unsigned int css_find_free_chpid(uint8_t cssid) 1888 { 1889 CssImage *css = channel_subsys.css[cssid]; 1890 unsigned int chpid; 1891 1892 if (!css) { 1893 return MAX_CHPID + 1; 1894 } 1895 1896 for (chpid = 0; chpid <= MAX_CHPID; chpid++) { 1897 /* skip reserved chpid */ 1898 if (chpid == VIRTIO_CCW_CHPID) { 1899 continue; 1900 } 1901 if (!css->chpids[chpid].in_use) { 1902 return chpid; 1903 } 1904 } 1905 return MAX_CHPID + 1; 1906 } 1907 1908 static int css_add_chpid(uint8_t cssid, uint8_t chpid, uint8_t type, 1909 bool is_virt) 1910 { 1911 CssImage *css; 1912 1913 trace_css_chpid_add(cssid, chpid, type); 1914 css = channel_subsys.css[cssid]; 1915 if (!css) { 1916 return -EINVAL; 1917 } 1918 if (css->chpids[chpid].in_use) { 1919 return -EEXIST; 1920 } 1921 css->chpids[chpid].in_use = 1; 1922 css->chpids[chpid].type = type; 1923 css->chpids[chpid].is_virtual = is_virt; 1924 1925 css_generate_chp_crws(cssid, chpid); 1926 1927 return 0; 1928 } 1929 1930 void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type) 1931 { 1932 SCHIB *schib = &sch->curr_status; 1933 int i; 1934 CssImage *css = channel_subsys.css[sch->cssid]; 1935 1936 assert(css != NULL); 1937 memset(&schib->pmcw, 0, sizeof(PMCW)); 1938 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV; 1939 schib->pmcw.devno = sch->devno; 1940 /* single path */ 1941 schib->pmcw.pim = 0x80; 1942 schib->pmcw.pom = 0xff; 1943 schib->pmcw.pam = 0x80; 1944 schib->pmcw.chpid[0] = chpid; 1945 if (!css->chpids[chpid].in_use) { 1946 css_add_chpid(sch->cssid, chpid, type, true); 1947 } 1948 1949 memset(&schib->scsw, 0, sizeof(SCSW)); 1950 schib->mba = 0; 1951 for (i = 0; i < ARRAY_SIZE(schib->mda); i++) { 1952 schib->mda[i] = 0; 1953 } 1954 } 1955 1956 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1957 { 1958 uint8_t real_cssid; 1959 1960 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid; 1961 1962 if (!channel_subsys.css[real_cssid]) { 1963 return NULL; 1964 } 1965 1966 if (!channel_subsys.css[real_cssid]->sch_set[ssid]) { 1967 return NULL; 1968 } 1969 1970 return channel_subsys.css[real_cssid]->sch_set[ssid]->sch[schid]; 1971 } 1972 1973 /** 1974 * Return free device number in subchannel set. 1975 * 1976 * Return index of the first free device number in the subchannel set 1977 * identified by @p cssid and @p ssid, beginning the search at @p 1978 * start and wrapping around at MAX_DEVNO. Return a value exceeding 1979 * MAX_SCHID if there are no free device numbers in the subchannel 1980 * set. 1981 */ 1982 static uint32_t css_find_free_devno(uint8_t cssid, uint8_t ssid, 1983 uint16_t start) 1984 { 1985 uint32_t round; 1986 1987 for (round = 0; round <= MAX_DEVNO; round++) { 1988 uint16_t devno = (start + round) % MAX_DEVNO; 1989 1990 if (!css_devno_used(cssid, ssid, devno)) { 1991 return devno; 1992 } 1993 } 1994 return MAX_DEVNO + 1; 1995 } 1996 1997 /** 1998 * Return first free subchannel (id) in subchannel set. 1999 * 2000 * Return index of the first free subchannel in the subchannel set 2001 * identified by @p cssid and @p ssid, if there is any. Return a value 2002 * exceeding MAX_SCHID if there are no free subchannels in the 2003 * subchannel set. 2004 */ 2005 static uint32_t css_find_free_subch(uint8_t cssid, uint8_t ssid) 2006 { 2007 uint32_t schid; 2008 2009 for (schid = 0; schid <= MAX_SCHID; schid++) { 2010 if (!css_find_subch(1, cssid, ssid, schid)) { 2011 return schid; 2012 } 2013 } 2014 return MAX_SCHID + 1; 2015 } 2016 2017 /** 2018 * Return first free subchannel (id) in subchannel set for a device number 2019 * 2020 * Verify the device number @p devno is not used yet in the subchannel 2021 * set identified by @p cssid and @p ssid. Set @p schid to the index 2022 * of the first free subchannel in the subchannel set, if there is 2023 * any. Return true if everything succeeded and false otherwise. 2024 */ 2025 static bool css_find_free_subch_for_devno(uint8_t cssid, uint8_t ssid, 2026 uint16_t devno, uint16_t *schid, 2027 Error **errp) 2028 { 2029 uint32_t free_schid; 2030 2031 assert(schid); 2032 if (css_devno_used(cssid, ssid, devno)) { 2033 error_setg(errp, "Device %x.%x.%04x already exists", 2034 cssid, ssid, devno); 2035 return false; 2036 } 2037 free_schid = css_find_free_subch(cssid, ssid); 2038 if (free_schid > MAX_SCHID) { 2039 error_setg(errp, "No free subchannel found for %x.%x.%04x", 2040 cssid, ssid, devno); 2041 return false; 2042 } 2043 *schid = free_schid; 2044 return true; 2045 } 2046 2047 /** 2048 * Return first free subchannel (id) and device number 2049 * 2050 * Locate the first free subchannel and first free device number in 2051 * any of the subchannel sets of the channel subsystem identified by 2052 * @p cssid. Return false if no free subchannel / device number could 2053 * be found. Otherwise set @p ssid, @p devno and @p schid to identify 2054 * the available subchannel and device number and return true. 2055 * 2056 * May modify @p ssid, @p devno and / or @p schid even if no free 2057 * subchannel / device number could be found. 2058 */ 2059 static bool css_find_free_subch_and_devno(uint8_t cssid, uint8_t *ssid, 2060 uint16_t *devno, uint16_t *schid, 2061 Error **errp) 2062 { 2063 uint32_t free_schid, free_devno; 2064 2065 assert(ssid && devno && schid); 2066 for (*ssid = 0; *ssid <= MAX_SSID; (*ssid)++) { 2067 free_schid = css_find_free_subch(cssid, *ssid); 2068 if (free_schid > MAX_SCHID) { 2069 continue; 2070 } 2071 free_devno = css_find_free_devno(cssid, *ssid, free_schid); 2072 if (free_devno > MAX_DEVNO) { 2073 continue; 2074 } 2075 *schid = free_schid; 2076 *devno = free_devno; 2077 return true; 2078 } 2079 error_setg(errp, "Virtual channel subsystem is full!"); 2080 return false; 2081 } 2082 2083 bool css_subch_visible(SubchDev *sch) 2084 { 2085 if (sch->ssid > channel_subsys.max_ssid) { 2086 return false; 2087 } 2088 2089 if (sch->cssid != channel_subsys.default_cssid) { 2090 return (channel_subsys.max_cssid > 0); 2091 } 2092 2093 return true; 2094 } 2095 2096 bool css_present(uint8_t cssid) 2097 { 2098 return (channel_subsys.css[cssid] != NULL); 2099 } 2100 2101 bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno) 2102 { 2103 if (!channel_subsys.css[cssid]) { 2104 return false; 2105 } 2106 if (!channel_subsys.css[cssid]->sch_set[ssid]) { 2107 return false; 2108 } 2109 2110 return !!test_bit(devno, 2111 channel_subsys.css[cssid]->sch_set[ssid]->devnos_used); 2112 } 2113 2114 void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid, 2115 uint16_t devno, SubchDev *sch) 2116 { 2117 CssImage *css; 2118 SubchSet *s_set; 2119 2120 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid, 2121 devno); 2122 if (!channel_subsys.css[cssid]) { 2123 fprintf(stderr, 2124 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n", 2125 __func__, cssid, ssid, schid); 2126 return; 2127 } 2128 css = channel_subsys.css[cssid]; 2129 2130 if (!css->sch_set[ssid]) { 2131 css->sch_set[ssid] = g_new0(SubchSet, 1); 2132 } 2133 s_set = css->sch_set[ssid]; 2134 2135 s_set->sch[schid] = sch; 2136 if (sch) { 2137 set_bit(schid, s_set->schids_used); 2138 set_bit(devno, s_set->devnos_used); 2139 } else { 2140 clear_bit(schid, s_set->schids_used); 2141 clear_bit(devno, s_set->devnos_used); 2142 } 2143 } 2144 2145 void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited, 2146 int chain, uint16_t rsid) 2147 { 2148 CrwContainer *crw_cont; 2149 2150 trace_css_crw(rsc, erc, rsid, chain ? "(chained)" : ""); 2151 /* TODO: Maybe use a static crw pool? */ 2152 crw_cont = g_try_new0(CrwContainer, 1); 2153 if (!crw_cont) { 2154 channel_subsys.crws_lost = true; 2155 return; 2156 } 2157 crw_cont->crw.flags = (rsc << 8) | erc; 2158 if (solicited) { 2159 crw_cont->crw.flags |= CRW_FLAGS_MASK_S; 2160 } 2161 if (chain) { 2162 crw_cont->crw.flags |= CRW_FLAGS_MASK_C; 2163 } 2164 crw_cont->crw.rsid = rsid; 2165 if (channel_subsys.crws_lost) { 2166 crw_cont->crw.flags |= CRW_FLAGS_MASK_R; 2167 channel_subsys.crws_lost = false; 2168 } 2169 2170 QTAILQ_INSERT_TAIL(&channel_subsys.pending_crws, crw_cont, sibling); 2171 2172 if (channel_subsys.do_crw_mchk) { 2173 channel_subsys.do_crw_mchk = false; 2174 /* Inject crw pending machine check. */ 2175 s390_crw_mchk(); 2176 } 2177 } 2178 2179 void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid, 2180 int hotplugged, int add) 2181 { 2182 uint8_t guest_cssid; 2183 bool chain_crw; 2184 2185 if (add && !hotplugged) { 2186 return; 2187 } 2188 if (channel_subsys.max_cssid == 0) { 2189 /* Default cssid shows up as 0. */ 2190 guest_cssid = (cssid == channel_subsys.default_cssid) ? 0 : cssid; 2191 } else { 2192 /* Show real cssid to the guest. */ 2193 guest_cssid = cssid; 2194 } 2195 /* 2196 * Only notify for higher subchannel sets/channel subsystems if the 2197 * guest has enabled it. 2198 */ 2199 if ((ssid > channel_subsys.max_ssid) || 2200 (guest_cssid > channel_subsys.max_cssid) || 2201 ((channel_subsys.max_cssid == 0) && 2202 (cssid != channel_subsys.default_cssid))) { 2203 return; 2204 } 2205 chain_crw = (channel_subsys.max_ssid > 0) || 2206 (channel_subsys.max_cssid > 0); 2207 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, chain_crw ? 1 : 0, schid); 2208 if (chain_crw) { 2209 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 0, 2210 (guest_cssid << 8) | (ssid << 4)); 2211 } 2212 /* RW_ERC_IPI --> clear pending interrupts */ 2213 css_clear_io_interrupt(css_do_build_subchannel_id(cssid, ssid), schid); 2214 } 2215 2216 void css_generate_chp_crws(uint8_t cssid, uint8_t chpid) 2217 { 2218 /* TODO */ 2219 } 2220 2221 void css_generate_css_crws(uint8_t cssid) 2222 { 2223 if (!channel_subsys.sei_pending) { 2224 css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, 0, cssid); 2225 } 2226 channel_subsys.sei_pending = true; 2227 } 2228 2229 void css_clear_sei_pending(void) 2230 { 2231 channel_subsys.sei_pending = false; 2232 } 2233 2234 int css_enable_mcsse(void) 2235 { 2236 trace_css_enable_facility("mcsse"); 2237 channel_subsys.max_cssid = MAX_CSSID; 2238 return 0; 2239 } 2240 2241 int css_enable_mss(void) 2242 { 2243 trace_css_enable_facility("mss"); 2244 channel_subsys.max_ssid = MAX_SSID; 2245 return 0; 2246 } 2247 2248 void css_reset_sch(SubchDev *sch) 2249 { 2250 SCHIB *schib = &sch->curr_status; 2251 2252 if ((schib->pmcw.flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) { 2253 sch->disable_cb(sch); 2254 } 2255 2256 schib->pmcw.intparm = 0; 2257 schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 2258 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 2259 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF); 2260 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV; 2261 schib->pmcw.devno = sch->devno; 2262 schib->pmcw.pim = 0x80; 2263 schib->pmcw.lpm = schib->pmcw.pim; 2264 schib->pmcw.pnom = 0; 2265 schib->pmcw.lpum = 0; 2266 schib->pmcw.mbi = 0; 2267 schib->pmcw.pom = 0xff; 2268 schib->pmcw.pam = 0x80; 2269 schib->pmcw.chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME | 2270 PMCW_CHARS_MASK_CSENSE); 2271 2272 memset(&schib->scsw, 0, sizeof(schib->scsw)); 2273 schib->mba = 0; 2274 2275 sch->channel_prog = 0x0; 2276 sch->last_cmd_valid = false; 2277 sch->thinint_active = false; 2278 } 2279 2280 void css_reset(void) 2281 { 2282 CrwContainer *crw_cont; 2283 2284 /* Clean up monitoring. */ 2285 channel_subsys.chnmon_active = false; 2286 channel_subsys.chnmon_area = 0; 2287 2288 /* Clear pending CRWs. */ 2289 while ((crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws))) { 2290 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling); 2291 g_free(crw_cont); 2292 } 2293 channel_subsys.sei_pending = false; 2294 channel_subsys.do_crw_mchk = true; 2295 channel_subsys.crws_lost = false; 2296 2297 /* Reset maximum ids. */ 2298 channel_subsys.max_cssid = 0; 2299 channel_subsys.max_ssid = 0; 2300 } 2301 2302 static void get_css_devid(Object *obj, Visitor *v, const char *name, 2303 void *opaque, Error **errp) 2304 { 2305 DeviceState *dev = DEVICE(obj); 2306 Property *prop = opaque; 2307 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop); 2308 char buffer[] = "xx.x.xxxx"; 2309 char *p = buffer; 2310 int r; 2311 2312 if (dev_id->valid) { 2313 2314 r = snprintf(buffer, sizeof(buffer), "%02x.%1x.%04x", dev_id->cssid, 2315 dev_id->ssid, dev_id->devid); 2316 assert(r == sizeof(buffer) - 1); 2317 2318 /* drop leading zero */ 2319 if (dev_id->cssid <= 0xf) { 2320 p++; 2321 } 2322 } else { 2323 snprintf(buffer, sizeof(buffer), "<unset>"); 2324 } 2325 2326 visit_type_str(v, name, &p, errp); 2327 } 2328 2329 /* 2330 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid 2331 */ 2332 static void set_css_devid(Object *obj, Visitor *v, const char *name, 2333 void *opaque, Error **errp) 2334 { 2335 DeviceState *dev = DEVICE(obj); 2336 Property *prop = opaque; 2337 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop); 2338 Error *local_err = NULL; 2339 char *str; 2340 int num, n1, n2; 2341 unsigned int cssid, ssid, devid; 2342 2343 if (dev->realized) { 2344 qdev_prop_set_after_realize(dev, name, errp); 2345 return; 2346 } 2347 2348 visit_type_str(v, name, &str, &local_err); 2349 if (local_err) { 2350 error_propagate(errp, local_err); 2351 return; 2352 } 2353 2354 num = sscanf(str, "%2x.%1x%n.%4x%n", &cssid, &ssid, &n1, &devid, &n2); 2355 if (num != 3 || (n2 - n1) != 5 || strlen(str) != n2) { 2356 error_set_from_qdev_prop_error(errp, EINVAL, dev, prop, str); 2357 goto out; 2358 } 2359 if ((cssid > MAX_CSSID) || (ssid > MAX_SSID)) { 2360 error_setg(errp, "Invalid cssid or ssid: cssid %x, ssid %x", 2361 cssid, ssid); 2362 goto out; 2363 } 2364 2365 dev_id->cssid = cssid; 2366 dev_id->ssid = ssid; 2367 dev_id->devid = devid; 2368 dev_id->valid = true; 2369 2370 out: 2371 g_free(str); 2372 } 2373 2374 const PropertyInfo css_devid_propinfo = { 2375 .name = "str", 2376 .description = "Identifier of an I/O device in the channel " 2377 "subsystem, example: fe.1.23ab", 2378 .get = get_css_devid, 2379 .set = set_css_devid, 2380 }; 2381 2382 const PropertyInfo css_devid_ro_propinfo = { 2383 .name = "str", 2384 .description = "Read-only identifier of an I/O device in the channel " 2385 "subsystem, example: fe.1.23ab", 2386 .get = get_css_devid, 2387 }; 2388 2389 SubchDev *css_create_sch(CssDevId bus_id, Error **errp) 2390 { 2391 uint16_t schid = 0; 2392 SubchDev *sch; 2393 2394 if (bus_id.valid) { 2395 if (!channel_subsys.css[bus_id.cssid]) { 2396 css_create_css_image(bus_id.cssid, false); 2397 } 2398 2399 if (!css_find_free_subch_for_devno(bus_id.cssid, bus_id.ssid, 2400 bus_id.devid, &schid, errp)) { 2401 return NULL; 2402 } 2403 } else { 2404 for (bus_id.cssid = channel_subsys.default_cssid;;) { 2405 if (!channel_subsys.css[bus_id.cssid]) { 2406 css_create_css_image(bus_id.cssid, false); 2407 } 2408 2409 if (css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid, 2410 &bus_id.devid, &schid, 2411 NULL)) { 2412 break; 2413 } 2414 bus_id.cssid = (bus_id.cssid + 1) % MAX_CSSID; 2415 if (bus_id.cssid == channel_subsys.default_cssid) { 2416 error_setg(errp, "Virtual channel subsystem is full!"); 2417 return NULL; 2418 } 2419 } 2420 } 2421 2422 sch = g_new0(SubchDev, 1); 2423 sch->cssid = bus_id.cssid; 2424 sch->ssid = bus_id.ssid; 2425 sch->devno = bus_id.devid; 2426 sch->schid = schid; 2427 css_subch_assign(sch->cssid, sch->ssid, schid, sch->devno, sch); 2428 return sch; 2429 } 2430 2431 static int css_sch_get_chpids(SubchDev *sch, CssDevId *dev_id) 2432 { 2433 char *fid_path; 2434 FILE *fd; 2435 uint32_t chpid[8]; 2436 int i; 2437 SCHIB *schib = &sch->curr_status; 2438 2439 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids", 2440 dev_id->cssid, dev_id->ssid, dev_id->devid); 2441 fd = fopen(fid_path, "r"); 2442 if (fd == NULL) { 2443 error_report("%s: open %s failed", __func__, fid_path); 2444 g_free(fid_path); 2445 return -EINVAL; 2446 } 2447 2448 if (fscanf(fd, "%x %x %x %x %x %x %x %x", 2449 &chpid[0], &chpid[1], &chpid[2], &chpid[3], 2450 &chpid[4], &chpid[5], &chpid[6], &chpid[7]) != 8) { 2451 fclose(fd); 2452 g_free(fid_path); 2453 return -EINVAL; 2454 } 2455 2456 for (i = 0; i < ARRAY_SIZE(schib->pmcw.chpid); i++) { 2457 schib->pmcw.chpid[i] = chpid[i]; 2458 } 2459 2460 fclose(fd); 2461 g_free(fid_path); 2462 2463 return 0; 2464 } 2465 2466 static int css_sch_get_path_masks(SubchDev *sch, CssDevId *dev_id) 2467 { 2468 char *fid_path; 2469 FILE *fd; 2470 uint32_t pim, pam, pom; 2471 SCHIB *schib = &sch->curr_status; 2472 2473 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom", 2474 dev_id->cssid, dev_id->ssid, dev_id->devid); 2475 fd = fopen(fid_path, "r"); 2476 if (fd == NULL) { 2477 error_report("%s: open %s failed", __func__, fid_path); 2478 g_free(fid_path); 2479 return -EINVAL; 2480 } 2481 2482 if (fscanf(fd, "%x %x %x", &pim, &pam, &pom) != 3) { 2483 fclose(fd); 2484 g_free(fid_path); 2485 return -EINVAL; 2486 } 2487 2488 schib->pmcw.pim = pim; 2489 schib->pmcw.pam = pam; 2490 schib->pmcw.pom = pom; 2491 fclose(fd); 2492 g_free(fid_path); 2493 2494 return 0; 2495 } 2496 2497 static int css_sch_get_chpid_type(uint8_t chpid, uint32_t *type, 2498 CssDevId *dev_id) 2499 { 2500 char *fid_path; 2501 FILE *fd; 2502 2503 fid_path = g_strdup_printf("/sys/devices/css%x/chp0.%02x/type", 2504 dev_id->cssid, chpid); 2505 fd = fopen(fid_path, "r"); 2506 if (fd == NULL) { 2507 error_report("%s: open %s failed", __func__, fid_path); 2508 g_free(fid_path); 2509 return -EINVAL; 2510 } 2511 2512 if (fscanf(fd, "%x", type) != 1) { 2513 fclose(fd); 2514 g_free(fid_path); 2515 return -EINVAL; 2516 } 2517 2518 fclose(fd); 2519 g_free(fid_path); 2520 2521 return 0; 2522 } 2523 2524 /* 2525 * We currently retrieve the real device information from sysfs to build the 2526 * guest subchannel information block without considering the migration feature. 2527 * We need to revisit this problem when we want to add migration support. 2528 */ 2529 int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id) 2530 { 2531 CssImage *css = channel_subsys.css[sch->cssid]; 2532 SCHIB *schib = &sch->curr_status; 2533 uint32_t type; 2534 int i, ret; 2535 2536 assert(css != NULL); 2537 memset(&schib->pmcw, 0, sizeof(PMCW)); 2538 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV; 2539 /* We are dealing with I/O subchannels only. */ 2540 schib->pmcw.devno = sch->devno; 2541 2542 /* Grab path mask from sysfs. */ 2543 ret = css_sch_get_path_masks(sch, dev_id); 2544 if (ret) { 2545 return ret; 2546 } 2547 2548 /* Grab chpids from sysfs. */ 2549 ret = css_sch_get_chpids(sch, dev_id); 2550 if (ret) { 2551 return ret; 2552 } 2553 2554 /* Build chpid type. */ 2555 for (i = 0; i < ARRAY_SIZE(schib->pmcw.chpid); i++) { 2556 if (schib->pmcw.chpid[i] && !css->chpids[schib->pmcw.chpid[i]].in_use) { 2557 ret = css_sch_get_chpid_type(schib->pmcw.chpid[i], &type, dev_id); 2558 if (ret) { 2559 return ret; 2560 } 2561 css_add_chpid(sch->cssid, schib->pmcw.chpid[i], type, false); 2562 } 2563 } 2564 2565 memset(&schib->scsw, 0, sizeof(SCSW)); 2566 schib->mba = 0; 2567 for (i = 0; i < ARRAY_SIZE(schib->mda); i++) { 2568 schib->mda[i] = 0; 2569 } 2570 2571 return 0; 2572 } 2573