1 /* 2 * Channel subsystem base support. 3 * 4 * Copyright 2012 IBM Corp. 5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or (at 8 * your option) any later version. See the COPYING file in the top-level 9 * directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qapi/visitor.h" 15 #include "qemu/bitops.h" 16 #include "qemu/error-report.h" 17 #include "exec/address-spaces.h" 18 #include "cpu.h" 19 #include "hw/s390x/ioinst.h" 20 #include "hw/qdev-properties.h" 21 #include "hw/s390x/css.h" 22 #include "trace.h" 23 #include "hw/s390x/s390_flic.h" 24 #include "hw/s390x/s390-virtio-ccw.h" 25 #include "hw/s390x/s390-ccw.h" 26 27 typedef struct CrwContainer { 28 CRW crw; 29 QTAILQ_ENTRY(CrwContainer) sibling; 30 } CrwContainer; 31 32 static const VMStateDescription vmstate_crw = { 33 .name = "s390_crw", 34 .version_id = 1, 35 .minimum_version_id = 1, 36 .fields = (VMStateField[]) { 37 VMSTATE_UINT16(flags, CRW), 38 VMSTATE_UINT16(rsid, CRW), 39 VMSTATE_END_OF_LIST() 40 }, 41 }; 42 43 static const VMStateDescription vmstate_crw_container = { 44 .name = "s390_crw_container", 45 .version_id = 1, 46 .minimum_version_id = 1, 47 .fields = (VMStateField[]) { 48 VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW), 49 VMSTATE_END_OF_LIST() 50 }, 51 }; 52 53 typedef struct ChpInfo { 54 uint8_t in_use; 55 uint8_t type; 56 uint8_t is_virtual; 57 } ChpInfo; 58 59 static const VMStateDescription vmstate_chp_info = { 60 .name = "s390_chp_info", 61 .version_id = 1, 62 .minimum_version_id = 1, 63 .fields = (VMStateField[]) { 64 VMSTATE_UINT8(in_use, ChpInfo), 65 VMSTATE_UINT8(type, ChpInfo), 66 VMSTATE_UINT8(is_virtual, ChpInfo), 67 VMSTATE_END_OF_LIST() 68 } 69 }; 70 71 typedef struct SubchSet { 72 SubchDev *sch[MAX_SCHID + 1]; 73 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 74 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 75 } SubchSet; 76 77 static const VMStateDescription vmstate_scsw = { 78 .name = "s390_scsw", 79 .version_id = 1, 80 .minimum_version_id = 1, 81 .fields = (VMStateField[]) { 82 VMSTATE_UINT16(flags, SCSW), 83 VMSTATE_UINT16(ctrl, SCSW), 84 VMSTATE_UINT32(cpa, SCSW), 85 VMSTATE_UINT8(dstat, SCSW), 86 VMSTATE_UINT8(cstat, SCSW), 87 VMSTATE_UINT16(count, SCSW), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 static const VMStateDescription vmstate_pmcw = { 93 .name = "s390_pmcw", 94 .version_id = 1, 95 .minimum_version_id = 1, 96 .fields = (VMStateField[]) { 97 VMSTATE_UINT32(intparm, PMCW), 98 VMSTATE_UINT16(flags, PMCW), 99 VMSTATE_UINT16(devno, PMCW), 100 VMSTATE_UINT8(lpm, PMCW), 101 VMSTATE_UINT8(pnom, PMCW), 102 VMSTATE_UINT8(lpum, PMCW), 103 VMSTATE_UINT8(pim, PMCW), 104 VMSTATE_UINT16(mbi, PMCW), 105 VMSTATE_UINT8(pom, PMCW), 106 VMSTATE_UINT8(pam, PMCW), 107 VMSTATE_UINT8_ARRAY(chpid, PMCW, 8), 108 VMSTATE_UINT32(chars, PMCW), 109 VMSTATE_END_OF_LIST() 110 } 111 }; 112 113 static const VMStateDescription vmstate_schib = { 114 .name = "s390_schib", 115 .version_id = 1, 116 .minimum_version_id = 1, 117 .fields = (VMStateField[]) { 118 VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW), 119 VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW), 120 VMSTATE_UINT64(mba, SCHIB), 121 VMSTATE_UINT8_ARRAY(mda, SCHIB, 4), 122 VMSTATE_END_OF_LIST() 123 } 124 }; 125 126 127 static const VMStateDescription vmstate_ccw1 = { 128 .name = "s390_ccw1", 129 .version_id = 1, 130 .minimum_version_id = 1, 131 .fields = (VMStateField[]) { 132 VMSTATE_UINT8(cmd_code, CCW1), 133 VMSTATE_UINT8(flags, CCW1), 134 VMSTATE_UINT16(count, CCW1), 135 VMSTATE_UINT32(cda, CCW1), 136 VMSTATE_END_OF_LIST() 137 } 138 }; 139 140 static const VMStateDescription vmstate_ciw = { 141 .name = "s390_ciw", 142 .version_id = 1, 143 .minimum_version_id = 1, 144 .fields = (VMStateField[]) { 145 VMSTATE_UINT8(type, CIW), 146 VMSTATE_UINT8(command, CIW), 147 VMSTATE_UINT16(count, CIW), 148 VMSTATE_END_OF_LIST() 149 } 150 }; 151 152 static const VMStateDescription vmstate_sense_id = { 153 .name = "s390_sense_id", 154 .version_id = 1, 155 .minimum_version_id = 1, 156 .fields = (VMStateField[]) { 157 VMSTATE_UINT8(reserved, SenseId), 158 VMSTATE_UINT16(cu_type, SenseId), 159 VMSTATE_UINT8(cu_model, SenseId), 160 VMSTATE_UINT16(dev_type, SenseId), 161 VMSTATE_UINT8(dev_model, SenseId), 162 VMSTATE_UINT8(unused, SenseId), 163 VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW), 164 VMSTATE_END_OF_LIST() 165 } 166 }; 167 168 static const VMStateDescription vmstate_orb = { 169 .name = "s390_orb", 170 .version_id = 1, 171 .minimum_version_id = 1, 172 .fields = (VMStateField[]) { 173 VMSTATE_UINT32(intparm, ORB), 174 VMSTATE_UINT16(ctrl0, ORB), 175 VMSTATE_UINT8(lpm, ORB), 176 VMSTATE_UINT8(ctrl1, ORB), 177 VMSTATE_UINT32(cpa, ORB), 178 VMSTATE_END_OF_LIST() 179 } 180 }; 181 182 static bool vmstate_schdev_orb_needed(void *opaque) 183 { 184 return css_migration_enabled(); 185 } 186 187 static const VMStateDescription vmstate_schdev_orb = { 188 .name = "s390_subch_dev/orb", 189 .version_id = 1, 190 .minimum_version_id = 1, 191 .needed = vmstate_schdev_orb_needed, 192 .fields = (VMStateField[]) { 193 VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB), 194 VMSTATE_END_OF_LIST() 195 } 196 }; 197 198 static int subch_dev_post_load(void *opaque, int version_id); 199 static int subch_dev_pre_save(void *opaque); 200 201 const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!" 202 " Likely reason: some sequences of plug and unplug can break" 203 " migration for machine versions prior to 2.7 (known design flaw)."; 204 205 const VMStateDescription vmstate_subch_dev = { 206 .name = "s390_subch_dev", 207 .version_id = 1, 208 .minimum_version_id = 1, 209 .post_load = subch_dev_post_load, 210 .pre_save = subch_dev_pre_save, 211 .fields = (VMStateField[]) { 212 VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"), 213 VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"), 214 VMSTATE_UINT16(migrated_schid, SubchDev), 215 VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno), 216 VMSTATE_BOOL(thinint_active, SubchDev), 217 VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB), 218 VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32), 219 VMSTATE_UINT64(channel_prog, SubchDev), 220 VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1), 221 VMSTATE_BOOL(last_cmd_valid, SubchDev), 222 VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId), 223 VMSTATE_BOOL(ccw_fmt_1, SubchDev), 224 VMSTATE_UINT8(ccw_no_data_cnt, SubchDev), 225 VMSTATE_END_OF_LIST() 226 }, 227 .subsections = (const VMStateDescription * []) { 228 &vmstate_schdev_orb, 229 NULL 230 } 231 }; 232 233 typedef struct IndAddrPtrTmp { 234 IndAddr **parent; 235 uint64_t addr; 236 int32_t len; 237 } IndAddrPtrTmp; 238 239 static int post_load_ind_addr(void *opaque, int version_id) 240 { 241 IndAddrPtrTmp *ptmp = opaque; 242 IndAddr **ind_addr = ptmp->parent; 243 244 if (ptmp->len != 0) { 245 *ind_addr = get_indicator(ptmp->addr, ptmp->len); 246 } else { 247 *ind_addr = NULL; 248 } 249 return 0; 250 } 251 252 static int pre_save_ind_addr(void *opaque) 253 { 254 IndAddrPtrTmp *ptmp = opaque; 255 IndAddr *ind_addr = *(ptmp->parent); 256 257 if (ind_addr != NULL) { 258 ptmp->len = ind_addr->len; 259 ptmp->addr = ind_addr->addr; 260 } else { 261 ptmp->len = 0; 262 ptmp->addr = 0L; 263 } 264 265 return 0; 266 } 267 268 const VMStateDescription vmstate_ind_addr_tmp = { 269 .name = "s390_ind_addr_tmp", 270 .pre_save = pre_save_ind_addr, 271 .post_load = post_load_ind_addr, 272 273 .fields = (VMStateField[]) { 274 VMSTATE_INT32(len, IndAddrPtrTmp), 275 VMSTATE_UINT64(addr, IndAddrPtrTmp), 276 VMSTATE_END_OF_LIST() 277 } 278 }; 279 280 const VMStateDescription vmstate_ind_addr = { 281 .name = "s390_ind_addr_tmp", 282 .fields = (VMStateField[]) { 283 VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp), 284 VMSTATE_END_OF_LIST() 285 } 286 }; 287 288 typedef struct CssImage { 289 SubchSet *sch_set[MAX_SSID + 1]; 290 ChpInfo chpids[MAX_CHPID + 1]; 291 } CssImage; 292 293 static const VMStateDescription vmstate_css_img = { 294 .name = "s390_css_img", 295 .version_id = 1, 296 .minimum_version_id = 1, 297 .fields = (VMStateField[]) { 298 /* Subchannel sets have no relevant state. */ 299 VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0, 300 vmstate_chp_info, ChpInfo), 301 VMSTATE_END_OF_LIST() 302 } 303 304 }; 305 306 typedef struct IoAdapter { 307 uint32_t id; 308 uint8_t type; 309 uint8_t isc; 310 uint8_t flags; 311 } IoAdapter; 312 313 typedef struct ChannelSubSys { 314 QTAILQ_HEAD(, CrwContainer) pending_crws; 315 bool sei_pending; 316 bool do_crw_mchk; 317 bool crws_lost; 318 uint8_t max_cssid; 319 uint8_t max_ssid; 320 bool chnmon_active; 321 uint64_t chnmon_area; 322 CssImage *css[MAX_CSSID + 1]; 323 uint8_t default_cssid; 324 /* don't migrate, see css_register_io_adapters */ 325 IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1]; 326 /* don't migrate, see get_indicator and IndAddrPtrTmp */ 327 QTAILQ_HEAD(, IndAddr) indicator_addresses; 328 } ChannelSubSys; 329 330 static const VMStateDescription vmstate_css = { 331 .name = "s390_css", 332 .version_id = 1, 333 .minimum_version_id = 1, 334 .fields = (VMStateField[]) { 335 VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container, 336 CrwContainer, sibling), 337 VMSTATE_BOOL(sei_pending, ChannelSubSys), 338 VMSTATE_BOOL(do_crw_mchk, ChannelSubSys), 339 VMSTATE_BOOL(crws_lost, ChannelSubSys), 340 /* These were kind of migrated by virtio */ 341 VMSTATE_UINT8(max_cssid, ChannelSubSys), 342 VMSTATE_UINT8(max_ssid, ChannelSubSys), 343 VMSTATE_BOOL(chnmon_active, ChannelSubSys), 344 VMSTATE_UINT64(chnmon_area, ChannelSubSys), 345 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1, 346 0, vmstate_css_img, CssImage), 347 VMSTATE_UINT8(default_cssid, ChannelSubSys), 348 VMSTATE_END_OF_LIST() 349 } 350 }; 351 352 static ChannelSubSys channel_subsys = { 353 .pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws), 354 .do_crw_mchk = true, 355 .sei_pending = false, 356 .crws_lost = false, 357 .chnmon_active = false, 358 .indicator_addresses = 359 QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses), 360 }; 361 362 static int subch_dev_pre_save(void *opaque) 363 { 364 SubchDev *s = opaque; 365 366 /* Prepare remote_schid for save */ 367 s->migrated_schid = s->schid; 368 369 return 0; 370 } 371 372 static int subch_dev_post_load(void *opaque, int version_id) 373 { 374 375 SubchDev *s = opaque; 376 377 /* Re-assign the subchannel to remote_schid if necessary */ 378 if (s->migrated_schid != s->schid) { 379 if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) { 380 /* 381 * Cleanup the slot before moving to s->migrated_schid provided 382 * it still belongs to us, i.e. it was not changed by previous 383 * invocation of this function. 384 */ 385 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL); 386 } 387 /* It's OK to re-assign without a prior de-assign. */ 388 s->schid = s->migrated_schid; 389 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s); 390 } 391 392 if (css_migration_enabled()) { 393 /* No compat voodoo to do ;) */ 394 return 0; 395 } 396 /* 397 * Hack alert. If we don't migrate the channel subsystem status 398 * we still need to find out if the guest enabled mss/mcss-e. 399 * If the subchannel is enabled, it certainly was able to access it, 400 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid 401 * values. This is not watertight, but better than nothing. 402 */ 403 if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) { 404 if (s->ssid) { 405 channel_subsys.max_ssid = MAX_SSID; 406 } 407 if (s->cssid != channel_subsys.default_cssid) { 408 channel_subsys.max_cssid = MAX_CSSID; 409 } 410 } 411 return 0; 412 } 413 414 void css_register_vmstate(void) 415 { 416 vmstate_register(NULL, 0, &vmstate_css, &channel_subsys); 417 } 418 419 IndAddr *get_indicator(hwaddr ind_addr, int len) 420 { 421 IndAddr *indicator; 422 423 QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) { 424 if (indicator->addr == ind_addr) { 425 indicator->refcnt++; 426 return indicator; 427 } 428 } 429 indicator = g_new0(IndAddr, 1); 430 indicator->addr = ind_addr; 431 indicator->len = len; 432 indicator->refcnt = 1; 433 QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses, 434 indicator, sibling); 435 return indicator; 436 } 437 438 static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr, 439 bool do_map) 440 { 441 S390FLICState *fs = s390_get_flic(); 442 S390FLICStateClass *fsc = s390_get_flic_class(fs); 443 444 return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map); 445 } 446 447 void release_indicator(AdapterInfo *adapter, IndAddr *indicator) 448 { 449 assert(indicator->refcnt > 0); 450 indicator->refcnt--; 451 if (indicator->refcnt > 0) { 452 return; 453 } 454 QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling); 455 if (indicator->map) { 456 s390_io_adapter_map(adapter, indicator->map, false); 457 } 458 g_free(indicator); 459 } 460 461 int map_indicator(AdapterInfo *adapter, IndAddr *indicator) 462 { 463 int ret; 464 465 if (indicator->map) { 466 return 0; /* already mapped is not an error */ 467 } 468 indicator->map = indicator->addr; 469 ret = s390_io_adapter_map(adapter, indicator->map, true); 470 if ((ret != 0) && (ret != -ENOSYS)) { 471 goto out_err; 472 } 473 return 0; 474 475 out_err: 476 indicator->map = 0; 477 return ret; 478 } 479 480 int css_create_css_image(uint8_t cssid, bool default_image) 481 { 482 trace_css_new_image(cssid, default_image ? "(default)" : ""); 483 /* 255 is reserved */ 484 if (cssid == 255) { 485 return -EINVAL; 486 } 487 if (channel_subsys.css[cssid]) { 488 return -EBUSY; 489 } 490 channel_subsys.css[cssid] = g_new0(CssImage, 1); 491 if (default_image) { 492 channel_subsys.default_cssid = cssid; 493 } 494 return 0; 495 } 496 497 uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc) 498 { 499 if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC || 500 !channel_subsys.io_adapters[type][isc]) { 501 return -1; 502 } 503 504 return channel_subsys.io_adapters[type][isc]->id; 505 } 506 507 /** 508 * css_register_io_adapters: Register I/O adapters per ISC during init 509 * 510 * @swap: an indication if byte swap is needed. 511 * @maskable: an indication if the adapter is subject to the mask operation. 512 * @flags: further characteristics of the adapter. 513 * e.g. suppressible, an indication if the adapter is subject to AIS. 514 * @errp: location to store error information. 515 */ 516 void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable, 517 uint8_t flags, Error **errp) 518 { 519 uint32_t id; 520 int ret, isc; 521 IoAdapter *adapter; 522 S390FLICState *fs = s390_get_flic(); 523 S390FLICStateClass *fsc = s390_get_flic_class(fs); 524 525 /* 526 * Disallow multiple registrations for the same device type. 527 * Report an error if registering for an already registered type. 528 */ 529 if (channel_subsys.io_adapters[type][0]) { 530 error_setg(errp, "Adapters for type %d already registered", type); 531 } 532 533 for (isc = 0; isc <= MAX_ISC; isc++) { 534 id = (type << 3) | isc; 535 ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags); 536 if (ret == 0) { 537 adapter = g_new0(IoAdapter, 1); 538 adapter->id = id; 539 adapter->isc = isc; 540 adapter->type = type; 541 adapter->flags = flags; 542 channel_subsys.io_adapters[type][isc] = adapter; 543 } else { 544 error_setg_errno(errp, -ret, "Unexpected error %d when " 545 "registering adapter %d", ret, id); 546 break; 547 } 548 } 549 550 /* 551 * No need to free registered adapters in kvm: kvm will clean up 552 * when the machine goes away. 553 */ 554 if (ret) { 555 for (isc--; isc >= 0; isc--) { 556 g_free(channel_subsys.io_adapters[type][isc]); 557 channel_subsys.io_adapters[type][isc] = NULL; 558 } 559 } 560 561 } 562 563 static void css_clear_io_interrupt(uint16_t subchannel_id, 564 uint16_t subchannel_nr) 565 { 566 Error *err = NULL; 567 static bool no_clear_irq; 568 S390FLICState *fs = s390_get_flic(); 569 S390FLICStateClass *fsc = s390_get_flic_class(fs); 570 int r; 571 572 if (unlikely(no_clear_irq)) { 573 return; 574 } 575 r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr); 576 switch (r) { 577 case 0: 578 break; 579 case -ENOSYS: 580 no_clear_irq = true; 581 /* 582 * Ignore unavailability, as the user can't do anything 583 * about it anyway. 584 */ 585 break; 586 default: 587 error_setg_errno(&err, -r, "unexpected error condition"); 588 error_propagate(&error_abort, err); 589 } 590 } 591 592 static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid) 593 { 594 if (channel_subsys.max_cssid > 0) { 595 return (cssid << 8) | (1 << 3) | (ssid << 1) | 1; 596 } 597 return (ssid << 1) | 1; 598 } 599 600 uint16_t css_build_subchannel_id(SubchDev *sch) 601 { 602 return css_do_build_subchannel_id(sch->cssid, sch->ssid); 603 } 604 605 void css_inject_io_interrupt(SubchDev *sch) 606 { 607 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 608 609 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 610 sch->curr_status.pmcw.intparm, isc, ""); 611 s390_io_interrupt(css_build_subchannel_id(sch), 612 sch->schid, 613 sch->curr_status.pmcw.intparm, 614 isc << 27); 615 } 616 617 void css_conditional_io_interrupt(SubchDev *sch) 618 { 619 /* 620 * If the subchannel is not enabled, it is not made status pending 621 * (see PoP p. 16-17, "Status Control"). 622 */ 623 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA)) { 624 return; 625 } 626 627 /* 628 * If the subchannel is not currently status pending, make it pending 629 * with alert status. 630 */ 631 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) { 632 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 633 634 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 635 sch->curr_status.pmcw.intparm, isc, 636 "(unsolicited)"); 637 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 638 sch->curr_status.scsw.ctrl |= 639 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 640 /* Inject an I/O interrupt. */ 641 s390_io_interrupt(css_build_subchannel_id(sch), 642 sch->schid, 643 sch->curr_status.pmcw.intparm, 644 isc << 27); 645 } 646 } 647 648 int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode) 649 { 650 S390FLICState *fs = s390_get_flic(); 651 S390FLICStateClass *fsc = s390_get_flic_class(fs); 652 int r; 653 654 if (env->psw.mask & PSW_MASK_PSTATE) { 655 r = -PGM_PRIVILEGED; 656 goto out; 657 } 658 659 trace_css_do_sic(mode, isc); 660 switch (mode) { 661 case SIC_IRQ_MODE_ALL: 662 case SIC_IRQ_MODE_SINGLE: 663 break; 664 default: 665 r = -PGM_OPERAND; 666 goto out; 667 } 668 669 r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0; 670 out: 671 return r; 672 } 673 674 void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc) 675 { 676 S390FLICState *fs = s390_get_flic(); 677 S390FLICStateClass *fsc = s390_get_flic_class(fs); 678 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI; 679 IoAdapter *adapter = channel_subsys.io_adapters[type][isc]; 680 681 if (!adapter) { 682 return; 683 } 684 685 trace_css_adapter_interrupt(isc); 686 if (fs->ais_supported) { 687 if (fsc->inject_airq(fs, type, isc, adapter->flags)) { 688 error_report("Failed to inject airq with AIS supported"); 689 exit(1); 690 } 691 } else { 692 s390_io_interrupt(0, 0, 0, io_int_word); 693 } 694 } 695 696 static void sch_handle_clear_func(SubchDev *sch) 697 { 698 SCHIB *schib = &sch->curr_status; 699 int path; 700 701 /* Path management: In our simple css, we always choose the only path. */ 702 path = 0x80; 703 704 /* Reset values prior to 'issuing the clear signal'. */ 705 schib->pmcw.lpum = 0; 706 schib->pmcw.pom = 0xff; 707 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 708 709 /* We always 'attempt to issue the clear signal', and we always succeed. */ 710 sch->channel_prog = 0x0; 711 sch->last_cmd_valid = false; 712 schib->scsw.ctrl &= ~SCSW_ACTL_CLEAR_PEND; 713 schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND; 714 715 schib->scsw.dstat = 0; 716 schib->scsw.cstat = 0; 717 schib->pmcw.lpum = path; 718 719 } 720 721 static void sch_handle_halt_func(SubchDev *sch) 722 { 723 SCHIB *schib = &sch->curr_status; 724 hwaddr curr_ccw = sch->channel_prog; 725 int path; 726 727 /* Path management: In our simple css, we always choose the only path. */ 728 path = 0x80; 729 730 /* We always 'attempt to issue the halt signal', and we always succeed. */ 731 sch->channel_prog = 0x0; 732 sch->last_cmd_valid = false; 733 schib->scsw.ctrl &= ~SCSW_ACTL_HALT_PEND; 734 schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND; 735 736 if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE | 737 SCSW_ACTL_DEVICE_ACTIVE)) || 738 !((schib->scsw.ctrl & SCSW_ACTL_START_PEND) || 739 (schib->scsw.ctrl & SCSW_ACTL_SUSP))) { 740 schib->scsw.dstat = SCSW_DSTAT_DEVICE_END; 741 } 742 if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE | 743 SCSW_ACTL_DEVICE_ACTIVE)) || 744 (schib->scsw.ctrl & SCSW_ACTL_SUSP)) { 745 schib->scsw.cpa = curr_ccw + 8; 746 } 747 schib->scsw.cstat = 0; 748 schib->pmcw.lpum = path; 749 750 } 751 752 /* 753 * As the SenseId struct cannot be packed (would cause unaligned accesses), we 754 * have to copy the individual fields to an unstructured area using the correct 755 * layout (see SA22-7204-01 "Common I/O-Device Commands"). 756 */ 757 static void copy_sense_id_to_guest(uint8_t *dest, SenseId *src) 758 { 759 int i; 760 761 dest[0] = src->reserved; 762 stw_be_p(dest + 1, src->cu_type); 763 dest[3] = src->cu_model; 764 stw_be_p(dest + 4, src->dev_type); 765 dest[6] = src->dev_model; 766 dest[7] = src->unused; 767 for (i = 0; i < ARRAY_SIZE(src->ciw); i++) { 768 dest[8 + i * 4] = src->ciw[i].type; 769 dest[9 + i * 4] = src->ciw[i].command; 770 stw_be_p(dest + 10 + i * 4, src->ciw[i].count); 771 } 772 } 773 774 static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1) 775 { 776 CCW0 tmp0; 777 CCW1 tmp1; 778 CCW1 ret; 779 780 if (fmt1) { 781 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1)); 782 ret.cmd_code = tmp1.cmd_code; 783 ret.flags = tmp1.flags; 784 ret.count = be16_to_cpu(tmp1.count); 785 ret.cda = be32_to_cpu(tmp1.cda); 786 } else { 787 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0)); 788 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) { 789 ret.cmd_code = CCW_CMD_TIC; 790 ret.flags = 0; 791 ret.count = 0; 792 } else { 793 ret.cmd_code = tmp0.cmd_code; 794 ret.flags = tmp0.flags; 795 ret.count = be16_to_cpu(tmp0.count); 796 } 797 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16); 798 } 799 return ret; 800 } 801 /** 802 * If out of bounds marks the stream broken. If broken returns -EINVAL, 803 * otherwise the requested length (may be zero) 804 */ 805 static inline int cds_check_len(CcwDataStream *cds, int len) 806 { 807 if (cds->at_byte + len > cds->count) { 808 cds->flags |= CDS_F_STREAM_BROKEN; 809 } 810 return cds->flags & CDS_F_STREAM_BROKEN ? -EINVAL : len; 811 } 812 813 static inline bool cds_ccw_addrs_ok(hwaddr addr, int len, bool ccw_fmt1) 814 { 815 return (addr + len) < (ccw_fmt1 ? (1UL << 31) : (1UL << 24)); 816 } 817 818 static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len, 819 CcwDataStreamOp op) 820 { 821 int ret; 822 823 ret = cds_check_len(cds, len); 824 if (ret <= 0) { 825 return ret; 826 } 827 if (!cds_ccw_addrs_ok(cds->cda, len, cds->flags & CDS_F_FMT)) { 828 return -EINVAL; /* channel program check */ 829 } 830 if (op == CDS_OP_A) { 831 goto incr; 832 } 833 if (!cds->do_skip) { 834 ret = address_space_rw(&address_space_memory, cds->cda, 835 MEMTXATTRS_UNSPECIFIED, buff, len, op); 836 } else { 837 ret = MEMTX_OK; 838 } 839 if (ret != MEMTX_OK) { 840 cds->flags |= CDS_F_STREAM_BROKEN; 841 return -EINVAL; 842 } 843 incr: 844 cds->at_byte += len; 845 cds->cda += len; 846 return 0; 847 } 848 849 /* returns values between 1 and bsz, where bsz is a power of 2 */ 850 static inline uint16_t ida_continuous_left(hwaddr cda, uint64_t bsz) 851 { 852 return bsz - (cda & (bsz - 1)); 853 } 854 855 static inline uint64_t ccw_ida_block_size(uint8_t flags) 856 { 857 if ((flags & CDS_F_C64) && !(flags & CDS_F_I2K)) { 858 return 1ULL << 12; 859 } 860 return 1ULL << 11; 861 } 862 863 static inline int ida_read_next_idaw(CcwDataStream *cds) 864 { 865 union {uint64_t fmt2; uint32_t fmt1; } idaw; 866 int ret; 867 hwaddr idaw_addr; 868 bool idaw_fmt2 = cds->flags & CDS_F_C64; 869 bool ccw_fmt1 = cds->flags & CDS_F_FMT; 870 871 if (idaw_fmt2) { 872 idaw_addr = cds->cda_orig + sizeof(idaw.fmt2) * cds->at_idaw; 873 if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { 874 return -EINVAL; /* channel program check */ 875 } 876 ret = address_space_read(&address_space_memory, idaw_addr, 877 MEMTXATTRS_UNSPECIFIED, &idaw.fmt2, 878 sizeof(idaw.fmt2)); 879 cds->cda = be64_to_cpu(idaw.fmt2); 880 } else { 881 idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw; 882 if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { 883 return -EINVAL; /* channel program check */ 884 } 885 ret = address_space_read(&address_space_memory, idaw_addr, 886 MEMTXATTRS_UNSPECIFIED, &idaw.fmt1, 887 sizeof(idaw.fmt1)); 888 cds->cda = be64_to_cpu(idaw.fmt1); 889 if (cds->cda & 0x80000000) { 890 return -EINVAL; /* channel program check */ 891 } 892 } 893 ++(cds->at_idaw); 894 if (ret != MEMTX_OK) { 895 /* assume inaccessible address */ 896 return -EINVAL; /* channel program check */ 897 } 898 return 0; 899 } 900 901 static int ccw_dstream_rw_ida(CcwDataStream *cds, void *buff, int len, 902 CcwDataStreamOp op) 903 { 904 uint64_t bsz = ccw_ida_block_size(cds->flags); 905 int ret = 0; 906 uint16_t cont_left, iter_len; 907 908 ret = cds_check_len(cds, len); 909 if (ret <= 0) { 910 return ret; 911 } 912 if (!cds->at_idaw) { 913 /* read first idaw */ 914 ret = ida_read_next_idaw(cds); 915 if (ret) { 916 goto err; 917 } 918 cont_left = ida_continuous_left(cds->cda, bsz); 919 } else { 920 cont_left = ida_continuous_left(cds->cda, bsz); 921 if (cont_left == bsz) { 922 ret = ida_read_next_idaw(cds); 923 if (ret) { 924 goto err; 925 } 926 if (cds->cda & (bsz - 1)) { 927 ret = -EINVAL; /* channel program check */ 928 goto err; 929 } 930 } 931 } 932 do { 933 iter_len = MIN(len, cont_left); 934 if (op != CDS_OP_A) { 935 if (!cds->do_skip) { 936 ret = address_space_rw(&address_space_memory, cds->cda, 937 MEMTXATTRS_UNSPECIFIED, buff, iter_len, 938 op); 939 } else { 940 ret = MEMTX_OK; 941 } 942 if (ret != MEMTX_OK) { 943 /* assume inaccessible address */ 944 ret = -EINVAL; /* channel program check */ 945 goto err; 946 } 947 } 948 cds->at_byte += iter_len; 949 cds->cda += iter_len; 950 len -= iter_len; 951 if (!len) { 952 break; 953 } 954 ret = ida_read_next_idaw(cds); 955 if (ret) { 956 goto err; 957 } 958 cont_left = bsz; 959 } while (true); 960 return ret; 961 err: 962 cds->flags |= CDS_F_STREAM_BROKEN; 963 return ret; 964 } 965 966 void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb) 967 { 968 /* 969 * We don't support MIDA (an optional facility) yet and we 970 * catch this earlier. Just for expressing the precondition. 971 */ 972 g_assert(!(orb->ctrl1 & ORB_CTRL1_MASK_MIDAW)); 973 cds->flags = (orb->ctrl0 & ORB_CTRL0_MASK_I2K ? CDS_F_I2K : 0) | 974 (orb->ctrl0 & ORB_CTRL0_MASK_C64 ? CDS_F_C64 : 0) | 975 (orb->ctrl0 & ORB_CTRL0_MASK_FMT ? CDS_F_FMT : 0) | 976 (ccw->flags & CCW_FLAG_IDA ? CDS_F_IDA : 0); 977 978 cds->count = ccw->count; 979 cds->cda_orig = ccw->cda; 980 /* skip is only effective for read, read backwards, or sense commands */ 981 cds->do_skip = (ccw->flags & CCW_FLAG_SKIP) && 982 ((ccw->cmd_code & 0x0f) == CCW_CMD_BASIC_SENSE || 983 (ccw->cmd_code & 0x03) == 0x02 /* read */ || 984 (ccw->cmd_code & 0x0f) == 0x0c /* read backwards */); 985 ccw_dstream_rewind(cds); 986 if (!(cds->flags & CDS_F_IDA)) { 987 cds->op_handler = ccw_dstream_rw_noflags; 988 } else { 989 cds->op_handler = ccw_dstream_rw_ida; 990 } 991 } 992 993 static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr, 994 bool suspend_allowed) 995 { 996 int ret; 997 bool check_len; 998 int len; 999 CCW1 ccw; 1000 1001 if (!ccw_addr) { 1002 return -EINVAL; /* channel-program check */ 1003 } 1004 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */ 1005 if (ccw_addr & (sch->ccw_fmt_1 ? 0x80000007 : 0xff000007)) { 1006 return -EINVAL; 1007 } 1008 1009 /* Translate everything to format-1 ccws - the information is the same. */ 1010 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1); 1011 1012 /* Check for invalid command codes. */ 1013 if ((ccw.cmd_code & 0x0f) == 0) { 1014 return -EINVAL; 1015 } 1016 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) && 1017 ((ccw.cmd_code & 0xf0) != 0)) { 1018 return -EINVAL; 1019 } 1020 if (!sch->ccw_fmt_1 && (ccw.count == 0) && 1021 (ccw.cmd_code != CCW_CMD_TIC)) { 1022 return -EINVAL; 1023 } 1024 1025 /* We don't support MIDA. */ 1026 if (ccw.flags & CCW_FLAG_MIDA) { 1027 return -EINVAL; 1028 } 1029 1030 if (ccw.flags & CCW_FLAG_SUSPEND) { 1031 return suspend_allowed ? -EINPROGRESS : -EINVAL; 1032 } 1033 1034 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC)); 1035 1036 if (!ccw.cda) { 1037 if (sch->ccw_no_data_cnt == 255) { 1038 return -EINVAL; 1039 } 1040 sch->ccw_no_data_cnt++; 1041 } 1042 1043 /* Look at the command. */ 1044 ccw_dstream_init(&sch->cds, &ccw, &(sch->orb)); 1045 switch (ccw.cmd_code) { 1046 case CCW_CMD_NOOP: 1047 /* Nothing to do. */ 1048 ret = 0; 1049 break; 1050 case CCW_CMD_BASIC_SENSE: 1051 if (check_len) { 1052 if (ccw.count != sizeof(sch->sense_data)) { 1053 ret = -EINVAL; 1054 break; 1055 } 1056 } 1057 len = MIN(ccw.count, sizeof(sch->sense_data)); 1058 ret = ccw_dstream_write_buf(&sch->cds, sch->sense_data, len); 1059 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds); 1060 if (!ret) { 1061 memset(sch->sense_data, 0, sizeof(sch->sense_data)); 1062 } 1063 break; 1064 case CCW_CMD_SENSE_ID: 1065 { 1066 /* According to SA22-7204-01, Sense-ID can store up to 256 bytes */ 1067 uint8_t sense_id[256]; 1068 1069 copy_sense_id_to_guest(sense_id, &sch->id); 1070 /* Sense ID information is device specific. */ 1071 if (check_len) { 1072 if (ccw.count != sizeof(sense_id)) { 1073 ret = -EINVAL; 1074 break; 1075 } 1076 } 1077 len = MIN(ccw.count, sizeof(sense_id)); 1078 /* 1079 * Only indicate 0xff in the first sense byte if we actually 1080 * have enough place to store at least bytes 0-3. 1081 */ 1082 if (len >= 4) { 1083 sense_id[0] = 0xff; 1084 } else { 1085 sense_id[0] = 0; 1086 } 1087 ret = ccw_dstream_write_buf(&sch->cds, sense_id, len); 1088 if (!ret) { 1089 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds); 1090 } 1091 break; 1092 } 1093 case CCW_CMD_TIC: 1094 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) { 1095 ret = -EINVAL; 1096 break; 1097 } 1098 if (ccw.flags || ccw.count) { 1099 /* We have already sanitized these if converted from fmt 0. */ 1100 ret = -EINVAL; 1101 break; 1102 } 1103 sch->channel_prog = ccw.cda; 1104 ret = -EAGAIN; 1105 break; 1106 default: 1107 if (sch->ccw_cb) { 1108 /* Handle device specific commands. */ 1109 ret = sch->ccw_cb(sch, ccw); 1110 } else { 1111 ret = -ENOSYS; 1112 } 1113 break; 1114 } 1115 sch->last_cmd = ccw; 1116 sch->last_cmd_valid = true; 1117 if (ret == 0) { 1118 if (ccw.flags & CCW_FLAG_CC) { 1119 sch->channel_prog += 8; 1120 ret = -EAGAIN; 1121 } 1122 } 1123 1124 return ret; 1125 } 1126 1127 static void sch_handle_start_func_virtual(SubchDev *sch) 1128 { 1129 SCHIB *schib = &sch->curr_status; 1130 int path; 1131 int ret; 1132 bool suspend_allowed; 1133 1134 /* Path management: In our simple css, we always choose the only path. */ 1135 path = 0x80; 1136 1137 if (!(schib->scsw.ctrl & SCSW_ACTL_SUSP)) { 1138 /* Start Function triggered via ssch, i.e. we have an ORB */ 1139 ORB *orb = &sch->orb; 1140 schib->scsw.cstat = 0; 1141 schib->scsw.dstat = 0; 1142 /* Look at the orb and try to execute the channel program. */ 1143 schib->pmcw.intparm = orb->intparm; 1144 if (!(orb->lpm & path)) { 1145 /* Generate a deferred cc 3 condition. */ 1146 schib->scsw.flags |= SCSW_FLAGS_MASK_CC; 1147 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1148 schib->scsw.ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND); 1149 return; 1150 } 1151 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT); 1152 schib->scsw.flags |= (sch->ccw_fmt_1) ? SCSW_FLAGS_MASK_FMT : 0; 1153 sch->ccw_no_data_cnt = 0; 1154 suspend_allowed = !!(orb->ctrl0 & ORB_CTRL0_MASK_SPND); 1155 } else { 1156 /* Start Function resumed via rsch */ 1157 schib->scsw.ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND); 1158 /* The channel program had been suspended before. */ 1159 suspend_allowed = true; 1160 } 1161 sch->last_cmd_valid = false; 1162 do { 1163 ret = css_interpret_ccw(sch, sch->channel_prog, suspend_allowed); 1164 switch (ret) { 1165 case -EAGAIN: 1166 /* ccw chain, continue processing */ 1167 break; 1168 case 0: 1169 /* success */ 1170 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1171 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1172 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1173 SCSW_STCTL_STATUS_PEND; 1174 schib->scsw.dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END; 1175 schib->scsw.cpa = sch->channel_prog + 8; 1176 break; 1177 case -EIO: 1178 /* I/O errors, status depends on specific devices */ 1179 break; 1180 case -ENOSYS: 1181 /* unsupported command, generate unit check (command reject) */ 1182 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1183 schib->scsw.dstat = SCSW_DSTAT_UNIT_CHECK; 1184 /* Set sense bit 0 in ecw0. */ 1185 sch->sense_data[0] = 0x80; 1186 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1187 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1188 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 1189 schib->scsw.cpa = sch->channel_prog + 8; 1190 break; 1191 case -EINPROGRESS: 1192 /* channel program has been suspended */ 1193 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1194 schib->scsw.ctrl |= SCSW_ACTL_SUSP; 1195 break; 1196 default: 1197 /* error, generate channel program check */ 1198 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1199 schib->scsw.cstat = SCSW_CSTAT_PROG_CHECK; 1200 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1201 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1202 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 1203 schib->scsw.cpa = sch->channel_prog + 8; 1204 break; 1205 } 1206 } while (ret == -EAGAIN); 1207 1208 } 1209 1210 static void sch_handle_halt_func_passthrough(SubchDev *sch) 1211 { 1212 int ret; 1213 1214 ret = s390_ccw_halt(sch); 1215 if (ret == -ENOSYS) { 1216 sch_handle_halt_func(sch); 1217 } 1218 } 1219 1220 static void sch_handle_clear_func_passthrough(SubchDev *sch) 1221 { 1222 int ret; 1223 1224 ret = s390_ccw_clear(sch); 1225 if (ret == -ENOSYS) { 1226 sch_handle_clear_func(sch); 1227 } 1228 } 1229 1230 static IOInstEnding sch_handle_start_func_passthrough(SubchDev *sch) 1231 { 1232 SCHIB *schib = &sch->curr_status; 1233 ORB *orb = &sch->orb; 1234 if (!(schib->scsw.ctrl & SCSW_ACTL_SUSP)) { 1235 assert(orb != NULL); 1236 schib->pmcw.intparm = orb->intparm; 1237 } 1238 return s390_ccw_cmd_request(sch); 1239 } 1240 1241 /* 1242 * On real machines, this would run asynchronously to the main vcpus. 1243 * We might want to make some parts of the ssch handling (interpreting 1244 * read/writes) asynchronous later on if we start supporting more than 1245 * our current very simple devices. 1246 */ 1247 IOInstEnding do_subchannel_work_virtual(SubchDev *sch) 1248 { 1249 SCHIB *schib = &sch->curr_status; 1250 1251 if (schib->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) { 1252 sch_handle_clear_func(sch); 1253 } else if (schib->scsw.ctrl & SCSW_FCTL_HALT_FUNC) { 1254 sch_handle_halt_func(sch); 1255 } else if (schib->scsw.ctrl & SCSW_FCTL_START_FUNC) { 1256 /* Triggered by both ssch and rsch. */ 1257 sch_handle_start_func_virtual(sch); 1258 } 1259 css_inject_io_interrupt(sch); 1260 /* inst must succeed if this func is called */ 1261 return IOINST_CC_EXPECTED; 1262 } 1263 1264 IOInstEnding do_subchannel_work_passthrough(SubchDev *sch) 1265 { 1266 SCHIB *schib = &sch->curr_status; 1267 1268 if (schib->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) { 1269 sch_handle_clear_func_passthrough(sch); 1270 } else if (schib->scsw.ctrl & SCSW_FCTL_HALT_FUNC) { 1271 sch_handle_halt_func_passthrough(sch); 1272 } else if (schib->scsw.ctrl & SCSW_FCTL_START_FUNC) { 1273 return sch_handle_start_func_passthrough(sch); 1274 } 1275 return IOINST_CC_EXPECTED; 1276 } 1277 1278 static IOInstEnding do_subchannel_work(SubchDev *sch) 1279 { 1280 if (!sch->do_subchannel_work) { 1281 return IOINST_CC_STATUS_PRESENT; 1282 } 1283 g_assert(sch->curr_status.scsw.ctrl & SCSW_CTRL_MASK_FCTL); 1284 return sch->do_subchannel_work(sch); 1285 } 1286 1287 static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src) 1288 { 1289 int i; 1290 1291 dest->intparm = cpu_to_be32(src->intparm); 1292 dest->flags = cpu_to_be16(src->flags); 1293 dest->devno = cpu_to_be16(src->devno); 1294 dest->lpm = src->lpm; 1295 dest->pnom = src->pnom; 1296 dest->lpum = src->lpum; 1297 dest->pim = src->pim; 1298 dest->mbi = cpu_to_be16(src->mbi); 1299 dest->pom = src->pom; 1300 dest->pam = src->pam; 1301 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 1302 dest->chpid[i] = src->chpid[i]; 1303 } 1304 dest->chars = cpu_to_be32(src->chars); 1305 } 1306 1307 void copy_scsw_to_guest(SCSW *dest, const SCSW *src) 1308 { 1309 dest->flags = cpu_to_be16(src->flags); 1310 dest->ctrl = cpu_to_be16(src->ctrl); 1311 dest->cpa = cpu_to_be32(src->cpa); 1312 dest->dstat = src->dstat; 1313 dest->cstat = src->cstat; 1314 dest->count = cpu_to_be16(src->count); 1315 } 1316 1317 static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src) 1318 { 1319 int i; 1320 /* 1321 * We copy the PMCW and SCSW in and out of local variables to 1322 * avoid taking the address of members of a packed struct. 1323 */ 1324 PMCW src_pmcw, dest_pmcw; 1325 SCSW src_scsw, dest_scsw; 1326 1327 src_pmcw = src->pmcw; 1328 copy_pmcw_to_guest(&dest_pmcw, &src_pmcw); 1329 dest->pmcw = dest_pmcw; 1330 src_scsw = src->scsw; 1331 copy_scsw_to_guest(&dest_scsw, &src_scsw); 1332 dest->scsw = dest_scsw; 1333 dest->mba = cpu_to_be64(src->mba); 1334 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 1335 dest->mda[i] = src->mda[i]; 1336 } 1337 } 1338 1339 IOInstEnding css_do_stsch(SubchDev *sch, SCHIB *schib) 1340 { 1341 int ret; 1342 1343 /* 1344 * For some subchannels, we may want to update parts of 1345 * the schib (e.g., update path masks from the host device 1346 * for passthrough subchannels). 1347 */ 1348 ret = s390_ccw_store(sch); 1349 1350 /* Use current status. */ 1351 copy_schib_to_guest(schib, &sch->curr_status); 1352 return ret; 1353 } 1354 1355 static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src) 1356 { 1357 int i; 1358 1359 dest->intparm = be32_to_cpu(src->intparm); 1360 dest->flags = be16_to_cpu(src->flags); 1361 dest->devno = be16_to_cpu(src->devno); 1362 dest->lpm = src->lpm; 1363 dest->pnom = src->pnom; 1364 dest->lpum = src->lpum; 1365 dest->pim = src->pim; 1366 dest->mbi = be16_to_cpu(src->mbi); 1367 dest->pom = src->pom; 1368 dest->pam = src->pam; 1369 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 1370 dest->chpid[i] = src->chpid[i]; 1371 } 1372 dest->chars = be32_to_cpu(src->chars); 1373 } 1374 1375 static void copy_scsw_from_guest(SCSW *dest, const SCSW *src) 1376 { 1377 dest->flags = be16_to_cpu(src->flags); 1378 dest->ctrl = be16_to_cpu(src->ctrl); 1379 dest->cpa = be32_to_cpu(src->cpa); 1380 dest->dstat = src->dstat; 1381 dest->cstat = src->cstat; 1382 dest->count = be16_to_cpu(src->count); 1383 } 1384 1385 static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src) 1386 { 1387 int i; 1388 /* 1389 * We copy the PMCW and SCSW in and out of local variables to 1390 * avoid taking the address of members of a packed struct. 1391 */ 1392 PMCW src_pmcw, dest_pmcw; 1393 SCSW src_scsw, dest_scsw; 1394 1395 src_pmcw = src->pmcw; 1396 copy_pmcw_from_guest(&dest_pmcw, &src_pmcw); 1397 dest->pmcw = dest_pmcw; 1398 src_scsw = src->scsw; 1399 copy_scsw_from_guest(&dest_scsw, &src_scsw); 1400 dest->scsw = dest_scsw; 1401 dest->mba = be64_to_cpu(src->mba); 1402 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 1403 dest->mda[i] = src->mda[i]; 1404 } 1405 } 1406 1407 IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *orig_schib) 1408 { 1409 SCHIB *schib = &sch->curr_status; 1410 uint16_t oldflags; 1411 SCHIB schib_copy; 1412 1413 if (!(schib->pmcw.flags & PMCW_FLAGS_MASK_DNV)) { 1414 return IOINST_CC_EXPECTED; 1415 } 1416 1417 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) { 1418 return IOINST_CC_STATUS_PRESENT; 1419 } 1420 1421 if (schib->scsw.ctrl & 1422 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) { 1423 return IOINST_CC_BUSY; 1424 } 1425 1426 copy_schib_from_guest(&schib_copy, orig_schib); 1427 /* Only update the program-modifiable fields. */ 1428 schib->pmcw.intparm = schib_copy.pmcw.intparm; 1429 oldflags = schib->pmcw.flags; 1430 schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1431 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1432 PMCW_FLAGS_MASK_MP); 1433 schib->pmcw.flags |= schib_copy.pmcw.flags & 1434 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1435 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1436 PMCW_FLAGS_MASK_MP); 1437 schib->pmcw.lpm = schib_copy.pmcw.lpm; 1438 schib->pmcw.mbi = schib_copy.pmcw.mbi; 1439 schib->pmcw.pom = schib_copy.pmcw.pom; 1440 schib->pmcw.chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 1441 schib->pmcw.chars |= schib_copy.pmcw.chars & 1442 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 1443 schib->mba = schib_copy.mba; 1444 1445 /* Has the channel been disabled? */ 1446 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0 1447 && (schib->pmcw.flags & PMCW_FLAGS_MASK_ENA) == 0) { 1448 sch->disable_cb(sch); 1449 } 1450 return IOINST_CC_EXPECTED; 1451 } 1452 1453 IOInstEnding css_do_xsch(SubchDev *sch) 1454 { 1455 SCHIB *schib = &sch->curr_status; 1456 1457 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1458 return IOINST_CC_NOT_OPERATIONAL; 1459 } 1460 1461 if (schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) { 1462 return IOINST_CC_STATUS_PRESENT; 1463 } 1464 1465 if (!(schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) || 1466 ((schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1467 (!(schib->scsw.ctrl & 1468 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) || 1469 (schib->scsw.ctrl & SCSW_ACTL_SUBCH_ACTIVE)) { 1470 return IOINST_CC_BUSY; 1471 } 1472 1473 /* Cancel the current operation. */ 1474 schib->scsw.ctrl &= ~(SCSW_FCTL_START_FUNC | 1475 SCSW_ACTL_RESUME_PEND | 1476 SCSW_ACTL_START_PEND | 1477 SCSW_ACTL_SUSP); 1478 sch->channel_prog = 0x0; 1479 sch->last_cmd_valid = false; 1480 schib->scsw.dstat = 0; 1481 schib->scsw.cstat = 0; 1482 return IOINST_CC_EXPECTED; 1483 } 1484 1485 IOInstEnding css_do_csch(SubchDev *sch) 1486 { 1487 SCHIB *schib = &sch->curr_status; 1488 1489 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1490 return IOINST_CC_NOT_OPERATIONAL; 1491 } 1492 1493 /* Trigger the clear function. */ 1494 schib->scsw.ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL); 1495 schib->scsw.ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND; 1496 1497 return do_subchannel_work(sch); 1498 } 1499 1500 IOInstEnding css_do_hsch(SubchDev *sch) 1501 { 1502 SCHIB *schib = &sch->curr_status; 1503 1504 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1505 return IOINST_CC_NOT_OPERATIONAL; 1506 } 1507 1508 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) || 1509 (schib->scsw.ctrl & (SCSW_STCTL_PRIMARY | 1510 SCSW_STCTL_SECONDARY | 1511 SCSW_STCTL_ALERT))) { 1512 return IOINST_CC_STATUS_PRESENT; 1513 } 1514 1515 if (schib->scsw.ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) { 1516 return IOINST_CC_BUSY; 1517 } 1518 1519 /* Trigger the halt function. */ 1520 schib->scsw.ctrl |= SCSW_FCTL_HALT_FUNC; 1521 schib->scsw.ctrl &= ~SCSW_FCTL_START_FUNC; 1522 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_ACTL) == 1523 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) && 1524 ((schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) == 1525 SCSW_STCTL_INTERMEDIATE)) { 1526 schib->scsw.ctrl &= ~SCSW_STCTL_STATUS_PEND; 1527 } 1528 schib->scsw.ctrl |= SCSW_ACTL_HALT_PEND; 1529 1530 return do_subchannel_work(sch); 1531 } 1532 1533 static void css_update_chnmon(SubchDev *sch) 1534 { 1535 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) { 1536 /* Not active. */ 1537 return; 1538 } 1539 /* The counter is conveniently located at the beginning of the struct. */ 1540 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) { 1541 /* Format 1, per-subchannel area. */ 1542 uint32_t count; 1543 1544 count = address_space_ldl(&address_space_memory, 1545 sch->curr_status.mba, 1546 MEMTXATTRS_UNSPECIFIED, 1547 NULL); 1548 count++; 1549 address_space_stl(&address_space_memory, sch->curr_status.mba, count, 1550 MEMTXATTRS_UNSPECIFIED, NULL); 1551 } else { 1552 /* Format 0, global area. */ 1553 uint32_t offset; 1554 uint16_t count; 1555 1556 offset = sch->curr_status.pmcw.mbi << 5; 1557 count = address_space_lduw(&address_space_memory, 1558 channel_subsys.chnmon_area + offset, 1559 MEMTXATTRS_UNSPECIFIED, 1560 NULL); 1561 count++; 1562 address_space_stw(&address_space_memory, 1563 channel_subsys.chnmon_area + offset, count, 1564 MEMTXATTRS_UNSPECIFIED, NULL); 1565 } 1566 } 1567 1568 IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb) 1569 { 1570 SCHIB *schib = &sch->curr_status; 1571 1572 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1573 return IOINST_CC_NOT_OPERATIONAL; 1574 } 1575 1576 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) { 1577 return IOINST_CC_STATUS_PRESENT; 1578 } 1579 1580 if (schib->scsw.ctrl & (SCSW_FCTL_START_FUNC | 1581 SCSW_FCTL_HALT_FUNC | 1582 SCSW_FCTL_CLEAR_FUNC)) { 1583 return IOINST_CC_BUSY; 1584 } 1585 1586 /* If monitoring is active, update counter. */ 1587 if (channel_subsys.chnmon_active) { 1588 css_update_chnmon(sch); 1589 } 1590 sch->orb = *orb; 1591 sch->channel_prog = orb->cpa; 1592 /* Trigger the start function. */ 1593 schib->scsw.ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND); 1594 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 1595 1596 return do_subchannel_work(sch); 1597 } 1598 1599 static void copy_irb_to_guest(IRB *dest, const IRB *src, const PMCW *pmcw, 1600 int *irb_len) 1601 { 1602 int i; 1603 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1604 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 1605 1606 copy_scsw_to_guest(&dest->scsw, &src->scsw); 1607 1608 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) { 1609 dest->esw[i] = cpu_to_be32(src->esw[i]); 1610 } 1611 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) { 1612 dest->ecw[i] = cpu_to_be32(src->ecw[i]); 1613 } 1614 *irb_len = sizeof(*dest) - sizeof(dest->emw); 1615 1616 /* extended measurements enabled? */ 1617 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) || 1618 !(pmcw->flags & PMCW_FLAGS_MASK_TF) || 1619 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) { 1620 return; 1621 } 1622 /* extended measurements pending? */ 1623 if (!(stctl & SCSW_STCTL_STATUS_PEND)) { 1624 return; 1625 } 1626 if ((stctl & SCSW_STCTL_PRIMARY) || 1627 (stctl == SCSW_STCTL_SECONDARY) || 1628 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) { 1629 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) { 1630 dest->emw[i] = cpu_to_be32(src->emw[i]); 1631 } 1632 } 1633 *irb_len = sizeof(*dest); 1634 } 1635 1636 int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len) 1637 { 1638 SCHIB *schib = &sch->curr_status; 1639 PMCW p; 1640 uint16_t stctl; 1641 IRB irb; 1642 1643 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1644 return 3; 1645 } 1646 1647 stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1648 1649 /* Prepare the irb for the guest. */ 1650 memset(&irb, 0, sizeof(IRB)); 1651 1652 /* Copy scsw from current status. */ 1653 irb.scsw = schib->scsw; 1654 if (stctl & SCSW_STCTL_STATUS_PEND) { 1655 if (schib->scsw.cstat & (SCSW_CSTAT_DATA_CHECK | 1656 SCSW_CSTAT_CHN_CTRL_CHK | 1657 SCSW_CSTAT_INTF_CTRL_CHK)) { 1658 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF; 1659 irb.esw[0] = 0x04804000; 1660 } else { 1661 irb.esw[0] = 0x00800000; 1662 } 1663 /* If a unit check is pending, copy sense data. */ 1664 if ((schib->scsw.dstat & SCSW_DSTAT_UNIT_CHECK) && 1665 (schib->pmcw.chars & PMCW_CHARS_MASK_CSENSE)) { 1666 int i; 1667 1668 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL; 1669 /* Attention: sense_data is already BE! */ 1670 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data)); 1671 for (i = 0; i < ARRAY_SIZE(irb.ecw); i++) { 1672 irb.ecw[i] = be32_to_cpu(irb.ecw[i]); 1673 } 1674 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8); 1675 } 1676 } 1677 /* Store the irb to the guest. */ 1678 p = schib->pmcw; 1679 copy_irb_to_guest(target_irb, &irb, &p, irb_len); 1680 1681 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0); 1682 } 1683 1684 void css_do_tsch_update_subch(SubchDev *sch) 1685 { 1686 SCHIB *schib = &sch->curr_status; 1687 uint16_t stctl; 1688 uint16_t fctl; 1689 uint16_t actl; 1690 1691 stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1692 fctl = schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL; 1693 actl = schib->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 1694 1695 /* Clear conditions on subchannel, if applicable. */ 1696 if (stctl & SCSW_STCTL_STATUS_PEND) { 1697 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1698 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) || 1699 ((fctl & SCSW_FCTL_HALT_FUNC) && 1700 (actl & SCSW_ACTL_SUSP))) { 1701 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_FCTL; 1702 } 1703 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) { 1704 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 1705 schib->scsw.ctrl &= ~(SCSW_ACTL_RESUME_PEND | 1706 SCSW_ACTL_START_PEND | 1707 SCSW_ACTL_HALT_PEND | 1708 SCSW_ACTL_CLEAR_PEND | 1709 SCSW_ACTL_SUSP); 1710 } else { 1711 if ((actl & SCSW_ACTL_SUSP) && 1712 (fctl & SCSW_FCTL_START_FUNC)) { 1713 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 1714 if (fctl & SCSW_FCTL_HALT_FUNC) { 1715 schib->scsw.ctrl &= ~(SCSW_ACTL_RESUME_PEND | 1716 SCSW_ACTL_START_PEND | 1717 SCSW_ACTL_HALT_PEND | 1718 SCSW_ACTL_CLEAR_PEND | 1719 SCSW_ACTL_SUSP); 1720 } else { 1721 schib->scsw.ctrl &= ~SCSW_ACTL_RESUME_PEND; 1722 } 1723 } 1724 } 1725 /* Clear pending sense data. */ 1726 if (schib->pmcw.chars & PMCW_CHARS_MASK_CSENSE) { 1727 memset(sch->sense_data, 0 , sizeof(sch->sense_data)); 1728 } 1729 } 1730 } 1731 1732 static void copy_crw_to_guest(CRW *dest, const CRW *src) 1733 { 1734 dest->flags = cpu_to_be16(src->flags); 1735 dest->rsid = cpu_to_be16(src->rsid); 1736 } 1737 1738 int css_do_stcrw(CRW *crw) 1739 { 1740 CrwContainer *crw_cont; 1741 int ret; 1742 1743 crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws); 1744 if (crw_cont) { 1745 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling); 1746 copy_crw_to_guest(crw, &crw_cont->crw); 1747 g_free(crw_cont); 1748 ret = 0; 1749 } else { 1750 /* List was empty, turn crw machine checks on again. */ 1751 memset(crw, 0, sizeof(*crw)); 1752 channel_subsys.do_crw_mchk = true; 1753 ret = 1; 1754 } 1755 1756 return ret; 1757 } 1758 1759 static void copy_crw_from_guest(CRW *dest, const CRW *src) 1760 { 1761 dest->flags = be16_to_cpu(src->flags); 1762 dest->rsid = be16_to_cpu(src->rsid); 1763 } 1764 1765 void css_undo_stcrw(CRW *crw) 1766 { 1767 CrwContainer *crw_cont; 1768 1769 crw_cont = g_try_new0(CrwContainer, 1); 1770 if (!crw_cont) { 1771 channel_subsys.crws_lost = true; 1772 return; 1773 } 1774 copy_crw_from_guest(&crw_cont->crw, crw); 1775 1776 QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling); 1777 } 1778 1779 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, 1780 int rfmt, void *buf) 1781 { 1782 int i, desc_size; 1783 uint32_t words[8]; 1784 uint32_t chpid_type_word; 1785 CssImage *css; 1786 1787 if (!m && !cssid) { 1788 css = channel_subsys.css[channel_subsys.default_cssid]; 1789 } else { 1790 css = channel_subsys.css[cssid]; 1791 } 1792 if (!css) { 1793 return 0; 1794 } 1795 desc_size = 0; 1796 for (i = f_chpid; i <= l_chpid; i++) { 1797 if (css->chpids[i].in_use) { 1798 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i; 1799 if (rfmt == 0) { 1800 words[0] = cpu_to_be32(chpid_type_word); 1801 words[1] = 0; 1802 memcpy(buf + desc_size, words, 8); 1803 desc_size += 8; 1804 } else if (rfmt == 1) { 1805 words[0] = cpu_to_be32(chpid_type_word); 1806 words[1] = 0; 1807 words[2] = 0; 1808 words[3] = 0; 1809 words[4] = 0; 1810 words[5] = 0; 1811 words[6] = 0; 1812 words[7] = 0; 1813 memcpy(buf + desc_size, words, 32); 1814 desc_size += 32; 1815 } 1816 } 1817 } 1818 return desc_size; 1819 } 1820 1821 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo) 1822 { 1823 /* dct is currently ignored (not really meaningful for our devices) */ 1824 /* TODO: Don't ignore mbk. */ 1825 if (update && !channel_subsys.chnmon_active) { 1826 /* Enable measuring. */ 1827 channel_subsys.chnmon_area = mbo; 1828 channel_subsys.chnmon_active = true; 1829 } 1830 if (!update && channel_subsys.chnmon_active) { 1831 /* Disable measuring. */ 1832 channel_subsys.chnmon_area = 0; 1833 channel_subsys.chnmon_active = false; 1834 } 1835 } 1836 1837 IOInstEnding css_do_rsch(SubchDev *sch) 1838 { 1839 SCHIB *schib = &sch->curr_status; 1840 1841 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1842 return IOINST_CC_NOT_OPERATIONAL; 1843 } 1844 1845 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) { 1846 return IOINST_CC_STATUS_PRESENT; 1847 } 1848 1849 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1850 (schib->scsw.ctrl & SCSW_ACTL_RESUME_PEND) || 1851 (!(schib->scsw.ctrl & SCSW_ACTL_SUSP))) { 1852 return IOINST_CC_BUSY; 1853 } 1854 1855 /* If monitoring is active, update counter. */ 1856 if (channel_subsys.chnmon_active) { 1857 css_update_chnmon(sch); 1858 } 1859 1860 schib->scsw.ctrl |= SCSW_ACTL_RESUME_PEND; 1861 return do_subchannel_work(sch); 1862 } 1863 1864 int css_do_rchp(uint8_t cssid, uint8_t chpid) 1865 { 1866 uint8_t real_cssid; 1867 1868 if (cssid > channel_subsys.max_cssid) { 1869 return -EINVAL; 1870 } 1871 if (channel_subsys.max_cssid == 0) { 1872 real_cssid = channel_subsys.default_cssid; 1873 } else { 1874 real_cssid = cssid; 1875 } 1876 if (!channel_subsys.css[real_cssid]) { 1877 return -EINVAL; 1878 } 1879 1880 if (!channel_subsys.css[real_cssid]->chpids[chpid].in_use) { 1881 return -ENODEV; 1882 } 1883 1884 if (!channel_subsys.css[real_cssid]->chpids[chpid].is_virtual) { 1885 fprintf(stderr, 1886 "rchp unsupported for non-virtual chpid %x.%02x!\n", 1887 real_cssid, chpid); 1888 return -ENODEV; 1889 } 1890 1891 /* We don't really use a channel path, so we're done here. */ 1892 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 1893 channel_subsys.max_cssid > 0 ? 1 : 0, chpid); 1894 if (channel_subsys.max_cssid > 0) { 1895 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 0, real_cssid << 8); 1896 } 1897 return 0; 1898 } 1899 1900 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1901 { 1902 SubchSet *set; 1903 uint8_t real_cssid; 1904 1905 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid; 1906 if (ssid > MAX_SSID || 1907 !channel_subsys.css[real_cssid] || 1908 !channel_subsys.css[real_cssid]->sch_set[ssid]) { 1909 return true; 1910 } 1911 set = channel_subsys.css[real_cssid]->sch_set[ssid]; 1912 return schid > find_last_bit(set->schids_used, 1913 (MAX_SCHID + 1) / sizeof(unsigned long)); 1914 } 1915 1916 unsigned int css_find_free_chpid(uint8_t cssid) 1917 { 1918 CssImage *css = channel_subsys.css[cssid]; 1919 unsigned int chpid; 1920 1921 if (!css) { 1922 return MAX_CHPID + 1; 1923 } 1924 1925 for (chpid = 0; chpid <= MAX_CHPID; chpid++) { 1926 /* skip reserved chpid */ 1927 if (chpid == VIRTIO_CCW_CHPID) { 1928 continue; 1929 } 1930 if (!css->chpids[chpid].in_use) { 1931 return chpid; 1932 } 1933 } 1934 return MAX_CHPID + 1; 1935 } 1936 1937 static int css_add_chpid(uint8_t cssid, uint8_t chpid, uint8_t type, 1938 bool is_virt) 1939 { 1940 CssImage *css; 1941 1942 trace_css_chpid_add(cssid, chpid, type); 1943 css = channel_subsys.css[cssid]; 1944 if (!css) { 1945 return -EINVAL; 1946 } 1947 if (css->chpids[chpid].in_use) { 1948 return -EEXIST; 1949 } 1950 css->chpids[chpid].in_use = 1; 1951 css->chpids[chpid].type = type; 1952 css->chpids[chpid].is_virtual = is_virt; 1953 1954 css_generate_chp_crws(cssid, chpid); 1955 1956 return 0; 1957 } 1958 1959 void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type) 1960 { 1961 SCHIB *schib = &sch->curr_status; 1962 int i; 1963 CssImage *css = channel_subsys.css[sch->cssid]; 1964 1965 assert(css != NULL); 1966 memset(&schib->pmcw, 0, sizeof(PMCW)); 1967 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV; 1968 schib->pmcw.devno = sch->devno; 1969 /* single path */ 1970 schib->pmcw.pim = 0x80; 1971 schib->pmcw.pom = 0xff; 1972 schib->pmcw.pam = 0x80; 1973 schib->pmcw.chpid[0] = chpid; 1974 if (!css->chpids[chpid].in_use) { 1975 css_add_chpid(sch->cssid, chpid, type, true); 1976 } 1977 1978 memset(&schib->scsw, 0, sizeof(SCSW)); 1979 schib->mba = 0; 1980 for (i = 0; i < ARRAY_SIZE(schib->mda); i++) { 1981 schib->mda[i] = 0; 1982 } 1983 } 1984 1985 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1986 { 1987 uint8_t real_cssid; 1988 1989 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid; 1990 1991 if (!channel_subsys.css[real_cssid]) { 1992 return NULL; 1993 } 1994 1995 if (!channel_subsys.css[real_cssid]->sch_set[ssid]) { 1996 return NULL; 1997 } 1998 1999 return channel_subsys.css[real_cssid]->sch_set[ssid]->sch[schid]; 2000 } 2001 2002 /** 2003 * Return free device number in subchannel set. 2004 * 2005 * Return index of the first free device number in the subchannel set 2006 * identified by @p cssid and @p ssid, beginning the search at @p 2007 * start and wrapping around at MAX_DEVNO. Return a value exceeding 2008 * MAX_SCHID if there are no free device numbers in the subchannel 2009 * set. 2010 */ 2011 static uint32_t css_find_free_devno(uint8_t cssid, uint8_t ssid, 2012 uint16_t start) 2013 { 2014 uint32_t round; 2015 2016 for (round = 0; round <= MAX_DEVNO; round++) { 2017 uint16_t devno = (start + round) % MAX_DEVNO; 2018 2019 if (!css_devno_used(cssid, ssid, devno)) { 2020 return devno; 2021 } 2022 } 2023 return MAX_DEVNO + 1; 2024 } 2025 2026 /** 2027 * Return first free subchannel (id) in subchannel set. 2028 * 2029 * Return index of the first free subchannel in the subchannel set 2030 * identified by @p cssid and @p ssid, if there is any. Return a value 2031 * exceeding MAX_SCHID if there are no free subchannels in the 2032 * subchannel set. 2033 */ 2034 static uint32_t css_find_free_subch(uint8_t cssid, uint8_t ssid) 2035 { 2036 uint32_t schid; 2037 2038 for (schid = 0; schid <= MAX_SCHID; schid++) { 2039 if (!css_find_subch(1, cssid, ssid, schid)) { 2040 return schid; 2041 } 2042 } 2043 return MAX_SCHID + 1; 2044 } 2045 2046 /** 2047 * Return first free subchannel (id) in subchannel set for a device number 2048 * 2049 * Verify the device number @p devno is not used yet in the subchannel 2050 * set identified by @p cssid and @p ssid. Set @p schid to the index 2051 * of the first free subchannel in the subchannel set, if there is 2052 * any. Return true if everything succeeded and false otherwise. 2053 */ 2054 static bool css_find_free_subch_for_devno(uint8_t cssid, uint8_t ssid, 2055 uint16_t devno, uint16_t *schid, 2056 Error **errp) 2057 { 2058 uint32_t free_schid; 2059 2060 assert(schid); 2061 if (css_devno_used(cssid, ssid, devno)) { 2062 error_setg(errp, "Device %x.%x.%04x already exists", 2063 cssid, ssid, devno); 2064 return false; 2065 } 2066 free_schid = css_find_free_subch(cssid, ssid); 2067 if (free_schid > MAX_SCHID) { 2068 error_setg(errp, "No free subchannel found for %x.%x.%04x", 2069 cssid, ssid, devno); 2070 return false; 2071 } 2072 *schid = free_schid; 2073 return true; 2074 } 2075 2076 /** 2077 * Return first free subchannel (id) and device number 2078 * 2079 * Locate the first free subchannel and first free device number in 2080 * any of the subchannel sets of the channel subsystem identified by 2081 * @p cssid. Return false if no free subchannel / device number could 2082 * be found. Otherwise set @p ssid, @p devno and @p schid to identify 2083 * the available subchannel and device number and return true. 2084 * 2085 * May modify @p ssid, @p devno and / or @p schid even if no free 2086 * subchannel / device number could be found. 2087 */ 2088 static bool css_find_free_subch_and_devno(uint8_t cssid, uint8_t *ssid, 2089 uint16_t *devno, uint16_t *schid, 2090 Error **errp) 2091 { 2092 uint32_t free_schid, free_devno; 2093 2094 assert(ssid && devno && schid); 2095 for (*ssid = 0; *ssid <= MAX_SSID; (*ssid)++) { 2096 free_schid = css_find_free_subch(cssid, *ssid); 2097 if (free_schid > MAX_SCHID) { 2098 continue; 2099 } 2100 free_devno = css_find_free_devno(cssid, *ssid, free_schid); 2101 if (free_devno > MAX_DEVNO) { 2102 continue; 2103 } 2104 *schid = free_schid; 2105 *devno = free_devno; 2106 return true; 2107 } 2108 error_setg(errp, "Virtual channel subsystem is full!"); 2109 return false; 2110 } 2111 2112 bool css_subch_visible(SubchDev *sch) 2113 { 2114 if (sch->ssid > channel_subsys.max_ssid) { 2115 return false; 2116 } 2117 2118 if (sch->cssid != channel_subsys.default_cssid) { 2119 return (channel_subsys.max_cssid > 0); 2120 } 2121 2122 return true; 2123 } 2124 2125 bool css_present(uint8_t cssid) 2126 { 2127 return (channel_subsys.css[cssid] != NULL); 2128 } 2129 2130 bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno) 2131 { 2132 if (!channel_subsys.css[cssid]) { 2133 return false; 2134 } 2135 if (!channel_subsys.css[cssid]->sch_set[ssid]) { 2136 return false; 2137 } 2138 2139 return !!test_bit(devno, 2140 channel_subsys.css[cssid]->sch_set[ssid]->devnos_used); 2141 } 2142 2143 void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid, 2144 uint16_t devno, SubchDev *sch) 2145 { 2146 CssImage *css; 2147 SubchSet *s_set; 2148 2149 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid, 2150 devno); 2151 if (!channel_subsys.css[cssid]) { 2152 fprintf(stderr, 2153 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n", 2154 __func__, cssid, ssid, schid); 2155 return; 2156 } 2157 css = channel_subsys.css[cssid]; 2158 2159 if (!css->sch_set[ssid]) { 2160 css->sch_set[ssid] = g_new0(SubchSet, 1); 2161 } 2162 s_set = css->sch_set[ssid]; 2163 2164 s_set->sch[schid] = sch; 2165 if (sch) { 2166 set_bit(schid, s_set->schids_used); 2167 set_bit(devno, s_set->devnos_used); 2168 } else { 2169 clear_bit(schid, s_set->schids_used); 2170 clear_bit(devno, s_set->devnos_used); 2171 } 2172 } 2173 2174 void css_crw_add_to_queue(CRW crw) 2175 { 2176 CrwContainer *crw_cont; 2177 2178 trace_css_crw((crw.flags & CRW_FLAGS_MASK_RSC) >> 8, 2179 crw.flags & CRW_FLAGS_MASK_ERC, 2180 crw.rsid, 2181 (crw.flags & CRW_FLAGS_MASK_C) ? "(chained)" : ""); 2182 2183 /* TODO: Maybe use a static crw pool? */ 2184 crw_cont = g_try_new0(CrwContainer, 1); 2185 if (!crw_cont) { 2186 channel_subsys.crws_lost = true; 2187 return; 2188 } 2189 2190 crw_cont->crw = crw; 2191 2192 QTAILQ_INSERT_TAIL(&channel_subsys.pending_crws, crw_cont, sibling); 2193 2194 if (channel_subsys.do_crw_mchk) { 2195 channel_subsys.do_crw_mchk = false; 2196 /* Inject crw pending machine check. */ 2197 s390_crw_mchk(); 2198 } 2199 } 2200 2201 void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited, 2202 int chain, uint16_t rsid) 2203 { 2204 CRW crw; 2205 2206 crw.flags = (rsc << 8) | erc; 2207 if (solicited) { 2208 crw.flags |= CRW_FLAGS_MASK_S; 2209 } 2210 if (chain) { 2211 crw.flags |= CRW_FLAGS_MASK_C; 2212 } 2213 crw.rsid = rsid; 2214 if (channel_subsys.crws_lost) { 2215 crw.flags |= CRW_FLAGS_MASK_R; 2216 channel_subsys.crws_lost = false; 2217 } 2218 2219 css_crw_add_to_queue(crw); 2220 } 2221 2222 void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid, 2223 int hotplugged, int add) 2224 { 2225 uint8_t guest_cssid; 2226 bool chain_crw; 2227 2228 if (add && !hotplugged) { 2229 return; 2230 } 2231 if (channel_subsys.max_cssid == 0) { 2232 /* Default cssid shows up as 0. */ 2233 guest_cssid = (cssid == channel_subsys.default_cssid) ? 0 : cssid; 2234 } else { 2235 /* Show real cssid to the guest. */ 2236 guest_cssid = cssid; 2237 } 2238 /* 2239 * Only notify for higher subchannel sets/channel subsystems if the 2240 * guest has enabled it. 2241 */ 2242 if ((ssid > channel_subsys.max_ssid) || 2243 (guest_cssid > channel_subsys.max_cssid) || 2244 ((channel_subsys.max_cssid == 0) && 2245 (cssid != channel_subsys.default_cssid))) { 2246 return; 2247 } 2248 chain_crw = (channel_subsys.max_ssid > 0) || 2249 (channel_subsys.max_cssid > 0); 2250 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, chain_crw ? 1 : 0, schid); 2251 if (chain_crw) { 2252 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 0, 2253 (guest_cssid << 8) | (ssid << 4)); 2254 } 2255 /* RW_ERC_IPI --> clear pending interrupts */ 2256 css_clear_io_interrupt(css_do_build_subchannel_id(cssid, ssid), schid); 2257 } 2258 2259 void css_generate_chp_crws(uint8_t cssid, uint8_t chpid) 2260 { 2261 /* TODO */ 2262 } 2263 2264 void css_generate_css_crws(uint8_t cssid) 2265 { 2266 if (!channel_subsys.sei_pending) { 2267 css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, 0, cssid); 2268 } 2269 channel_subsys.sei_pending = true; 2270 } 2271 2272 void css_clear_sei_pending(void) 2273 { 2274 channel_subsys.sei_pending = false; 2275 } 2276 2277 int css_enable_mcsse(void) 2278 { 2279 trace_css_enable_facility("mcsse"); 2280 channel_subsys.max_cssid = MAX_CSSID; 2281 return 0; 2282 } 2283 2284 int css_enable_mss(void) 2285 { 2286 trace_css_enable_facility("mss"); 2287 channel_subsys.max_ssid = MAX_SSID; 2288 return 0; 2289 } 2290 2291 void css_reset_sch(SubchDev *sch) 2292 { 2293 SCHIB *schib = &sch->curr_status; 2294 2295 if ((schib->pmcw.flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) { 2296 sch->disable_cb(sch); 2297 } 2298 2299 schib->pmcw.intparm = 0; 2300 schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 2301 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 2302 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF); 2303 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV; 2304 schib->pmcw.devno = sch->devno; 2305 schib->pmcw.pim = 0x80; 2306 schib->pmcw.lpm = schib->pmcw.pim; 2307 schib->pmcw.pnom = 0; 2308 schib->pmcw.lpum = 0; 2309 schib->pmcw.mbi = 0; 2310 schib->pmcw.pom = 0xff; 2311 schib->pmcw.pam = 0x80; 2312 schib->pmcw.chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME | 2313 PMCW_CHARS_MASK_CSENSE); 2314 2315 memset(&schib->scsw, 0, sizeof(schib->scsw)); 2316 schib->mba = 0; 2317 2318 sch->channel_prog = 0x0; 2319 sch->last_cmd_valid = false; 2320 sch->thinint_active = false; 2321 } 2322 2323 void css_reset(void) 2324 { 2325 CrwContainer *crw_cont; 2326 2327 /* Clean up monitoring. */ 2328 channel_subsys.chnmon_active = false; 2329 channel_subsys.chnmon_area = 0; 2330 2331 /* Clear pending CRWs. */ 2332 while ((crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws))) { 2333 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling); 2334 g_free(crw_cont); 2335 } 2336 channel_subsys.sei_pending = false; 2337 channel_subsys.do_crw_mchk = true; 2338 channel_subsys.crws_lost = false; 2339 2340 /* Reset maximum ids. */ 2341 channel_subsys.max_cssid = 0; 2342 channel_subsys.max_ssid = 0; 2343 } 2344 2345 static void get_css_devid(Object *obj, Visitor *v, const char *name, 2346 void *opaque, Error **errp) 2347 { 2348 Property *prop = opaque; 2349 CssDevId *dev_id = object_field_prop_ptr(obj, prop); 2350 char buffer[] = "xx.x.xxxx"; 2351 char *p = buffer; 2352 int r; 2353 2354 if (dev_id->valid) { 2355 2356 r = snprintf(buffer, sizeof(buffer), "%02x.%1x.%04x", dev_id->cssid, 2357 dev_id->ssid, dev_id->devid); 2358 assert(r == sizeof(buffer) - 1); 2359 2360 /* drop leading zero */ 2361 if (dev_id->cssid <= 0xf) { 2362 p++; 2363 } 2364 } else { 2365 snprintf(buffer, sizeof(buffer), "<unset>"); 2366 } 2367 2368 visit_type_str(v, name, &p, errp); 2369 } 2370 2371 /* 2372 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid 2373 */ 2374 static void set_css_devid(Object *obj, Visitor *v, const char *name, 2375 void *opaque, Error **errp) 2376 { 2377 Property *prop = opaque; 2378 CssDevId *dev_id = object_field_prop_ptr(obj, prop); 2379 char *str; 2380 int num, n1, n2; 2381 unsigned int cssid, ssid, devid; 2382 2383 if (!visit_type_str(v, name, &str, errp)) { 2384 return; 2385 } 2386 2387 num = sscanf(str, "%2x.%1x%n.%4x%n", &cssid, &ssid, &n1, &devid, &n2); 2388 if (num != 3 || (n2 - n1) != 5 || strlen(str) != n2) { 2389 error_set_from_qdev_prop_error(errp, EINVAL, obj, name, str); 2390 goto out; 2391 } 2392 if ((cssid > MAX_CSSID) || (ssid > MAX_SSID)) { 2393 error_setg(errp, "Invalid cssid or ssid: cssid %x, ssid %x", 2394 cssid, ssid); 2395 goto out; 2396 } 2397 2398 dev_id->cssid = cssid; 2399 dev_id->ssid = ssid; 2400 dev_id->devid = devid; 2401 dev_id->valid = true; 2402 2403 out: 2404 g_free(str); 2405 } 2406 2407 const PropertyInfo css_devid_propinfo = { 2408 .name = "str", 2409 .description = "Identifier of an I/O device in the channel " 2410 "subsystem, example: fe.1.23ab", 2411 .get = get_css_devid, 2412 .set = set_css_devid, 2413 }; 2414 2415 const PropertyInfo css_devid_ro_propinfo = { 2416 .name = "str", 2417 .description = "Read-only identifier of an I/O device in the channel " 2418 "subsystem, example: fe.1.23ab", 2419 .get = get_css_devid, 2420 }; 2421 2422 SubchDev *css_create_sch(CssDevId bus_id, Error **errp) 2423 { 2424 uint16_t schid = 0; 2425 SubchDev *sch; 2426 2427 if (bus_id.valid) { 2428 if (!channel_subsys.css[bus_id.cssid]) { 2429 css_create_css_image(bus_id.cssid, false); 2430 } 2431 2432 if (!css_find_free_subch_for_devno(bus_id.cssid, bus_id.ssid, 2433 bus_id.devid, &schid, errp)) { 2434 return NULL; 2435 } 2436 } else { 2437 for (bus_id.cssid = channel_subsys.default_cssid;;) { 2438 if (!channel_subsys.css[bus_id.cssid]) { 2439 css_create_css_image(bus_id.cssid, false); 2440 } 2441 2442 if (css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid, 2443 &bus_id.devid, &schid, 2444 NULL)) { 2445 break; 2446 } 2447 bus_id.cssid = (bus_id.cssid + 1) % MAX_CSSID; 2448 if (bus_id.cssid == channel_subsys.default_cssid) { 2449 error_setg(errp, "Virtual channel subsystem is full!"); 2450 return NULL; 2451 } 2452 } 2453 } 2454 2455 sch = g_new0(SubchDev, 1); 2456 sch->cssid = bus_id.cssid; 2457 sch->ssid = bus_id.ssid; 2458 sch->devno = bus_id.devid; 2459 sch->schid = schid; 2460 css_subch_assign(sch->cssid, sch->ssid, schid, sch->devno, sch); 2461 return sch; 2462 } 2463 2464 static int css_sch_get_chpids(SubchDev *sch, CssDevId *dev_id) 2465 { 2466 char *fid_path; 2467 FILE *fd; 2468 uint32_t chpid[8]; 2469 int i; 2470 SCHIB *schib = &sch->curr_status; 2471 2472 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids", 2473 dev_id->cssid, dev_id->ssid, dev_id->devid); 2474 fd = fopen(fid_path, "r"); 2475 if (fd == NULL) { 2476 error_report("%s: open %s failed", __func__, fid_path); 2477 g_free(fid_path); 2478 return -EINVAL; 2479 } 2480 2481 if (fscanf(fd, "%x %x %x %x %x %x %x %x", 2482 &chpid[0], &chpid[1], &chpid[2], &chpid[3], 2483 &chpid[4], &chpid[5], &chpid[6], &chpid[7]) != 8) { 2484 fclose(fd); 2485 g_free(fid_path); 2486 return -EINVAL; 2487 } 2488 2489 for (i = 0; i < ARRAY_SIZE(schib->pmcw.chpid); i++) { 2490 schib->pmcw.chpid[i] = chpid[i]; 2491 } 2492 2493 fclose(fd); 2494 g_free(fid_path); 2495 2496 return 0; 2497 } 2498 2499 static int css_sch_get_path_masks(SubchDev *sch, CssDevId *dev_id) 2500 { 2501 char *fid_path; 2502 FILE *fd; 2503 uint32_t pim, pam, pom; 2504 SCHIB *schib = &sch->curr_status; 2505 2506 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom", 2507 dev_id->cssid, dev_id->ssid, dev_id->devid); 2508 fd = fopen(fid_path, "r"); 2509 if (fd == NULL) { 2510 error_report("%s: open %s failed", __func__, fid_path); 2511 g_free(fid_path); 2512 return -EINVAL; 2513 } 2514 2515 if (fscanf(fd, "%x %x %x", &pim, &pam, &pom) != 3) { 2516 fclose(fd); 2517 g_free(fid_path); 2518 return -EINVAL; 2519 } 2520 2521 schib->pmcw.pim = pim; 2522 schib->pmcw.pam = pam; 2523 schib->pmcw.pom = pom; 2524 fclose(fd); 2525 g_free(fid_path); 2526 2527 return 0; 2528 } 2529 2530 static int css_sch_get_chpid_type(uint8_t chpid, uint32_t *type, 2531 CssDevId *dev_id) 2532 { 2533 char *fid_path; 2534 FILE *fd; 2535 2536 fid_path = g_strdup_printf("/sys/devices/css%x/chp0.%02x/type", 2537 dev_id->cssid, chpid); 2538 fd = fopen(fid_path, "r"); 2539 if (fd == NULL) { 2540 error_report("%s: open %s failed", __func__, fid_path); 2541 g_free(fid_path); 2542 return -EINVAL; 2543 } 2544 2545 if (fscanf(fd, "%x", type) != 1) { 2546 fclose(fd); 2547 g_free(fid_path); 2548 return -EINVAL; 2549 } 2550 2551 fclose(fd); 2552 g_free(fid_path); 2553 2554 return 0; 2555 } 2556 2557 /* 2558 * We currently retrieve the real device information from sysfs to build the 2559 * guest subchannel information block without considering the migration feature. 2560 * We need to revisit this problem when we want to add migration support. 2561 */ 2562 int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id) 2563 { 2564 CssImage *css = channel_subsys.css[sch->cssid]; 2565 SCHIB *schib = &sch->curr_status; 2566 uint32_t type; 2567 int i, ret; 2568 2569 assert(css != NULL); 2570 memset(&schib->pmcw, 0, sizeof(PMCW)); 2571 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV; 2572 /* We are dealing with I/O subchannels only. */ 2573 schib->pmcw.devno = sch->devno; 2574 2575 /* Grab path mask from sysfs. */ 2576 ret = css_sch_get_path_masks(sch, dev_id); 2577 if (ret) { 2578 return ret; 2579 } 2580 2581 /* Grab chpids from sysfs. */ 2582 ret = css_sch_get_chpids(sch, dev_id); 2583 if (ret) { 2584 return ret; 2585 } 2586 2587 /* Build chpid type. */ 2588 for (i = 0; i < ARRAY_SIZE(schib->pmcw.chpid); i++) { 2589 if (schib->pmcw.chpid[i] && !css->chpids[schib->pmcw.chpid[i]].in_use) { 2590 ret = css_sch_get_chpid_type(schib->pmcw.chpid[i], &type, dev_id); 2591 if (ret) { 2592 return ret; 2593 } 2594 css_add_chpid(sch->cssid, schib->pmcw.chpid[i], type, false); 2595 } 2596 } 2597 2598 memset(&schib->scsw, 0, sizeof(SCSW)); 2599 schib->mba = 0; 2600 for (i = 0; i < ARRAY_SIZE(schib->mda); i++) { 2601 schib->mda[i] = 0; 2602 } 2603 2604 return 0; 2605 } 2606