1 /* 2 * Channel subsystem base support. 3 * 4 * Copyright 2012 IBM Corp. 5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or (at 8 * your option) any later version. See the COPYING file in the top-level 9 * directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qapi/visitor.h" 15 #include "hw/qdev.h" 16 #include "qemu/bitops.h" 17 #include "qemu/error-report.h" 18 #include "exec/address-spaces.h" 19 #include "cpu.h" 20 #include "hw/s390x/ioinst.h" 21 #include "hw/s390x/css.h" 22 #include "trace.h" 23 #include "hw/s390x/s390_flic.h" 24 #include "hw/s390x/s390-virtio-ccw.h" 25 26 typedef struct CrwContainer { 27 CRW crw; 28 QTAILQ_ENTRY(CrwContainer) sibling; 29 } CrwContainer; 30 31 static const VMStateDescription vmstate_crw = { 32 .name = "s390_crw", 33 .version_id = 1, 34 .minimum_version_id = 1, 35 .fields = (VMStateField[]) { 36 VMSTATE_UINT16(flags, CRW), 37 VMSTATE_UINT16(rsid, CRW), 38 VMSTATE_END_OF_LIST() 39 }, 40 }; 41 42 static const VMStateDescription vmstate_crw_container = { 43 .name = "s390_crw_container", 44 .version_id = 1, 45 .minimum_version_id = 1, 46 .fields = (VMStateField[]) { 47 VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW), 48 VMSTATE_END_OF_LIST() 49 }, 50 }; 51 52 typedef struct ChpInfo { 53 uint8_t in_use; 54 uint8_t type; 55 uint8_t is_virtual; 56 } ChpInfo; 57 58 static const VMStateDescription vmstate_chp_info = { 59 .name = "s390_chp_info", 60 .version_id = 1, 61 .minimum_version_id = 1, 62 .fields = (VMStateField[]) { 63 VMSTATE_UINT8(in_use, ChpInfo), 64 VMSTATE_UINT8(type, ChpInfo), 65 VMSTATE_UINT8(is_virtual, ChpInfo), 66 VMSTATE_END_OF_LIST() 67 } 68 }; 69 70 typedef struct SubchSet { 71 SubchDev *sch[MAX_SCHID + 1]; 72 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 73 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 74 } SubchSet; 75 76 static const VMStateDescription vmstate_scsw = { 77 .name = "s390_scsw", 78 .version_id = 1, 79 .minimum_version_id = 1, 80 .fields = (VMStateField[]) { 81 VMSTATE_UINT16(flags, SCSW), 82 VMSTATE_UINT16(ctrl, SCSW), 83 VMSTATE_UINT32(cpa, SCSW), 84 VMSTATE_UINT8(dstat, SCSW), 85 VMSTATE_UINT8(cstat, SCSW), 86 VMSTATE_UINT16(count, SCSW), 87 VMSTATE_END_OF_LIST() 88 } 89 }; 90 91 static const VMStateDescription vmstate_pmcw = { 92 .name = "s390_pmcw", 93 .version_id = 1, 94 .minimum_version_id = 1, 95 .fields = (VMStateField[]) { 96 VMSTATE_UINT32(intparm, PMCW), 97 VMSTATE_UINT16(flags, PMCW), 98 VMSTATE_UINT16(devno, PMCW), 99 VMSTATE_UINT8(lpm, PMCW), 100 VMSTATE_UINT8(pnom, PMCW), 101 VMSTATE_UINT8(lpum, PMCW), 102 VMSTATE_UINT8(pim, PMCW), 103 VMSTATE_UINT16(mbi, PMCW), 104 VMSTATE_UINT8(pom, PMCW), 105 VMSTATE_UINT8(pam, PMCW), 106 VMSTATE_UINT8_ARRAY(chpid, PMCW, 8), 107 VMSTATE_UINT32(chars, PMCW), 108 VMSTATE_END_OF_LIST() 109 } 110 }; 111 112 static const VMStateDescription vmstate_schib = { 113 .name = "s390_schib", 114 .version_id = 1, 115 .minimum_version_id = 1, 116 .fields = (VMStateField[]) { 117 VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW), 118 VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW), 119 VMSTATE_UINT64(mba, SCHIB), 120 VMSTATE_UINT8_ARRAY(mda, SCHIB, 4), 121 VMSTATE_END_OF_LIST() 122 } 123 }; 124 125 126 static const VMStateDescription vmstate_ccw1 = { 127 .name = "s390_ccw1", 128 .version_id = 1, 129 .minimum_version_id = 1, 130 .fields = (VMStateField[]) { 131 VMSTATE_UINT8(cmd_code, CCW1), 132 VMSTATE_UINT8(flags, CCW1), 133 VMSTATE_UINT16(count, CCW1), 134 VMSTATE_UINT32(cda, CCW1), 135 VMSTATE_END_OF_LIST() 136 } 137 }; 138 139 static const VMStateDescription vmstate_ciw = { 140 .name = "s390_ciw", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .fields = (VMStateField[]) { 144 VMSTATE_UINT8(type, CIW), 145 VMSTATE_UINT8(command, CIW), 146 VMSTATE_UINT16(count, CIW), 147 VMSTATE_END_OF_LIST() 148 } 149 }; 150 151 static const VMStateDescription vmstate_sense_id = { 152 .name = "s390_sense_id", 153 .version_id = 1, 154 .minimum_version_id = 1, 155 .fields = (VMStateField[]) { 156 VMSTATE_UINT8(reserved, SenseId), 157 VMSTATE_UINT16(cu_type, SenseId), 158 VMSTATE_UINT8(cu_model, SenseId), 159 VMSTATE_UINT16(dev_type, SenseId), 160 VMSTATE_UINT8(dev_model, SenseId), 161 VMSTATE_UINT8(unused, SenseId), 162 VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW), 163 VMSTATE_END_OF_LIST() 164 } 165 }; 166 167 static const VMStateDescription vmstate_orb = { 168 .name = "s390_orb", 169 .version_id = 1, 170 .minimum_version_id = 1, 171 .fields = (VMStateField[]) { 172 VMSTATE_UINT32(intparm, ORB), 173 VMSTATE_UINT16(ctrl0, ORB), 174 VMSTATE_UINT8(lpm, ORB), 175 VMSTATE_UINT8(ctrl1, ORB), 176 VMSTATE_UINT32(cpa, ORB), 177 VMSTATE_END_OF_LIST() 178 } 179 }; 180 181 static bool vmstate_schdev_orb_needed(void *opaque) 182 { 183 return css_migration_enabled(); 184 } 185 186 static const VMStateDescription vmstate_schdev_orb = { 187 .name = "s390_subch_dev/orb", 188 .version_id = 1, 189 .minimum_version_id = 1, 190 .needed = vmstate_schdev_orb_needed, 191 .fields = (VMStateField[]) { 192 VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB), 193 VMSTATE_END_OF_LIST() 194 } 195 }; 196 197 static int subch_dev_post_load(void *opaque, int version_id); 198 static int subch_dev_pre_save(void *opaque); 199 200 const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!" 201 " Likely reason: some sequences of plug and unplug can break" 202 " migration for machine versions prior to 2.7 (known design flaw)."; 203 204 const VMStateDescription vmstate_subch_dev = { 205 .name = "s390_subch_dev", 206 .version_id = 1, 207 .minimum_version_id = 1, 208 .post_load = subch_dev_post_load, 209 .pre_save = subch_dev_pre_save, 210 .fields = (VMStateField[]) { 211 VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"), 212 VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"), 213 VMSTATE_UINT16(migrated_schid, SubchDev), 214 VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno), 215 VMSTATE_BOOL(thinint_active, SubchDev), 216 VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB), 217 VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32), 218 VMSTATE_UINT64(channel_prog, SubchDev), 219 VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1), 220 VMSTATE_BOOL(last_cmd_valid, SubchDev), 221 VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId), 222 VMSTATE_BOOL(ccw_fmt_1, SubchDev), 223 VMSTATE_UINT8(ccw_no_data_cnt, SubchDev), 224 VMSTATE_END_OF_LIST() 225 }, 226 .subsections = (const VMStateDescription * []) { 227 &vmstate_schdev_orb, 228 NULL 229 } 230 }; 231 232 typedef struct IndAddrPtrTmp { 233 IndAddr **parent; 234 uint64_t addr; 235 int32_t len; 236 } IndAddrPtrTmp; 237 238 static int post_load_ind_addr(void *opaque, int version_id) 239 { 240 IndAddrPtrTmp *ptmp = opaque; 241 IndAddr **ind_addr = ptmp->parent; 242 243 if (ptmp->len != 0) { 244 *ind_addr = get_indicator(ptmp->addr, ptmp->len); 245 } else { 246 *ind_addr = NULL; 247 } 248 return 0; 249 } 250 251 static int pre_save_ind_addr(void *opaque) 252 { 253 IndAddrPtrTmp *ptmp = opaque; 254 IndAddr *ind_addr = *(ptmp->parent); 255 256 if (ind_addr != NULL) { 257 ptmp->len = ind_addr->len; 258 ptmp->addr = ind_addr->addr; 259 } else { 260 ptmp->len = 0; 261 ptmp->addr = 0L; 262 } 263 264 return 0; 265 } 266 267 const VMStateDescription vmstate_ind_addr_tmp = { 268 .name = "s390_ind_addr_tmp", 269 .pre_save = pre_save_ind_addr, 270 .post_load = post_load_ind_addr, 271 272 .fields = (VMStateField[]) { 273 VMSTATE_INT32(len, IndAddrPtrTmp), 274 VMSTATE_UINT64(addr, IndAddrPtrTmp), 275 VMSTATE_END_OF_LIST() 276 } 277 }; 278 279 const VMStateDescription vmstate_ind_addr = { 280 .name = "s390_ind_addr_tmp", 281 .fields = (VMStateField[]) { 282 VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp), 283 VMSTATE_END_OF_LIST() 284 } 285 }; 286 287 typedef struct CssImage { 288 SubchSet *sch_set[MAX_SSID + 1]; 289 ChpInfo chpids[MAX_CHPID + 1]; 290 } CssImage; 291 292 static const VMStateDescription vmstate_css_img = { 293 .name = "s390_css_img", 294 .version_id = 1, 295 .minimum_version_id = 1, 296 .fields = (VMStateField[]) { 297 /* Subchannel sets have no relevant state. */ 298 VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0, 299 vmstate_chp_info, ChpInfo), 300 VMSTATE_END_OF_LIST() 301 } 302 303 }; 304 305 typedef struct IoAdapter { 306 uint32_t id; 307 uint8_t type; 308 uint8_t isc; 309 uint8_t flags; 310 } IoAdapter; 311 312 typedef struct ChannelSubSys { 313 QTAILQ_HEAD(, CrwContainer) pending_crws; 314 bool sei_pending; 315 bool do_crw_mchk; 316 bool crws_lost; 317 uint8_t max_cssid; 318 uint8_t max_ssid; 319 bool chnmon_active; 320 uint64_t chnmon_area; 321 CssImage *css[MAX_CSSID + 1]; 322 uint8_t default_cssid; 323 /* don't migrate, see css_register_io_adapters */ 324 IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1]; 325 /* don't migrate, see get_indicator and IndAddrPtrTmp */ 326 QTAILQ_HEAD(, IndAddr) indicator_addresses; 327 } ChannelSubSys; 328 329 static const VMStateDescription vmstate_css = { 330 .name = "s390_css", 331 .version_id = 1, 332 .minimum_version_id = 1, 333 .fields = (VMStateField[]) { 334 VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container, 335 CrwContainer, sibling), 336 VMSTATE_BOOL(sei_pending, ChannelSubSys), 337 VMSTATE_BOOL(do_crw_mchk, ChannelSubSys), 338 VMSTATE_BOOL(crws_lost, ChannelSubSys), 339 /* These were kind of migrated by virtio */ 340 VMSTATE_UINT8(max_cssid, ChannelSubSys), 341 VMSTATE_UINT8(max_ssid, ChannelSubSys), 342 VMSTATE_BOOL(chnmon_active, ChannelSubSys), 343 VMSTATE_UINT64(chnmon_area, ChannelSubSys), 344 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1, 345 0, vmstate_css_img, CssImage), 346 VMSTATE_UINT8(default_cssid, ChannelSubSys), 347 VMSTATE_END_OF_LIST() 348 } 349 }; 350 351 static ChannelSubSys channel_subsys = { 352 .pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws), 353 .do_crw_mchk = true, 354 .sei_pending = false, 355 .do_crw_mchk = true, 356 .crws_lost = false, 357 .chnmon_active = false, 358 .indicator_addresses = 359 QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses), 360 }; 361 362 static int subch_dev_pre_save(void *opaque) 363 { 364 SubchDev *s = opaque; 365 366 /* Prepare remote_schid for save */ 367 s->migrated_schid = s->schid; 368 369 return 0; 370 } 371 372 static int subch_dev_post_load(void *opaque, int version_id) 373 { 374 375 SubchDev *s = opaque; 376 377 /* Re-assign the subchannel to remote_schid if necessary */ 378 if (s->migrated_schid != s->schid) { 379 if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) { 380 /* 381 * Cleanup the slot before moving to s->migrated_schid provided 382 * it still belongs to us, i.e. it was not changed by previous 383 * invocation of this function. 384 */ 385 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL); 386 } 387 /* It's OK to re-assign without a prior de-assign. */ 388 s->schid = s->migrated_schid; 389 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s); 390 } 391 392 if (css_migration_enabled()) { 393 /* No compat voodoo to do ;) */ 394 return 0; 395 } 396 /* 397 * Hack alert. If we don't migrate the channel subsystem status 398 * we still need to find out if the guest enabled mss/mcss-e. 399 * If the subchannel is enabled, it certainly was able to access it, 400 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid 401 * values. This is not watertight, but better than nothing. 402 */ 403 if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) { 404 if (s->ssid) { 405 channel_subsys.max_ssid = MAX_SSID; 406 } 407 if (s->cssid != channel_subsys.default_cssid) { 408 channel_subsys.max_cssid = MAX_CSSID; 409 } 410 } 411 return 0; 412 } 413 414 void css_register_vmstate(void) 415 { 416 vmstate_register(NULL, 0, &vmstate_css, &channel_subsys); 417 } 418 419 IndAddr *get_indicator(hwaddr ind_addr, int len) 420 { 421 IndAddr *indicator; 422 423 QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) { 424 if (indicator->addr == ind_addr) { 425 indicator->refcnt++; 426 return indicator; 427 } 428 } 429 indicator = g_new0(IndAddr, 1); 430 indicator->addr = ind_addr; 431 indicator->len = len; 432 indicator->refcnt = 1; 433 QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses, 434 indicator, sibling); 435 return indicator; 436 } 437 438 static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr, 439 bool do_map) 440 { 441 S390FLICState *fs = s390_get_flic(); 442 S390FLICStateClass *fsc = s390_get_flic_class(fs); 443 444 return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map); 445 } 446 447 void release_indicator(AdapterInfo *adapter, IndAddr *indicator) 448 { 449 assert(indicator->refcnt > 0); 450 indicator->refcnt--; 451 if (indicator->refcnt > 0) { 452 return; 453 } 454 QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling); 455 if (indicator->map) { 456 s390_io_adapter_map(adapter, indicator->map, false); 457 } 458 g_free(indicator); 459 } 460 461 int map_indicator(AdapterInfo *adapter, IndAddr *indicator) 462 { 463 int ret; 464 465 if (indicator->map) { 466 return 0; /* already mapped is not an error */ 467 } 468 indicator->map = indicator->addr; 469 ret = s390_io_adapter_map(adapter, indicator->map, true); 470 if ((ret != 0) && (ret != -ENOSYS)) { 471 goto out_err; 472 } 473 return 0; 474 475 out_err: 476 indicator->map = 0; 477 return ret; 478 } 479 480 int css_create_css_image(uint8_t cssid, bool default_image) 481 { 482 trace_css_new_image(cssid, default_image ? "(default)" : ""); 483 /* 255 is reserved */ 484 if (cssid == 255) { 485 return -EINVAL; 486 } 487 if (channel_subsys.css[cssid]) { 488 return -EBUSY; 489 } 490 channel_subsys.css[cssid] = g_new0(CssImage, 1); 491 if (default_image) { 492 channel_subsys.default_cssid = cssid; 493 } 494 return 0; 495 } 496 497 uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc) 498 { 499 if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC || 500 !channel_subsys.io_adapters[type][isc]) { 501 return -1; 502 } 503 504 return channel_subsys.io_adapters[type][isc]->id; 505 } 506 507 /** 508 * css_register_io_adapters: Register I/O adapters per ISC during init 509 * 510 * @swap: an indication if byte swap is needed. 511 * @maskable: an indication if the adapter is subject to the mask operation. 512 * @flags: further characteristics of the adapter. 513 * e.g. suppressible, an indication if the adapter is subject to AIS. 514 * @errp: location to store error information. 515 */ 516 void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable, 517 uint8_t flags, Error **errp) 518 { 519 uint32_t id; 520 int ret, isc; 521 IoAdapter *adapter; 522 S390FLICState *fs = s390_get_flic(); 523 S390FLICStateClass *fsc = s390_get_flic_class(fs); 524 525 /* 526 * Disallow multiple registrations for the same device type. 527 * Report an error if registering for an already registered type. 528 */ 529 if (channel_subsys.io_adapters[type][0]) { 530 error_setg(errp, "Adapters for type %d already registered", type); 531 } 532 533 for (isc = 0; isc <= MAX_ISC; isc++) { 534 id = (type << 3) | isc; 535 ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags); 536 if (ret == 0) { 537 adapter = g_new0(IoAdapter, 1); 538 adapter->id = id; 539 adapter->isc = isc; 540 adapter->type = type; 541 adapter->flags = flags; 542 channel_subsys.io_adapters[type][isc] = adapter; 543 } else { 544 error_setg_errno(errp, -ret, "Unexpected error %d when " 545 "registering adapter %d", ret, id); 546 break; 547 } 548 } 549 550 /* 551 * No need to free registered adapters in kvm: kvm will clean up 552 * when the machine goes away. 553 */ 554 if (ret) { 555 for (isc--; isc >= 0; isc--) { 556 g_free(channel_subsys.io_adapters[type][isc]); 557 channel_subsys.io_adapters[type][isc] = NULL; 558 } 559 } 560 561 } 562 563 static void css_clear_io_interrupt(uint16_t subchannel_id, 564 uint16_t subchannel_nr) 565 { 566 Error *err = NULL; 567 static bool no_clear_irq; 568 S390FLICState *fs = s390_get_flic(); 569 S390FLICStateClass *fsc = s390_get_flic_class(fs); 570 int r; 571 572 if (unlikely(no_clear_irq)) { 573 return; 574 } 575 r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr); 576 switch (r) { 577 case 0: 578 break; 579 case -ENOSYS: 580 no_clear_irq = true; 581 /* 582 * Ignore unavailability, as the user can't do anything 583 * about it anyway. 584 */ 585 break; 586 default: 587 error_setg_errno(&err, -r, "unexpected error condition"); 588 error_propagate(&error_abort, err); 589 } 590 } 591 592 static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid) 593 { 594 if (channel_subsys.max_cssid > 0) { 595 return (cssid << 8) | (1 << 3) | (ssid << 1) | 1; 596 } 597 return (ssid << 1) | 1; 598 } 599 600 uint16_t css_build_subchannel_id(SubchDev *sch) 601 { 602 return css_do_build_subchannel_id(sch->cssid, sch->ssid); 603 } 604 605 void css_inject_io_interrupt(SubchDev *sch) 606 { 607 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 608 609 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 610 sch->curr_status.pmcw.intparm, isc, ""); 611 s390_io_interrupt(css_build_subchannel_id(sch), 612 sch->schid, 613 sch->curr_status.pmcw.intparm, 614 isc << 27); 615 } 616 617 void css_conditional_io_interrupt(SubchDev *sch) 618 { 619 /* 620 * If the subchannel is not enabled, it is not made status pending 621 * (see PoP p. 16-17, "Status Control"). 622 */ 623 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA)) { 624 return; 625 } 626 627 /* 628 * If the subchannel is not currently status pending, make it pending 629 * with alert status. 630 */ 631 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) { 632 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 633 634 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 635 sch->curr_status.pmcw.intparm, isc, 636 "(unsolicited)"); 637 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 638 sch->curr_status.scsw.ctrl |= 639 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 640 /* Inject an I/O interrupt. */ 641 s390_io_interrupt(css_build_subchannel_id(sch), 642 sch->schid, 643 sch->curr_status.pmcw.intparm, 644 isc << 27); 645 } 646 } 647 648 int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode) 649 { 650 S390FLICState *fs = s390_get_flic(); 651 S390FLICStateClass *fsc = s390_get_flic_class(fs); 652 int r; 653 654 if (env->psw.mask & PSW_MASK_PSTATE) { 655 r = -PGM_PRIVILEGED; 656 goto out; 657 } 658 659 trace_css_do_sic(mode, isc); 660 switch (mode) { 661 case SIC_IRQ_MODE_ALL: 662 case SIC_IRQ_MODE_SINGLE: 663 break; 664 default: 665 r = -PGM_OPERAND; 666 goto out; 667 } 668 669 r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0; 670 out: 671 return r; 672 } 673 674 void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc) 675 { 676 S390FLICState *fs = s390_get_flic(); 677 S390FLICStateClass *fsc = s390_get_flic_class(fs); 678 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI; 679 IoAdapter *adapter = channel_subsys.io_adapters[type][isc]; 680 681 if (!adapter) { 682 return; 683 } 684 685 trace_css_adapter_interrupt(isc); 686 if (fs->ais_supported) { 687 if (fsc->inject_airq(fs, type, isc, adapter->flags)) { 688 error_report("Failed to inject airq with AIS supported"); 689 exit(1); 690 } 691 } else { 692 s390_io_interrupt(0, 0, 0, io_int_word); 693 } 694 } 695 696 static void sch_handle_clear_func(SubchDev *sch) 697 { 698 PMCW *p = &sch->curr_status.pmcw; 699 SCSW *s = &sch->curr_status.scsw; 700 int path; 701 702 /* Path management: In our simple css, we always choose the only path. */ 703 path = 0x80; 704 705 /* Reset values prior to 'issuing the clear signal'. */ 706 p->lpum = 0; 707 p->pom = 0xff; 708 s->flags &= ~SCSW_FLAGS_MASK_PNO; 709 710 /* We always 'attempt to issue the clear signal', and we always succeed. */ 711 sch->channel_prog = 0x0; 712 sch->last_cmd_valid = false; 713 s->ctrl &= ~SCSW_ACTL_CLEAR_PEND; 714 s->ctrl |= SCSW_STCTL_STATUS_PEND; 715 716 s->dstat = 0; 717 s->cstat = 0; 718 p->lpum = path; 719 720 } 721 722 static void sch_handle_halt_func(SubchDev *sch) 723 { 724 725 PMCW *p = &sch->curr_status.pmcw; 726 SCSW *s = &sch->curr_status.scsw; 727 hwaddr curr_ccw = sch->channel_prog; 728 int path; 729 730 /* Path management: In our simple css, we always choose the only path. */ 731 path = 0x80; 732 733 /* We always 'attempt to issue the halt signal', and we always succeed. */ 734 sch->channel_prog = 0x0; 735 sch->last_cmd_valid = false; 736 s->ctrl &= ~SCSW_ACTL_HALT_PEND; 737 s->ctrl |= SCSW_STCTL_STATUS_PEND; 738 739 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) || 740 !((s->ctrl & SCSW_ACTL_START_PEND) || 741 (s->ctrl & SCSW_ACTL_SUSP))) { 742 s->dstat = SCSW_DSTAT_DEVICE_END; 743 } 744 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) || 745 (s->ctrl & SCSW_ACTL_SUSP)) { 746 s->cpa = curr_ccw + 8; 747 } 748 s->cstat = 0; 749 p->lpum = path; 750 751 } 752 753 /* 754 * As the SenseId struct cannot be packed (would cause unaligned accesses), we 755 * have to copy the individual fields to an unstructured area using the correct 756 * layout (see SA22-7204-01 "Common I/O-Device Commands"). 757 */ 758 static void copy_sense_id_to_guest(uint8_t *dest, SenseId *src) 759 { 760 int i; 761 762 dest[0] = src->reserved; 763 stw_be_p(dest + 1, src->cu_type); 764 dest[3] = src->cu_model; 765 stw_be_p(dest + 4, src->dev_type); 766 dest[6] = src->dev_model; 767 dest[7] = src->unused; 768 for (i = 0; i < ARRAY_SIZE(src->ciw); i++) { 769 dest[8 + i * 4] = src->ciw[i].type; 770 dest[9 + i * 4] = src->ciw[i].command; 771 stw_be_p(dest + 10 + i * 4, src->ciw[i].count); 772 } 773 } 774 775 static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1) 776 { 777 CCW0 tmp0; 778 CCW1 tmp1; 779 CCW1 ret; 780 781 if (fmt1) { 782 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1)); 783 ret.cmd_code = tmp1.cmd_code; 784 ret.flags = tmp1.flags; 785 ret.count = be16_to_cpu(tmp1.count); 786 ret.cda = be32_to_cpu(tmp1.cda); 787 } else { 788 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0)); 789 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) { 790 ret.cmd_code = CCW_CMD_TIC; 791 ret.flags = 0; 792 ret.count = 0; 793 } else { 794 ret.cmd_code = tmp0.cmd_code; 795 ret.flags = tmp0.flags; 796 ret.count = be16_to_cpu(tmp0.count); 797 } 798 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16); 799 } 800 return ret; 801 } 802 /** 803 * If out of bounds marks the stream broken. If broken returns -EINVAL, 804 * otherwise the requested length (may be zero) 805 */ 806 static inline int cds_check_len(CcwDataStream *cds, int len) 807 { 808 if (cds->at_byte + len > cds->count) { 809 cds->flags |= CDS_F_STREAM_BROKEN; 810 } 811 return cds->flags & CDS_F_STREAM_BROKEN ? -EINVAL : len; 812 } 813 814 static inline bool cds_ccw_addrs_ok(hwaddr addr, int len, bool ccw_fmt1) 815 { 816 return (addr + len) < (ccw_fmt1 ? (1UL << 31) : (1UL << 24)); 817 } 818 819 static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len, 820 CcwDataStreamOp op) 821 { 822 int ret; 823 824 ret = cds_check_len(cds, len); 825 if (ret <= 0) { 826 return ret; 827 } 828 if (!cds_ccw_addrs_ok(cds->cda, len, cds->flags & CDS_F_FMT)) { 829 return -EINVAL; /* channel program check */ 830 } 831 if (op == CDS_OP_A) { 832 goto incr; 833 } 834 ret = address_space_rw(&address_space_memory, cds->cda, 835 MEMTXATTRS_UNSPECIFIED, buff, len, op); 836 if (ret != MEMTX_OK) { 837 cds->flags |= CDS_F_STREAM_BROKEN; 838 return -EINVAL; 839 } 840 incr: 841 cds->at_byte += len; 842 cds->cda += len; 843 return 0; 844 } 845 846 /* returns values between 1 and bsz, where bsz is a power of 2 */ 847 static inline uint16_t ida_continuous_left(hwaddr cda, uint64_t bsz) 848 { 849 return bsz - (cda & (bsz - 1)); 850 } 851 852 static inline uint64_t ccw_ida_block_size(uint8_t flags) 853 { 854 if ((flags & CDS_F_C64) && !(flags & CDS_F_I2K)) { 855 return 1ULL << 12; 856 } 857 return 1ULL << 11; 858 } 859 860 static inline int ida_read_next_idaw(CcwDataStream *cds) 861 { 862 union {uint64_t fmt2; uint32_t fmt1; } idaw; 863 int ret; 864 hwaddr idaw_addr; 865 bool idaw_fmt2 = cds->flags & CDS_F_C64; 866 bool ccw_fmt1 = cds->flags & CDS_F_FMT; 867 868 if (idaw_fmt2) { 869 idaw_addr = cds->cda_orig + sizeof(idaw.fmt2) * cds->at_idaw; 870 if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { 871 return -EINVAL; /* channel program check */ 872 } 873 ret = address_space_rw(&address_space_memory, idaw_addr, 874 MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt2, 875 sizeof(idaw.fmt2), false); 876 cds->cda = be64_to_cpu(idaw.fmt2); 877 } else { 878 idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw; 879 if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { 880 return -EINVAL; /* channel program check */ 881 } 882 ret = address_space_rw(&address_space_memory, idaw_addr, 883 MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt1, 884 sizeof(idaw.fmt1), false); 885 cds->cda = be64_to_cpu(idaw.fmt1); 886 if (cds->cda & 0x80000000) { 887 return -EINVAL; /* channel program check */ 888 } 889 } 890 ++(cds->at_idaw); 891 if (ret != MEMTX_OK) { 892 /* assume inaccessible address */ 893 return -EINVAL; /* channel program check */ 894 } 895 return 0; 896 } 897 898 static int ccw_dstream_rw_ida(CcwDataStream *cds, void *buff, int len, 899 CcwDataStreamOp op) 900 { 901 uint64_t bsz = ccw_ida_block_size(cds->flags); 902 int ret = 0; 903 uint16_t cont_left, iter_len; 904 905 ret = cds_check_len(cds, len); 906 if (ret <= 0) { 907 return ret; 908 } 909 if (!cds->at_idaw) { 910 /* read first idaw */ 911 ret = ida_read_next_idaw(cds); 912 if (ret) { 913 goto err; 914 } 915 cont_left = ida_continuous_left(cds->cda, bsz); 916 } else { 917 cont_left = ida_continuous_left(cds->cda, bsz); 918 if (cont_left == bsz) { 919 ret = ida_read_next_idaw(cds); 920 if (ret) { 921 goto err; 922 } 923 if (cds->cda & (bsz - 1)) { 924 ret = -EINVAL; /* channel program check */ 925 goto err; 926 } 927 } 928 } 929 do { 930 iter_len = MIN(len, cont_left); 931 if (op != CDS_OP_A) { 932 ret = address_space_rw(&address_space_memory, cds->cda, 933 MEMTXATTRS_UNSPECIFIED, buff, iter_len, op); 934 if (ret != MEMTX_OK) { 935 /* assume inaccessible address */ 936 ret = -EINVAL; /* channel program check */ 937 goto err; 938 } 939 } 940 cds->at_byte += iter_len; 941 cds->cda += iter_len; 942 len -= iter_len; 943 if (!len) { 944 break; 945 } 946 ret = ida_read_next_idaw(cds); 947 if (ret) { 948 goto err; 949 } 950 cont_left = bsz; 951 } while (true); 952 return ret; 953 err: 954 cds->flags |= CDS_F_STREAM_BROKEN; 955 return ret; 956 } 957 958 void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb) 959 { 960 /* 961 * We don't support MIDA (an optional facility) yet and we 962 * catch this earlier. Just for expressing the precondition. 963 */ 964 g_assert(!(orb->ctrl1 & ORB_CTRL1_MASK_MIDAW)); 965 cds->flags = (orb->ctrl0 & ORB_CTRL0_MASK_I2K ? CDS_F_I2K : 0) | 966 (orb->ctrl0 & ORB_CTRL0_MASK_C64 ? CDS_F_C64 : 0) | 967 (orb->ctrl0 & ORB_CTRL0_MASK_FMT ? CDS_F_FMT : 0) | 968 (ccw->flags & CCW_FLAG_IDA ? CDS_F_IDA : 0); 969 970 cds->count = ccw->count; 971 cds->cda_orig = ccw->cda; 972 ccw_dstream_rewind(cds); 973 if (!(cds->flags & CDS_F_IDA)) { 974 cds->op_handler = ccw_dstream_rw_noflags; 975 } else { 976 cds->op_handler = ccw_dstream_rw_ida; 977 } 978 } 979 980 static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr, 981 bool suspend_allowed) 982 { 983 int ret; 984 bool check_len; 985 int len; 986 CCW1 ccw; 987 988 if (!ccw_addr) { 989 return -EINVAL; /* channel-program check */ 990 } 991 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */ 992 if (ccw_addr & (sch->ccw_fmt_1 ? 0x80000007 : 0xff000007)) { 993 return -EINVAL; 994 } 995 996 /* Translate everything to format-1 ccws - the information is the same. */ 997 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1); 998 999 /* Check for invalid command codes. */ 1000 if ((ccw.cmd_code & 0x0f) == 0) { 1001 return -EINVAL; 1002 } 1003 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) && 1004 ((ccw.cmd_code & 0xf0) != 0)) { 1005 return -EINVAL; 1006 } 1007 if (!sch->ccw_fmt_1 && (ccw.count == 0) && 1008 (ccw.cmd_code != CCW_CMD_TIC)) { 1009 return -EINVAL; 1010 } 1011 1012 /* We don't support MIDA. */ 1013 if (ccw.flags & CCW_FLAG_MIDA) { 1014 return -EINVAL; 1015 } 1016 1017 if (ccw.flags & CCW_FLAG_SUSPEND) { 1018 return suspend_allowed ? -EINPROGRESS : -EINVAL; 1019 } 1020 1021 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC)); 1022 1023 if (!ccw.cda) { 1024 if (sch->ccw_no_data_cnt == 255) { 1025 return -EINVAL; 1026 } 1027 sch->ccw_no_data_cnt++; 1028 } 1029 1030 /* Look at the command. */ 1031 ccw_dstream_init(&sch->cds, &ccw, &(sch->orb)); 1032 switch (ccw.cmd_code) { 1033 case CCW_CMD_NOOP: 1034 /* Nothing to do. */ 1035 ret = 0; 1036 break; 1037 case CCW_CMD_BASIC_SENSE: 1038 if (check_len) { 1039 if (ccw.count != sizeof(sch->sense_data)) { 1040 ret = -EINVAL; 1041 break; 1042 } 1043 } 1044 len = MIN(ccw.count, sizeof(sch->sense_data)); 1045 ccw_dstream_write_buf(&sch->cds, sch->sense_data, len); 1046 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds); 1047 memset(sch->sense_data, 0, sizeof(sch->sense_data)); 1048 ret = 0; 1049 break; 1050 case CCW_CMD_SENSE_ID: 1051 { 1052 /* According to SA22-7204-01, Sense-ID can store up to 256 bytes */ 1053 uint8_t sense_id[256]; 1054 1055 copy_sense_id_to_guest(sense_id, &sch->id); 1056 /* Sense ID information is device specific. */ 1057 if (check_len) { 1058 if (ccw.count != sizeof(sense_id)) { 1059 ret = -EINVAL; 1060 break; 1061 } 1062 } 1063 len = MIN(ccw.count, sizeof(sense_id)); 1064 /* 1065 * Only indicate 0xff in the first sense byte if we actually 1066 * have enough place to store at least bytes 0-3. 1067 */ 1068 if (len >= 4) { 1069 sense_id[0] = 0xff; 1070 } else { 1071 sense_id[0] = 0; 1072 } 1073 ccw_dstream_write_buf(&sch->cds, sense_id, len); 1074 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds); 1075 ret = 0; 1076 break; 1077 } 1078 case CCW_CMD_TIC: 1079 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) { 1080 ret = -EINVAL; 1081 break; 1082 } 1083 if (ccw.flags || ccw.count) { 1084 /* We have already sanitized these if converted from fmt 0. */ 1085 ret = -EINVAL; 1086 break; 1087 } 1088 sch->channel_prog = ccw.cda; 1089 ret = -EAGAIN; 1090 break; 1091 default: 1092 if (sch->ccw_cb) { 1093 /* Handle device specific commands. */ 1094 ret = sch->ccw_cb(sch, ccw); 1095 } else { 1096 ret = -ENOSYS; 1097 } 1098 break; 1099 } 1100 sch->last_cmd = ccw; 1101 sch->last_cmd_valid = true; 1102 if (ret == 0) { 1103 if (ccw.flags & CCW_FLAG_CC) { 1104 sch->channel_prog += 8; 1105 ret = -EAGAIN; 1106 } 1107 } 1108 1109 return ret; 1110 } 1111 1112 static void sch_handle_start_func_virtual(SubchDev *sch) 1113 { 1114 1115 PMCW *p = &sch->curr_status.pmcw; 1116 SCSW *s = &sch->curr_status.scsw; 1117 int path; 1118 int ret; 1119 bool suspend_allowed; 1120 1121 /* Path management: In our simple css, we always choose the only path. */ 1122 path = 0x80; 1123 1124 if (!(s->ctrl & SCSW_ACTL_SUSP)) { 1125 /* Start Function triggered via ssch, i.e. we have an ORB */ 1126 ORB *orb = &sch->orb; 1127 s->cstat = 0; 1128 s->dstat = 0; 1129 /* Look at the orb and try to execute the channel program. */ 1130 p->intparm = orb->intparm; 1131 if (!(orb->lpm & path)) { 1132 /* Generate a deferred cc 3 condition. */ 1133 s->flags |= SCSW_FLAGS_MASK_CC; 1134 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 1135 s->ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND); 1136 return; 1137 } 1138 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT); 1139 s->flags |= (sch->ccw_fmt_1) ? SCSW_FLAGS_MASK_FMT : 0; 1140 sch->ccw_no_data_cnt = 0; 1141 suspend_allowed = !!(orb->ctrl0 & ORB_CTRL0_MASK_SPND); 1142 } else { 1143 /* Start Function resumed via rsch */ 1144 s->ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND); 1145 /* The channel program had been suspended before. */ 1146 suspend_allowed = true; 1147 } 1148 sch->last_cmd_valid = false; 1149 do { 1150 ret = css_interpret_ccw(sch, sch->channel_prog, suspend_allowed); 1151 switch (ret) { 1152 case -EAGAIN: 1153 /* ccw chain, continue processing */ 1154 break; 1155 case 0: 1156 /* success */ 1157 s->ctrl &= ~SCSW_ACTL_START_PEND; 1158 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 1159 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1160 SCSW_STCTL_STATUS_PEND; 1161 s->dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END; 1162 s->cpa = sch->channel_prog + 8; 1163 break; 1164 case -EIO: 1165 /* I/O errors, status depends on specific devices */ 1166 break; 1167 case -ENOSYS: 1168 /* unsupported command, generate unit check (command reject) */ 1169 s->ctrl &= ~SCSW_ACTL_START_PEND; 1170 s->dstat = SCSW_DSTAT_UNIT_CHECK; 1171 /* Set sense bit 0 in ecw0. */ 1172 sch->sense_data[0] = 0x80; 1173 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 1174 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1175 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 1176 s->cpa = sch->channel_prog + 8; 1177 break; 1178 case -EINPROGRESS: 1179 /* channel program has been suspended */ 1180 s->ctrl &= ~SCSW_ACTL_START_PEND; 1181 s->ctrl |= SCSW_ACTL_SUSP; 1182 break; 1183 default: 1184 /* error, generate channel program check */ 1185 s->ctrl &= ~SCSW_ACTL_START_PEND; 1186 s->cstat = SCSW_CSTAT_PROG_CHECK; 1187 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 1188 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1189 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 1190 s->cpa = sch->channel_prog + 8; 1191 break; 1192 } 1193 } while (ret == -EAGAIN); 1194 1195 } 1196 1197 static IOInstEnding sch_handle_start_func_passthrough(SubchDev *sch) 1198 { 1199 1200 PMCW *p = &sch->curr_status.pmcw; 1201 SCSW *s = &sch->curr_status.scsw; 1202 1203 ORB *orb = &sch->orb; 1204 if (!(s->ctrl & SCSW_ACTL_SUSP)) { 1205 assert(orb != NULL); 1206 p->intparm = orb->intparm; 1207 } 1208 return s390_ccw_cmd_request(sch); 1209 } 1210 1211 /* 1212 * On real machines, this would run asynchronously to the main vcpus. 1213 * We might want to make some parts of the ssch handling (interpreting 1214 * read/writes) asynchronous later on if we start supporting more than 1215 * our current very simple devices. 1216 */ 1217 IOInstEnding do_subchannel_work_virtual(SubchDev *sch) 1218 { 1219 1220 SCSW *s = &sch->curr_status.scsw; 1221 1222 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) { 1223 sch_handle_clear_func(sch); 1224 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) { 1225 sch_handle_halt_func(sch); 1226 } else if (s->ctrl & SCSW_FCTL_START_FUNC) { 1227 /* Triggered by both ssch and rsch. */ 1228 sch_handle_start_func_virtual(sch); 1229 } 1230 css_inject_io_interrupt(sch); 1231 /* inst must succeed if this func is called */ 1232 return IOINST_CC_EXPECTED; 1233 } 1234 1235 IOInstEnding do_subchannel_work_passthrough(SubchDev *sch) 1236 { 1237 SCSW *s = &sch->curr_status.scsw; 1238 1239 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) { 1240 /* TODO: Clear handling */ 1241 sch_handle_clear_func(sch); 1242 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) { 1243 /* TODO: Halt handling */ 1244 sch_handle_halt_func(sch); 1245 } else if (s->ctrl & SCSW_FCTL_START_FUNC) { 1246 return sch_handle_start_func_passthrough(sch); 1247 } 1248 return IOINST_CC_EXPECTED; 1249 } 1250 1251 static IOInstEnding do_subchannel_work(SubchDev *sch) 1252 { 1253 if (!sch->do_subchannel_work) { 1254 return IOINST_CC_STATUS_PRESENT; 1255 } 1256 g_assert(sch->curr_status.scsw.ctrl & SCSW_CTRL_MASK_FCTL); 1257 return sch->do_subchannel_work(sch); 1258 } 1259 1260 static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src) 1261 { 1262 int i; 1263 1264 dest->intparm = cpu_to_be32(src->intparm); 1265 dest->flags = cpu_to_be16(src->flags); 1266 dest->devno = cpu_to_be16(src->devno); 1267 dest->lpm = src->lpm; 1268 dest->pnom = src->pnom; 1269 dest->lpum = src->lpum; 1270 dest->pim = src->pim; 1271 dest->mbi = cpu_to_be16(src->mbi); 1272 dest->pom = src->pom; 1273 dest->pam = src->pam; 1274 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 1275 dest->chpid[i] = src->chpid[i]; 1276 } 1277 dest->chars = cpu_to_be32(src->chars); 1278 } 1279 1280 void copy_scsw_to_guest(SCSW *dest, const SCSW *src) 1281 { 1282 dest->flags = cpu_to_be16(src->flags); 1283 dest->ctrl = cpu_to_be16(src->ctrl); 1284 dest->cpa = cpu_to_be32(src->cpa); 1285 dest->dstat = src->dstat; 1286 dest->cstat = src->cstat; 1287 dest->count = cpu_to_be16(src->count); 1288 } 1289 1290 static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src) 1291 { 1292 int i; 1293 1294 copy_pmcw_to_guest(&dest->pmcw, &src->pmcw); 1295 copy_scsw_to_guest(&dest->scsw, &src->scsw); 1296 dest->mba = cpu_to_be64(src->mba); 1297 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 1298 dest->mda[i] = src->mda[i]; 1299 } 1300 } 1301 1302 int css_do_stsch(SubchDev *sch, SCHIB *schib) 1303 { 1304 /* Use current status. */ 1305 copy_schib_to_guest(schib, &sch->curr_status); 1306 return 0; 1307 } 1308 1309 static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src) 1310 { 1311 int i; 1312 1313 dest->intparm = be32_to_cpu(src->intparm); 1314 dest->flags = be16_to_cpu(src->flags); 1315 dest->devno = be16_to_cpu(src->devno); 1316 dest->lpm = src->lpm; 1317 dest->pnom = src->pnom; 1318 dest->lpum = src->lpum; 1319 dest->pim = src->pim; 1320 dest->mbi = be16_to_cpu(src->mbi); 1321 dest->pom = src->pom; 1322 dest->pam = src->pam; 1323 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 1324 dest->chpid[i] = src->chpid[i]; 1325 } 1326 dest->chars = be32_to_cpu(src->chars); 1327 } 1328 1329 static void copy_scsw_from_guest(SCSW *dest, const SCSW *src) 1330 { 1331 dest->flags = be16_to_cpu(src->flags); 1332 dest->ctrl = be16_to_cpu(src->ctrl); 1333 dest->cpa = be32_to_cpu(src->cpa); 1334 dest->dstat = src->dstat; 1335 dest->cstat = src->cstat; 1336 dest->count = be16_to_cpu(src->count); 1337 } 1338 1339 static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src) 1340 { 1341 int i; 1342 1343 copy_pmcw_from_guest(&dest->pmcw, &src->pmcw); 1344 copy_scsw_from_guest(&dest->scsw, &src->scsw); 1345 dest->mba = be64_to_cpu(src->mba); 1346 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 1347 dest->mda[i] = src->mda[i]; 1348 } 1349 } 1350 1351 IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *orig_schib) 1352 { 1353 SCSW *s = &sch->curr_status.scsw; 1354 PMCW *p = &sch->curr_status.pmcw; 1355 uint16_t oldflags; 1356 SCHIB schib; 1357 1358 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_DNV)) { 1359 return IOINST_CC_EXPECTED; 1360 } 1361 1362 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 1363 return IOINST_CC_STATUS_PRESENT; 1364 } 1365 1366 if (s->ctrl & 1367 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) { 1368 return IOINST_CC_BUSY; 1369 } 1370 1371 copy_schib_from_guest(&schib, orig_schib); 1372 /* Only update the program-modifiable fields. */ 1373 p->intparm = schib.pmcw.intparm; 1374 oldflags = p->flags; 1375 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1376 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1377 PMCW_FLAGS_MASK_MP); 1378 p->flags |= schib.pmcw.flags & 1379 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1380 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1381 PMCW_FLAGS_MASK_MP); 1382 p->lpm = schib.pmcw.lpm; 1383 p->mbi = schib.pmcw.mbi; 1384 p->pom = schib.pmcw.pom; 1385 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 1386 p->chars |= schib.pmcw.chars & 1387 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 1388 sch->curr_status.mba = schib.mba; 1389 1390 /* Has the channel been disabled? */ 1391 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0 1392 && (p->flags & PMCW_FLAGS_MASK_ENA) == 0) { 1393 sch->disable_cb(sch); 1394 } 1395 return IOINST_CC_EXPECTED; 1396 } 1397 1398 IOInstEnding css_do_xsch(SubchDev *sch) 1399 { 1400 SCSW *s = &sch->curr_status.scsw; 1401 PMCW *p = &sch->curr_status.pmcw; 1402 1403 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1404 return IOINST_CC_NOT_OPERATIONAL; 1405 } 1406 1407 if (s->ctrl & SCSW_CTRL_MASK_STCTL) { 1408 return IOINST_CC_STATUS_PRESENT; 1409 } 1410 1411 if (!(s->ctrl & SCSW_CTRL_MASK_FCTL) || 1412 ((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1413 (!(s->ctrl & 1414 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) || 1415 (s->ctrl & SCSW_ACTL_SUBCH_ACTIVE)) { 1416 return IOINST_CC_BUSY; 1417 } 1418 1419 /* Cancel the current operation. */ 1420 s->ctrl &= ~(SCSW_FCTL_START_FUNC | 1421 SCSW_ACTL_RESUME_PEND | 1422 SCSW_ACTL_START_PEND | 1423 SCSW_ACTL_SUSP); 1424 sch->channel_prog = 0x0; 1425 sch->last_cmd_valid = false; 1426 s->dstat = 0; 1427 s->cstat = 0; 1428 return IOINST_CC_EXPECTED; 1429 } 1430 1431 IOInstEnding css_do_csch(SubchDev *sch) 1432 { 1433 SCSW *s = &sch->curr_status.scsw; 1434 PMCW *p = &sch->curr_status.pmcw; 1435 1436 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1437 return IOINST_CC_NOT_OPERATIONAL; 1438 } 1439 1440 /* Trigger the clear function. */ 1441 s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL); 1442 s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND; 1443 1444 return do_subchannel_work(sch); 1445 } 1446 1447 IOInstEnding css_do_hsch(SubchDev *sch) 1448 { 1449 SCSW *s = &sch->curr_status.scsw; 1450 PMCW *p = &sch->curr_status.pmcw; 1451 1452 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1453 return IOINST_CC_NOT_OPERATIONAL; 1454 } 1455 1456 if (((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) || 1457 (s->ctrl & (SCSW_STCTL_PRIMARY | 1458 SCSW_STCTL_SECONDARY | 1459 SCSW_STCTL_ALERT))) { 1460 return IOINST_CC_STATUS_PRESENT; 1461 } 1462 1463 if (s->ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) { 1464 return IOINST_CC_BUSY; 1465 } 1466 1467 /* Trigger the halt function. */ 1468 s->ctrl |= SCSW_FCTL_HALT_FUNC; 1469 s->ctrl &= ~SCSW_FCTL_START_FUNC; 1470 if (((s->ctrl & SCSW_CTRL_MASK_ACTL) == 1471 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) && 1472 ((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_INTERMEDIATE)) { 1473 s->ctrl &= ~SCSW_STCTL_STATUS_PEND; 1474 } 1475 s->ctrl |= SCSW_ACTL_HALT_PEND; 1476 1477 return do_subchannel_work(sch); 1478 } 1479 1480 static void css_update_chnmon(SubchDev *sch) 1481 { 1482 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) { 1483 /* Not active. */ 1484 return; 1485 } 1486 /* The counter is conveniently located at the beginning of the struct. */ 1487 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) { 1488 /* Format 1, per-subchannel area. */ 1489 uint32_t count; 1490 1491 count = address_space_ldl(&address_space_memory, 1492 sch->curr_status.mba, 1493 MEMTXATTRS_UNSPECIFIED, 1494 NULL); 1495 count++; 1496 address_space_stl(&address_space_memory, sch->curr_status.mba, count, 1497 MEMTXATTRS_UNSPECIFIED, NULL); 1498 } else { 1499 /* Format 0, global area. */ 1500 uint32_t offset; 1501 uint16_t count; 1502 1503 offset = sch->curr_status.pmcw.mbi << 5; 1504 count = address_space_lduw(&address_space_memory, 1505 channel_subsys.chnmon_area + offset, 1506 MEMTXATTRS_UNSPECIFIED, 1507 NULL); 1508 count++; 1509 address_space_stw(&address_space_memory, 1510 channel_subsys.chnmon_area + offset, count, 1511 MEMTXATTRS_UNSPECIFIED, NULL); 1512 } 1513 } 1514 1515 IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb) 1516 { 1517 SCSW *s = &sch->curr_status.scsw; 1518 PMCW *p = &sch->curr_status.pmcw; 1519 1520 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1521 return IOINST_CC_NOT_OPERATIONAL; 1522 } 1523 1524 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 1525 return IOINST_CC_STATUS_PRESENT; 1526 } 1527 1528 if (s->ctrl & (SCSW_FCTL_START_FUNC | 1529 SCSW_FCTL_HALT_FUNC | 1530 SCSW_FCTL_CLEAR_FUNC)) { 1531 return IOINST_CC_BUSY; 1532 } 1533 1534 /* If monitoring is active, update counter. */ 1535 if (channel_subsys.chnmon_active) { 1536 css_update_chnmon(sch); 1537 } 1538 sch->orb = *orb; 1539 sch->channel_prog = orb->cpa; 1540 /* Trigger the start function. */ 1541 s->ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND); 1542 s->flags &= ~SCSW_FLAGS_MASK_PNO; 1543 1544 return do_subchannel_work(sch); 1545 } 1546 1547 static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw, 1548 int *irb_len) 1549 { 1550 int i; 1551 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1552 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 1553 1554 copy_scsw_to_guest(&dest->scsw, &src->scsw); 1555 1556 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) { 1557 dest->esw[i] = cpu_to_be32(src->esw[i]); 1558 } 1559 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) { 1560 dest->ecw[i] = cpu_to_be32(src->ecw[i]); 1561 } 1562 *irb_len = sizeof(*dest) - sizeof(dest->emw); 1563 1564 /* extended measurements enabled? */ 1565 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) || 1566 !(pmcw->flags & PMCW_FLAGS_MASK_TF) || 1567 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) { 1568 return; 1569 } 1570 /* extended measurements pending? */ 1571 if (!(stctl & SCSW_STCTL_STATUS_PEND)) { 1572 return; 1573 } 1574 if ((stctl & SCSW_STCTL_PRIMARY) || 1575 (stctl == SCSW_STCTL_SECONDARY) || 1576 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) { 1577 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) { 1578 dest->emw[i] = cpu_to_be32(src->emw[i]); 1579 } 1580 } 1581 *irb_len = sizeof(*dest); 1582 } 1583 1584 int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len) 1585 { 1586 SCSW *s = &sch->curr_status.scsw; 1587 PMCW *p = &sch->curr_status.pmcw; 1588 uint16_t stctl; 1589 IRB irb; 1590 1591 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1592 return 3; 1593 } 1594 1595 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL; 1596 1597 /* Prepare the irb for the guest. */ 1598 memset(&irb, 0, sizeof(IRB)); 1599 1600 /* Copy scsw from current status. */ 1601 memcpy(&irb.scsw, s, sizeof(SCSW)); 1602 if (stctl & SCSW_STCTL_STATUS_PEND) { 1603 if (s->cstat & (SCSW_CSTAT_DATA_CHECK | 1604 SCSW_CSTAT_CHN_CTRL_CHK | 1605 SCSW_CSTAT_INTF_CTRL_CHK)) { 1606 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF; 1607 irb.esw[0] = 0x04804000; 1608 } else { 1609 irb.esw[0] = 0x00800000; 1610 } 1611 /* If a unit check is pending, copy sense data. */ 1612 if ((s->dstat & SCSW_DSTAT_UNIT_CHECK) && 1613 (p->chars & PMCW_CHARS_MASK_CSENSE)) { 1614 int i; 1615 1616 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL; 1617 /* Attention: sense_data is already BE! */ 1618 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data)); 1619 for (i = 0; i < ARRAY_SIZE(irb.ecw); i++) { 1620 irb.ecw[i] = be32_to_cpu(irb.ecw[i]); 1621 } 1622 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8); 1623 } 1624 } 1625 /* Store the irb to the guest. */ 1626 copy_irb_to_guest(target_irb, &irb, p, irb_len); 1627 1628 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0); 1629 } 1630 1631 void css_do_tsch_update_subch(SubchDev *sch) 1632 { 1633 SCSW *s = &sch->curr_status.scsw; 1634 PMCW *p = &sch->curr_status.pmcw; 1635 uint16_t stctl; 1636 uint16_t fctl; 1637 uint16_t actl; 1638 1639 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL; 1640 fctl = s->ctrl & SCSW_CTRL_MASK_FCTL; 1641 actl = s->ctrl & SCSW_CTRL_MASK_ACTL; 1642 1643 /* Clear conditions on subchannel, if applicable. */ 1644 if (stctl & SCSW_STCTL_STATUS_PEND) { 1645 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 1646 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) || 1647 ((fctl & SCSW_FCTL_HALT_FUNC) && 1648 (actl & SCSW_ACTL_SUSP))) { 1649 s->ctrl &= ~SCSW_CTRL_MASK_FCTL; 1650 } 1651 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) { 1652 s->flags &= ~SCSW_FLAGS_MASK_PNO; 1653 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 1654 SCSW_ACTL_START_PEND | 1655 SCSW_ACTL_HALT_PEND | 1656 SCSW_ACTL_CLEAR_PEND | 1657 SCSW_ACTL_SUSP); 1658 } else { 1659 if ((actl & SCSW_ACTL_SUSP) && 1660 (fctl & SCSW_FCTL_START_FUNC)) { 1661 s->flags &= ~SCSW_FLAGS_MASK_PNO; 1662 if (fctl & SCSW_FCTL_HALT_FUNC) { 1663 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 1664 SCSW_ACTL_START_PEND | 1665 SCSW_ACTL_HALT_PEND | 1666 SCSW_ACTL_CLEAR_PEND | 1667 SCSW_ACTL_SUSP); 1668 } else { 1669 s->ctrl &= ~SCSW_ACTL_RESUME_PEND; 1670 } 1671 } 1672 } 1673 /* Clear pending sense data. */ 1674 if (p->chars & PMCW_CHARS_MASK_CSENSE) { 1675 memset(sch->sense_data, 0 , sizeof(sch->sense_data)); 1676 } 1677 } 1678 } 1679 1680 static void copy_crw_to_guest(CRW *dest, const CRW *src) 1681 { 1682 dest->flags = cpu_to_be16(src->flags); 1683 dest->rsid = cpu_to_be16(src->rsid); 1684 } 1685 1686 int css_do_stcrw(CRW *crw) 1687 { 1688 CrwContainer *crw_cont; 1689 int ret; 1690 1691 crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws); 1692 if (crw_cont) { 1693 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling); 1694 copy_crw_to_guest(crw, &crw_cont->crw); 1695 g_free(crw_cont); 1696 ret = 0; 1697 } else { 1698 /* List was empty, turn crw machine checks on again. */ 1699 memset(crw, 0, sizeof(*crw)); 1700 channel_subsys.do_crw_mchk = true; 1701 ret = 1; 1702 } 1703 1704 return ret; 1705 } 1706 1707 static void copy_crw_from_guest(CRW *dest, const CRW *src) 1708 { 1709 dest->flags = be16_to_cpu(src->flags); 1710 dest->rsid = be16_to_cpu(src->rsid); 1711 } 1712 1713 void css_undo_stcrw(CRW *crw) 1714 { 1715 CrwContainer *crw_cont; 1716 1717 crw_cont = g_try_new0(CrwContainer, 1); 1718 if (!crw_cont) { 1719 channel_subsys.crws_lost = true; 1720 return; 1721 } 1722 copy_crw_from_guest(&crw_cont->crw, crw); 1723 1724 QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling); 1725 } 1726 1727 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, 1728 int rfmt, void *buf) 1729 { 1730 int i, desc_size; 1731 uint32_t words[8]; 1732 uint32_t chpid_type_word; 1733 CssImage *css; 1734 1735 if (!m && !cssid) { 1736 css = channel_subsys.css[channel_subsys.default_cssid]; 1737 } else { 1738 css = channel_subsys.css[cssid]; 1739 } 1740 if (!css) { 1741 return 0; 1742 } 1743 desc_size = 0; 1744 for (i = f_chpid; i <= l_chpid; i++) { 1745 if (css->chpids[i].in_use) { 1746 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i; 1747 if (rfmt == 0) { 1748 words[0] = cpu_to_be32(chpid_type_word); 1749 words[1] = 0; 1750 memcpy(buf + desc_size, words, 8); 1751 desc_size += 8; 1752 } else if (rfmt == 1) { 1753 words[0] = cpu_to_be32(chpid_type_word); 1754 words[1] = 0; 1755 words[2] = 0; 1756 words[3] = 0; 1757 words[4] = 0; 1758 words[5] = 0; 1759 words[6] = 0; 1760 words[7] = 0; 1761 memcpy(buf + desc_size, words, 32); 1762 desc_size += 32; 1763 } 1764 } 1765 } 1766 return desc_size; 1767 } 1768 1769 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo) 1770 { 1771 /* dct is currently ignored (not really meaningful for our devices) */ 1772 /* TODO: Don't ignore mbk. */ 1773 if (update && !channel_subsys.chnmon_active) { 1774 /* Enable measuring. */ 1775 channel_subsys.chnmon_area = mbo; 1776 channel_subsys.chnmon_active = true; 1777 } 1778 if (!update && channel_subsys.chnmon_active) { 1779 /* Disable measuring. */ 1780 channel_subsys.chnmon_area = 0; 1781 channel_subsys.chnmon_active = false; 1782 } 1783 } 1784 1785 IOInstEnding css_do_rsch(SubchDev *sch) 1786 { 1787 SCSW *s = &sch->curr_status.scsw; 1788 PMCW *p = &sch->curr_status.pmcw; 1789 1790 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1791 return IOINST_CC_NOT_OPERATIONAL; 1792 } 1793 1794 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 1795 return IOINST_CC_STATUS_PRESENT; 1796 } 1797 1798 if (((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1799 (s->ctrl & SCSW_ACTL_RESUME_PEND) || 1800 (!(s->ctrl & SCSW_ACTL_SUSP))) { 1801 return IOINST_CC_BUSY; 1802 } 1803 1804 /* If monitoring is active, update counter. */ 1805 if (channel_subsys.chnmon_active) { 1806 css_update_chnmon(sch); 1807 } 1808 1809 s->ctrl |= SCSW_ACTL_RESUME_PEND; 1810 return do_subchannel_work(sch); 1811 } 1812 1813 int css_do_rchp(uint8_t cssid, uint8_t chpid) 1814 { 1815 uint8_t real_cssid; 1816 1817 if (cssid > channel_subsys.max_cssid) { 1818 return -EINVAL; 1819 } 1820 if (channel_subsys.max_cssid == 0) { 1821 real_cssid = channel_subsys.default_cssid; 1822 } else { 1823 real_cssid = cssid; 1824 } 1825 if (!channel_subsys.css[real_cssid]) { 1826 return -EINVAL; 1827 } 1828 1829 if (!channel_subsys.css[real_cssid]->chpids[chpid].in_use) { 1830 return -ENODEV; 1831 } 1832 1833 if (!channel_subsys.css[real_cssid]->chpids[chpid].is_virtual) { 1834 fprintf(stderr, 1835 "rchp unsupported for non-virtual chpid %x.%02x!\n", 1836 real_cssid, chpid); 1837 return -ENODEV; 1838 } 1839 1840 /* We don't really use a channel path, so we're done here. */ 1841 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 1842 channel_subsys.max_cssid > 0 ? 1 : 0, chpid); 1843 if (channel_subsys.max_cssid > 0) { 1844 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 0, real_cssid << 8); 1845 } 1846 return 0; 1847 } 1848 1849 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1850 { 1851 SubchSet *set; 1852 uint8_t real_cssid; 1853 1854 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid; 1855 if (ssid > MAX_SSID || 1856 !channel_subsys.css[real_cssid] || 1857 !channel_subsys.css[real_cssid]->sch_set[ssid]) { 1858 return true; 1859 } 1860 set = channel_subsys.css[real_cssid]->sch_set[ssid]; 1861 return schid > find_last_bit(set->schids_used, 1862 (MAX_SCHID + 1) / sizeof(unsigned long)); 1863 } 1864 1865 unsigned int css_find_free_chpid(uint8_t cssid) 1866 { 1867 CssImage *css = channel_subsys.css[cssid]; 1868 unsigned int chpid; 1869 1870 if (!css) { 1871 return MAX_CHPID + 1; 1872 } 1873 1874 for (chpid = 0; chpid <= MAX_CHPID; chpid++) { 1875 /* skip reserved chpid */ 1876 if (chpid == VIRTIO_CCW_CHPID) { 1877 continue; 1878 } 1879 if (!css->chpids[chpid].in_use) { 1880 return chpid; 1881 } 1882 } 1883 return MAX_CHPID + 1; 1884 } 1885 1886 static int css_add_chpid(uint8_t cssid, uint8_t chpid, uint8_t type, 1887 bool is_virt) 1888 { 1889 CssImage *css; 1890 1891 trace_css_chpid_add(cssid, chpid, type); 1892 css = channel_subsys.css[cssid]; 1893 if (!css) { 1894 return -EINVAL; 1895 } 1896 if (css->chpids[chpid].in_use) { 1897 return -EEXIST; 1898 } 1899 css->chpids[chpid].in_use = 1; 1900 css->chpids[chpid].type = type; 1901 css->chpids[chpid].is_virtual = is_virt; 1902 1903 css_generate_chp_crws(cssid, chpid); 1904 1905 return 0; 1906 } 1907 1908 void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type) 1909 { 1910 PMCW *p = &sch->curr_status.pmcw; 1911 SCSW *s = &sch->curr_status.scsw; 1912 int i; 1913 CssImage *css = channel_subsys.css[sch->cssid]; 1914 1915 assert(css != NULL); 1916 memset(p, 0, sizeof(PMCW)); 1917 p->flags |= PMCW_FLAGS_MASK_DNV; 1918 p->devno = sch->devno; 1919 /* single path */ 1920 p->pim = 0x80; 1921 p->pom = 0xff; 1922 p->pam = 0x80; 1923 p->chpid[0] = chpid; 1924 if (!css->chpids[chpid].in_use) { 1925 css_add_chpid(sch->cssid, chpid, type, true); 1926 } 1927 1928 memset(s, 0, sizeof(SCSW)); 1929 sch->curr_status.mba = 0; 1930 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) { 1931 sch->curr_status.mda[i] = 0; 1932 } 1933 } 1934 1935 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1936 { 1937 uint8_t real_cssid; 1938 1939 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid; 1940 1941 if (!channel_subsys.css[real_cssid]) { 1942 return NULL; 1943 } 1944 1945 if (!channel_subsys.css[real_cssid]->sch_set[ssid]) { 1946 return NULL; 1947 } 1948 1949 return channel_subsys.css[real_cssid]->sch_set[ssid]->sch[schid]; 1950 } 1951 1952 /** 1953 * Return free device number in subchannel set. 1954 * 1955 * Return index of the first free device number in the subchannel set 1956 * identified by @p cssid and @p ssid, beginning the search at @p 1957 * start and wrapping around at MAX_DEVNO. Return a value exceeding 1958 * MAX_SCHID if there are no free device numbers in the subchannel 1959 * set. 1960 */ 1961 static uint32_t css_find_free_devno(uint8_t cssid, uint8_t ssid, 1962 uint16_t start) 1963 { 1964 uint32_t round; 1965 1966 for (round = 0; round <= MAX_DEVNO; round++) { 1967 uint16_t devno = (start + round) % MAX_DEVNO; 1968 1969 if (!css_devno_used(cssid, ssid, devno)) { 1970 return devno; 1971 } 1972 } 1973 return MAX_DEVNO + 1; 1974 } 1975 1976 /** 1977 * Return first free subchannel (id) in subchannel set. 1978 * 1979 * Return index of the first free subchannel in the subchannel set 1980 * identified by @p cssid and @p ssid, if there is any. Return a value 1981 * exceeding MAX_SCHID if there are no free subchannels in the 1982 * subchannel set. 1983 */ 1984 static uint32_t css_find_free_subch(uint8_t cssid, uint8_t ssid) 1985 { 1986 uint32_t schid; 1987 1988 for (schid = 0; schid <= MAX_SCHID; schid++) { 1989 if (!css_find_subch(1, cssid, ssid, schid)) { 1990 return schid; 1991 } 1992 } 1993 return MAX_SCHID + 1; 1994 } 1995 1996 /** 1997 * Return first free subchannel (id) in subchannel set for a device number 1998 * 1999 * Verify the device number @p devno is not used yet in the subchannel 2000 * set identified by @p cssid and @p ssid. Set @p schid to the index 2001 * of the first free subchannel in the subchannel set, if there is 2002 * any. Return true if everything succeeded and false otherwise. 2003 */ 2004 static bool css_find_free_subch_for_devno(uint8_t cssid, uint8_t ssid, 2005 uint16_t devno, uint16_t *schid, 2006 Error **errp) 2007 { 2008 uint32_t free_schid; 2009 2010 assert(schid); 2011 if (css_devno_used(cssid, ssid, devno)) { 2012 error_setg(errp, "Device %x.%x.%04x already exists", 2013 cssid, ssid, devno); 2014 return false; 2015 } 2016 free_schid = css_find_free_subch(cssid, ssid); 2017 if (free_schid > MAX_SCHID) { 2018 error_setg(errp, "No free subchannel found for %x.%x.%04x", 2019 cssid, ssid, devno); 2020 return false; 2021 } 2022 *schid = free_schid; 2023 return true; 2024 } 2025 2026 /** 2027 * Return first free subchannel (id) and device number 2028 * 2029 * Locate the first free subchannel and first free device number in 2030 * any of the subchannel sets of the channel subsystem identified by 2031 * @p cssid. Return false if no free subchannel / device number could 2032 * be found. Otherwise set @p ssid, @p devno and @p schid to identify 2033 * the available subchannel and device number and return true. 2034 * 2035 * May modify @p ssid, @p devno and / or @p schid even if no free 2036 * subchannel / device number could be found. 2037 */ 2038 static bool css_find_free_subch_and_devno(uint8_t cssid, uint8_t *ssid, 2039 uint16_t *devno, uint16_t *schid, 2040 Error **errp) 2041 { 2042 uint32_t free_schid, free_devno; 2043 2044 assert(ssid && devno && schid); 2045 for (*ssid = 0; *ssid <= MAX_SSID; (*ssid)++) { 2046 free_schid = css_find_free_subch(cssid, *ssid); 2047 if (free_schid > MAX_SCHID) { 2048 continue; 2049 } 2050 free_devno = css_find_free_devno(cssid, *ssid, free_schid); 2051 if (free_devno > MAX_DEVNO) { 2052 continue; 2053 } 2054 *schid = free_schid; 2055 *devno = free_devno; 2056 return true; 2057 } 2058 error_setg(errp, "Virtual channel subsystem is full!"); 2059 return false; 2060 } 2061 2062 bool css_subch_visible(SubchDev *sch) 2063 { 2064 if (sch->ssid > channel_subsys.max_ssid) { 2065 return false; 2066 } 2067 2068 if (sch->cssid != channel_subsys.default_cssid) { 2069 return (channel_subsys.max_cssid > 0); 2070 } 2071 2072 return true; 2073 } 2074 2075 bool css_present(uint8_t cssid) 2076 { 2077 return (channel_subsys.css[cssid] != NULL); 2078 } 2079 2080 bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno) 2081 { 2082 if (!channel_subsys.css[cssid]) { 2083 return false; 2084 } 2085 if (!channel_subsys.css[cssid]->sch_set[ssid]) { 2086 return false; 2087 } 2088 2089 return !!test_bit(devno, 2090 channel_subsys.css[cssid]->sch_set[ssid]->devnos_used); 2091 } 2092 2093 void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid, 2094 uint16_t devno, SubchDev *sch) 2095 { 2096 CssImage *css; 2097 SubchSet *s_set; 2098 2099 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid, 2100 devno); 2101 if (!channel_subsys.css[cssid]) { 2102 fprintf(stderr, 2103 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n", 2104 __func__, cssid, ssid, schid); 2105 return; 2106 } 2107 css = channel_subsys.css[cssid]; 2108 2109 if (!css->sch_set[ssid]) { 2110 css->sch_set[ssid] = g_new0(SubchSet, 1); 2111 } 2112 s_set = css->sch_set[ssid]; 2113 2114 s_set->sch[schid] = sch; 2115 if (sch) { 2116 set_bit(schid, s_set->schids_used); 2117 set_bit(devno, s_set->devnos_used); 2118 } else { 2119 clear_bit(schid, s_set->schids_used); 2120 clear_bit(devno, s_set->devnos_used); 2121 } 2122 } 2123 2124 void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited, 2125 int chain, uint16_t rsid) 2126 { 2127 CrwContainer *crw_cont; 2128 2129 trace_css_crw(rsc, erc, rsid, chain ? "(chained)" : ""); 2130 /* TODO: Maybe use a static crw pool? */ 2131 crw_cont = g_try_new0(CrwContainer, 1); 2132 if (!crw_cont) { 2133 channel_subsys.crws_lost = true; 2134 return; 2135 } 2136 crw_cont->crw.flags = (rsc << 8) | erc; 2137 if (solicited) { 2138 crw_cont->crw.flags |= CRW_FLAGS_MASK_S; 2139 } 2140 if (chain) { 2141 crw_cont->crw.flags |= CRW_FLAGS_MASK_C; 2142 } 2143 crw_cont->crw.rsid = rsid; 2144 if (channel_subsys.crws_lost) { 2145 crw_cont->crw.flags |= CRW_FLAGS_MASK_R; 2146 channel_subsys.crws_lost = false; 2147 } 2148 2149 QTAILQ_INSERT_TAIL(&channel_subsys.pending_crws, crw_cont, sibling); 2150 2151 if (channel_subsys.do_crw_mchk) { 2152 channel_subsys.do_crw_mchk = false; 2153 /* Inject crw pending machine check. */ 2154 s390_crw_mchk(); 2155 } 2156 } 2157 2158 void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid, 2159 int hotplugged, int add) 2160 { 2161 uint8_t guest_cssid; 2162 bool chain_crw; 2163 2164 if (add && !hotplugged) { 2165 return; 2166 } 2167 if (channel_subsys.max_cssid == 0) { 2168 /* Default cssid shows up as 0. */ 2169 guest_cssid = (cssid == channel_subsys.default_cssid) ? 0 : cssid; 2170 } else { 2171 /* Show real cssid to the guest. */ 2172 guest_cssid = cssid; 2173 } 2174 /* 2175 * Only notify for higher subchannel sets/channel subsystems if the 2176 * guest has enabled it. 2177 */ 2178 if ((ssid > channel_subsys.max_ssid) || 2179 (guest_cssid > channel_subsys.max_cssid) || 2180 ((channel_subsys.max_cssid == 0) && 2181 (cssid != channel_subsys.default_cssid))) { 2182 return; 2183 } 2184 chain_crw = (channel_subsys.max_ssid > 0) || 2185 (channel_subsys.max_cssid > 0); 2186 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, chain_crw ? 1 : 0, schid); 2187 if (chain_crw) { 2188 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 0, 2189 (guest_cssid << 8) | (ssid << 4)); 2190 } 2191 /* RW_ERC_IPI --> clear pending interrupts */ 2192 css_clear_io_interrupt(css_do_build_subchannel_id(cssid, ssid), schid); 2193 } 2194 2195 void css_generate_chp_crws(uint8_t cssid, uint8_t chpid) 2196 { 2197 /* TODO */ 2198 } 2199 2200 void css_generate_css_crws(uint8_t cssid) 2201 { 2202 if (!channel_subsys.sei_pending) { 2203 css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, 0, cssid); 2204 } 2205 channel_subsys.sei_pending = true; 2206 } 2207 2208 void css_clear_sei_pending(void) 2209 { 2210 channel_subsys.sei_pending = false; 2211 } 2212 2213 int css_enable_mcsse(void) 2214 { 2215 trace_css_enable_facility("mcsse"); 2216 channel_subsys.max_cssid = MAX_CSSID; 2217 return 0; 2218 } 2219 2220 int css_enable_mss(void) 2221 { 2222 trace_css_enable_facility("mss"); 2223 channel_subsys.max_ssid = MAX_SSID; 2224 return 0; 2225 } 2226 2227 void css_reset_sch(SubchDev *sch) 2228 { 2229 PMCW *p = &sch->curr_status.pmcw; 2230 2231 if ((p->flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) { 2232 sch->disable_cb(sch); 2233 } 2234 2235 p->intparm = 0; 2236 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 2237 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 2238 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF); 2239 p->flags |= PMCW_FLAGS_MASK_DNV; 2240 p->devno = sch->devno; 2241 p->pim = 0x80; 2242 p->lpm = p->pim; 2243 p->pnom = 0; 2244 p->lpum = 0; 2245 p->mbi = 0; 2246 p->pom = 0xff; 2247 p->pam = 0x80; 2248 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME | 2249 PMCW_CHARS_MASK_CSENSE); 2250 2251 memset(&sch->curr_status.scsw, 0, sizeof(sch->curr_status.scsw)); 2252 sch->curr_status.mba = 0; 2253 2254 sch->channel_prog = 0x0; 2255 sch->last_cmd_valid = false; 2256 sch->thinint_active = false; 2257 } 2258 2259 void css_reset(void) 2260 { 2261 CrwContainer *crw_cont; 2262 2263 /* Clean up monitoring. */ 2264 channel_subsys.chnmon_active = false; 2265 channel_subsys.chnmon_area = 0; 2266 2267 /* Clear pending CRWs. */ 2268 while ((crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws))) { 2269 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling); 2270 g_free(crw_cont); 2271 } 2272 channel_subsys.sei_pending = false; 2273 channel_subsys.do_crw_mchk = true; 2274 channel_subsys.crws_lost = false; 2275 2276 /* Reset maximum ids. */ 2277 channel_subsys.max_cssid = 0; 2278 channel_subsys.max_ssid = 0; 2279 } 2280 2281 static void get_css_devid(Object *obj, Visitor *v, const char *name, 2282 void *opaque, Error **errp) 2283 { 2284 DeviceState *dev = DEVICE(obj); 2285 Property *prop = opaque; 2286 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop); 2287 char buffer[] = "xx.x.xxxx"; 2288 char *p = buffer; 2289 int r; 2290 2291 if (dev_id->valid) { 2292 2293 r = snprintf(buffer, sizeof(buffer), "%02x.%1x.%04x", dev_id->cssid, 2294 dev_id->ssid, dev_id->devid); 2295 assert(r == sizeof(buffer) - 1); 2296 2297 /* drop leading zero */ 2298 if (dev_id->cssid <= 0xf) { 2299 p++; 2300 } 2301 } else { 2302 snprintf(buffer, sizeof(buffer), "<unset>"); 2303 } 2304 2305 visit_type_str(v, name, &p, errp); 2306 } 2307 2308 /* 2309 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid 2310 */ 2311 static void set_css_devid(Object *obj, Visitor *v, const char *name, 2312 void *opaque, Error **errp) 2313 { 2314 DeviceState *dev = DEVICE(obj); 2315 Property *prop = opaque; 2316 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop); 2317 Error *local_err = NULL; 2318 char *str; 2319 int num, n1, n2; 2320 unsigned int cssid, ssid, devid; 2321 2322 if (dev->realized) { 2323 qdev_prop_set_after_realize(dev, name, errp); 2324 return; 2325 } 2326 2327 visit_type_str(v, name, &str, &local_err); 2328 if (local_err) { 2329 error_propagate(errp, local_err); 2330 return; 2331 } 2332 2333 num = sscanf(str, "%2x.%1x%n.%4x%n", &cssid, &ssid, &n1, &devid, &n2); 2334 if (num != 3 || (n2 - n1) != 5 || strlen(str) != n2) { 2335 error_set_from_qdev_prop_error(errp, EINVAL, dev, prop, str); 2336 goto out; 2337 } 2338 if ((cssid > MAX_CSSID) || (ssid > MAX_SSID)) { 2339 error_setg(errp, "Invalid cssid or ssid: cssid %x, ssid %x", 2340 cssid, ssid); 2341 goto out; 2342 } 2343 2344 dev_id->cssid = cssid; 2345 dev_id->ssid = ssid; 2346 dev_id->devid = devid; 2347 dev_id->valid = true; 2348 2349 out: 2350 g_free(str); 2351 } 2352 2353 const PropertyInfo css_devid_propinfo = { 2354 .name = "str", 2355 .description = "Identifier of an I/O device in the channel " 2356 "subsystem, example: fe.1.23ab", 2357 .get = get_css_devid, 2358 .set = set_css_devid, 2359 }; 2360 2361 const PropertyInfo css_devid_ro_propinfo = { 2362 .name = "str", 2363 .description = "Read-only identifier of an I/O device in the channel " 2364 "subsystem, example: fe.1.23ab", 2365 .get = get_css_devid, 2366 }; 2367 2368 SubchDev *css_create_sch(CssDevId bus_id, Error **errp) 2369 { 2370 uint16_t schid = 0; 2371 SubchDev *sch; 2372 2373 if (bus_id.valid) { 2374 if (!channel_subsys.css[bus_id.cssid]) { 2375 css_create_css_image(bus_id.cssid, false); 2376 } 2377 2378 if (!css_find_free_subch_for_devno(bus_id.cssid, bus_id.ssid, 2379 bus_id.devid, &schid, errp)) { 2380 return NULL; 2381 } 2382 } else { 2383 for (bus_id.cssid = channel_subsys.default_cssid;;) { 2384 if (!channel_subsys.css[bus_id.cssid]) { 2385 css_create_css_image(bus_id.cssid, false); 2386 } 2387 2388 if (css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid, 2389 &bus_id.devid, &schid, 2390 NULL)) { 2391 break; 2392 } 2393 bus_id.cssid = (bus_id.cssid + 1) % MAX_CSSID; 2394 if (bus_id.cssid == channel_subsys.default_cssid) { 2395 error_setg(errp, "Virtual channel subsystem is full!"); 2396 return NULL; 2397 } 2398 } 2399 } 2400 2401 sch = g_new0(SubchDev, 1); 2402 sch->cssid = bus_id.cssid; 2403 sch->ssid = bus_id.ssid; 2404 sch->devno = bus_id.devid; 2405 sch->schid = schid; 2406 css_subch_assign(sch->cssid, sch->ssid, schid, sch->devno, sch); 2407 return sch; 2408 } 2409 2410 static int css_sch_get_chpids(SubchDev *sch, CssDevId *dev_id) 2411 { 2412 char *fid_path; 2413 FILE *fd; 2414 uint32_t chpid[8]; 2415 int i; 2416 PMCW *p = &sch->curr_status.pmcw; 2417 2418 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids", 2419 dev_id->cssid, dev_id->ssid, dev_id->devid); 2420 fd = fopen(fid_path, "r"); 2421 if (fd == NULL) { 2422 error_report("%s: open %s failed", __func__, fid_path); 2423 g_free(fid_path); 2424 return -EINVAL; 2425 } 2426 2427 if (fscanf(fd, "%x %x %x %x %x %x %x %x", 2428 &chpid[0], &chpid[1], &chpid[2], &chpid[3], 2429 &chpid[4], &chpid[5], &chpid[6], &chpid[7]) != 8) { 2430 fclose(fd); 2431 g_free(fid_path); 2432 return -EINVAL; 2433 } 2434 2435 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) { 2436 p->chpid[i] = chpid[i]; 2437 } 2438 2439 fclose(fd); 2440 g_free(fid_path); 2441 2442 return 0; 2443 } 2444 2445 static int css_sch_get_path_masks(SubchDev *sch, CssDevId *dev_id) 2446 { 2447 char *fid_path; 2448 FILE *fd; 2449 uint32_t pim, pam, pom; 2450 PMCW *p = &sch->curr_status.pmcw; 2451 2452 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom", 2453 dev_id->cssid, dev_id->ssid, dev_id->devid); 2454 fd = fopen(fid_path, "r"); 2455 if (fd == NULL) { 2456 error_report("%s: open %s failed", __func__, fid_path); 2457 g_free(fid_path); 2458 return -EINVAL; 2459 } 2460 2461 if (fscanf(fd, "%x %x %x", &pim, &pam, &pom) != 3) { 2462 fclose(fd); 2463 g_free(fid_path); 2464 return -EINVAL; 2465 } 2466 2467 p->pim = pim; 2468 p->pam = pam; 2469 p->pom = pom; 2470 fclose(fd); 2471 g_free(fid_path); 2472 2473 return 0; 2474 } 2475 2476 static int css_sch_get_chpid_type(uint8_t chpid, uint32_t *type, 2477 CssDevId *dev_id) 2478 { 2479 char *fid_path; 2480 FILE *fd; 2481 2482 fid_path = g_strdup_printf("/sys/devices/css%x/chp0.%02x/type", 2483 dev_id->cssid, chpid); 2484 fd = fopen(fid_path, "r"); 2485 if (fd == NULL) { 2486 error_report("%s: open %s failed", __func__, fid_path); 2487 g_free(fid_path); 2488 return -EINVAL; 2489 } 2490 2491 if (fscanf(fd, "%x", type) != 1) { 2492 fclose(fd); 2493 g_free(fid_path); 2494 return -EINVAL; 2495 } 2496 2497 fclose(fd); 2498 g_free(fid_path); 2499 2500 return 0; 2501 } 2502 2503 /* 2504 * We currently retrieve the real device information from sysfs to build the 2505 * guest subchannel information block without considering the migration feature. 2506 * We need to revisit this problem when we want to add migration support. 2507 */ 2508 int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id) 2509 { 2510 CssImage *css = channel_subsys.css[sch->cssid]; 2511 PMCW *p = &sch->curr_status.pmcw; 2512 SCSW *s = &sch->curr_status.scsw; 2513 uint32_t type; 2514 int i, ret; 2515 2516 assert(css != NULL); 2517 memset(p, 0, sizeof(PMCW)); 2518 p->flags |= PMCW_FLAGS_MASK_DNV; 2519 /* We are dealing with I/O subchannels only. */ 2520 p->devno = sch->devno; 2521 2522 /* Grab path mask from sysfs. */ 2523 ret = css_sch_get_path_masks(sch, dev_id); 2524 if (ret) { 2525 return ret; 2526 } 2527 2528 /* Grab chpids from sysfs. */ 2529 ret = css_sch_get_chpids(sch, dev_id); 2530 if (ret) { 2531 return ret; 2532 } 2533 2534 /* Build chpid type. */ 2535 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) { 2536 if (p->chpid[i] && !css->chpids[p->chpid[i]].in_use) { 2537 ret = css_sch_get_chpid_type(p->chpid[i], &type, dev_id); 2538 if (ret) { 2539 return ret; 2540 } 2541 css_add_chpid(sch->cssid, p->chpid[i], type, false); 2542 } 2543 } 2544 2545 memset(s, 0, sizeof(SCSW)); 2546 sch->curr_status.mba = 0; 2547 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) { 2548 sch->curr_status.mda[i] = 0; 2549 } 2550 2551 return 0; 2552 } 2553