1 /* 2 * Channel subsystem base support. 3 * 4 * Copyright 2012 IBM Corp. 5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or (at 8 * your option) any later version. See the COPYING file in the top-level 9 * directory. 10 */ 11 12 #include <hw/qdev.h> 13 #include "qemu/bitops.h" 14 #include "exec/address-spaces.h" 15 #include "cpu.h" 16 #include "ioinst.h" 17 #include "css.h" 18 #include "trace.h" 19 #include "hw/s390x/s390_flic.h" 20 21 typedef struct CrwContainer { 22 CRW crw; 23 QTAILQ_ENTRY(CrwContainer) sibling; 24 } CrwContainer; 25 26 typedef struct ChpInfo { 27 uint8_t in_use; 28 uint8_t type; 29 uint8_t is_virtual; 30 } ChpInfo; 31 32 typedef struct SubchSet { 33 SubchDev *sch[MAX_SCHID + 1]; 34 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 35 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 36 } SubchSet; 37 38 typedef struct CssImage { 39 SubchSet *sch_set[MAX_SSID + 1]; 40 ChpInfo chpids[MAX_CHPID + 1]; 41 } CssImage; 42 43 typedef struct IoAdapter { 44 uint32_t id; 45 uint8_t type; 46 uint8_t isc; 47 QTAILQ_ENTRY(IoAdapter) sibling; 48 } IoAdapter; 49 50 typedef struct ChannelSubSys { 51 QTAILQ_HEAD(, CrwContainer) pending_crws; 52 bool sei_pending; 53 bool do_crw_mchk; 54 bool crws_lost; 55 uint8_t max_cssid; 56 uint8_t max_ssid; 57 bool chnmon_active; 58 uint64_t chnmon_area; 59 CssImage *css[MAX_CSSID + 1]; 60 uint8_t default_cssid; 61 QTAILQ_HEAD(, IoAdapter) io_adapters; 62 } ChannelSubSys; 63 64 static ChannelSubSys *channel_subsys; 65 66 int css_create_css_image(uint8_t cssid, bool default_image) 67 { 68 trace_css_new_image(cssid, default_image ? "(default)" : ""); 69 if (cssid > MAX_CSSID) { 70 return -EINVAL; 71 } 72 if (channel_subsys->css[cssid]) { 73 return -EBUSY; 74 } 75 channel_subsys->css[cssid] = g_malloc0(sizeof(CssImage)); 76 if (default_image) { 77 channel_subsys->default_cssid = cssid; 78 } 79 return 0; 80 } 81 82 int css_register_io_adapter(uint8_t type, uint8_t isc, bool swap, 83 bool maskable, uint32_t *id) 84 { 85 IoAdapter *adapter; 86 bool found = false; 87 int ret; 88 S390FLICState *fs = s390_get_flic(); 89 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs); 90 91 *id = 0; 92 QTAILQ_FOREACH(adapter, &channel_subsys->io_adapters, sibling) { 93 if ((adapter->type == type) && (adapter->isc == isc)) { 94 *id = adapter->id; 95 found = true; 96 ret = 0; 97 break; 98 } 99 if (adapter->id >= *id) { 100 *id = adapter->id + 1; 101 } 102 } 103 if (found) { 104 goto out; 105 } 106 adapter = g_new0(IoAdapter, 1); 107 ret = fsc->register_io_adapter(fs, *id, isc, swap, maskable); 108 if (ret == 0) { 109 adapter->id = *id; 110 adapter->isc = isc; 111 adapter->type = type; 112 QTAILQ_INSERT_TAIL(&channel_subsys->io_adapters, adapter, sibling); 113 } else { 114 g_free(adapter); 115 fprintf(stderr, "Unexpected error %d when registering adapter %d\n", 116 ret, *id); 117 } 118 out: 119 return ret; 120 } 121 122 uint16_t css_build_subchannel_id(SubchDev *sch) 123 { 124 if (channel_subsys->max_cssid > 0) { 125 return (sch->cssid << 8) | (1 << 3) | (sch->ssid << 1) | 1; 126 } 127 return (sch->ssid << 1) | 1; 128 } 129 130 static void css_inject_io_interrupt(SubchDev *sch) 131 { 132 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 133 134 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 135 sch->curr_status.pmcw.intparm, isc, ""); 136 s390_io_interrupt(css_build_subchannel_id(sch), 137 sch->schid, 138 sch->curr_status.pmcw.intparm, 139 isc << 27); 140 } 141 142 void css_conditional_io_interrupt(SubchDev *sch) 143 { 144 /* 145 * If the subchannel is not currently status pending, make it pending 146 * with alert status. 147 */ 148 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) { 149 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 150 151 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 152 sch->curr_status.pmcw.intparm, isc, 153 "(unsolicited)"); 154 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 155 sch->curr_status.scsw.ctrl |= 156 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 157 /* Inject an I/O interrupt. */ 158 s390_io_interrupt(css_build_subchannel_id(sch), 159 sch->schid, 160 sch->curr_status.pmcw.intparm, 161 isc << 27); 162 } 163 } 164 165 void css_adapter_interrupt(uint8_t isc) 166 { 167 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI; 168 169 trace_css_adapter_interrupt(isc); 170 s390_io_interrupt(0, 0, 0, io_int_word); 171 } 172 173 static void sch_handle_clear_func(SubchDev *sch) 174 { 175 PMCW *p = &sch->curr_status.pmcw; 176 SCSW *s = &sch->curr_status.scsw; 177 int path; 178 179 /* Path management: In our simple css, we always choose the only path. */ 180 path = 0x80; 181 182 /* Reset values prior to 'issuing the clear signal'. */ 183 p->lpum = 0; 184 p->pom = 0xff; 185 s->flags &= ~SCSW_FLAGS_MASK_PNO; 186 187 /* We always 'attempt to issue the clear signal', and we always succeed. */ 188 sch->channel_prog = 0x0; 189 sch->last_cmd_valid = false; 190 s->ctrl &= ~SCSW_ACTL_CLEAR_PEND; 191 s->ctrl |= SCSW_STCTL_STATUS_PEND; 192 193 s->dstat = 0; 194 s->cstat = 0; 195 p->lpum = path; 196 197 } 198 199 static void sch_handle_halt_func(SubchDev *sch) 200 { 201 202 PMCW *p = &sch->curr_status.pmcw; 203 SCSW *s = &sch->curr_status.scsw; 204 hwaddr curr_ccw = sch->channel_prog; 205 int path; 206 207 /* Path management: In our simple css, we always choose the only path. */ 208 path = 0x80; 209 210 /* We always 'attempt to issue the halt signal', and we always succeed. */ 211 sch->channel_prog = 0x0; 212 sch->last_cmd_valid = false; 213 s->ctrl &= ~SCSW_ACTL_HALT_PEND; 214 s->ctrl |= SCSW_STCTL_STATUS_PEND; 215 216 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) || 217 !((s->ctrl & SCSW_ACTL_START_PEND) || 218 (s->ctrl & SCSW_ACTL_SUSP))) { 219 s->dstat = SCSW_DSTAT_DEVICE_END; 220 } 221 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) || 222 (s->ctrl & SCSW_ACTL_SUSP)) { 223 s->cpa = curr_ccw + 8; 224 } 225 s->cstat = 0; 226 p->lpum = path; 227 228 } 229 230 static void copy_sense_id_to_guest(SenseId *dest, SenseId *src) 231 { 232 int i; 233 234 dest->reserved = src->reserved; 235 dest->cu_type = cpu_to_be16(src->cu_type); 236 dest->cu_model = src->cu_model; 237 dest->dev_type = cpu_to_be16(src->dev_type); 238 dest->dev_model = src->dev_model; 239 dest->unused = src->unused; 240 for (i = 0; i < ARRAY_SIZE(dest->ciw); i++) { 241 dest->ciw[i].type = src->ciw[i].type; 242 dest->ciw[i].command = src->ciw[i].command; 243 dest->ciw[i].count = cpu_to_be16(src->ciw[i].count); 244 } 245 } 246 247 static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1) 248 { 249 CCW0 tmp0; 250 CCW1 tmp1; 251 CCW1 ret; 252 253 if (fmt1) { 254 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1)); 255 ret.cmd_code = tmp1.cmd_code; 256 ret.flags = tmp1.flags; 257 ret.count = be16_to_cpu(tmp1.count); 258 ret.cda = be32_to_cpu(tmp1.cda); 259 } else { 260 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0)); 261 ret.cmd_code = tmp0.cmd_code; 262 ret.flags = tmp0.flags; 263 ret.count = be16_to_cpu(tmp0.count); 264 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16); 265 if ((ret.cmd_code & 0x0f) == CCW_CMD_TIC) { 266 ret.cmd_code &= 0x0f; 267 } 268 } 269 return ret; 270 } 271 272 static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr) 273 { 274 int ret; 275 bool check_len; 276 int len; 277 CCW1 ccw; 278 279 if (!ccw_addr) { 280 return -EIO; 281 } 282 283 /* Translate everything to format-1 ccws - the information is the same. */ 284 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1); 285 286 /* Check for invalid command codes. */ 287 if ((ccw.cmd_code & 0x0f) == 0) { 288 return -EINVAL; 289 } 290 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) && 291 ((ccw.cmd_code & 0xf0) != 0)) { 292 return -EINVAL; 293 } 294 if (!sch->ccw_fmt_1 && (ccw.count == 0) && 295 (ccw.cmd_code != CCW_CMD_TIC)) { 296 return -EINVAL; 297 } 298 299 if (ccw.flags & CCW_FLAG_SUSPEND) { 300 return -EINPROGRESS; 301 } 302 303 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC)); 304 305 if (!ccw.cda) { 306 if (sch->ccw_no_data_cnt == 255) { 307 return -EINVAL; 308 } 309 sch->ccw_no_data_cnt++; 310 } 311 312 /* Look at the command. */ 313 switch (ccw.cmd_code) { 314 case CCW_CMD_NOOP: 315 /* Nothing to do. */ 316 ret = 0; 317 break; 318 case CCW_CMD_BASIC_SENSE: 319 if (check_len) { 320 if (ccw.count != sizeof(sch->sense_data)) { 321 ret = -EINVAL; 322 break; 323 } 324 } 325 len = MIN(ccw.count, sizeof(sch->sense_data)); 326 cpu_physical_memory_write(ccw.cda, sch->sense_data, len); 327 sch->curr_status.scsw.count = ccw.count - len; 328 memset(sch->sense_data, 0, sizeof(sch->sense_data)); 329 ret = 0; 330 break; 331 case CCW_CMD_SENSE_ID: 332 { 333 SenseId sense_id; 334 335 copy_sense_id_to_guest(&sense_id, &sch->id); 336 /* Sense ID information is device specific. */ 337 if (check_len) { 338 if (ccw.count != sizeof(sense_id)) { 339 ret = -EINVAL; 340 break; 341 } 342 } 343 len = MIN(ccw.count, sizeof(sense_id)); 344 /* 345 * Only indicate 0xff in the first sense byte if we actually 346 * have enough place to store at least bytes 0-3. 347 */ 348 if (len >= 4) { 349 sense_id.reserved = 0xff; 350 } else { 351 sense_id.reserved = 0; 352 } 353 cpu_physical_memory_write(ccw.cda, &sense_id, len); 354 sch->curr_status.scsw.count = ccw.count - len; 355 ret = 0; 356 break; 357 } 358 case CCW_CMD_TIC: 359 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) { 360 ret = -EINVAL; 361 break; 362 } 363 if (ccw.flags & (CCW_FLAG_CC | CCW_FLAG_DC)) { 364 ret = -EINVAL; 365 break; 366 } 367 sch->channel_prog = ccw.cda; 368 ret = -EAGAIN; 369 break; 370 default: 371 if (sch->ccw_cb) { 372 /* Handle device specific commands. */ 373 ret = sch->ccw_cb(sch, ccw); 374 } else { 375 ret = -ENOSYS; 376 } 377 break; 378 } 379 sch->last_cmd = ccw; 380 sch->last_cmd_valid = true; 381 if (ret == 0) { 382 if (ccw.flags & CCW_FLAG_CC) { 383 sch->channel_prog += 8; 384 ret = -EAGAIN; 385 } 386 } 387 388 return ret; 389 } 390 391 static void sch_handle_start_func(SubchDev *sch, ORB *orb) 392 { 393 394 PMCW *p = &sch->curr_status.pmcw; 395 SCSW *s = &sch->curr_status.scsw; 396 int path; 397 int ret; 398 399 /* Path management: In our simple css, we always choose the only path. */ 400 path = 0x80; 401 402 if (!(s->ctrl & SCSW_ACTL_SUSP)) { 403 s->cstat = 0; 404 s->dstat = 0; 405 /* Look at the orb and try to execute the channel program. */ 406 assert(orb != NULL); /* resume does not pass an orb */ 407 p->intparm = orb->intparm; 408 if (!(orb->lpm & path)) { 409 /* Generate a deferred cc 3 condition. */ 410 s->flags |= SCSW_FLAGS_MASK_CC; 411 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 412 s->ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND); 413 return; 414 } 415 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT); 416 sch->ccw_no_data_cnt = 0; 417 } else { 418 s->ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND); 419 } 420 sch->last_cmd_valid = false; 421 do { 422 ret = css_interpret_ccw(sch, sch->channel_prog); 423 switch (ret) { 424 case -EAGAIN: 425 /* ccw chain, continue processing */ 426 break; 427 case 0: 428 /* success */ 429 s->ctrl &= ~SCSW_ACTL_START_PEND; 430 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 431 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 432 SCSW_STCTL_STATUS_PEND; 433 s->dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END; 434 s->cpa = sch->channel_prog + 8; 435 break; 436 case -ENOSYS: 437 /* unsupported command, generate unit check (command reject) */ 438 s->ctrl &= ~SCSW_ACTL_START_PEND; 439 s->dstat = SCSW_DSTAT_UNIT_CHECK; 440 /* Set sense bit 0 in ecw0. */ 441 sch->sense_data[0] = 0x80; 442 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 443 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 444 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 445 s->cpa = sch->channel_prog + 8; 446 break; 447 case -EFAULT: 448 /* memory problem, generate channel data check */ 449 s->ctrl &= ~SCSW_ACTL_START_PEND; 450 s->cstat = SCSW_CSTAT_DATA_CHECK; 451 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 452 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 453 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 454 s->cpa = sch->channel_prog + 8; 455 break; 456 case -EBUSY: 457 /* subchannel busy, generate deferred cc 1 */ 458 s->flags &= ~SCSW_FLAGS_MASK_CC; 459 s->flags |= (1 << 8); 460 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 461 s->ctrl |= SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 462 break; 463 case -EINPROGRESS: 464 /* channel program has been suspended */ 465 s->ctrl &= ~SCSW_ACTL_START_PEND; 466 s->ctrl |= SCSW_ACTL_SUSP; 467 break; 468 default: 469 /* error, generate channel program check */ 470 s->ctrl &= ~SCSW_ACTL_START_PEND; 471 s->cstat = SCSW_CSTAT_PROG_CHECK; 472 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 473 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 474 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 475 s->cpa = sch->channel_prog + 8; 476 break; 477 } 478 } while (ret == -EAGAIN); 479 480 } 481 482 /* 483 * On real machines, this would run asynchronously to the main vcpus. 484 * We might want to make some parts of the ssch handling (interpreting 485 * read/writes) asynchronous later on if we start supporting more than 486 * our current very simple devices. 487 */ 488 static void do_subchannel_work(SubchDev *sch, ORB *orb) 489 { 490 491 SCSW *s = &sch->curr_status.scsw; 492 493 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) { 494 sch_handle_clear_func(sch); 495 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) { 496 sch_handle_halt_func(sch); 497 } else if (s->ctrl & SCSW_FCTL_START_FUNC) { 498 sch_handle_start_func(sch, orb); 499 } else { 500 /* Cannot happen. */ 501 return; 502 } 503 css_inject_io_interrupt(sch); 504 } 505 506 static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src) 507 { 508 int i; 509 510 dest->intparm = cpu_to_be32(src->intparm); 511 dest->flags = cpu_to_be16(src->flags); 512 dest->devno = cpu_to_be16(src->devno); 513 dest->lpm = src->lpm; 514 dest->pnom = src->pnom; 515 dest->lpum = src->lpum; 516 dest->pim = src->pim; 517 dest->mbi = cpu_to_be16(src->mbi); 518 dest->pom = src->pom; 519 dest->pam = src->pam; 520 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 521 dest->chpid[i] = src->chpid[i]; 522 } 523 dest->chars = cpu_to_be32(src->chars); 524 } 525 526 static void copy_scsw_to_guest(SCSW *dest, const SCSW *src) 527 { 528 dest->flags = cpu_to_be16(src->flags); 529 dest->ctrl = cpu_to_be16(src->ctrl); 530 dest->cpa = cpu_to_be32(src->cpa); 531 dest->dstat = src->dstat; 532 dest->cstat = src->cstat; 533 dest->count = cpu_to_be16(src->count); 534 } 535 536 static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src) 537 { 538 int i; 539 540 copy_pmcw_to_guest(&dest->pmcw, &src->pmcw); 541 copy_scsw_to_guest(&dest->scsw, &src->scsw); 542 dest->mba = cpu_to_be64(src->mba); 543 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 544 dest->mda[i] = src->mda[i]; 545 } 546 } 547 548 int css_do_stsch(SubchDev *sch, SCHIB *schib) 549 { 550 /* Use current status. */ 551 copy_schib_to_guest(schib, &sch->curr_status); 552 return 0; 553 } 554 555 static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src) 556 { 557 int i; 558 559 dest->intparm = be32_to_cpu(src->intparm); 560 dest->flags = be16_to_cpu(src->flags); 561 dest->devno = be16_to_cpu(src->devno); 562 dest->lpm = src->lpm; 563 dest->pnom = src->pnom; 564 dest->lpum = src->lpum; 565 dest->pim = src->pim; 566 dest->mbi = be16_to_cpu(src->mbi); 567 dest->pom = src->pom; 568 dest->pam = src->pam; 569 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 570 dest->chpid[i] = src->chpid[i]; 571 } 572 dest->chars = be32_to_cpu(src->chars); 573 } 574 575 static void copy_scsw_from_guest(SCSW *dest, const SCSW *src) 576 { 577 dest->flags = be16_to_cpu(src->flags); 578 dest->ctrl = be16_to_cpu(src->ctrl); 579 dest->cpa = be32_to_cpu(src->cpa); 580 dest->dstat = src->dstat; 581 dest->cstat = src->cstat; 582 dest->count = be16_to_cpu(src->count); 583 } 584 585 static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src) 586 { 587 int i; 588 589 copy_pmcw_from_guest(&dest->pmcw, &src->pmcw); 590 copy_scsw_from_guest(&dest->scsw, &src->scsw); 591 dest->mba = be64_to_cpu(src->mba); 592 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 593 dest->mda[i] = src->mda[i]; 594 } 595 } 596 597 int css_do_msch(SubchDev *sch, const SCHIB *orig_schib) 598 { 599 SCSW *s = &sch->curr_status.scsw; 600 PMCW *p = &sch->curr_status.pmcw; 601 uint16_t oldflags; 602 int ret; 603 SCHIB schib; 604 605 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_DNV)) { 606 ret = 0; 607 goto out; 608 } 609 610 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 611 ret = -EINPROGRESS; 612 goto out; 613 } 614 615 if (s->ctrl & 616 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) { 617 ret = -EBUSY; 618 goto out; 619 } 620 621 copy_schib_from_guest(&schib, orig_schib); 622 /* Only update the program-modifiable fields. */ 623 p->intparm = schib.pmcw.intparm; 624 oldflags = p->flags; 625 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 626 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 627 PMCW_FLAGS_MASK_MP); 628 p->flags |= schib.pmcw.flags & 629 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 630 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 631 PMCW_FLAGS_MASK_MP); 632 p->lpm = schib.pmcw.lpm; 633 p->mbi = schib.pmcw.mbi; 634 p->pom = schib.pmcw.pom; 635 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 636 p->chars |= schib.pmcw.chars & 637 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 638 sch->curr_status.mba = schib.mba; 639 640 /* Has the channel been disabled? */ 641 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0 642 && (p->flags & PMCW_FLAGS_MASK_ENA) == 0) { 643 sch->disable_cb(sch); 644 } 645 646 ret = 0; 647 648 out: 649 return ret; 650 } 651 652 int css_do_xsch(SubchDev *sch) 653 { 654 SCSW *s = &sch->curr_status.scsw; 655 PMCW *p = &sch->curr_status.pmcw; 656 int ret; 657 658 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 659 ret = -ENODEV; 660 goto out; 661 } 662 663 if (!(s->ctrl & SCSW_CTRL_MASK_FCTL) || 664 ((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 665 (!(s->ctrl & 666 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) || 667 (s->ctrl & SCSW_ACTL_SUBCH_ACTIVE)) { 668 ret = -EINPROGRESS; 669 goto out; 670 } 671 672 if (s->ctrl & SCSW_CTRL_MASK_STCTL) { 673 ret = -EBUSY; 674 goto out; 675 } 676 677 /* Cancel the current operation. */ 678 s->ctrl &= ~(SCSW_FCTL_START_FUNC | 679 SCSW_ACTL_RESUME_PEND | 680 SCSW_ACTL_START_PEND | 681 SCSW_ACTL_SUSP); 682 sch->channel_prog = 0x0; 683 sch->last_cmd_valid = false; 684 s->dstat = 0; 685 s->cstat = 0; 686 ret = 0; 687 688 out: 689 return ret; 690 } 691 692 int css_do_csch(SubchDev *sch) 693 { 694 SCSW *s = &sch->curr_status.scsw; 695 PMCW *p = &sch->curr_status.pmcw; 696 int ret; 697 698 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 699 ret = -ENODEV; 700 goto out; 701 } 702 703 /* Trigger the clear function. */ 704 s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL); 705 s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND; 706 707 do_subchannel_work(sch, NULL); 708 ret = 0; 709 710 out: 711 return ret; 712 } 713 714 int css_do_hsch(SubchDev *sch) 715 { 716 SCSW *s = &sch->curr_status.scsw; 717 PMCW *p = &sch->curr_status.pmcw; 718 int ret; 719 720 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 721 ret = -ENODEV; 722 goto out; 723 } 724 725 if (((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) || 726 (s->ctrl & (SCSW_STCTL_PRIMARY | 727 SCSW_STCTL_SECONDARY | 728 SCSW_STCTL_ALERT))) { 729 ret = -EINPROGRESS; 730 goto out; 731 } 732 733 if (s->ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) { 734 ret = -EBUSY; 735 goto out; 736 } 737 738 /* Trigger the halt function. */ 739 s->ctrl |= SCSW_FCTL_HALT_FUNC; 740 s->ctrl &= ~SCSW_FCTL_START_FUNC; 741 if (((s->ctrl & SCSW_CTRL_MASK_ACTL) == 742 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) && 743 ((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_INTERMEDIATE)) { 744 s->ctrl &= ~SCSW_STCTL_STATUS_PEND; 745 } 746 s->ctrl |= SCSW_ACTL_HALT_PEND; 747 748 do_subchannel_work(sch, NULL); 749 ret = 0; 750 751 out: 752 return ret; 753 } 754 755 static void css_update_chnmon(SubchDev *sch) 756 { 757 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) { 758 /* Not active. */ 759 return; 760 } 761 /* The counter is conveniently located at the beginning of the struct. */ 762 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) { 763 /* Format 1, per-subchannel area. */ 764 uint32_t count; 765 766 count = address_space_ldl(&address_space_memory, 767 sch->curr_status.mba, 768 MEMTXATTRS_UNSPECIFIED, 769 NULL); 770 count++; 771 address_space_stl(&address_space_memory, sch->curr_status.mba, count, 772 MEMTXATTRS_UNSPECIFIED, NULL); 773 } else { 774 /* Format 0, global area. */ 775 uint32_t offset; 776 uint16_t count; 777 778 offset = sch->curr_status.pmcw.mbi << 5; 779 count = address_space_lduw(&address_space_memory, 780 channel_subsys->chnmon_area + offset, 781 MEMTXATTRS_UNSPECIFIED, 782 NULL); 783 count++; 784 address_space_stw(&address_space_memory, 785 channel_subsys->chnmon_area + offset, count, 786 MEMTXATTRS_UNSPECIFIED, NULL); 787 } 788 } 789 790 int css_do_ssch(SubchDev *sch, ORB *orb) 791 { 792 SCSW *s = &sch->curr_status.scsw; 793 PMCW *p = &sch->curr_status.pmcw; 794 int ret; 795 796 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 797 ret = -ENODEV; 798 goto out; 799 } 800 801 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 802 ret = -EINPROGRESS; 803 goto out; 804 } 805 806 if (s->ctrl & (SCSW_FCTL_START_FUNC | 807 SCSW_FCTL_HALT_FUNC | 808 SCSW_FCTL_CLEAR_FUNC)) { 809 ret = -EBUSY; 810 goto out; 811 } 812 813 /* If monitoring is active, update counter. */ 814 if (channel_subsys->chnmon_active) { 815 css_update_chnmon(sch); 816 } 817 sch->channel_prog = orb->cpa; 818 /* Trigger the start function. */ 819 s->ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND); 820 s->flags &= ~SCSW_FLAGS_MASK_PNO; 821 822 do_subchannel_work(sch, orb); 823 ret = 0; 824 825 out: 826 return ret; 827 } 828 829 static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw, 830 int *irb_len) 831 { 832 int i; 833 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 834 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 835 836 copy_scsw_to_guest(&dest->scsw, &src->scsw); 837 838 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) { 839 dest->esw[i] = cpu_to_be32(src->esw[i]); 840 } 841 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) { 842 dest->ecw[i] = cpu_to_be32(src->ecw[i]); 843 } 844 *irb_len = sizeof(*dest) - sizeof(dest->emw); 845 846 /* extended measurements enabled? */ 847 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) || 848 !(pmcw->flags & PMCW_FLAGS_MASK_TF) || 849 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) { 850 return; 851 } 852 /* extended measurements pending? */ 853 if (!(stctl & SCSW_STCTL_STATUS_PEND)) { 854 return; 855 } 856 if ((stctl & SCSW_STCTL_PRIMARY) || 857 (stctl == SCSW_STCTL_SECONDARY) || 858 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) { 859 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) { 860 dest->emw[i] = cpu_to_be32(src->emw[i]); 861 } 862 } 863 *irb_len = sizeof(*dest); 864 } 865 866 int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len) 867 { 868 SCSW *s = &sch->curr_status.scsw; 869 PMCW *p = &sch->curr_status.pmcw; 870 uint16_t stctl; 871 IRB irb; 872 873 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 874 return 3; 875 } 876 877 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL; 878 879 /* Prepare the irb for the guest. */ 880 memset(&irb, 0, sizeof(IRB)); 881 882 /* Copy scsw from current status. */ 883 memcpy(&irb.scsw, s, sizeof(SCSW)); 884 if (stctl & SCSW_STCTL_STATUS_PEND) { 885 if (s->cstat & (SCSW_CSTAT_DATA_CHECK | 886 SCSW_CSTAT_CHN_CTRL_CHK | 887 SCSW_CSTAT_INTF_CTRL_CHK)) { 888 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF; 889 irb.esw[0] = 0x04804000; 890 } else { 891 irb.esw[0] = 0x00800000; 892 } 893 /* If a unit check is pending, copy sense data. */ 894 if ((s->dstat & SCSW_DSTAT_UNIT_CHECK) && 895 (p->chars & PMCW_CHARS_MASK_CSENSE)) { 896 int i; 897 898 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL; 899 /* Attention: sense_data is already BE! */ 900 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data)); 901 for (i = 0; i < ARRAY_SIZE(irb.ecw); i++) { 902 irb.ecw[i] = be32_to_cpu(irb.ecw[i]); 903 } 904 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8); 905 } 906 } 907 /* Store the irb to the guest. */ 908 copy_irb_to_guest(target_irb, &irb, p, irb_len); 909 910 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0); 911 } 912 913 void css_do_tsch_update_subch(SubchDev *sch) 914 { 915 SCSW *s = &sch->curr_status.scsw; 916 PMCW *p = &sch->curr_status.pmcw; 917 uint16_t stctl; 918 uint16_t fctl; 919 uint16_t actl; 920 921 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL; 922 fctl = s->ctrl & SCSW_CTRL_MASK_FCTL; 923 actl = s->ctrl & SCSW_CTRL_MASK_ACTL; 924 925 /* Clear conditions on subchannel, if applicable. */ 926 if (stctl & SCSW_STCTL_STATUS_PEND) { 927 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 928 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) || 929 ((fctl & SCSW_FCTL_HALT_FUNC) && 930 (actl & SCSW_ACTL_SUSP))) { 931 s->ctrl &= ~SCSW_CTRL_MASK_FCTL; 932 } 933 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) { 934 s->flags &= ~SCSW_FLAGS_MASK_PNO; 935 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 936 SCSW_ACTL_START_PEND | 937 SCSW_ACTL_HALT_PEND | 938 SCSW_ACTL_CLEAR_PEND | 939 SCSW_ACTL_SUSP); 940 } else { 941 if ((actl & SCSW_ACTL_SUSP) && 942 (fctl & SCSW_FCTL_START_FUNC)) { 943 s->flags &= ~SCSW_FLAGS_MASK_PNO; 944 if (fctl & SCSW_FCTL_HALT_FUNC) { 945 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 946 SCSW_ACTL_START_PEND | 947 SCSW_ACTL_HALT_PEND | 948 SCSW_ACTL_CLEAR_PEND | 949 SCSW_ACTL_SUSP); 950 } else { 951 s->ctrl &= ~SCSW_ACTL_RESUME_PEND; 952 } 953 } 954 } 955 /* Clear pending sense data. */ 956 if (p->chars & PMCW_CHARS_MASK_CSENSE) { 957 memset(sch->sense_data, 0 , sizeof(sch->sense_data)); 958 } 959 } 960 } 961 962 static void copy_crw_to_guest(CRW *dest, const CRW *src) 963 { 964 dest->flags = cpu_to_be16(src->flags); 965 dest->rsid = cpu_to_be16(src->rsid); 966 } 967 968 int css_do_stcrw(CRW *crw) 969 { 970 CrwContainer *crw_cont; 971 int ret; 972 973 crw_cont = QTAILQ_FIRST(&channel_subsys->pending_crws); 974 if (crw_cont) { 975 QTAILQ_REMOVE(&channel_subsys->pending_crws, crw_cont, sibling); 976 copy_crw_to_guest(crw, &crw_cont->crw); 977 g_free(crw_cont); 978 ret = 0; 979 } else { 980 /* List was empty, turn crw machine checks on again. */ 981 memset(crw, 0, sizeof(*crw)); 982 channel_subsys->do_crw_mchk = true; 983 ret = 1; 984 } 985 986 return ret; 987 } 988 989 static void copy_crw_from_guest(CRW *dest, const CRW *src) 990 { 991 dest->flags = be16_to_cpu(src->flags); 992 dest->rsid = be16_to_cpu(src->rsid); 993 } 994 995 void css_undo_stcrw(CRW *crw) 996 { 997 CrwContainer *crw_cont; 998 999 crw_cont = g_try_malloc0(sizeof(CrwContainer)); 1000 if (!crw_cont) { 1001 channel_subsys->crws_lost = true; 1002 return; 1003 } 1004 copy_crw_from_guest(&crw_cont->crw, crw); 1005 1006 QTAILQ_INSERT_HEAD(&channel_subsys->pending_crws, crw_cont, sibling); 1007 } 1008 1009 int css_do_tpi(IOIntCode *int_code, int lowcore) 1010 { 1011 /* No pending interrupts for !KVM. */ 1012 return 0; 1013 } 1014 1015 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, 1016 int rfmt, void *buf) 1017 { 1018 int i, desc_size; 1019 uint32_t words[8]; 1020 uint32_t chpid_type_word; 1021 CssImage *css; 1022 1023 if (!m && !cssid) { 1024 css = channel_subsys->css[channel_subsys->default_cssid]; 1025 } else { 1026 css = channel_subsys->css[cssid]; 1027 } 1028 if (!css) { 1029 return 0; 1030 } 1031 desc_size = 0; 1032 for (i = f_chpid; i <= l_chpid; i++) { 1033 if (css->chpids[i].in_use) { 1034 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i; 1035 if (rfmt == 0) { 1036 words[0] = cpu_to_be32(chpid_type_word); 1037 words[1] = 0; 1038 memcpy(buf + desc_size, words, 8); 1039 desc_size += 8; 1040 } else if (rfmt == 1) { 1041 words[0] = cpu_to_be32(chpid_type_word); 1042 words[1] = 0; 1043 words[2] = 0; 1044 words[3] = 0; 1045 words[4] = 0; 1046 words[5] = 0; 1047 words[6] = 0; 1048 words[7] = 0; 1049 memcpy(buf + desc_size, words, 32); 1050 desc_size += 32; 1051 } 1052 } 1053 } 1054 return desc_size; 1055 } 1056 1057 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo) 1058 { 1059 /* dct is currently ignored (not really meaningful for our devices) */ 1060 /* TODO: Don't ignore mbk. */ 1061 if (update && !channel_subsys->chnmon_active) { 1062 /* Enable measuring. */ 1063 channel_subsys->chnmon_area = mbo; 1064 channel_subsys->chnmon_active = true; 1065 } 1066 if (!update && channel_subsys->chnmon_active) { 1067 /* Disable measuring. */ 1068 channel_subsys->chnmon_area = 0; 1069 channel_subsys->chnmon_active = false; 1070 } 1071 } 1072 1073 int css_do_rsch(SubchDev *sch) 1074 { 1075 SCSW *s = &sch->curr_status.scsw; 1076 PMCW *p = &sch->curr_status.pmcw; 1077 int ret; 1078 1079 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 1080 ret = -ENODEV; 1081 goto out; 1082 } 1083 1084 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 1085 ret = -EINPROGRESS; 1086 goto out; 1087 } 1088 1089 if (((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1090 (s->ctrl & SCSW_ACTL_RESUME_PEND) || 1091 (!(s->ctrl & SCSW_ACTL_SUSP))) { 1092 ret = -EINVAL; 1093 goto out; 1094 } 1095 1096 /* If monitoring is active, update counter. */ 1097 if (channel_subsys->chnmon_active) { 1098 css_update_chnmon(sch); 1099 } 1100 1101 s->ctrl |= SCSW_ACTL_RESUME_PEND; 1102 do_subchannel_work(sch, NULL); 1103 ret = 0; 1104 1105 out: 1106 return ret; 1107 } 1108 1109 int css_do_rchp(uint8_t cssid, uint8_t chpid) 1110 { 1111 uint8_t real_cssid; 1112 1113 if (cssid > channel_subsys->max_cssid) { 1114 return -EINVAL; 1115 } 1116 if (channel_subsys->max_cssid == 0) { 1117 real_cssid = channel_subsys->default_cssid; 1118 } else { 1119 real_cssid = cssid; 1120 } 1121 if (!channel_subsys->css[real_cssid]) { 1122 return -EINVAL; 1123 } 1124 1125 if (!channel_subsys->css[real_cssid]->chpids[chpid].in_use) { 1126 return -ENODEV; 1127 } 1128 1129 if (!channel_subsys->css[real_cssid]->chpids[chpid].is_virtual) { 1130 fprintf(stderr, 1131 "rchp unsupported for non-virtual chpid %x.%02x!\n", 1132 real_cssid, chpid); 1133 return -ENODEV; 1134 } 1135 1136 /* We don't really use a channel path, so we're done here. */ 1137 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1138 channel_subsys->max_cssid > 0 ? 1 : 0, chpid); 1139 if (channel_subsys->max_cssid > 0) { 1140 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 0, real_cssid << 8); 1141 } 1142 return 0; 1143 } 1144 1145 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1146 { 1147 SubchSet *set; 1148 uint8_t real_cssid; 1149 1150 real_cssid = (!m && (cssid == 0)) ? channel_subsys->default_cssid : cssid; 1151 if (real_cssid > MAX_CSSID || ssid > MAX_SSID || 1152 !channel_subsys->css[real_cssid] || 1153 !channel_subsys->css[real_cssid]->sch_set[ssid]) { 1154 return true; 1155 } 1156 set = channel_subsys->css[real_cssid]->sch_set[ssid]; 1157 return schid > find_last_bit(set->schids_used, 1158 (MAX_SCHID + 1) / sizeof(unsigned long)); 1159 } 1160 1161 static int css_add_virtual_chpid(uint8_t cssid, uint8_t chpid, uint8_t type) 1162 { 1163 CssImage *css; 1164 1165 trace_css_chpid_add(cssid, chpid, type); 1166 if (cssid > MAX_CSSID) { 1167 return -EINVAL; 1168 } 1169 css = channel_subsys->css[cssid]; 1170 if (!css) { 1171 return -EINVAL; 1172 } 1173 if (css->chpids[chpid].in_use) { 1174 return -EEXIST; 1175 } 1176 css->chpids[chpid].in_use = 1; 1177 css->chpids[chpid].type = type; 1178 css->chpids[chpid].is_virtual = 1; 1179 1180 css_generate_chp_crws(cssid, chpid); 1181 1182 return 0; 1183 } 1184 1185 void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type) 1186 { 1187 PMCW *p = &sch->curr_status.pmcw; 1188 SCSW *s = &sch->curr_status.scsw; 1189 int i; 1190 CssImage *css = channel_subsys->css[sch->cssid]; 1191 1192 assert(css != NULL); 1193 memset(p, 0, sizeof(PMCW)); 1194 p->flags |= PMCW_FLAGS_MASK_DNV; 1195 p->devno = sch->devno; 1196 /* single path */ 1197 p->pim = 0x80; 1198 p->pom = 0xff; 1199 p->pam = 0x80; 1200 p->chpid[0] = chpid; 1201 if (!css->chpids[chpid].in_use) { 1202 css_add_virtual_chpid(sch->cssid, chpid, type); 1203 } 1204 1205 memset(s, 0, sizeof(SCSW)); 1206 sch->curr_status.mba = 0; 1207 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) { 1208 sch->curr_status.mda[i] = 0; 1209 } 1210 } 1211 1212 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1213 { 1214 uint8_t real_cssid; 1215 1216 real_cssid = (!m && (cssid == 0)) ? channel_subsys->default_cssid : cssid; 1217 1218 if (!channel_subsys->css[real_cssid]) { 1219 return NULL; 1220 } 1221 1222 if (!channel_subsys->css[real_cssid]->sch_set[ssid]) { 1223 return NULL; 1224 } 1225 1226 return channel_subsys->css[real_cssid]->sch_set[ssid]->sch[schid]; 1227 } 1228 1229 bool css_subch_visible(SubchDev *sch) 1230 { 1231 if (sch->ssid > channel_subsys->max_ssid) { 1232 return false; 1233 } 1234 1235 if (sch->cssid != channel_subsys->default_cssid) { 1236 return (channel_subsys->max_cssid > 0); 1237 } 1238 1239 return true; 1240 } 1241 1242 bool css_present(uint8_t cssid) 1243 { 1244 return (channel_subsys->css[cssid] != NULL); 1245 } 1246 1247 bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno) 1248 { 1249 if (!channel_subsys->css[cssid]) { 1250 return false; 1251 } 1252 if (!channel_subsys->css[cssid]->sch_set[ssid]) { 1253 return false; 1254 } 1255 1256 return !!test_bit(devno, 1257 channel_subsys->css[cssid]->sch_set[ssid]->devnos_used); 1258 } 1259 1260 void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid, 1261 uint16_t devno, SubchDev *sch) 1262 { 1263 CssImage *css; 1264 SubchSet *s_set; 1265 1266 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid, 1267 devno); 1268 if (!channel_subsys->css[cssid]) { 1269 fprintf(stderr, 1270 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n", 1271 __func__, cssid, ssid, schid); 1272 return; 1273 } 1274 css = channel_subsys->css[cssid]; 1275 1276 if (!css->sch_set[ssid]) { 1277 css->sch_set[ssid] = g_malloc0(sizeof(SubchSet)); 1278 } 1279 s_set = css->sch_set[ssid]; 1280 1281 s_set->sch[schid] = sch; 1282 if (sch) { 1283 set_bit(schid, s_set->schids_used); 1284 set_bit(devno, s_set->devnos_used); 1285 } else { 1286 clear_bit(schid, s_set->schids_used); 1287 clear_bit(devno, s_set->devnos_used); 1288 } 1289 } 1290 1291 void css_queue_crw(uint8_t rsc, uint8_t erc, int chain, uint16_t rsid) 1292 { 1293 CrwContainer *crw_cont; 1294 1295 trace_css_crw(rsc, erc, rsid, chain ? "(chained)" : ""); 1296 /* TODO: Maybe use a static crw pool? */ 1297 crw_cont = g_try_malloc0(sizeof(CrwContainer)); 1298 if (!crw_cont) { 1299 channel_subsys->crws_lost = true; 1300 return; 1301 } 1302 crw_cont->crw.flags = (rsc << 8) | erc; 1303 if (chain) { 1304 crw_cont->crw.flags |= CRW_FLAGS_MASK_C; 1305 } 1306 crw_cont->crw.rsid = rsid; 1307 if (channel_subsys->crws_lost) { 1308 crw_cont->crw.flags |= CRW_FLAGS_MASK_R; 1309 channel_subsys->crws_lost = false; 1310 } 1311 1312 QTAILQ_INSERT_TAIL(&channel_subsys->pending_crws, crw_cont, sibling); 1313 1314 if (channel_subsys->do_crw_mchk) { 1315 channel_subsys->do_crw_mchk = false; 1316 /* Inject crw pending machine check. */ 1317 s390_crw_mchk(); 1318 } 1319 } 1320 1321 void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid, 1322 int hotplugged, int add) 1323 { 1324 uint8_t guest_cssid; 1325 bool chain_crw; 1326 1327 if (add && !hotplugged) { 1328 return; 1329 } 1330 if (channel_subsys->max_cssid == 0) { 1331 /* Default cssid shows up as 0. */ 1332 guest_cssid = (cssid == channel_subsys->default_cssid) ? 0 : cssid; 1333 } else { 1334 /* Show real cssid to the guest. */ 1335 guest_cssid = cssid; 1336 } 1337 /* 1338 * Only notify for higher subchannel sets/channel subsystems if the 1339 * guest has enabled it. 1340 */ 1341 if ((ssid > channel_subsys->max_ssid) || 1342 (guest_cssid > channel_subsys->max_cssid) || 1343 ((channel_subsys->max_cssid == 0) && 1344 (cssid != channel_subsys->default_cssid))) { 1345 return; 1346 } 1347 chain_crw = (channel_subsys->max_ssid > 0) || 1348 (channel_subsys->max_cssid > 0); 1349 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, chain_crw ? 1 : 0, schid); 1350 if (chain_crw) { 1351 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 1352 (guest_cssid << 8) | (ssid << 4)); 1353 } 1354 } 1355 1356 void css_generate_chp_crws(uint8_t cssid, uint8_t chpid) 1357 { 1358 /* TODO */ 1359 } 1360 1361 void css_generate_css_crws(uint8_t cssid) 1362 { 1363 if (!channel_subsys->sei_pending) { 1364 css_queue_crw(CRW_RSC_CSS, 0, 0, cssid); 1365 } 1366 channel_subsys->sei_pending = true; 1367 } 1368 1369 void css_clear_sei_pending(void) 1370 { 1371 channel_subsys->sei_pending = false; 1372 } 1373 1374 int css_enable_mcsse(void) 1375 { 1376 trace_css_enable_facility("mcsse"); 1377 channel_subsys->max_cssid = MAX_CSSID; 1378 return 0; 1379 } 1380 1381 int css_enable_mss(void) 1382 { 1383 trace_css_enable_facility("mss"); 1384 channel_subsys->max_ssid = MAX_SSID; 1385 return 0; 1386 } 1387 1388 void subch_device_save(SubchDev *s, QEMUFile *f) 1389 { 1390 int i; 1391 1392 qemu_put_byte(f, s->cssid); 1393 qemu_put_byte(f, s->ssid); 1394 qemu_put_be16(f, s->schid); 1395 qemu_put_be16(f, s->devno); 1396 qemu_put_byte(f, s->thinint_active); 1397 /* SCHIB */ 1398 /* PMCW */ 1399 qemu_put_be32(f, s->curr_status.pmcw.intparm); 1400 qemu_put_be16(f, s->curr_status.pmcw.flags); 1401 qemu_put_be16(f, s->curr_status.pmcw.devno); 1402 qemu_put_byte(f, s->curr_status.pmcw.lpm); 1403 qemu_put_byte(f, s->curr_status.pmcw.pnom); 1404 qemu_put_byte(f, s->curr_status.pmcw.lpum); 1405 qemu_put_byte(f, s->curr_status.pmcw.pim); 1406 qemu_put_be16(f, s->curr_status.pmcw.mbi); 1407 qemu_put_byte(f, s->curr_status.pmcw.pom); 1408 qemu_put_byte(f, s->curr_status.pmcw.pam); 1409 qemu_put_buffer(f, s->curr_status.pmcw.chpid, 8); 1410 qemu_put_be32(f, s->curr_status.pmcw.chars); 1411 /* SCSW */ 1412 qemu_put_be16(f, s->curr_status.scsw.flags); 1413 qemu_put_be16(f, s->curr_status.scsw.ctrl); 1414 qemu_put_be32(f, s->curr_status.scsw.cpa); 1415 qemu_put_byte(f, s->curr_status.scsw.dstat); 1416 qemu_put_byte(f, s->curr_status.scsw.cstat); 1417 qemu_put_be16(f, s->curr_status.scsw.count); 1418 qemu_put_be64(f, s->curr_status.mba); 1419 qemu_put_buffer(f, s->curr_status.mda, 4); 1420 /* end SCHIB */ 1421 qemu_put_buffer(f, s->sense_data, 32); 1422 qemu_put_be64(f, s->channel_prog); 1423 /* last cmd */ 1424 qemu_put_byte(f, s->last_cmd.cmd_code); 1425 qemu_put_byte(f, s->last_cmd.flags); 1426 qemu_put_be16(f, s->last_cmd.count); 1427 qemu_put_be32(f, s->last_cmd.cda); 1428 qemu_put_byte(f, s->last_cmd_valid); 1429 qemu_put_byte(f, s->id.reserved); 1430 qemu_put_be16(f, s->id.cu_type); 1431 qemu_put_byte(f, s->id.cu_model); 1432 qemu_put_be16(f, s->id.dev_type); 1433 qemu_put_byte(f, s->id.dev_model); 1434 qemu_put_byte(f, s->id.unused); 1435 for (i = 0; i < ARRAY_SIZE(s->id.ciw); i++) { 1436 qemu_put_byte(f, s->id.ciw[i].type); 1437 qemu_put_byte(f, s->id.ciw[i].command); 1438 qemu_put_be16(f, s->id.ciw[i].count); 1439 } 1440 qemu_put_byte(f, s->ccw_fmt_1); 1441 qemu_put_byte(f, s->ccw_no_data_cnt); 1442 } 1443 1444 int subch_device_load(SubchDev *s, QEMUFile *f) 1445 { 1446 int i; 1447 1448 s->cssid = qemu_get_byte(f); 1449 s->ssid = qemu_get_byte(f); 1450 s->schid = qemu_get_be16(f); 1451 s->devno = qemu_get_be16(f); 1452 s->thinint_active = qemu_get_byte(f); 1453 /* SCHIB */ 1454 /* PMCW */ 1455 s->curr_status.pmcw.intparm = qemu_get_be32(f); 1456 s->curr_status.pmcw.flags = qemu_get_be16(f); 1457 s->curr_status.pmcw.devno = qemu_get_be16(f); 1458 s->curr_status.pmcw.lpm = qemu_get_byte(f); 1459 s->curr_status.pmcw.pnom = qemu_get_byte(f); 1460 s->curr_status.pmcw.lpum = qemu_get_byte(f); 1461 s->curr_status.pmcw.pim = qemu_get_byte(f); 1462 s->curr_status.pmcw.mbi = qemu_get_be16(f); 1463 s->curr_status.pmcw.pom = qemu_get_byte(f); 1464 s->curr_status.pmcw.pam = qemu_get_byte(f); 1465 qemu_get_buffer(f, s->curr_status.pmcw.chpid, 8); 1466 s->curr_status.pmcw.chars = qemu_get_be32(f); 1467 /* SCSW */ 1468 s->curr_status.scsw.flags = qemu_get_be16(f); 1469 s->curr_status.scsw.ctrl = qemu_get_be16(f); 1470 s->curr_status.scsw.cpa = qemu_get_be32(f); 1471 s->curr_status.scsw.dstat = qemu_get_byte(f); 1472 s->curr_status.scsw.cstat = qemu_get_byte(f); 1473 s->curr_status.scsw.count = qemu_get_be16(f); 1474 s->curr_status.mba = qemu_get_be64(f); 1475 qemu_get_buffer(f, s->curr_status.mda, 4); 1476 /* end SCHIB */ 1477 qemu_get_buffer(f, s->sense_data, 32); 1478 s->channel_prog = qemu_get_be64(f); 1479 /* last cmd */ 1480 s->last_cmd.cmd_code = qemu_get_byte(f); 1481 s->last_cmd.flags = qemu_get_byte(f); 1482 s->last_cmd.count = qemu_get_be16(f); 1483 s->last_cmd.cda = qemu_get_be32(f); 1484 s->last_cmd_valid = qemu_get_byte(f); 1485 s->id.reserved = qemu_get_byte(f); 1486 s->id.cu_type = qemu_get_be16(f); 1487 s->id.cu_model = qemu_get_byte(f); 1488 s->id.dev_type = qemu_get_be16(f); 1489 s->id.dev_model = qemu_get_byte(f); 1490 s->id.unused = qemu_get_byte(f); 1491 for (i = 0; i < ARRAY_SIZE(s->id.ciw); i++) { 1492 s->id.ciw[i].type = qemu_get_byte(f); 1493 s->id.ciw[i].command = qemu_get_byte(f); 1494 s->id.ciw[i].count = qemu_get_be16(f); 1495 } 1496 s->ccw_fmt_1 = qemu_get_byte(f); 1497 s->ccw_no_data_cnt = qemu_get_byte(f); 1498 /* 1499 * Hack alert. We don't migrate the channel subsystem status (no 1500 * device!), but we need to find out if the guest enabled mss/mcss-e. 1501 * If the subchannel is enabled, it certainly was able to access it, 1502 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid 1503 * values. This is not watertight, but better than nothing. 1504 */ 1505 if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) { 1506 if (s->ssid) { 1507 channel_subsys->max_ssid = MAX_SSID; 1508 } 1509 if (s->cssid != channel_subsys->default_cssid) { 1510 channel_subsys->max_cssid = MAX_CSSID; 1511 } 1512 } 1513 return 0; 1514 } 1515 1516 1517 static void css_init(void) 1518 { 1519 channel_subsys = g_malloc0(sizeof(*channel_subsys)); 1520 QTAILQ_INIT(&channel_subsys->pending_crws); 1521 channel_subsys->sei_pending = false; 1522 channel_subsys->do_crw_mchk = true; 1523 channel_subsys->crws_lost = false; 1524 channel_subsys->chnmon_active = false; 1525 QTAILQ_INIT(&channel_subsys->io_adapters); 1526 } 1527 machine_init(css_init); 1528 1529 void css_reset_sch(SubchDev *sch) 1530 { 1531 PMCW *p = &sch->curr_status.pmcw; 1532 1533 if ((p->flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) { 1534 sch->disable_cb(sch); 1535 } 1536 1537 p->intparm = 0; 1538 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1539 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1540 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF); 1541 p->flags |= PMCW_FLAGS_MASK_DNV; 1542 p->devno = sch->devno; 1543 p->pim = 0x80; 1544 p->lpm = p->pim; 1545 p->pnom = 0; 1546 p->lpum = 0; 1547 p->mbi = 0; 1548 p->pom = 0xff; 1549 p->pam = 0x80; 1550 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME | 1551 PMCW_CHARS_MASK_CSENSE); 1552 1553 memset(&sch->curr_status.scsw, 0, sizeof(sch->curr_status.scsw)); 1554 sch->curr_status.mba = 0; 1555 1556 sch->channel_prog = 0x0; 1557 sch->last_cmd_valid = false; 1558 sch->thinint_active = false; 1559 } 1560 1561 void css_reset(void) 1562 { 1563 CrwContainer *crw_cont; 1564 1565 /* Clean up monitoring. */ 1566 channel_subsys->chnmon_active = false; 1567 channel_subsys->chnmon_area = 0; 1568 1569 /* Clear pending CRWs. */ 1570 while ((crw_cont = QTAILQ_FIRST(&channel_subsys->pending_crws))) { 1571 QTAILQ_REMOVE(&channel_subsys->pending_crws, crw_cont, sibling); 1572 g_free(crw_cont); 1573 } 1574 channel_subsys->sei_pending = false; 1575 channel_subsys->do_crw_mchk = true; 1576 channel_subsys->crws_lost = false; 1577 1578 /* Reset maximum ids. */ 1579 channel_subsys->max_cssid = 0; 1580 channel_subsys->max_ssid = 0; 1581 } 1582