1 /* 2 * Channel subsystem base support. 3 * 4 * Copyright 2012 IBM Corp. 5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or (at 8 * your option) any later version. See the COPYING file in the top-level 9 * directory. 10 */ 11 12 #include <hw/qdev.h> 13 #include "qemu/bitops.h" 14 #include "exec/address-spaces.h" 15 #include "cpu.h" 16 #include "ioinst.h" 17 #include "css.h" 18 #include "trace.h" 19 #include "hw/s390x/s390_flic.h" 20 21 typedef struct CrwContainer { 22 CRW crw; 23 QTAILQ_ENTRY(CrwContainer) sibling; 24 } CrwContainer; 25 26 typedef struct ChpInfo { 27 uint8_t in_use; 28 uint8_t type; 29 uint8_t is_virtual; 30 } ChpInfo; 31 32 typedef struct SubchSet { 33 SubchDev *sch[MAX_SCHID + 1]; 34 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 35 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 36 } SubchSet; 37 38 typedef struct CssImage { 39 SubchSet *sch_set[MAX_SSID + 1]; 40 ChpInfo chpids[MAX_CHPID + 1]; 41 } CssImage; 42 43 typedef struct IoAdapter { 44 uint32_t id; 45 uint8_t type; 46 uint8_t isc; 47 QTAILQ_ENTRY(IoAdapter) sibling; 48 } IoAdapter; 49 50 typedef struct ChannelSubSys { 51 QTAILQ_HEAD(, CrwContainer) pending_crws; 52 bool do_crw_mchk; 53 bool crws_lost; 54 uint8_t max_cssid; 55 uint8_t max_ssid; 56 bool chnmon_active; 57 uint64_t chnmon_area; 58 CssImage *css[MAX_CSSID + 1]; 59 uint8_t default_cssid; 60 QTAILQ_HEAD(, IoAdapter) io_adapters; 61 } ChannelSubSys; 62 63 static ChannelSubSys *channel_subsys; 64 65 int css_create_css_image(uint8_t cssid, bool default_image) 66 { 67 trace_css_new_image(cssid, default_image ? "(default)" : ""); 68 if (cssid > MAX_CSSID) { 69 return -EINVAL; 70 } 71 if (channel_subsys->css[cssid]) { 72 return -EBUSY; 73 } 74 channel_subsys->css[cssid] = g_malloc0(sizeof(CssImage)); 75 if (default_image) { 76 channel_subsys->default_cssid = cssid; 77 } 78 return 0; 79 } 80 81 int css_register_io_adapter(uint8_t type, uint8_t isc, bool swap, 82 bool maskable, uint32_t *id) 83 { 84 IoAdapter *adapter; 85 bool found = false; 86 int ret; 87 S390FLICState *fs = s390_get_flic(); 88 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs); 89 90 *id = 0; 91 QTAILQ_FOREACH(adapter, &channel_subsys->io_adapters, sibling) { 92 if ((adapter->type == type) && (adapter->isc == isc)) { 93 *id = adapter->id; 94 found = true; 95 ret = 0; 96 break; 97 } 98 if (adapter->id >= *id) { 99 *id = adapter->id + 1; 100 } 101 } 102 if (found) { 103 goto out; 104 } 105 adapter = g_new0(IoAdapter, 1); 106 ret = fsc->register_io_adapter(fs, *id, isc, swap, maskable); 107 if (ret == 0) { 108 adapter->id = *id; 109 adapter->isc = isc; 110 adapter->type = type; 111 QTAILQ_INSERT_TAIL(&channel_subsys->io_adapters, adapter, sibling); 112 } else { 113 g_free(adapter); 114 fprintf(stderr, "Unexpected error %d when registering adapter %d\n", 115 ret, *id); 116 } 117 out: 118 return ret; 119 } 120 121 uint16_t css_build_subchannel_id(SubchDev *sch) 122 { 123 if (channel_subsys->max_cssid > 0) { 124 return (sch->cssid << 8) | (1 << 3) | (sch->ssid << 1) | 1; 125 } 126 return (sch->ssid << 1) | 1; 127 } 128 129 static void css_inject_io_interrupt(SubchDev *sch) 130 { 131 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 132 133 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 134 sch->curr_status.pmcw.intparm, isc, ""); 135 s390_io_interrupt(css_build_subchannel_id(sch), 136 sch->schid, 137 sch->curr_status.pmcw.intparm, 138 isc << 27); 139 } 140 141 void css_conditional_io_interrupt(SubchDev *sch) 142 { 143 /* 144 * If the subchannel is not currently status pending, make it pending 145 * with alert status. 146 */ 147 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) { 148 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 149 150 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 151 sch->curr_status.pmcw.intparm, isc, 152 "(unsolicited)"); 153 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 154 sch->curr_status.scsw.ctrl |= 155 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 156 /* Inject an I/O interrupt. */ 157 s390_io_interrupt(css_build_subchannel_id(sch), 158 sch->schid, 159 sch->curr_status.pmcw.intparm, 160 isc << 27); 161 } 162 } 163 164 void css_adapter_interrupt(uint8_t isc) 165 { 166 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI; 167 168 trace_css_adapter_interrupt(isc); 169 s390_io_interrupt(0, 0, 0, io_int_word); 170 } 171 172 static void sch_handle_clear_func(SubchDev *sch) 173 { 174 PMCW *p = &sch->curr_status.pmcw; 175 SCSW *s = &sch->curr_status.scsw; 176 int path; 177 178 /* Path management: In our simple css, we always choose the only path. */ 179 path = 0x80; 180 181 /* Reset values prior to 'issuing the clear signal'. */ 182 p->lpum = 0; 183 p->pom = 0xff; 184 s->flags &= ~SCSW_FLAGS_MASK_PNO; 185 186 /* We always 'attempt to issue the clear signal', and we always succeed. */ 187 sch->channel_prog = 0x0; 188 sch->last_cmd_valid = false; 189 s->ctrl &= ~SCSW_ACTL_CLEAR_PEND; 190 s->ctrl |= SCSW_STCTL_STATUS_PEND; 191 192 s->dstat = 0; 193 s->cstat = 0; 194 p->lpum = path; 195 196 } 197 198 static void sch_handle_halt_func(SubchDev *sch) 199 { 200 201 PMCW *p = &sch->curr_status.pmcw; 202 SCSW *s = &sch->curr_status.scsw; 203 int path; 204 205 /* Path management: In our simple css, we always choose the only path. */ 206 path = 0x80; 207 208 /* We always 'attempt to issue the halt signal', and we always succeed. */ 209 sch->channel_prog = 0x0; 210 sch->last_cmd_valid = false; 211 s->ctrl &= ~SCSW_ACTL_HALT_PEND; 212 s->ctrl |= SCSW_STCTL_STATUS_PEND; 213 214 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) || 215 !((s->ctrl & SCSW_ACTL_START_PEND) || 216 (s->ctrl & SCSW_ACTL_SUSP))) { 217 s->dstat = SCSW_DSTAT_DEVICE_END; 218 } 219 s->cstat = 0; 220 p->lpum = path; 221 222 } 223 224 static void copy_sense_id_to_guest(SenseId *dest, SenseId *src) 225 { 226 int i; 227 228 dest->reserved = src->reserved; 229 dest->cu_type = cpu_to_be16(src->cu_type); 230 dest->cu_model = src->cu_model; 231 dest->dev_type = cpu_to_be16(src->dev_type); 232 dest->dev_model = src->dev_model; 233 dest->unused = src->unused; 234 for (i = 0; i < ARRAY_SIZE(dest->ciw); i++) { 235 dest->ciw[i].type = src->ciw[i].type; 236 dest->ciw[i].command = src->ciw[i].command; 237 dest->ciw[i].count = cpu_to_be16(src->ciw[i].count); 238 } 239 } 240 241 static CCW1 copy_ccw_from_guest(hwaddr addr) 242 { 243 CCW1 tmp; 244 CCW1 ret; 245 246 cpu_physical_memory_read(addr, &tmp, sizeof(tmp)); 247 ret.cmd_code = tmp.cmd_code; 248 ret.flags = tmp.flags; 249 ret.count = be16_to_cpu(tmp.count); 250 ret.cda = be32_to_cpu(tmp.cda); 251 252 return ret; 253 } 254 255 static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr) 256 { 257 int ret; 258 bool check_len; 259 int len; 260 CCW1 ccw; 261 262 if (!ccw_addr) { 263 return -EIO; 264 } 265 266 ccw = copy_ccw_from_guest(ccw_addr); 267 268 /* Check for invalid command codes. */ 269 if ((ccw.cmd_code & 0x0f) == 0) { 270 return -EINVAL; 271 } 272 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) && 273 ((ccw.cmd_code & 0xf0) != 0)) { 274 return -EINVAL; 275 } 276 277 if (ccw.flags & CCW_FLAG_SUSPEND) { 278 return -EINPROGRESS; 279 } 280 281 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC)); 282 283 /* Look at the command. */ 284 switch (ccw.cmd_code) { 285 case CCW_CMD_NOOP: 286 /* Nothing to do. */ 287 ret = 0; 288 break; 289 case CCW_CMD_BASIC_SENSE: 290 if (check_len) { 291 if (ccw.count != sizeof(sch->sense_data)) { 292 ret = -EINVAL; 293 break; 294 } 295 } 296 len = MIN(ccw.count, sizeof(sch->sense_data)); 297 cpu_physical_memory_write(ccw.cda, sch->sense_data, len); 298 sch->curr_status.scsw.count = ccw.count - len; 299 memset(sch->sense_data, 0, sizeof(sch->sense_data)); 300 ret = 0; 301 break; 302 case CCW_CMD_SENSE_ID: 303 { 304 SenseId sense_id; 305 306 copy_sense_id_to_guest(&sense_id, &sch->id); 307 /* Sense ID information is device specific. */ 308 if (check_len) { 309 if (ccw.count != sizeof(sense_id)) { 310 ret = -EINVAL; 311 break; 312 } 313 } 314 len = MIN(ccw.count, sizeof(sense_id)); 315 /* 316 * Only indicate 0xff in the first sense byte if we actually 317 * have enough place to store at least bytes 0-3. 318 */ 319 if (len >= 4) { 320 sense_id.reserved = 0xff; 321 } else { 322 sense_id.reserved = 0; 323 } 324 cpu_physical_memory_write(ccw.cda, &sense_id, len); 325 sch->curr_status.scsw.count = ccw.count - len; 326 ret = 0; 327 break; 328 } 329 case CCW_CMD_TIC: 330 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) { 331 ret = -EINVAL; 332 break; 333 } 334 if (ccw.flags & (CCW_FLAG_CC | CCW_FLAG_DC)) { 335 ret = -EINVAL; 336 break; 337 } 338 sch->channel_prog = ccw.cda; 339 ret = -EAGAIN; 340 break; 341 default: 342 if (sch->ccw_cb) { 343 /* Handle device specific commands. */ 344 ret = sch->ccw_cb(sch, ccw); 345 } else { 346 ret = -ENOSYS; 347 } 348 break; 349 } 350 sch->last_cmd = ccw; 351 sch->last_cmd_valid = true; 352 if (ret == 0) { 353 if (ccw.flags & CCW_FLAG_CC) { 354 sch->channel_prog += 8; 355 ret = -EAGAIN; 356 } 357 } 358 359 return ret; 360 } 361 362 static void sch_handle_start_func(SubchDev *sch, ORB *orb) 363 { 364 365 PMCW *p = &sch->curr_status.pmcw; 366 SCSW *s = &sch->curr_status.scsw; 367 int path; 368 int ret; 369 370 /* Path management: In our simple css, we always choose the only path. */ 371 path = 0x80; 372 373 if (!(s->ctrl & SCSW_ACTL_SUSP)) { 374 /* Look at the orb and try to execute the channel program. */ 375 assert(orb != NULL); /* resume does not pass an orb */ 376 p->intparm = orb->intparm; 377 if (!(orb->lpm & path)) { 378 /* Generate a deferred cc 3 condition. */ 379 s->flags |= SCSW_FLAGS_MASK_CC; 380 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 381 s->ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND); 382 return; 383 } 384 } else { 385 s->ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND); 386 } 387 sch->last_cmd_valid = false; 388 do { 389 ret = css_interpret_ccw(sch, sch->channel_prog); 390 switch (ret) { 391 case -EAGAIN: 392 /* ccw chain, continue processing */ 393 break; 394 case 0: 395 /* success */ 396 s->ctrl &= ~SCSW_ACTL_START_PEND; 397 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 398 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 399 SCSW_STCTL_STATUS_PEND; 400 s->dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END; 401 break; 402 case -ENOSYS: 403 /* unsupported command, generate unit check (command reject) */ 404 s->ctrl &= ~SCSW_ACTL_START_PEND; 405 s->dstat = SCSW_DSTAT_UNIT_CHECK; 406 /* Set sense bit 0 in ecw0. */ 407 sch->sense_data[0] = 0x80; 408 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 409 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 410 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 411 break; 412 case -EFAULT: 413 /* memory problem, generate channel data check */ 414 s->ctrl &= ~SCSW_ACTL_START_PEND; 415 s->cstat = SCSW_CSTAT_DATA_CHECK; 416 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 417 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 418 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 419 break; 420 case -EBUSY: 421 /* subchannel busy, generate deferred cc 1 */ 422 s->flags &= ~SCSW_FLAGS_MASK_CC; 423 s->flags |= (1 << 8); 424 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 425 s->ctrl |= SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 426 break; 427 case -EINPROGRESS: 428 /* channel program has been suspended */ 429 s->ctrl &= ~SCSW_ACTL_START_PEND; 430 s->ctrl |= SCSW_ACTL_SUSP; 431 break; 432 default: 433 /* error, generate channel program check */ 434 s->ctrl &= ~SCSW_ACTL_START_PEND; 435 s->cstat = SCSW_CSTAT_PROG_CHECK; 436 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 437 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 438 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 439 break; 440 } 441 } while (ret == -EAGAIN); 442 443 } 444 445 /* 446 * On real machines, this would run asynchronously to the main vcpus. 447 * We might want to make some parts of the ssch handling (interpreting 448 * read/writes) asynchronous later on if we start supporting more than 449 * our current very simple devices. 450 */ 451 static void do_subchannel_work(SubchDev *sch, ORB *orb) 452 { 453 454 SCSW *s = &sch->curr_status.scsw; 455 456 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) { 457 sch_handle_clear_func(sch); 458 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) { 459 sch_handle_halt_func(sch); 460 } else if (s->ctrl & SCSW_FCTL_START_FUNC) { 461 sch_handle_start_func(sch, orb); 462 } else { 463 /* Cannot happen. */ 464 return; 465 } 466 css_inject_io_interrupt(sch); 467 } 468 469 static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src) 470 { 471 int i; 472 473 dest->intparm = cpu_to_be32(src->intparm); 474 dest->flags = cpu_to_be16(src->flags); 475 dest->devno = cpu_to_be16(src->devno); 476 dest->lpm = src->lpm; 477 dest->pnom = src->pnom; 478 dest->lpum = src->lpum; 479 dest->pim = src->pim; 480 dest->mbi = cpu_to_be16(src->mbi); 481 dest->pom = src->pom; 482 dest->pam = src->pam; 483 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 484 dest->chpid[i] = src->chpid[i]; 485 } 486 dest->chars = cpu_to_be32(src->chars); 487 } 488 489 static void copy_scsw_to_guest(SCSW *dest, const SCSW *src) 490 { 491 dest->flags = cpu_to_be16(src->flags); 492 dest->ctrl = cpu_to_be16(src->ctrl); 493 dest->cpa = cpu_to_be32(src->cpa); 494 dest->dstat = src->dstat; 495 dest->cstat = src->cstat; 496 dest->count = cpu_to_be16(src->count); 497 } 498 499 static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src) 500 { 501 int i; 502 503 copy_pmcw_to_guest(&dest->pmcw, &src->pmcw); 504 copy_scsw_to_guest(&dest->scsw, &src->scsw); 505 dest->mba = cpu_to_be64(src->mba); 506 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 507 dest->mda[i] = src->mda[i]; 508 } 509 } 510 511 int css_do_stsch(SubchDev *sch, SCHIB *schib) 512 { 513 /* Use current status. */ 514 copy_schib_to_guest(schib, &sch->curr_status); 515 return 0; 516 } 517 518 static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src) 519 { 520 int i; 521 522 dest->intparm = be32_to_cpu(src->intparm); 523 dest->flags = be16_to_cpu(src->flags); 524 dest->devno = be16_to_cpu(src->devno); 525 dest->lpm = src->lpm; 526 dest->pnom = src->pnom; 527 dest->lpum = src->lpum; 528 dest->pim = src->pim; 529 dest->mbi = be16_to_cpu(src->mbi); 530 dest->pom = src->pom; 531 dest->pam = src->pam; 532 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 533 dest->chpid[i] = src->chpid[i]; 534 } 535 dest->chars = be32_to_cpu(src->chars); 536 } 537 538 static void copy_scsw_from_guest(SCSW *dest, const SCSW *src) 539 { 540 dest->flags = be16_to_cpu(src->flags); 541 dest->ctrl = be16_to_cpu(src->ctrl); 542 dest->cpa = be32_to_cpu(src->cpa); 543 dest->dstat = src->dstat; 544 dest->cstat = src->cstat; 545 dest->count = be16_to_cpu(src->count); 546 } 547 548 static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src) 549 { 550 int i; 551 552 copy_pmcw_from_guest(&dest->pmcw, &src->pmcw); 553 copy_scsw_from_guest(&dest->scsw, &src->scsw); 554 dest->mba = be64_to_cpu(src->mba); 555 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 556 dest->mda[i] = src->mda[i]; 557 } 558 } 559 560 int css_do_msch(SubchDev *sch, SCHIB *orig_schib) 561 { 562 SCSW *s = &sch->curr_status.scsw; 563 PMCW *p = &sch->curr_status.pmcw; 564 int ret; 565 SCHIB schib; 566 567 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_DNV)) { 568 ret = 0; 569 goto out; 570 } 571 572 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 573 ret = -EINPROGRESS; 574 goto out; 575 } 576 577 if (s->ctrl & 578 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) { 579 ret = -EBUSY; 580 goto out; 581 } 582 583 copy_schib_from_guest(&schib, orig_schib); 584 /* Only update the program-modifiable fields. */ 585 p->intparm = schib.pmcw.intparm; 586 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 587 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 588 PMCW_FLAGS_MASK_MP); 589 p->flags |= schib.pmcw.flags & 590 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 591 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 592 PMCW_FLAGS_MASK_MP); 593 p->lpm = schib.pmcw.lpm; 594 p->mbi = schib.pmcw.mbi; 595 p->pom = schib.pmcw.pom; 596 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 597 p->chars |= schib.pmcw.chars & 598 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 599 sch->curr_status.mba = schib.mba; 600 601 ret = 0; 602 603 out: 604 return ret; 605 } 606 607 int css_do_xsch(SubchDev *sch) 608 { 609 SCSW *s = &sch->curr_status.scsw; 610 PMCW *p = &sch->curr_status.pmcw; 611 int ret; 612 613 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 614 ret = -ENODEV; 615 goto out; 616 } 617 618 if (!(s->ctrl & SCSW_CTRL_MASK_FCTL) || 619 ((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 620 (!(s->ctrl & 621 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) || 622 (s->ctrl & SCSW_ACTL_SUBCH_ACTIVE)) { 623 ret = -EINPROGRESS; 624 goto out; 625 } 626 627 if (s->ctrl & SCSW_CTRL_MASK_STCTL) { 628 ret = -EBUSY; 629 goto out; 630 } 631 632 /* Cancel the current operation. */ 633 s->ctrl &= ~(SCSW_FCTL_START_FUNC | 634 SCSW_ACTL_RESUME_PEND | 635 SCSW_ACTL_START_PEND | 636 SCSW_ACTL_SUSP); 637 sch->channel_prog = 0x0; 638 sch->last_cmd_valid = false; 639 s->dstat = 0; 640 s->cstat = 0; 641 ret = 0; 642 643 out: 644 return ret; 645 } 646 647 int css_do_csch(SubchDev *sch) 648 { 649 SCSW *s = &sch->curr_status.scsw; 650 PMCW *p = &sch->curr_status.pmcw; 651 int ret; 652 653 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 654 ret = -ENODEV; 655 goto out; 656 } 657 658 /* Trigger the clear function. */ 659 s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL); 660 s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_FCTL_CLEAR_FUNC; 661 662 do_subchannel_work(sch, NULL); 663 ret = 0; 664 665 out: 666 return ret; 667 } 668 669 int css_do_hsch(SubchDev *sch) 670 { 671 SCSW *s = &sch->curr_status.scsw; 672 PMCW *p = &sch->curr_status.pmcw; 673 int ret; 674 675 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 676 ret = -ENODEV; 677 goto out; 678 } 679 680 if (((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) || 681 (s->ctrl & (SCSW_STCTL_PRIMARY | 682 SCSW_STCTL_SECONDARY | 683 SCSW_STCTL_ALERT))) { 684 ret = -EINPROGRESS; 685 goto out; 686 } 687 688 if (s->ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) { 689 ret = -EBUSY; 690 goto out; 691 } 692 693 /* Trigger the halt function. */ 694 s->ctrl |= SCSW_FCTL_HALT_FUNC; 695 s->ctrl &= ~SCSW_FCTL_START_FUNC; 696 if (((s->ctrl & SCSW_CTRL_MASK_ACTL) == 697 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) && 698 ((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_INTERMEDIATE)) { 699 s->ctrl &= ~SCSW_STCTL_STATUS_PEND; 700 } 701 s->ctrl |= SCSW_ACTL_HALT_PEND; 702 703 do_subchannel_work(sch, NULL); 704 ret = 0; 705 706 out: 707 return ret; 708 } 709 710 static void css_update_chnmon(SubchDev *sch) 711 { 712 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) { 713 /* Not active. */ 714 return; 715 } 716 /* The counter is conveniently located at the beginning of the struct. */ 717 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) { 718 /* Format 1, per-subchannel area. */ 719 uint32_t count; 720 721 count = ldl_phys(&address_space_memory, sch->curr_status.mba); 722 count++; 723 stl_phys(&address_space_memory, sch->curr_status.mba, count); 724 } else { 725 /* Format 0, global area. */ 726 uint32_t offset; 727 uint16_t count; 728 729 offset = sch->curr_status.pmcw.mbi << 5; 730 count = lduw_phys(&address_space_memory, 731 channel_subsys->chnmon_area + offset); 732 count++; 733 stw_phys(&address_space_memory, 734 channel_subsys->chnmon_area + offset, count); 735 } 736 } 737 738 int css_do_ssch(SubchDev *sch, ORB *orb) 739 { 740 SCSW *s = &sch->curr_status.scsw; 741 PMCW *p = &sch->curr_status.pmcw; 742 int ret; 743 744 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 745 ret = -ENODEV; 746 goto out; 747 } 748 749 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 750 ret = -EINPROGRESS; 751 goto out; 752 } 753 754 if (s->ctrl & (SCSW_FCTL_START_FUNC | 755 SCSW_FCTL_HALT_FUNC | 756 SCSW_FCTL_CLEAR_FUNC)) { 757 ret = -EBUSY; 758 goto out; 759 } 760 761 /* If monitoring is active, update counter. */ 762 if (channel_subsys->chnmon_active) { 763 css_update_chnmon(sch); 764 } 765 sch->channel_prog = orb->cpa; 766 /* Trigger the start function. */ 767 s->ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND); 768 s->flags &= ~SCSW_FLAGS_MASK_PNO; 769 770 do_subchannel_work(sch, orb); 771 ret = 0; 772 773 out: 774 return ret; 775 } 776 777 static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw) 778 { 779 int i; 780 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 781 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 782 783 copy_scsw_to_guest(&dest->scsw, &src->scsw); 784 785 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) { 786 dest->esw[i] = cpu_to_be32(src->esw[i]); 787 } 788 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) { 789 dest->ecw[i] = cpu_to_be32(src->ecw[i]); 790 } 791 /* extended measurements enabled? */ 792 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) || 793 !(pmcw->flags & PMCW_FLAGS_MASK_TF) || 794 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) { 795 return; 796 } 797 /* extended measurements pending? */ 798 if (!(stctl & SCSW_STCTL_STATUS_PEND)) { 799 return; 800 } 801 if ((stctl & SCSW_STCTL_PRIMARY) || 802 (stctl == SCSW_STCTL_SECONDARY) || 803 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) { 804 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) { 805 dest->emw[i] = cpu_to_be32(src->emw[i]); 806 } 807 } 808 } 809 810 int css_do_tsch(SubchDev *sch, IRB *target_irb) 811 { 812 SCSW *s = &sch->curr_status.scsw; 813 PMCW *p = &sch->curr_status.pmcw; 814 uint16_t stctl; 815 uint16_t fctl; 816 uint16_t actl; 817 IRB irb; 818 int ret; 819 820 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 821 ret = 3; 822 goto out; 823 } 824 825 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL; 826 fctl = s->ctrl & SCSW_CTRL_MASK_FCTL; 827 actl = s->ctrl & SCSW_CTRL_MASK_ACTL; 828 829 /* Prepare the irb for the guest. */ 830 memset(&irb, 0, sizeof(IRB)); 831 832 /* Copy scsw from current status. */ 833 memcpy(&irb.scsw, s, sizeof(SCSW)); 834 if (stctl & SCSW_STCTL_STATUS_PEND) { 835 if (s->cstat & (SCSW_CSTAT_DATA_CHECK | 836 SCSW_CSTAT_CHN_CTRL_CHK | 837 SCSW_CSTAT_INTF_CTRL_CHK)) { 838 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF; 839 irb.esw[0] = 0x04804000; 840 } else { 841 irb.esw[0] = 0x00800000; 842 } 843 /* If a unit check is pending, copy sense data. */ 844 if ((s->dstat & SCSW_DSTAT_UNIT_CHECK) && 845 (p->chars & PMCW_CHARS_MASK_CSENSE)) { 846 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL; 847 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data)); 848 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8); 849 } 850 } 851 /* Store the irb to the guest. */ 852 copy_irb_to_guest(target_irb, &irb, p); 853 854 /* Clear conditions on subchannel, if applicable. */ 855 if (stctl & SCSW_STCTL_STATUS_PEND) { 856 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 857 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) || 858 ((fctl & SCSW_FCTL_HALT_FUNC) && 859 (actl & SCSW_ACTL_SUSP))) { 860 s->ctrl &= ~SCSW_CTRL_MASK_FCTL; 861 } 862 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) { 863 s->flags &= ~SCSW_FLAGS_MASK_PNO; 864 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 865 SCSW_ACTL_START_PEND | 866 SCSW_ACTL_HALT_PEND | 867 SCSW_ACTL_CLEAR_PEND | 868 SCSW_ACTL_SUSP); 869 } else { 870 if ((actl & SCSW_ACTL_SUSP) && 871 (fctl & SCSW_FCTL_START_FUNC)) { 872 s->flags &= ~SCSW_FLAGS_MASK_PNO; 873 if (fctl & SCSW_FCTL_HALT_FUNC) { 874 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 875 SCSW_ACTL_START_PEND | 876 SCSW_ACTL_HALT_PEND | 877 SCSW_ACTL_CLEAR_PEND | 878 SCSW_ACTL_SUSP); 879 } else { 880 s->ctrl &= ~SCSW_ACTL_RESUME_PEND; 881 } 882 } 883 } 884 /* Clear pending sense data. */ 885 if (p->chars & PMCW_CHARS_MASK_CSENSE) { 886 memset(sch->sense_data, 0 , sizeof(sch->sense_data)); 887 } 888 } 889 890 ret = ((stctl & SCSW_STCTL_STATUS_PEND) == 0); 891 892 out: 893 return ret; 894 } 895 896 static void copy_crw_to_guest(CRW *dest, const CRW *src) 897 { 898 dest->flags = cpu_to_be16(src->flags); 899 dest->rsid = cpu_to_be16(src->rsid); 900 } 901 902 int css_do_stcrw(CRW *crw) 903 { 904 CrwContainer *crw_cont; 905 int ret; 906 907 crw_cont = QTAILQ_FIRST(&channel_subsys->pending_crws); 908 if (crw_cont) { 909 QTAILQ_REMOVE(&channel_subsys->pending_crws, crw_cont, sibling); 910 copy_crw_to_guest(crw, &crw_cont->crw); 911 g_free(crw_cont); 912 ret = 0; 913 } else { 914 /* List was empty, turn crw machine checks on again. */ 915 memset(crw, 0, sizeof(*crw)); 916 channel_subsys->do_crw_mchk = true; 917 ret = 1; 918 } 919 920 return ret; 921 } 922 923 int css_do_tpi(IOIntCode *int_code, int lowcore) 924 { 925 /* No pending interrupts for !KVM. */ 926 return 0; 927 } 928 929 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, 930 int rfmt, void *buf) 931 { 932 int i, desc_size; 933 uint32_t words[8]; 934 uint32_t chpid_type_word; 935 CssImage *css; 936 937 if (!m && !cssid) { 938 css = channel_subsys->css[channel_subsys->default_cssid]; 939 } else { 940 css = channel_subsys->css[cssid]; 941 } 942 if (!css) { 943 return 0; 944 } 945 desc_size = 0; 946 for (i = f_chpid; i <= l_chpid; i++) { 947 if (css->chpids[i].in_use) { 948 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i; 949 if (rfmt == 0) { 950 words[0] = cpu_to_be32(chpid_type_word); 951 words[1] = 0; 952 memcpy(buf + desc_size, words, 8); 953 desc_size += 8; 954 } else if (rfmt == 1) { 955 words[0] = cpu_to_be32(chpid_type_word); 956 words[1] = 0; 957 words[2] = 0; 958 words[3] = 0; 959 words[4] = 0; 960 words[5] = 0; 961 words[6] = 0; 962 words[7] = 0; 963 memcpy(buf + desc_size, words, 32); 964 desc_size += 32; 965 } 966 } 967 } 968 return desc_size; 969 } 970 971 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo) 972 { 973 /* dct is currently ignored (not really meaningful for our devices) */ 974 /* TODO: Don't ignore mbk. */ 975 if (update && !channel_subsys->chnmon_active) { 976 /* Enable measuring. */ 977 channel_subsys->chnmon_area = mbo; 978 channel_subsys->chnmon_active = true; 979 } 980 if (!update && channel_subsys->chnmon_active) { 981 /* Disable measuring. */ 982 channel_subsys->chnmon_area = 0; 983 channel_subsys->chnmon_active = false; 984 } 985 } 986 987 int css_do_rsch(SubchDev *sch) 988 { 989 SCSW *s = &sch->curr_status.scsw; 990 PMCW *p = &sch->curr_status.pmcw; 991 int ret; 992 993 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 994 ret = -ENODEV; 995 goto out; 996 } 997 998 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 999 ret = -EINPROGRESS; 1000 goto out; 1001 } 1002 1003 if (((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1004 (s->ctrl & SCSW_ACTL_RESUME_PEND) || 1005 (!(s->ctrl & SCSW_ACTL_SUSP))) { 1006 ret = -EINVAL; 1007 goto out; 1008 } 1009 1010 /* If monitoring is active, update counter. */ 1011 if (channel_subsys->chnmon_active) { 1012 css_update_chnmon(sch); 1013 } 1014 1015 s->ctrl |= SCSW_ACTL_RESUME_PEND; 1016 do_subchannel_work(sch, NULL); 1017 ret = 0; 1018 1019 out: 1020 return ret; 1021 } 1022 1023 int css_do_rchp(uint8_t cssid, uint8_t chpid) 1024 { 1025 uint8_t real_cssid; 1026 1027 if (cssid > channel_subsys->max_cssid) { 1028 return -EINVAL; 1029 } 1030 if (channel_subsys->max_cssid == 0) { 1031 real_cssid = channel_subsys->default_cssid; 1032 } else { 1033 real_cssid = cssid; 1034 } 1035 if (!channel_subsys->css[real_cssid]) { 1036 return -EINVAL; 1037 } 1038 1039 if (!channel_subsys->css[real_cssid]->chpids[chpid].in_use) { 1040 return -ENODEV; 1041 } 1042 1043 if (!channel_subsys->css[real_cssid]->chpids[chpid].is_virtual) { 1044 fprintf(stderr, 1045 "rchp unsupported for non-virtual chpid %x.%02x!\n", 1046 real_cssid, chpid); 1047 return -ENODEV; 1048 } 1049 1050 /* We don't really use a channel path, so we're done here. */ 1051 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1052 channel_subsys->max_cssid > 0 ? 1 : 0, chpid); 1053 if (channel_subsys->max_cssid > 0) { 1054 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 0, real_cssid << 8); 1055 } 1056 return 0; 1057 } 1058 1059 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1060 { 1061 SubchSet *set; 1062 uint8_t real_cssid; 1063 1064 real_cssid = (!m && (cssid == 0)) ? channel_subsys->default_cssid : cssid; 1065 if (real_cssid > MAX_CSSID || ssid > MAX_SSID || 1066 !channel_subsys->css[real_cssid] || 1067 !channel_subsys->css[real_cssid]->sch_set[ssid]) { 1068 return true; 1069 } 1070 set = channel_subsys->css[real_cssid]->sch_set[ssid]; 1071 return schid > find_last_bit(set->schids_used, 1072 (MAX_SCHID + 1) / sizeof(unsigned long)); 1073 } 1074 1075 static int css_add_virtual_chpid(uint8_t cssid, uint8_t chpid, uint8_t type) 1076 { 1077 CssImage *css; 1078 1079 trace_css_chpid_add(cssid, chpid, type); 1080 if (cssid > MAX_CSSID) { 1081 return -EINVAL; 1082 } 1083 css = channel_subsys->css[cssid]; 1084 if (!css) { 1085 return -EINVAL; 1086 } 1087 if (css->chpids[chpid].in_use) { 1088 return -EEXIST; 1089 } 1090 css->chpids[chpid].in_use = 1; 1091 css->chpids[chpid].type = type; 1092 css->chpids[chpid].is_virtual = 1; 1093 1094 css_generate_chp_crws(cssid, chpid); 1095 1096 return 0; 1097 } 1098 1099 void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type) 1100 { 1101 PMCW *p = &sch->curr_status.pmcw; 1102 SCSW *s = &sch->curr_status.scsw; 1103 int i; 1104 CssImage *css = channel_subsys->css[sch->cssid]; 1105 1106 assert(css != NULL); 1107 memset(p, 0, sizeof(PMCW)); 1108 p->flags |= PMCW_FLAGS_MASK_DNV; 1109 p->devno = sch->devno; 1110 /* single path */ 1111 p->pim = 0x80; 1112 p->pom = 0xff; 1113 p->pam = 0x80; 1114 p->chpid[0] = chpid; 1115 if (!css->chpids[chpid].in_use) { 1116 css_add_virtual_chpid(sch->cssid, chpid, type); 1117 } 1118 1119 memset(s, 0, sizeof(SCSW)); 1120 sch->curr_status.mba = 0; 1121 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) { 1122 sch->curr_status.mda[i] = 0; 1123 } 1124 } 1125 1126 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1127 { 1128 uint8_t real_cssid; 1129 1130 real_cssid = (!m && (cssid == 0)) ? channel_subsys->default_cssid : cssid; 1131 1132 if (!channel_subsys->css[real_cssid]) { 1133 return NULL; 1134 } 1135 1136 if (!channel_subsys->css[real_cssid]->sch_set[ssid]) { 1137 return NULL; 1138 } 1139 1140 return channel_subsys->css[real_cssid]->sch_set[ssid]->sch[schid]; 1141 } 1142 1143 bool css_subch_visible(SubchDev *sch) 1144 { 1145 if (sch->ssid > channel_subsys->max_ssid) { 1146 return false; 1147 } 1148 1149 if (sch->cssid != channel_subsys->default_cssid) { 1150 return (channel_subsys->max_cssid > 0); 1151 } 1152 1153 return true; 1154 } 1155 1156 bool css_present(uint8_t cssid) 1157 { 1158 return (channel_subsys->css[cssid] != NULL); 1159 } 1160 1161 bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno) 1162 { 1163 if (!channel_subsys->css[cssid]) { 1164 return false; 1165 } 1166 if (!channel_subsys->css[cssid]->sch_set[ssid]) { 1167 return false; 1168 } 1169 1170 return !!test_bit(devno, 1171 channel_subsys->css[cssid]->sch_set[ssid]->devnos_used); 1172 } 1173 1174 void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid, 1175 uint16_t devno, SubchDev *sch) 1176 { 1177 CssImage *css; 1178 SubchSet *s_set; 1179 1180 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid, 1181 devno); 1182 if (!channel_subsys->css[cssid]) { 1183 fprintf(stderr, 1184 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n", 1185 __func__, cssid, ssid, schid); 1186 return; 1187 } 1188 css = channel_subsys->css[cssid]; 1189 1190 if (!css->sch_set[ssid]) { 1191 css->sch_set[ssid] = g_malloc0(sizeof(SubchSet)); 1192 } 1193 s_set = css->sch_set[ssid]; 1194 1195 s_set->sch[schid] = sch; 1196 if (sch) { 1197 set_bit(schid, s_set->schids_used); 1198 set_bit(devno, s_set->devnos_used); 1199 } else { 1200 clear_bit(schid, s_set->schids_used); 1201 clear_bit(devno, s_set->devnos_used); 1202 } 1203 } 1204 1205 void css_queue_crw(uint8_t rsc, uint8_t erc, int chain, uint16_t rsid) 1206 { 1207 CrwContainer *crw_cont; 1208 1209 trace_css_crw(rsc, erc, rsid, chain ? "(chained)" : ""); 1210 /* TODO: Maybe use a static crw pool? */ 1211 crw_cont = g_try_malloc0(sizeof(CrwContainer)); 1212 if (!crw_cont) { 1213 channel_subsys->crws_lost = true; 1214 return; 1215 } 1216 crw_cont->crw.flags = (rsc << 8) | erc; 1217 if (chain) { 1218 crw_cont->crw.flags |= CRW_FLAGS_MASK_C; 1219 } 1220 crw_cont->crw.rsid = rsid; 1221 if (channel_subsys->crws_lost) { 1222 crw_cont->crw.flags |= CRW_FLAGS_MASK_R; 1223 channel_subsys->crws_lost = false; 1224 } 1225 1226 QTAILQ_INSERT_TAIL(&channel_subsys->pending_crws, crw_cont, sibling); 1227 1228 if (channel_subsys->do_crw_mchk) { 1229 channel_subsys->do_crw_mchk = false; 1230 /* Inject crw pending machine check. */ 1231 s390_crw_mchk(); 1232 } 1233 } 1234 1235 void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid, 1236 int hotplugged, int add) 1237 { 1238 uint8_t guest_cssid; 1239 bool chain_crw; 1240 1241 if (add && !hotplugged) { 1242 return; 1243 } 1244 if (channel_subsys->max_cssid == 0) { 1245 /* Default cssid shows up as 0. */ 1246 guest_cssid = (cssid == channel_subsys->default_cssid) ? 0 : cssid; 1247 } else { 1248 /* Show real cssid to the guest. */ 1249 guest_cssid = cssid; 1250 } 1251 /* 1252 * Only notify for higher subchannel sets/channel subsystems if the 1253 * guest has enabled it. 1254 */ 1255 if ((ssid > channel_subsys->max_ssid) || 1256 (guest_cssid > channel_subsys->max_cssid) || 1257 ((channel_subsys->max_cssid == 0) && 1258 (cssid != channel_subsys->default_cssid))) { 1259 return; 1260 } 1261 chain_crw = (channel_subsys->max_ssid > 0) || 1262 (channel_subsys->max_cssid > 0); 1263 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, chain_crw ? 1 : 0, schid); 1264 if (chain_crw) { 1265 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 1266 (guest_cssid << 8) | (ssid << 4)); 1267 } 1268 } 1269 1270 void css_generate_chp_crws(uint8_t cssid, uint8_t chpid) 1271 { 1272 /* TODO */ 1273 } 1274 1275 int css_enable_mcsse(void) 1276 { 1277 trace_css_enable_facility("mcsse"); 1278 channel_subsys->max_cssid = MAX_CSSID; 1279 return 0; 1280 } 1281 1282 int css_enable_mss(void) 1283 { 1284 trace_css_enable_facility("mss"); 1285 channel_subsys->max_ssid = MAX_SSID; 1286 return 0; 1287 } 1288 1289 void subch_device_save(SubchDev *s, QEMUFile *f) 1290 { 1291 int i; 1292 1293 qemu_put_byte(f, s->cssid); 1294 qemu_put_byte(f, s->ssid); 1295 qemu_put_be16(f, s->schid); 1296 qemu_put_be16(f, s->devno); 1297 qemu_put_byte(f, s->thinint_active); 1298 /* SCHIB */ 1299 /* PMCW */ 1300 qemu_put_be32(f, s->curr_status.pmcw.intparm); 1301 qemu_put_be16(f, s->curr_status.pmcw.flags); 1302 qemu_put_be16(f, s->curr_status.pmcw.devno); 1303 qemu_put_byte(f, s->curr_status.pmcw.lpm); 1304 qemu_put_byte(f, s->curr_status.pmcw.pnom); 1305 qemu_put_byte(f, s->curr_status.pmcw.lpum); 1306 qemu_put_byte(f, s->curr_status.pmcw.pim); 1307 qemu_put_be16(f, s->curr_status.pmcw.mbi); 1308 qemu_put_byte(f, s->curr_status.pmcw.pom); 1309 qemu_put_byte(f, s->curr_status.pmcw.pam); 1310 qemu_put_buffer(f, s->curr_status.pmcw.chpid, 8); 1311 qemu_put_be32(f, s->curr_status.pmcw.chars); 1312 /* SCSW */ 1313 qemu_put_be16(f, s->curr_status.scsw.flags); 1314 qemu_put_be16(f, s->curr_status.scsw.ctrl); 1315 qemu_put_be32(f, s->curr_status.scsw.cpa); 1316 qemu_put_byte(f, s->curr_status.scsw.dstat); 1317 qemu_put_byte(f, s->curr_status.scsw.cstat); 1318 qemu_put_be16(f, s->curr_status.scsw.count); 1319 qemu_put_be64(f, s->curr_status.mba); 1320 qemu_put_buffer(f, s->curr_status.mda, 4); 1321 /* end SCHIB */ 1322 qemu_put_buffer(f, s->sense_data, 32); 1323 qemu_put_be64(f, s->channel_prog); 1324 /* last cmd */ 1325 qemu_put_byte(f, s->last_cmd.cmd_code); 1326 qemu_put_byte(f, s->last_cmd.flags); 1327 qemu_put_be16(f, s->last_cmd.count); 1328 qemu_put_be32(f, s->last_cmd.cda); 1329 qemu_put_byte(f, s->last_cmd_valid); 1330 qemu_put_byte(f, s->id.reserved); 1331 qemu_put_be16(f, s->id.cu_type); 1332 qemu_put_byte(f, s->id.cu_model); 1333 qemu_put_be16(f, s->id.dev_type); 1334 qemu_put_byte(f, s->id.dev_model); 1335 qemu_put_byte(f, s->id.unused); 1336 for (i = 0; i < ARRAY_SIZE(s->id.ciw); i++) { 1337 qemu_put_byte(f, s->id.ciw[i].type); 1338 qemu_put_byte(f, s->id.ciw[i].command); 1339 qemu_put_be16(f, s->id.ciw[i].count); 1340 } 1341 return; 1342 } 1343 1344 int subch_device_load(SubchDev *s, QEMUFile *f) 1345 { 1346 int i; 1347 1348 s->cssid = qemu_get_byte(f); 1349 s->ssid = qemu_get_byte(f); 1350 s->schid = qemu_get_be16(f); 1351 s->devno = qemu_get_be16(f); 1352 s->thinint_active = qemu_get_byte(f); 1353 /* SCHIB */ 1354 /* PMCW */ 1355 s->curr_status.pmcw.intparm = qemu_get_be32(f); 1356 s->curr_status.pmcw.flags = qemu_get_be16(f); 1357 s->curr_status.pmcw.devno = qemu_get_be16(f); 1358 s->curr_status.pmcw.lpm = qemu_get_byte(f); 1359 s->curr_status.pmcw.pnom = qemu_get_byte(f); 1360 s->curr_status.pmcw.lpum = qemu_get_byte(f); 1361 s->curr_status.pmcw.pim = qemu_get_byte(f); 1362 s->curr_status.pmcw.mbi = qemu_get_be16(f); 1363 s->curr_status.pmcw.pom = qemu_get_byte(f); 1364 s->curr_status.pmcw.pam = qemu_get_byte(f); 1365 qemu_get_buffer(f, s->curr_status.pmcw.chpid, 8); 1366 s->curr_status.pmcw.chars = qemu_get_be32(f); 1367 /* SCSW */ 1368 s->curr_status.scsw.flags = qemu_get_be16(f); 1369 s->curr_status.scsw.ctrl = qemu_get_be16(f); 1370 s->curr_status.scsw.cpa = qemu_get_be32(f); 1371 s->curr_status.scsw.dstat = qemu_get_byte(f); 1372 s->curr_status.scsw.cstat = qemu_get_byte(f); 1373 s->curr_status.scsw.count = qemu_get_be16(f); 1374 s->curr_status.mba = qemu_get_be64(f); 1375 qemu_get_buffer(f, s->curr_status.mda, 4); 1376 /* end SCHIB */ 1377 qemu_get_buffer(f, s->sense_data, 32); 1378 s->channel_prog = qemu_get_be64(f); 1379 /* last cmd */ 1380 s->last_cmd.cmd_code = qemu_get_byte(f); 1381 s->last_cmd.flags = qemu_get_byte(f); 1382 s->last_cmd.count = qemu_get_be16(f); 1383 s->last_cmd.cda = qemu_get_be32(f); 1384 s->last_cmd_valid = qemu_get_byte(f); 1385 s->id.reserved = qemu_get_byte(f); 1386 s->id.cu_type = qemu_get_be16(f); 1387 s->id.cu_model = qemu_get_byte(f); 1388 s->id.dev_type = qemu_get_be16(f); 1389 s->id.dev_model = qemu_get_byte(f); 1390 s->id.unused = qemu_get_byte(f); 1391 for (i = 0; i < ARRAY_SIZE(s->id.ciw); i++) { 1392 s->id.ciw[i].type = qemu_get_byte(f); 1393 s->id.ciw[i].command = qemu_get_byte(f); 1394 s->id.ciw[i].count = qemu_get_be16(f); 1395 } 1396 return 0; 1397 } 1398 1399 1400 static void css_init(void) 1401 { 1402 channel_subsys = g_malloc0(sizeof(*channel_subsys)); 1403 QTAILQ_INIT(&channel_subsys->pending_crws); 1404 channel_subsys->do_crw_mchk = true; 1405 channel_subsys->crws_lost = false; 1406 channel_subsys->chnmon_active = false; 1407 QTAILQ_INIT(&channel_subsys->io_adapters); 1408 } 1409 machine_init(css_init); 1410 1411 void css_reset_sch(SubchDev *sch) 1412 { 1413 PMCW *p = &sch->curr_status.pmcw; 1414 1415 p->intparm = 0; 1416 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1417 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1418 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF); 1419 p->flags |= PMCW_FLAGS_MASK_DNV; 1420 p->devno = sch->devno; 1421 p->pim = 0x80; 1422 p->lpm = p->pim; 1423 p->pnom = 0; 1424 p->lpum = 0; 1425 p->mbi = 0; 1426 p->pom = 0xff; 1427 p->pam = 0x80; 1428 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME | 1429 PMCW_CHARS_MASK_CSENSE); 1430 1431 memset(&sch->curr_status.scsw, 0, sizeof(sch->curr_status.scsw)); 1432 sch->curr_status.mba = 0; 1433 1434 sch->channel_prog = 0x0; 1435 sch->last_cmd_valid = false; 1436 sch->thinint_active = false; 1437 } 1438 1439 void css_reset(void) 1440 { 1441 CrwContainer *crw_cont; 1442 1443 /* Clean up monitoring. */ 1444 channel_subsys->chnmon_active = false; 1445 channel_subsys->chnmon_area = 0; 1446 1447 /* Clear pending CRWs. */ 1448 while ((crw_cont = QTAILQ_FIRST(&channel_subsys->pending_crws))) { 1449 QTAILQ_REMOVE(&channel_subsys->pending_crws, crw_cont, sibling); 1450 g_free(crw_cont); 1451 } 1452 channel_subsys->do_crw_mchk = true; 1453 channel_subsys->crws_lost = false; 1454 1455 /* Reset maximum ids. */ 1456 channel_subsys->max_cssid = 0; 1457 channel_subsys->max_ssid = 0; 1458 } 1459