1 /* 2 * Channel subsystem base support. 3 * 4 * Copyright 2012 IBM Corp. 5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or (at 8 * your option) any later version. See the COPYING file in the top-level 9 * directory. 10 */ 11 12 #include <hw/qdev.h> 13 #include "qemu/bitops.h" 14 #include "exec/address-spaces.h" 15 #include "cpu.h" 16 #include "ioinst.h" 17 #include "css.h" 18 #include "trace.h" 19 #include "hw/s390x/s390_flic.h" 20 21 typedef struct CrwContainer { 22 CRW crw; 23 QTAILQ_ENTRY(CrwContainer) sibling; 24 } CrwContainer; 25 26 typedef struct ChpInfo { 27 uint8_t in_use; 28 uint8_t type; 29 uint8_t is_virtual; 30 } ChpInfo; 31 32 typedef struct SubchSet { 33 SubchDev *sch[MAX_SCHID + 1]; 34 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 35 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 36 } SubchSet; 37 38 typedef struct CssImage { 39 SubchSet *sch_set[MAX_SSID + 1]; 40 ChpInfo chpids[MAX_CHPID + 1]; 41 } CssImage; 42 43 typedef struct IoAdapter { 44 uint32_t id; 45 uint8_t type; 46 uint8_t isc; 47 QTAILQ_ENTRY(IoAdapter) sibling; 48 } IoAdapter; 49 50 typedef struct ChannelSubSys { 51 QTAILQ_HEAD(, CrwContainer) pending_crws; 52 bool do_crw_mchk; 53 bool crws_lost; 54 uint8_t max_cssid; 55 uint8_t max_ssid; 56 bool chnmon_active; 57 uint64_t chnmon_area; 58 CssImage *css[MAX_CSSID + 1]; 59 uint8_t default_cssid; 60 QTAILQ_HEAD(, IoAdapter) io_adapters; 61 } ChannelSubSys; 62 63 static ChannelSubSys *channel_subsys; 64 65 int css_create_css_image(uint8_t cssid, bool default_image) 66 { 67 trace_css_new_image(cssid, default_image ? "(default)" : ""); 68 if (cssid > MAX_CSSID) { 69 return -EINVAL; 70 } 71 if (channel_subsys->css[cssid]) { 72 return -EBUSY; 73 } 74 channel_subsys->css[cssid] = g_malloc0(sizeof(CssImage)); 75 if (default_image) { 76 channel_subsys->default_cssid = cssid; 77 } 78 return 0; 79 } 80 81 int css_register_io_adapter(uint8_t type, uint8_t isc, bool swap, 82 bool maskable, uint32_t *id) 83 { 84 IoAdapter *adapter; 85 bool found = false; 86 int ret; 87 S390FLICState *fs = s390_get_flic(); 88 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs); 89 90 *id = 0; 91 QTAILQ_FOREACH(adapter, &channel_subsys->io_adapters, sibling) { 92 if ((adapter->type == type) && (adapter->isc == isc)) { 93 *id = adapter->id; 94 found = true; 95 ret = 0; 96 break; 97 } 98 if (adapter->id >= *id) { 99 *id = adapter->id + 1; 100 } 101 } 102 if (found) { 103 goto out; 104 } 105 adapter = g_new0(IoAdapter, 1); 106 ret = fsc->register_io_adapter(fs, *id, isc, swap, maskable); 107 if (ret == 0) { 108 adapter->id = *id; 109 adapter->isc = isc; 110 adapter->type = type; 111 QTAILQ_INSERT_TAIL(&channel_subsys->io_adapters, adapter, sibling); 112 } else { 113 g_free(adapter); 114 fprintf(stderr, "Unexpected error %d when registering adapter %d\n", 115 ret, *id); 116 } 117 out: 118 return ret; 119 } 120 121 uint16_t css_build_subchannel_id(SubchDev *sch) 122 { 123 if (channel_subsys->max_cssid > 0) { 124 return (sch->cssid << 8) | (1 << 3) | (sch->ssid << 1) | 1; 125 } 126 return (sch->ssid << 1) | 1; 127 } 128 129 static void css_inject_io_interrupt(SubchDev *sch) 130 { 131 S390CPU *cpu = s390_cpu_addr2state(0); 132 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 133 134 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 135 sch->curr_status.pmcw.intparm, isc, ""); 136 s390_io_interrupt(cpu, 137 css_build_subchannel_id(sch), 138 sch->schid, 139 sch->curr_status.pmcw.intparm, 140 isc << 27); 141 } 142 143 void css_conditional_io_interrupt(SubchDev *sch) 144 { 145 /* 146 * If the subchannel is not currently status pending, make it pending 147 * with alert status. 148 */ 149 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) { 150 S390CPU *cpu = s390_cpu_addr2state(0); 151 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 152 153 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 154 sch->curr_status.pmcw.intparm, isc, 155 "(unsolicited)"); 156 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 157 sch->curr_status.scsw.ctrl |= 158 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 159 /* Inject an I/O interrupt. */ 160 s390_io_interrupt(cpu, 161 css_build_subchannel_id(sch), 162 sch->schid, 163 sch->curr_status.pmcw.intparm, 164 isc << 27); 165 } 166 } 167 168 void css_adapter_interrupt(uint8_t isc) 169 { 170 S390CPU *cpu = s390_cpu_addr2state(0); 171 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI; 172 173 trace_css_adapter_interrupt(isc); 174 s390_io_interrupt(cpu, 0, 0, 0, io_int_word); 175 } 176 177 static void sch_handle_clear_func(SubchDev *sch) 178 { 179 PMCW *p = &sch->curr_status.pmcw; 180 SCSW *s = &sch->curr_status.scsw; 181 int path; 182 183 /* Path management: In our simple css, we always choose the only path. */ 184 path = 0x80; 185 186 /* Reset values prior to 'issuing the clear signal'. */ 187 p->lpum = 0; 188 p->pom = 0xff; 189 s->flags &= ~SCSW_FLAGS_MASK_PNO; 190 191 /* We always 'attempt to issue the clear signal', and we always succeed. */ 192 sch->channel_prog = 0x0; 193 sch->last_cmd_valid = false; 194 s->ctrl &= ~SCSW_ACTL_CLEAR_PEND; 195 s->ctrl |= SCSW_STCTL_STATUS_PEND; 196 197 s->dstat = 0; 198 s->cstat = 0; 199 p->lpum = path; 200 201 } 202 203 static void sch_handle_halt_func(SubchDev *sch) 204 { 205 206 PMCW *p = &sch->curr_status.pmcw; 207 SCSW *s = &sch->curr_status.scsw; 208 int path; 209 210 /* Path management: In our simple css, we always choose the only path. */ 211 path = 0x80; 212 213 /* We always 'attempt to issue the halt signal', and we always succeed. */ 214 sch->channel_prog = 0x0; 215 sch->last_cmd_valid = false; 216 s->ctrl &= ~SCSW_ACTL_HALT_PEND; 217 s->ctrl |= SCSW_STCTL_STATUS_PEND; 218 219 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) || 220 !((s->ctrl & SCSW_ACTL_START_PEND) || 221 (s->ctrl & SCSW_ACTL_SUSP))) { 222 s->dstat = SCSW_DSTAT_DEVICE_END; 223 } 224 s->cstat = 0; 225 p->lpum = path; 226 227 } 228 229 static void copy_sense_id_to_guest(SenseId *dest, SenseId *src) 230 { 231 int i; 232 233 dest->reserved = src->reserved; 234 dest->cu_type = cpu_to_be16(src->cu_type); 235 dest->cu_model = src->cu_model; 236 dest->dev_type = cpu_to_be16(src->dev_type); 237 dest->dev_model = src->dev_model; 238 dest->unused = src->unused; 239 for (i = 0; i < ARRAY_SIZE(dest->ciw); i++) { 240 dest->ciw[i].type = src->ciw[i].type; 241 dest->ciw[i].command = src->ciw[i].command; 242 dest->ciw[i].count = cpu_to_be16(src->ciw[i].count); 243 } 244 } 245 246 static CCW1 copy_ccw_from_guest(hwaddr addr) 247 { 248 CCW1 tmp; 249 CCW1 ret; 250 251 cpu_physical_memory_read(addr, &tmp, sizeof(tmp)); 252 ret.cmd_code = tmp.cmd_code; 253 ret.flags = tmp.flags; 254 ret.count = be16_to_cpu(tmp.count); 255 ret.cda = be32_to_cpu(tmp.cda); 256 257 return ret; 258 } 259 260 static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr) 261 { 262 int ret; 263 bool check_len; 264 int len; 265 CCW1 ccw; 266 267 if (!ccw_addr) { 268 return -EIO; 269 } 270 271 ccw = copy_ccw_from_guest(ccw_addr); 272 273 /* Check for invalid command codes. */ 274 if ((ccw.cmd_code & 0x0f) == 0) { 275 return -EINVAL; 276 } 277 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) && 278 ((ccw.cmd_code & 0xf0) != 0)) { 279 return -EINVAL; 280 } 281 282 if (ccw.flags & CCW_FLAG_SUSPEND) { 283 return -EINPROGRESS; 284 } 285 286 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC)); 287 288 /* Look at the command. */ 289 switch (ccw.cmd_code) { 290 case CCW_CMD_NOOP: 291 /* Nothing to do. */ 292 ret = 0; 293 break; 294 case CCW_CMD_BASIC_SENSE: 295 if (check_len) { 296 if (ccw.count != sizeof(sch->sense_data)) { 297 ret = -EINVAL; 298 break; 299 } 300 } 301 len = MIN(ccw.count, sizeof(sch->sense_data)); 302 cpu_physical_memory_write(ccw.cda, sch->sense_data, len); 303 sch->curr_status.scsw.count = ccw.count - len; 304 memset(sch->sense_data, 0, sizeof(sch->sense_data)); 305 ret = 0; 306 break; 307 case CCW_CMD_SENSE_ID: 308 { 309 SenseId sense_id; 310 311 copy_sense_id_to_guest(&sense_id, &sch->id); 312 /* Sense ID information is device specific. */ 313 if (check_len) { 314 if (ccw.count != sizeof(sense_id)) { 315 ret = -EINVAL; 316 break; 317 } 318 } 319 len = MIN(ccw.count, sizeof(sense_id)); 320 /* 321 * Only indicate 0xff in the first sense byte if we actually 322 * have enough place to store at least bytes 0-3. 323 */ 324 if (len >= 4) { 325 sense_id.reserved = 0xff; 326 } else { 327 sense_id.reserved = 0; 328 } 329 cpu_physical_memory_write(ccw.cda, &sense_id, len); 330 sch->curr_status.scsw.count = ccw.count - len; 331 ret = 0; 332 break; 333 } 334 case CCW_CMD_TIC: 335 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) { 336 ret = -EINVAL; 337 break; 338 } 339 if (ccw.flags & (CCW_FLAG_CC | CCW_FLAG_DC)) { 340 ret = -EINVAL; 341 break; 342 } 343 sch->channel_prog = ccw.cda; 344 ret = -EAGAIN; 345 break; 346 default: 347 if (sch->ccw_cb) { 348 /* Handle device specific commands. */ 349 ret = sch->ccw_cb(sch, ccw); 350 } else { 351 ret = -ENOSYS; 352 } 353 break; 354 } 355 sch->last_cmd = ccw; 356 sch->last_cmd_valid = true; 357 if (ret == 0) { 358 if (ccw.flags & CCW_FLAG_CC) { 359 sch->channel_prog += 8; 360 ret = -EAGAIN; 361 } 362 } 363 364 return ret; 365 } 366 367 static void sch_handle_start_func(SubchDev *sch, ORB *orb) 368 { 369 370 PMCW *p = &sch->curr_status.pmcw; 371 SCSW *s = &sch->curr_status.scsw; 372 int path; 373 int ret; 374 375 /* Path management: In our simple css, we always choose the only path. */ 376 path = 0x80; 377 378 if (!(s->ctrl & SCSW_ACTL_SUSP)) { 379 /* Look at the orb and try to execute the channel program. */ 380 assert(orb != NULL); /* resume does not pass an orb */ 381 p->intparm = orb->intparm; 382 if (!(orb->lpm & path)) { 383 /* Generate a deferred cc 3 condition. */ 384 s->flags |= SCSW_FLAGS_MASK_CC; 385 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 386 s->ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND); 387 return; 388 } 389 } else { 390 s->ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND); 391 } 392 sch->last_cmd_valid = false; 393 do { 394 ret = css_interpret_ccw(sch, sch->channel_prog); 395 switch (ret) { 396 case -EAGAIN: 397 /* ccw chain, continue processing */ 398 break; 399 case 0: 400 /* success */ 401 s->ctrl &= ~SCSW_ACTL_START_PEND; 402 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 403 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 404 SCSW_STCTL_STATUS_PEND; 405 s->dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END; 406 break; 407 case -ENOSYS: 408 /* unsupported command, generate unit check (command reject) */ 409 s->ctrl &= ~SCSW_ACTL_START_PEND; 410 s->dstat = SCSW_DSTAT_UNIT_CHECK; 411 /* Set sense bit 0 in ecw0. */ 412 sch->sense_data[0] = 0x80; 413 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 414 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 415 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 416 break; 417 case -EFAULT: 418 /* memory problem, generate channel data check */ 419 s->ctrl &= ~SCSW_ACTL_START_PEND; 420 s->cstat = SCSW_CSTAT_DATA_CHECK; 421 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 422 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 423 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 424 break; 425 case -EBUSY: 426 /* subchannel busy, generate deferred cc 1 */ 427 s->flags &= ~SCSW_FLAGS_MASK_CC; 428 s->flags |= (1 << 8); 429 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 430 s->ctrl |= SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 431 break; 432 case -EINPROGRESS: 433 /* channel program has been suspended */ 434 s->ctrl &= ~SCSW_ACTL_START_PEND; 435 s->ctrl |= SCSW_ACTL_SUSP; 436 break; 437 default: 438 /* error, generate channel program check */ 439 s->ctrl &= ~SCSW_ACTL_START_PEND; 440 s->cstat = SCSW_CSTAT_PROG_CHECK; 441 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 442 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 443 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 444 break; 445 } 446 } while (ret == -EAGAIN); 447 448 } 449 450 /* 451 * On real machines, this would run asynchronously to the main vcpus. 452 * We might want to make some parts of the ssch handling (interpreting 453 * read/writes) asynchronous later on if we start supporting more than 454 * our current very simple devices. 455 */ 456 static void do_subchannel_work(SubchDev *sch, ORB *orb) 457 { 458 459 SCSW *s = &sch->curr_status.scsw; 460 461 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) { 462 sch_handle_clear_func(sch); 463 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) { 464 sch_handle_halt_func(sch); 465 } else if (s->ctrl & SCSW_FCTL_START_FUNC) { 466 sch_handle_start_func(sch, orb); 467 } else { 468 /* Cannot happen. */ 469 return; 470 } 471 css_inject_io_interrupt(sch); 472 } 473 474 static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src) 475 { 476 int i; 477 478 dest->intparm = cpu_to_be32(src->intparm); 479 dest->flags = cpu_to_be16(src->flags); 480 dest->devno = cpu_to_be16(src->devno); 481 dest->lpm = src->lpm; 482 dest->pnom = src->pnom; 483 dest->lpum = src->lpum; 484 dest->pim = src->pim; 485 dest->mbi = cpu_to_be16(src->mbi); 486 dest->pom = src->pom; 487 dest->pam = src->pam; 488 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 489 dest->chpid[i] = src->chpid[i]; 490 } 491 dest->chars = cpu_to_be32(src->chars); 492 } 493 494 static void copy_scsw_to_guest(SCSW *dest, const SCSW *src) 495 { 496 dest->flags = cpu_to_be16(src->flags); 497 dest->ctrl = cpu_to_be16(src->ctrl); 498 dest->cpa = cpu_to_be32(src->cpa); 499 dest->dstat = src->dstat; 500 dest->cstat = src->cstat; 501 dest->count = cpu_to_be16(src->count); 502 } 503 504 static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src) 505 { 506 int i; 507 508 copy_pmcw_to_guest(&dest->pmcw, &src->pmcw); 509 copy_scsw_to_guest(&dest->scsw, &src->scsw); 510 dest->mba = cpu_to_be64(src->mba); 511 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 512 dest->mda[i] = src->mda[i]; 513 } 514 } 515 516 int css_do_stsch(SubchDev *sch, SCHIB *schib) 517 { 518 /* Use current status. */ 519 copy_schib_to_guest(schib, &sch->curr_status); 520 return 0; 521 } 522 523 static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src) 524 { 525 int i; 526 527 dest->intparm = be32_to_cpu(src->intparm); 528 dest->flags = be16_to_cpu(src->flags); 529 dest->devno = be16_to_cpu(src->devno); 530 dest->lpm = src->lpm; 531 dest->pnom = src->pnom; 532 dest->lpum = src->lpum; 533 dest->pim = src->pim; 534 dest->mbi = be16_to_cpu(src->mbi); 535 dest->pom = src->pom; 536 dest->pam = src->pam; 537 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 538 dest->chpid[i] = src->chpid[i]; 539 } 540 dest->chars = be32_to_cpu(src->chars); 541 } 542 543 static void copy_scsw_from_guest(SCSW *dest, const SCSW *src) 544 { 545 dest->flags = be16_to_cpu(src->flags); 546 dest->ctrl = be16_to_cpu(src->ctrl); 547 dest->cpa = be32_to_cpu(src->cpa); 548 dest->dstat = src->dstat; 549 dest->cstat = src->cstat; 550 dest->count = be16_to_cpu(src->count); 551 } 552 553 static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src) 554 { 555 int i; 556 557 copy_pmcw_from_guest(&dest->pmcw, &src->pmcw); 558 copy_scsw_from_guest(&dest->scsw, &src->scsw); 559 dest->mba = be64_to_cpu(src->mba); 560 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 561 dest->mda[i] = src->mda[i]; 562 } 563 } 564 565 int css_do_msch(SubchDev *sch, SCHIB *orig_schib) 566 { 567 SCSW *s = &sch->curr_status.scsw; 568 PMCW *p = &sch->curr_status.pmcw; 569 int ret; 570 SCHIB schib; 571 572 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_DNV)) { 573 ret = 0; 574 goto out; 575 } 576 577 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 578 ret = -EINPROGRESS; 579 goto out; 580 } 581 582 if (s->ctrl & 583 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) { 584 ret = -EBUSY; 585 goto out; 586 } 587 588 copy_schib_from_guest(&schib, orig_schib); 589 /* Only update the program-modifiable fields. */ 590 p->intparm = schib.pmcw.intparm; 591 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 592 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 593 PMCW_FLAGS_MASK_MP); 594 p->flags |= schib.pmcw.flags & 595 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 596 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 597 PMCW_FLAGS_MASK_MP); 598 p->lpm = schib.pmcw.lpm; 599 p->mbi = schib.pmcw.mbi; 600 p->pom = schib.pmcw.pom; 601 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 602 p->chars |= schib.pmcw.chars & 603 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 604 sch->curr_status.mba = schib.mba; 605 606 ret = 0; 607 608 out: 609 return ret; 610 } 611 612 int css_do_xsch(SubchDev *sch) 613 { 614 SCSW *s = &sch->curr_status.scsw; 615 PMCW *p = &sch->curr_status.pmcw; 616 int ret; 617 618 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 619 ret = -ENODEV; 620 goto out; 621 } 622 623 if (!(s->ctrl & SCSW_CTRL_MASK_FCTL) || 624 ((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 625 (!(s->ctrl & 626 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) || 627 (s->ctrl & SCSW_ACTL_SUBCH_ACTIVE)) { 628 ret = -EINPROGRESS; 629 goto out; 630 } 631 632 if (s->ctrl & SCSW_CTRL_MASK_STCTL) { 633 ret = -EBUSY; 634 goto out; 635 } 636 637 /* Cancel the current operation. */ 638 s->ctrl &= ~(SCSW_FCTL_START_FUNC | 639 SCSW_ACTL_RESUME_PEND | 640 SCSW_ACTL_START_PEND | 641 SCSW_ACTL_SUSP); 642 sch->channel_prog = 0x0; 643 sch->last_cmd_valid = false; 644 s->dstat = 0; 645 s->cstat = 0; 646 ret = 0; 647 648 out: 649 return ret; 650 } 651 652 int css_do_csch(SubchDev *sch) 653 { 654 SCSW *s = &sch->curr_status.scsw; 655 PMCW *p = &sch->curr_status.pmcw; 656 int ret; 657 658 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 659 ret = -ENODEV; 660 goto out; 661 } 662 663 /* Trigger the clear function. */ 664 s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL); 665 s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_FCTL_CLEAR_FUNC; 666 667 do_subchannel_work(sch, NULL); 668 ret = 0; 669 670 out: 671 return ret; 672 } 673 674 int css_do_hsch(SubchDev *sch) 675 { 676 SCSW *s = &sch->curr_status.scsw; 677 PMCW *p = &sch->curr_status.pmcw; 678 int ret; 679 680 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 681 ret = -ENODEV; 682 goto out; 683 } 684 685 if (((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) || 686 (s->ctrl & (SCSW_STCTL_PRIMARY | 687 SCSW_STCTL_SECONDARY | 688 SCSW_STCTL_ALERT))) { 689 ret = -EINPROGRESS; 690 goto out; 691 } 692 693 if (s->ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) { 694 ret = -EBUSY; 695 goto out; 696 } 697 698 /* Trigger the halt function. */ 699 s->ctrl |= SCSW_FCTL_HALT_FUNC; 700 s->ctrl &= ~SCSW_FCTL_START_FUNC; 701 if (((s->ctrl & SCSW_CTRL_MASK_ACTL) == 702 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) && 703 ((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_INTERMEDIATE)) { 704 s->ctrl &= ~SCSW_STCTL_STATUS_PEND; 705 } 706 s->ctrl |= SCSW_ACTL_HALT_PEND; 707 708 do_subchannel_work(sch, NULL); 709 ret = 0; 710 711 out: 712 return ret; 713 } 714 715 static void css_update_chnmon(SubchDev *sch) 716 { 717 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) { 718 /* Not active. */ 719 return; 720 } 721 /* The counter is conveniently located at the beginning of the struct. */ 722 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) { 723 /* Format 1, per-subchannel area. */ 724 uint32_t count; 725 726 count = ldl_phys(&address_space_memory, sch->curr_status.mba); 727 count++; 728 stl_phys(&address_space_memory, sch->curr_status.mba, count); 729 } else { 730 /* Format 0, global area. */ 731 uint32_t offset; 732 uint16_t count; 733 734 offset = sch->curr_status.pmcw.mbi << 5; 735 count = lduw_phys(&address_space_memory, 736 channel_subsys->chnmon_area + offset); 737 count++; 738 stw_phys(&address_space_memory, 739 channel_subsys->chnmon_area + offset, count); 740 } 741 } 742 743 int css_do_ssch(SubchDev *sch, ORB *orb) 744 { 745 SCSW *s = &sch->curr_status.scsw; 746 PMCW *p = &sch->curr_status.pmcw; 747 int ret; 748 749 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 750 ret = -ENODEV; 751 goto out; 752 } 753 754 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 755 ret = -EINPROGRESS; 756 goto out; 757 } 758 759 if (s->ctrl & (SCSW_FCTL_START_FUNC | 760 SCSW_FCTL_HALT_FUNC | 761 SCSW_FCTL_CLEAR_FUNC)) { 762 ret = -EBUSY; 763 goto out; 764 } 765 766 /* If monitoring is active, update counter. */ 767 if (channel_subsys->chnmon_active) { 768 css_update_chnmon(sch); 769 } 770 sch->channel_prog = orb->cpa; 771 /* Trigger the start function. */ 772 s->ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND); 773 s->flags &= ~SCSW_FLAGS_MASK_PNO; 774 775 do_subchannel_work(sch, orb); 776 ret = 0; 777 778 out: 779 return ret; 780 } 781 782 static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw) 783 { 784 int i; 785 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 786 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 787 788 copy_scsw_to_guest(&dest->scsw, &src->scsw); 789 790 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) { 791 dest->esw[i] = cpu_to_be32(src->esw[i]); 792 } 793 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) { 794 dest->ecw[i] = cpu_to_be32(src->ecw[i]); 795 } 796 /* extended measurements enabled? */ 797 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) || 798 !(pmcw->flags & PMCW_FLAGS_MASK_TF) || 799 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) { 800 return; 801 } 802 /* extended measurements pending? */ 803 if (!(stctl & SCSW_STCTL_STATUS_PEND)) { 804 return; 805 } 806 if ((stctl & SCSW_STCTL_PRIMARY) || 807 (stctl == SCSW_STCTL_SECONDARY) || 808 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) { 809 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) { 810 dest->emw[i] = cpu_to_be32(src->emw[i]); 811 } 812 } 813 } 814 815 int css_do_tsch(SubchDev *sch, IRB *target_irb) 816 { 817 SCSW *s = &sch->curr_status.scsw; 818 PMCW *p = &sch->curr_status.pmcw; 819 uint16_t stctl; 820 uint16_t fctl; 821 uint16_t actl; 822 IRB irb; 823 int ret; 824 825 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 826 ret = 3; 827 goto out; 828 } 829 830 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL; 831 fctl = s->ctrl & SCSW_CTRL_MASK_FCTL; 832 actl = s->ctrl & SCSW_CTRL_MASK_ACTL; 833 834 /* Prepare the irb for the guest. */ 835 memset(&irb, 0, sizeof(IRB)); 836 837 /* Copy scsw from current status. */ 838 memcpy(&irb.scsw, s, sizeof(SCSW)); 839 if (stctl & SCSW_STCTL_STATUS_PEND) { 840 if (s->cstat & (SCSW_CSTAT_DATA_CHECK | 841 SCSW_CSTAT_CHN_CTRL_CHK | 842 SCSW_CSTAT_INTF_CTRL_CHK)) { 843 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF; 844 irb.esw[0] = 0x04804000; 845 } else { 846 irb.esw[0] = 0x00800000; 847 } 848 /* If a unit check is pending, copy sense data. */ 849 if ((s->dstat & SCSW_DSTAT_UNIT_CHECK) && 850 (p->chars & PMCW_CHARS_MASK_CSENSE)) { 851 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL; 852 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data)); 853 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8); 854 } 855 } 856 /* Store the irb to the guest. */ 857 copy_irb_to_guest(target_irb, &irb, p); 858 859 /* Clear conditions on subchannel, if applicable. */ 860 if (stctl & SCSW_STCTL_STATUS_PEND) { 861 s->ctrl &= ~SCSW_CTRL_MASK_STCTL; 862 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) || 863 ((fctl & SCSW_FCTL_HALT_FUNC) && 864 (actl & SCSW_ACTL_SUSP))) { 865 s->ctrl &= ~SCSW_CTRL_MASK_FCTL; 866 } 867 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) { 868 s->flags &= ~SCSW_FLAGS_MASK_PNO; 869 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 870 SCSW_ACTL_START_PEND | 871 SCSW_ACTL_HALT_PEND | 872 SCSW_ACTL_CLEAR_PEND | 873 SCSW_ACTL_SUSP); 874 } else { 875 if ((actl & SCSW_ACTL_SUSP) && 876 (fctl & SCSW_FCTL_START_FUNC)) { 877 s->flags &= ~SCSW_FLAGS_MASK_PNO; 878 if (fctl & SCSW_FCTL_HALT_FUNC) { 879 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND | 880 SCSW_ACTL_START_PEND | 881 SCSW_ACTL_HALT_PEND | 882 SCSW_ACTL_CLEAR_PEND | 883 SCSW_ACTL_SUSP); 884 } else { 885 s->ctrl &= ~SCSW_ACTL_RESUME_PEND; 886 } 887 } 888 } 889 /* Clear pending sense data. */ 890 if (p->chars & PMCW_CHARS_MASK_CSENSE) { 891 memset(sch->sense_data, 0 , sizeof(sch->sense_data)); 892 } 893 } 894 895 ret = ((stctl & SCSW_STCTL_STATUS_PEND) == 0); 896 897 out: 898 return ret; 899 } 900 901 static void copy_crw_to_guest(CRW *dest, const CRW *src) 902 { 903 dest->flags = cpu_to_be16(src->flags); 904 dest->rsid = cpu_to_be16(src->rsid); 905 } 906 907 int css_do_stcrw(CRW *crw) 908 { 909 CrwContainer *crw_cont; 910 int ret; 911 912 crw_cont = QTAILQ_FIRST(&channel_subsys->pending_crws); 913 if (crw_cont) { 914 QTAILQ_REMOVE(&channel_subsys->pending_crws, crw_cont, sibling); 915 copy_crw_to_guest(crw, &crw_cont->crw); 916 g_free(crw_cont); 917 ret = 0; 918 } else { 919 /* List was empty, turn crw machine checks on again. */ 920 memset(crw, 0, sizeof(*crw)); 921 channel_subsys->do_crw_mchk = true; 922 ret = 1; 923 } 924 925 return ret; 926 } 927 928 int css_do_tpi(IOIntCode *int_code, int lowcore) 929 { 930 /* No pending interrupts for !KVM. */ 931 return 0; 932 } 933 934 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, 935 int rfmt, void *buf) 936 { 937 int i, desc_size; 938 uint32_t words[8]; 939 uint32_t chpid_type_word; 940 CssImage *css; 941 942 if (!m && !cssid) { 943 css = channel_subsys->css[channel_subsys->default_cssid]; 944 } else { 945 css = channel_subsys->css[cssid]; 946 } 947 if (!css) { 948 return 0; 949 } 950 desc_size = 0; 951 for (i = f_chpid; i <= l_chpid; i++) { 952 if (css->chpids[i].in_use) { 953 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i; 954 if (rfmt == 0) { 955 words[0] = cpu_to_be32(chpid_type_word); 956 words[1] = 0; 957 memcpy(buf + desc_size, words, 8); 958 desc_size += 8; 959 } else if (rfmt == 1) { 960 words[0] = cpu_to_be32(chpid_type_word); 961 words[1] = 0; 962 words[2] = 0; 963 words[3] = 0; 964 words[4] = 0; 965 words[5] = 0; 966 words[6] = 0; 967 words[7] = 0; 968 memcpy(buf + desc_size, words, 32); 969 desc_size += 32; 970 } 971 } 972 } 973 return desc_size; 974 } 975 976 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo) 977 { 978 /* dct is currently ignored (not really meaningful for our devices) */ 979 /* TODO: Don't ignore mbk. */ 980 if (update && !channel_subsys->chnmon_active) { 981 /* Enable measuring. */ 982 channel_subsys->chnmon_area = mbo; 983 channel_subsys->chnmon_active = true; 984 } 985 if (!update && channel_subsys->chnmon_active) { 986 /* Disable measuring. */ 987 channel_subsys->chnmon_area = 0; 988 channel_subsys->chnmon_active = false; 989 } 990 } 991 992 int css_do_rsch(SubchDev *sch) 993 { 994 SCSW *s = &sch->curr_status.scsw; 995 PMCW *p = &sch->curr_status.pmcw; 996 int ret; 997 998 if (!(p->flags & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA))) { 999 ret = -ENODEV; 1000 goto out; 1001 } 1002 1003 if (s->ctrl & SCSW_STCTL_STATUS_PEND) { 1004 ret = -EINPROGRESS; 1005 goto out; 1006 } 1007 1008 if (((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1009 (s->ctrl & SCSW_ACTL_RESUME_PEND) || 1010 (!(s->ctrl & SCSW_ACTL_SUSP))) { 1011 ret = -EINVAL; 1012 goto out; 1013 } 1014 1015 /* If monitoring is active, update counter. */ 1016 if (channel_subsys->chnmon_active) { 1017 css_update_chnmon(sch); 1018 } 1019 1020 s->ctrl |= SCSW_ACTL_RESUME_PEND; 1021 do_subchannel_work(sch, NULL); 1022 ret = 0; 1023 1024 out: 1025 return ret; 1026 } 1027 1028 int css_do_rchp(uint8_t cssid, uint8_t chpid) 1029 { 1030 uint8_t real_cssid; 1031 1032 if (cssid > channel_subsys->max_cssid) { 1033 return -EINVAL; 1034 } 1035 if (channel_subsys->max_cssid == 0) { 1036 real_cssid = channel_subsys->default_cssid; 1037 } else { 1038 real_cssid = cssid; 1039 } 1040 if (!channel_subsys->css[real_cssid]) { 1041 return -EINVAL; 1042 } 1043 1044 if (!channel_subsys->css[real_cssid]->chpids[chpid].in_use) { 1045 return -ENODEV; 1046 } 1047 1048 if (!channel_subsys->css[real_cssid]->chpids[chpid].is_virtual) { 1049 fprintf(stderr, 1050 "rchp unsupported for non-virtual chpid %x.%02x!\n", 1051 real_cssid, chpid); 1052 return -ENODEV; 1053 } 1054 1055 /* We don't really use a channel path, so we're done here. */ 1056 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1057 channel_subsys->max_cssid > 0 ? 1 : 0, chpid); 1058 if (channel_subsys->max_cssid > 0) { 1059 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 0, real_cssid << 8); 1060 } 1061 return 0; 1062 } 1063 1064 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1065 { 1066 SubchSet *set; 1067 uint8_t real_cssid; 1068 1069 real_cssid = (!m && (cssid == 0)) ? channel_subsys->default_cssid : cssid; 1070 if (real_cssid > MAX_CSSID || ssid > MAX_SSID || 1071 !channel_subsys->css[real_cssid] || 1072 !channel_subsys->css[real_cssid]->sch_set[ssid]) { 1073 return true; 1074 } 1075 set = channel_subsys->css[real_cssid]->sch_set[ssid]; 1076 return schid > find_last_bit(set->schids_used, 1077 (MAX_SCHID + 1) / sizeof(unsigned long)); 1078 } 1079 1080 static int css_add_virtual_chpid(uint8_t cssid, uint8_t chpid, uint8_t type) 1081 { 1082 CssImage *css; 1083 1084 trace_css_chpid_add(cssid, chpid, type); 1085 if (cssid > MAX_CSSID) { 1086 return -EINVAL; 1087 } 1088 css = channel_subsys->css[cssid]; 1089 if (!css) { 1090 return -EINVAL; 1091 } 1092 if (css->chpids[chpid].in_use) { 1093 return -EEXIST; 1094 } 1095 css->chpids[chpid].in_use = 1; 1096 css->chpids[chpid].type = type; 1097 css->chpids[chpid].is_virtual = 1; 1098 1099 css_generate_chp_crws(cssid, chpid); 1100 1101 return 0; 1102 } 1103 1104 void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type) 1105 { 1106 PMCW *p = &sch->curr_status.pmcw; 1107 SCSW *s = &sch->curr_status.scsw; 1108 int i; 1109 CssImage *css = channel_subsys->css[sch->cssid]; 1110 1111 assert(css != NULL); 1112 memset(p, 0, sizeof(PMCW)); 1113 p->flags |= PMCW_FLAGS_MASK_DNV; 1114 p->devno = sch->devno; 1115 /* single path */ 1116 p->pim = 0x80; 1117 p->pom = 0xff; 1118 p->pam = 0x80; 1119 p->chpid[0] = chpid; 1120 if (!css->chpids[chpid].in_use) { 1121 css_add_virtual_chpid(sch->cssid, chpid, type); 1122 } 1123 1124 memset(s, 0, sizeof(SCSW)); 1125 sch->curr_status.mba = 0; 1126 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) { 1127 sch->curr_status.mda[i] = 0; 1128 } 1129 } 1130 1131 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1132 { 1133 uint8_t real_cssid; 1134 1135 real_cssid = (!m && (cssid == 0)) ? channel_subsys->default_cssid : cssid; 1136 1137 if (!channel_subsys->css[real_cssid]) { 1138 return NULL; 1139 } 1140 1141 if (!channel_subsys->css[real_cssid]->sch_set[ssid]) { 1142 return NULL; 1143 } 1144 1145 return channel_subsys->css[real_cssid]->sch_set[ssid]->sch[schid]; 1146 } 1147 1148 bool css_subch_visible(SubchDev *sch) 1149 { 1150 if (sch->ssid > channel_subsys->max_ssid) { 1151 return false; 1152 } 1153 1154 if (sch->cssid != channel_subsys->default_cssid) { 1155 return (channel_subsys->max_cssid > 0); 1156 } 1157 1158 return true; 1159 } 1160 1161 bool css_present(uint8_t cssid) 1162 { 1163 return (channel_subsys->css[cssid] != NULL); 1164 } 1165 1166 bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno) 1167 { 1168 if (!channel_subsys->css[cssid]) { 1169 return false; 1170 } 1171 if (!channel_subsys->css[cssid]->sch_set[ssid]) { 1172 return false; 1173 } 1174 1175 return !!test_bit(devno, 1176 channel_subsys->css[cssid]->sch_set[ssid]->devnos_used); 1177 } 1178 1179 void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid, 1180 uint16_t devno, SubchDev *sch) 1181 { 1182 CssImage *css; 1183 SubchSet *s_set; 1184 1185 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid, 1186 devno); 1187 if (!channel_subsys->css[cssid]) { 1188 fprintf(stderr, 1189 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n", 1190 __func__, cssid, ssid, schid); 1191 return; 1192 } 1193 css = channel_subsys->css[cssid]; 1194 1195 if (!css->sch_set[ssid]) { 1196 css->sch_set[ssid] = g_malloc0(sizeof(SubchSet)); 1197 } 1198 s_set = css->sch_set[ssid]; 1199 1200 s_set->sch[schid] = sch; 1201 if (sch) { 1202 set_bit(schid, s_set->schids_used); 1203 set_bit(devno, s_set->devnos_used); 1204 } else { 1205 clear_bit(schid, s_set->schids_used); 1206 clear_bit(devno, s_set->devnos_used); 1207 } 1208 } 1209 1210 void css_queue_crw(uint8_t rsc, uint8_t erc, int chain, uint16_t rsid) 1211 { 1212 CrwContainer *crw_cont; 1213 1214 trace_css_crw(rsc, erc, rsid, chain ? "(chained)" : ""); 1215 /* TODO: Maybe use a static crw pool? */ 1216 crw_cont = g_try_malloc0(sizeof(CrwContainer)); 1217 if (!crw_cont) { 1218 channel_subsys->crws_lost = true; 1219 return; 1220 } 1221 crw_cont->crw.flags = (rsc << 8) | erc; 1222 if (chain) { 1223 crw_cont->crw.flags |= CRW_FLAGS_MASK_C; 1224 } 1225 crw_cont->crw.rsid = rsid; 1226 if (channel_subsys->crws_lost) { 1227 crw_cont->crw.flags |= CRW_FLAGS_MASK_R; 1228 channel_subsys->crws_lost = false; 1229 } 1230 1231 QTAILQ_INSERT_TAIL(&channel_subsys->pending_crws, crw_cont, sibling); 1232 1233 if (channel_subsys->do_crw_mchk) { 1234 S390CPU *cpu = s390_cpu_addr2state(0); 1235 1236 channel_subsys->do_crw_mchk = false; 1237 /* Inject crw pending machine check. */ 1238 s390_crw_mchk(cpu); 1239 } 1240 } 1241 1242 void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid, 1243 int hotplugged, int add) 1244 { 1245 uint8_t guest_cssid; 1246 bool chain_crw; 1247 1248 if (add && !hotplugged) { 1249 return; 1250 } 1251 if (channel_subsys->max_cssid == 0) { 1252 /* Default cssid shows up as 0. */ 1253 guest_cssid = (cssid == channel_subsys->default_cssid) ? 0 : cssid; 1254 } else { 1255 /* Show real cssid to the guest. */ 1256 guest_cssid = cssid; 1257 } 1258 /* 1259 * Only notify for higher subchannel sets/channel subsystems if the 1260 * guest has enabled it. 1261 */ 1262 if ((ssid > channel_subsys->max_ssid) || 1263 (guest_cssid > channel_subsys->max_cssid) || 1264 ((channel_subsys->max_cssid == 0) && 1265 (cssid != channel_subsys->default_cssid))) { 1266 return; 1267 } 1268 chain_crw = (channel_subsys->max_ssid > 0) || 1269 (channel_subsys->max_cssid > 0); 1270 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, chain_crw ? 1 : 0, schid); 1271 if (chain_crw) { 1272 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 1273 (guest_cssid << 8) | (ssid << 4)); 1274 } 1275 } 1276 1277 void css_generate_chp_crws(uint8_t cssid, uint8_t chpid) 1278 { 1279 /* TODO */ 1280 } 1281 1282 int css_enable_mcsse(void) 1283 { 1284 trace_css_enable_facility("mcsse"); 1285 channel_subsys->max_cssid = MAX_CSSID; 1286 return 0; 1287 } 1288 1289 int css_enable_mss(void) 1290 { 1291 trace_css_enable_facility("mss"); 1292 channel_subsys->max_ssid = MAX_SSID; 1293 return 0; 1294 } 1295 1296 static void css_init(void) 1297 { 1298 channel_subsys = g_malloc0(sizeof(*channel_subsys)); 1299 QTAILQ_INIT(&channel_subsys->pending_crws); 1300 channel_subsys->do_crw_mchk = true; 1301 channel_subsys->crws_lost = false; 1302 channel_subsys->chnmon_active = false; 1303 QTAILQ_INIT(&channel_subsys->io_adapters); 1304 } 1305 machine_init(css_init); 1306 1307 void css_reset_sch(SubchDev *sch) 1308 { 1309 PMCW *p = &sch->curr_status.pmcw; 1310 1311 p->intparm = 0; 1312 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1313 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1314 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF); 1315 p->flags |= PMCW_FLAGS_MASK_DNV; 1316 p->devno = sch->devno; 1317 p->pim = 0x80; 1318 p->lpm = p->pim; 1319 p->pnom = 0; 1320 p->lpum = 0; 1321 p->mbi = 0; 1322 p->pom = 0xff; 1323 p->pam = 0x80; 1324 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME | 1325 PMCW_CHARS_MASK_CSENSE); 1326 1327 memset(&sch->curr_status.scsw, 0, sizeof(sch->curr_status.scsw)); 1328 sch->curr_status.mba = 0; 1329 1330 sch->channel_prog = 0x0; 1331 sch->last_cmd_valid = false; 1332 sch->thinint_active = false; 1333 } 1334 1335 void css_reset(void) 1336 { 1337 CrwContainer *crw_cont; 1338 1339 /* Clean up monitoring. */ 1340 channel_subsys->chnmon_active = false; 1341 channel_subsys->chnmon_area = 0; 1342 1343 /* Clear pending CRWs. */ 1344 while ((crw_cont = QTAILQ_FIRST(&channel_subsys->pending_crws))) { 1345 QTAILQ_REMOVE(&channel_subsys->pending_crws, crw_cont, sibling); 1346 g_free(crw_cont); 1347 } 1348 channel_subsys->do_crw_mchk = true; 1349 channel_subsys->crws_lost = false; 1350 1351 /* Reset maximum ids. */ 1352 channel_subsys->max_cssid = 0; 1353 channel_subsys->max_ssid = 0; 1354 } 1355