1 /* 2 * ARM AMBA PrimeCell PL031 RTC 3 * 4 * Copyright (c) 2007 CodeSourcery 5 * 6 * This file is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Contributions after 2012-01-13 are licensed under the terms of the 11 * GNU GPL, version 2 or (at your option) any later version. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu-common.h" 16 #include "hw/rtc/pl031.h" 17 #include "migration/vmstate.h" 18 #include "hw/irq.h" 19 #include "hw/qdev-properties.h" 20 #include "hw/sysbus.h" 21 #include "qemu/timer.h" 22 #include "sysemu/sysemu.h" 23 #include "qemu/cutils.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 #include "trace.h" 27 #include "qapi/qapi-events-misc-target.h" 28 29 #define RTC_DR 0x00 /* Data read register */ 30 #define RTC_MR 0x04 /* Match register */ 31 #define RTC_LR 0x08 /* Data load register */ 32 #define RTC_CR 0x0c /* Control register */ 33 #define RTC_IMSC 0x10 /* Interrupt mask and set register */ 34 #define RTC_RIS 0x14 /* Raw interrupt status register */ 35 #define RTC_MIS 0x18 /* Masked interrupt status register */ 36 #define RTC_ICR 0x1c /* Interrupt clear register */ 37 38 static const unsigned char pl031_id[] = { 39 0x31, 0x10, 0x14, 0x00, /* Device ID */ 40 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ 41 }; 42 43 static void pl031_update(PL031State *s) 44 { 45 uint32_t flags = s->is & s->im; 46 47 trace_pl031_irq_state(flags); 48 qemu_set_irq(s->irq, flags); 49 } 50 51 static void pl031_interrupt(void * opaque) 52 { 53 PL031State *s = (PL031State *)opaque; 54 55 s->is = 1; 56 trace_pl031_alarm_raised(); 57 pl031_update(s); 58 } 59 60 static uint32_t pl031_get_count(PL031State *s) 61 { 62 int64_t now = qemu_clock_get_ns(rtc_clock); 63 return s->tick_offset + now / NANOSECONDS_PER_SECOND; 64 } 65 66 static void pl031_set_alarm(PL031State *s) 67 { 68 uint32_t ticks; 69 70 /* The timer wraps around. This subtraction also wraps in the same way, 71 and gives correct results when alarm < now_ticks. */ 72 ticks = s->mr - pl031_get_count(s); 73 trace_pl031_set_alarm(ticks); 74 if (ticks == 0) { 75 timer_del(s->timer); 76 pl031_interrupt(s); 77 } else { 78 int64_t now = qemu_clock_get_ns(rtc_clock); 79 timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND); 80 } 81 } 82 83 static uint64_t pl031_read(void *opaque, hwaddr offset, 84 unsigned size) 85 { 86 PL031State *s = (PL031State *)opaque; 87 uint64_t r; 88 89 switch (offset) { 90 case RTC_DR: 91 r = pl031_get_count(s); 92 break; 93 case RTC_MR: 94 r = s->mr; 95 break; 96 case RTC_IMSC: 97 r = s->im; 98 break; 99 case RTC_RIS: 100 r = s->is; 101 break; 102 case RTC_LR: 103 r = s->lr; 104 break; 105 case RTC_CR: 106 /* RTC is permanently enabled. */ 107 r = 1; 108 break; 109 case RTC_MIS: 110 r = s->is & s->im; 111 break; 112 case 0xfe0 ... 0xfff: 113 r = pl031_id[(offset - 0xfe0) >> 2]; 114 break; 115 case RTC_ICR: 116 qemu_log_mask(LOG_GUEST_ERROR, 117 "pl031: read of write-only register at offset 0x%x\n", 118 (int)offset); 119 r = 0; 120 break; 121 default: 122 qemu_log_mask(LOG_GUEST_ERROR, 123 "pl031_read: Bad offset 0x%x\n", (int)offset); 124 r = 0; 125 break; 126 } 127 128 trace_pl031_read(offset, r); 129 return r; 130 } 131 132 static void pl031_write(void * opaque, hwaddr offset, 133 uint64_t value, unsigned size) 134 { 135 PL031State *s = (PL031State *)opaque; 136 137 trace_pl031_write(offset, value); 138 139 switch (offset) { 140 case RTC_LR: { 141 struct tm tm; 142 143 s->tick_offset += value - pl031_get_count(s); 144 145 qemu_get_timedate(&tm, s->tick_offset); 146 qapi_event_send_rtc_change(qemu_timedate_diff(&tm)); 147 148 pl031_set_alarm(s); 149 break; 150 } 151 case RTC_MR: 152 s->mr = value; 153 pl031_set_alarm(s); 154 break; 155 case RTC_IMSC: 156 s->im = value & 1; 157 pl031_update(s); 158 break; 159 case RTC_ICR: 160 s->is &= ~value; 161 pl031_update(s); 162 break; 163 case RTC_CR: 164 /* Written value is ignored. */ 165 break; 166 167 case RTC_DR: 168 case RTC_MIS: 169 case RTC_RIS: 170 qemu_log_mask(LOG_GUEST_ERROR, 171 "pl031: write to read-only register at offset 0x%x\n", 172 (int)offset); 173 break; 174 175 default: 176 qemu_log_mask(LOG_GUEST_ERROR, 177 "pl031_write: Bad offset 0x%x\n", (int)offset); 178 break; 179 } 180 } 181 182 static const MemoryRegionOps pl031_ops = { 183 .read = pl031_read, 184 .write = pl031_write, 185 .endianness = DEVICE_NATIVE_ENDIAN, 186 }; 187 188 static void pl031_init(Object *obj) 189 { 190 PL031State *s = PL031(obj); 191 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 192 struct tm tm; 193 194 memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000); 195 sysbus_init_mmio(dev, &s->iomem); 196 197 sysbus_init_irq(dev, &s->irq); 198 qemu_get_timedate(&tm, 0); 199 s->tick_offset = mktimegm(&tm) - 200 qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; 201 202 s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s); 203 } 204 205 static void pl031_finalize(Object *obj) 206 { 207 PL031State *s = PL031(obj); 208 209 timer_free(s->timer); 210 } 211 212 static int pl031_pre_save(void *opaque) 213 { 214 PL031State *s = opaque; 215 216 /* 217 * The PL031 device model code uses the tick_offset field, which is 218 * the offset between what the guest RTC should read and what the 219 * QEMU rtc_clock reads: 220 * guest_rtc = rtc_clock + tick_offset 221 * and so 222 * tick_offset = guest_rtc - rtc_clock 223 * 224 * We want to migrate this offset, which sounds straightforward. 225 * Unfortunately older versions of QEMU migrated a conversion of this 226 * offset into an offset from the vm_clock. (This was in turn an 227 * attempt to be compatible with even older QEMU versions, but it 228 * has incorrect behaviour if the rtc_clock is not the same as the 229 * vm_clock.) So we put the actual tick_offset into a migration 230 * subsection, and the backwards-compatible time-relative-to-vm_clock 231 * in the main migration state. 232 * 233 * Calculate base time relative to QEMU_CLOCK_VIRTUAL: 234 */ 235 int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 236 s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND; 237 238 return 0; 239 } 240 241 static int pl031_pre_load(void *opaque) 242 { 243 PL031State *s = opaque; 244 245 s->tick_offset_migrated = false; 246 return 0; 247 } 248 249 static int pl031_post_load(void *opaque, int version_id) 250 { 251 PL031State *s = opaque; 252 253 /* 254 * If we got the tick_offset subsection, then we can just use 255 * the value in that. Otherwise the source is an older QEMU and 256 * has given us the offset from the vm_clock; convert it back to 257 * an offset from the rtc_clock. This will cause time to incorrectly 258 * go backwards compared to the host RTC, but this is unavoidable. 259 */ 260 261 if (!s->tick_offset_migrated) { 262 int64_t delta = qemu_clock_get_ns(rtc_clock) - 263 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 264 s->tick_offset = s->tick_offset_vmstate - 265 delta / NANOSECONDS_PER_SECOND; 266 } 267 pl031_set_alarm(s); 268 return 0; 269 } 270 271 static int pl031_tick_offset_post_load(void *opaque, int version_id) 272 { 273 PL031State *s = opaque; 274 275 s->tick_offset_migrated = true; 276 return 0; 277 } 278 279 static bool pl031_tick_offset_needed(void *opaque) 280 { 281 PL031State *s = opaque; 282 283 return s->migrate_tick_offset; 284 } 285 286 static const VMStateDescription vmstate_pl031_tick_offset = { 287 .name = "pl031/tick-offset", 288 .version_id = 1, 289 .minimum_version_id = 1, 290 .needed = pl031_tick_offset_needed, 291 .post_load = pl031_tick_offset_post_load, 292 .fields = (VMStateField[]) { 293 VMSTATE_UINT32(tick_offset, PL031State), 294 VMSTATE_END_OF_LIST() 295 } 296 }; 297 298 static const VMStateDescription vmstate_pl031 = { 299 .name = "pl031", 300 .version_id = 1, 301 .minimum_version_id = 1, 302 .pre_save = pl031_pre_save, 303 .pre_load = pl031_pre_load, 304 .post_load = pl031_post_load, 305 .fields = (VMStateField[]) { 306 VMSTATE_UINT32(tick_offset_vmstate, PL031State), 307 VMSTATE_UINT32(mr, PL031State), 308 VMSTATE_UINT32(lr, PL031State), 309 VMSTATE_UINT32(cr, PL031State), 310 VMSTATE_UINT32(im, PL031State), 311 VMSTATE_UINT32(is, PL031State), 312 VMSTATE_END_OF_LIST() 313 }, 314 .subsections = (const VMStateDescription*[]) { 315 &vmstate_pl031_tick_offset, 316 NULL 317 } 318 }; 319 320 static Property pl031_properties[] = { 321 /* 322 * True to correctly migrate the tick offset of the RTC. False to 323 * obtain backward migration compatibility with older QEMU versions, 324 * at the expense of the guest RTC going backwards compared with the 325 * host RTC when the VM is saved/restored if using -rtc host. 326 * (Even if set to 'true' older QEMU can migrate forward to newer QEMU; 327 * 'false' also permits newer QEMU to migrate to older QEMU.) 328 */ 329 DEFINE_PROP_BOOL("migrate-tick-offset", 330 PL031State, migrate_tick_offset, true), 331 DEFINE_PROP_END_OF_LIST() 332 }; 333 334 static void pl031_class_init(ObjectClass *klass, void *data) 335 { 336 DeviceClass *dc = DEVICE_CLASS(klass); 337 338 dc->vmsd = &vmstate_pl031; 339 device_class_set_props(dc, pl031_properties); 340 } 341 342 static const TypeInfo pl031_info = { 343 .name = TYPE_PL031, 344 .parent = TYPE_SYS_BUS_DEVICE, 345 .instance_size = sizeof(PL031State), 346 .instance_init = pl031_init, 347 .instance_finalize = pl031_finalize, 348 .class_init = pl031_class_init, 349 }; 350 351 static void pl031_register_types(void) 352 { 353 type_register_static(&pl031_info); 354 } 355 356 type_init(pl031_register_types) 357