1 /* 2 * QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface) 3 * 4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer 5 * Copyright (c) 2013 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/isa/isa.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/rtc/m48t59.h" 30 #include "m48t59-internal.h" 31 #include "qapi/error.h" 32 #include "qemu/module.h" 33 34 #define TYPE_M48TXX_ISA "isa-m48txx" 35 #define M48TXX_ISA_GET_CLASS(obj) \ 36 OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA) 37 #define M48TXX_ISA_CLASS(klass) \ 38 OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA) 39 #define M48TXX_ISA(obj) \ 40 OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA) 41 42 typedef struct M48txxISAState { 43 ISADevice parent_obj; 44 M48t59State state; 45 uint32_t io_base; 46 MemoryRegion io; 47 } M48txxISAState; 48 49 typedef struct M48txxISADeviceClass { 50 ISADeviceClass parent_class; 51 M48txxInfo info; 52 } M48txxISADeviceClass; 53 54 static M48txxInfo m48txx_isa_info[] = { 55 { 56 .bus_name = "isa-m48t59", 57 .model = 59, 58 .size = 0x2000, 59 } 60 }; 61 62 Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, 63 int base_year, int model) 64 { 65 ISADevice *isa_dev; 66 DeviceState *dev; 67 int i; 68 69 for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) { 70 if (m48txx_isa_info[i].size != size || 71 m48txx_isa_info[i].model != model) { 72 continue; 73 } 74 75 isa_dev = isa_new(m48txx_isa_info[i].bus_name); 76 dev = DEVICE(isa_dev); 77 qdev_prop_set_uint32(dev, "iobase", io_base); 78 qdev_prop_set_int32(dev, "base-year", base_year); 79 isa_realize_and_unref(isa_dev, bus, &error_fatal); 80 return NVRAM(dev); 81 } 82 83 assert(false); 84 return NULL; 85 } 86 87 static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr) 88 { 89 M48txxISAState *d = M48TXX_ISA(obj); 90 return m48t59_read(&d->state, addr); 91 } 92 93 static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val) 94 { 95 M48txxISAState *d = M48TXX_ISA(obj); 96 m48t59_write(&d->state, addr, val); 97 } 98 99 static void m48txx_isa_toggle_lock(Nvram *obj, int lock) 100 { 101 M48txxISAState *d = M48TXX_ISA(obj); 102 m48t59_toggle_lock(&d->state, lock); 103 } 104 105 static Property m48t59_isa_properties[] = { 106 DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0), 107 DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74), 108 DEFINE_PROP_END_OF_LIST(), 109 }; 110 111 static void m48t59_reset_isa(DeviceState *d) 112 { 113 M48txxISAState *isa = M48TXX_ISA(d); 114 M48t59State *NVRAM = &isa->state; 115 116 m48t59_reset_common(NVRAM); 117 } 118 119 static void m48t59_isa_realize(DeviceState *dev, Error **errp) 120 { 121 M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev); 122 ISADevice *isadev = ISA_DEVICE(dev); 123 M48txxISAState *d = M48TXX_ISA(dev); 124 M48t59State *s = &d->state; 125 126 s->model = u->info.model; 127 s->size = u->info.size; 128 isa_init_irq(isadev, &s->IRQ, 8); 129 m48t59_realize_common(s, errp); 130 memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4); 131 if (d->io_base != 0) { 132 isa_register_ioport(isadev, &d->io, d->io_base); 133 } 134 } 135 136 static void m48txx_isa_class_init(ObjectClass *klass, void *data) 137 { 138 DeviceClass *dc = DEVICE_CLASS(klass); 139 NvramClass *nc = NVRAM_CLASS(klass); 140 141 dc->realize = m48t59_isa_realize; 142 dc->reset = m48t59_reset_isa; 143 device_class_set_props(dc, m48t59_isa_properties); 144 nc->read = m48txx_isa_read; 145 nc->write = m48txx_isa_write; 146 nc->toggle_lock = m48txx_isa_toggle_lock; 147 } 148 149 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data) 150 { 151 M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass); 152 M48txxInfo *info = data; 153 154 u->info = *info; 155 } 156 157 static const TypeInfo m48txx_isa_type_info = { 158 .name = TYPE_M48TXX_ISA, 159 .parent = TYPE_ISA_DEVICE, 160 .instance_size = sizeof(M48txxISAState), 161 .abstract = true, 162 .class_init = m48txx_isa_class_init, 163 .interfaces = (InterfaceInfo[]) { 164 { TYPE_NVRAM }, 165 { } 166 } 167 }; 168 169 static void m48t59_isa_register_types(void) 170 { 171 TypeInfo isa_type_info = { 172 .parent = TYPE_M48TXX_ISA, 173 .class_size = sizeof(M48txxISADeviceClass), 174 .class_init = m48txx_isa_concrete_class_init, 175 }; 176 int i; 177 178 type_register_static(&m48txx_isa_type_info); 179 180 for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) { 181 isa_type_info.name = m48txx_isa_info[i].bus_name; 182 isa_type_info.class_data = &m48txx_isa_info[i]; 183 type_register(&isa_type_info); 184 } 185 } 186 187 type_init(m48t59_isa_register_types) 188