1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/log.h" 24 #include "qemu/error-report.h" 25 #include "qapi/error.h" 26 #include "hw/hw.h" 27 #include "hw/boards.h" 28 #include "hw/loader.h" 29 #include "hw/sysbus.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/riscv/riscv_hart.h" 33 #include "hw/riscv/sifive_plic.h" 34 #include "hw/riscv/sifive_clint.h" 35 #include "hw/riscv/sifive_test.h" 36 #include "hw/riscv/virt.h" 37 #include "chardev/char.h" 38 #include "sysemu/arch_init.h" 39 #include "sysemu/device_tree.h" 40 #include "exec/address-spaces.h" 41 #include "hw/pci/pci.h" 42 #include "hw/pci-host/gpex.h" 43 #include "elf.h" 44 45 #include <libfdt.h> 46 47 static const struct MemmapEntry { 48 hwaddr base; 49 hwaddr size; 50 } virt_memmap[] = { 51 [VIRT_DEBUG] = { 0x0, 0x100 }, 52 [VIRT_MROM] = { 0x1000, 0x11000 }, 53 [VIRT_TEST] = { 0x100000, 0x1000 }, 54 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 55 [VIRT_PLIC] = { 0xc000000, 0x4000000 }, 56 [VIRT_UART0] = { 0x10000000, 0x100 }, 57 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 58 [VIRT_DRAM] = { 0x80000000, 0x0 }, 59 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 60 [VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 }, 61 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 62 }; 63 64 static target_ulong load_kernel(const char *kernel_filename) 65 { 66 uint64_t kernel_entry, kernel_high; 67 68 if (load_elf(kernel_filename, NULL, NULL, NULL, 69 &kernel_entry, NULL, &kernel_high, 70 0, EM_RISCV, 1, 0) < 0) { 71 error_report("could not load kernel '%s'", kernel_filename); 72 exit(1); 73 } 74 return kernel_entry; 75 } 76 77 static hwaddr load_initrd(const char *filename, uint64_t mem_size, 78 uint64_t kernel_entry, hwaddr *start) 79 { 80 int size; 81 82 /* We want to put the initrd far enough into RAM that when the 83 * kernel is uncompressed it will not clobber the initrd. However 84 * on boards without much RAM we must ensure that we still leave 85 * enough room for a decent sized initrd, and on boards with large 86 * amounts of RAM we must avoid the initrd being so far up in RAM 87 * that it is outside lowmem and inaccessible to the kernel. 88 * So for boards with less than 256MB of RAM we put the initrd 89 * halfway into RAM, and for boards with 256MB of RAM or more we put 90 * the initrd at 128MB. 91 */ 92 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); 93 94 size = load_ramdisk(filename, *start, mem_size - *start); 95 if (size == -1) { 96 size = load_image_targphys(filename, *start, mem_size - *start); 97 if (size == -1) { 98 error_report("could not load ramdisk '%s'", filename); 99 exit(1); 100 } 101 } 102 return *start + size; 103 } 104 105 static void create_pcie_irq_map(void *fdt, char *nodename, 106 uint32_t plic_phandle) 107 { 108 int pin, dev; 109 uint32_t 110 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; 111 uint32_t *irq_map = full_irq_map; 112 113 /* This code creates a standard swizzle of interrupts such that 114 * each device's first interrupt is based on it's PCI_SLOT number. 115 * (See pci_swizzle_map_irq_fn()) 116 * 117 * We only need one entry per interrupt in the table (not one per 118 * possible slot) seeing the interrupt-map-mask will allow the table 119 * to wrap to any number of devices. 120 */ 121 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 122 int devfn = dev * 0x8; 123 124 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 125 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 126 int i = 0; 127 128 irq_map[i] = cpu_to_be32(devfn << 8); 129 130 i += FDT_PCI_ADDR_CELLS; 131 irq_map[i] = cpu_to_be32(pin + 1); 132 133 i += FDT_PCI_INT_CELLS; 134 irq_map[i++] = cpu_to_be32(plic_phandle); 135 136 i += FDT_PLIC_ADDR_CELLS; 137 irq_map[i] = cpu_to_be32(irq_nr); 138 139 irq_map += FDT_INT_MAP_WIDTH; 140 } 141 } 142 143 qemu_fdt_setprop(fdt, nodename, "interrupt-map", 144 full_irq_map, sizeof(full_irq_map)); 145 146 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 147 0x1800, 0, 0, 0x7); 148 } 149 150 static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, 151 uint64_t mem_size, const char *cmdline) 152 { 153 void *fdt; 154 int cpu; 155 uint32_t *cells; 156 char *nodename; 157 uint32_t plic_phandle, phandle = 1; 158 int i; 159 160 fdt = s->fdt = create_device_tree(&s->fdt_size); 161 if (!fdt) { 162 error_report("create_device_tree() failed"); 163 exit(1); 164 } 165 166 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); 167 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); 168 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 169 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 170 171 qemu_fdt_add_subnode(fdt, "/soc"); 172 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 173 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 174 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 175 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 176 177 nodename = g_strdup_printf("/memory@%lx", 178 (long)memmap[VIRT_DRAM].base); 179 qemu_fdt_add_subnode(fdt, nodename); 180 qemu_fdt_setprop_cells(fdt, nodename, "reg", 181 memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base, 182 mem_size >> 32, mem_size); 183 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 184 g_free(nodename); 185 186 qemu_fdt_add_subnode(fdt, "/cpus"); 187 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 188 SIFIVE_CLINT_TIMEBASE_FREQ); 189 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 190 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 191 192 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { 193 int cpu_phandle = phandle++; 194 int intc_phandle; 195 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 196 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 197 char *isa = riscv_isa_string(&s->soc.harts[cpu]); 198 qemu_fdt_add_subnode(fdt, nodename); 199 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 200 VIRT_CLOCK_FREQ); 201 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 202 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 203 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 204 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 205 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 206 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 207 qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); 208 qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle); 209 intc_phandle = phandle++; 210 qemu_fdt_add_subnode(fdt, intc); 211 qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle); 212 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle); 213 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 214 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 215 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 216 g_free(isa); 217 g_free(intc); 218 g_free(nodename); 219 } 220 221 /* Add cpu-topology node */ 222 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 223 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0"); 224 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { 225 char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d", 226 cpu); 227 char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 228 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename); 229 qemu_fdt_add_subnode(fdt, core_nodename); 230 qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle); 231 g_free(core_nodename); 232 g_free(cpu_nodename); 233 } 234 235 cells = g_new0(uint32_t, s->soc.num_harts * 4); 236 for (cpu = 0; cpu < s->soc.num_harts; cpu++) { 237 nodename = 238 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 239 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 240 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 241 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 242 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 243 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 244 g_free(nodename); 245 } 246 nodename = g_strdup_printf("/soc/clint@%lx", 247 (long)memmap[VIRT_CLINT].base); 248 qemu_fdt_add_subnode(fdt, nodename); 249 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 250 qemu_fdt_setprop_cells(fdt, nodename, "reg", 251 0x0, memmap[VIRT_CLINT].base, 252 0x0, memmap[VIRT_CLINT].size); 253 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 254 cells, s->soc.num_harts * sizeof(uint32_t) * 4); 255 g_free(cells); 256 g_free(nodename); 257 258 plic_phandle = phandle++; 259 cells = g_new0(uint32_t, s->soc.num_harts * 4); 260 for (cpu = 0; cpu < s->soc.num_harts; cpu++) { 261 nodename = 262 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 263 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 264 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 265 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 266 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 267 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 268 g_free(nodename); 269 } 270 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 271 (long)memmap[VIRT_PLIC].base); 272 qemu_fdt_add_subnode(fdt, nodename); 273 qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 274 FDT_PLIC_ADDR_CELLS); 275 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 276 FDT_PLIC_INT_CELLS); 277 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 278 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 279 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 280 cells, s->soc.num_harts * sizeof(uint32_t) * 4); 281 qemu_fdt_setprop_cells(fdt, nodename, "reg", 282 0x0, memmap[VIRT_PLIC].base, 283 0x0, memmap[VIRT_PLIC].size); 284 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 285 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); 286 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); 287 qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); 288 qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); 289 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 290 g_free(cells); 291 g_free(nodename); 292 293 for (i = 0; i < VIRTIO_COUNT; i++) { 294 nodename = g_strdup_printf("/virtio_mmio@%lx", 295 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 296 qemu_fdt_add_subnode(fdt, nodename); 297 qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio"); 298 qemu_fdt_setprop_cells(fdt, nodename, "reg", 299 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 300 0x0, memmap[VIRT_VIRTIO].size); 301 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 302 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i); 303 g_free(nodename); 304 } 305 306 nodename = g_strdup_printf("/soc/pci@%lx", 307 (long) memmap[VIRT_PCIE_ECAM].base); 308 qemu_fdt_add_subnode(fdt, nodename); 309 qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 310 FDT_PCI_ADDR_CELLS); 311 qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 312 FDT_PCI_INT_CELLS); 313 qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2); 314 qemu_fdt_setprop_string(fdt, nodename, "compatible", 315 "pci-host-ecam-generic"); 316 qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); 317 qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0); 318 qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0, 319 memmap[VIRT_PCIE_ECAM].size / 320 PCIE_MMCFG_SIZE_MIN - 1); 321 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); 322 qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base, 323 0, memmap[VIRT_PCIE_ECAM].size); 324 qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges", 325 1, FDT_PCI_RANGE_IOPORT, 2, 0, 326 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 327 1, FDT_PCI_RANGE_MMIO, 328 2, memmap[VIRT_PCIE_MMIO].base, 329 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); 330 create_pcie_irq_map(fdt, nodename, plic_phandle); 331 g_free(nodename); 332 333 nodename = g_strdup_printf("/test@%lx", 334 (long)memmap[VIRT_TEST].base); 335 qemu_fdt_add_subnode(fdt, nodename); 336 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0"); 337 qemu_fdt_setprop_cells(fdt, nodename, "reg", 338 0x0, memmap[VIRT_TEST].base, 339 0x0, memmap[VIRT_TEST].size); 340 g_free(nodename); 341 342 nodename = g_strdup_printf("/uart@%lx", 343 (long)memmap[VIRT_UART0].base); 344 qemu_fdt_add_subnode(fdt, nodename); 345 qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a"); 346 qemu_fdt_setprop_cells(fdt, nodename, "reg", 347 0x0, memmap[VIRT_UART0].base, 348 0x0, memmap[VIRT_UART0].size); 349 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); 350 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 351 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ); 352 353 qemu_fdt_add_subnode(fdt, "/chosen"); 354 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 355 if (cmdline) { 356 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 357 } 358 g_free(nodename); 359 360 return fdt; 361 } 362 363 364 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 365 hwaddr ecam_base, hwaddr ecam_size, 366 hwaddr mmio_base, hwaddr mmio_size, 367 hwaddr pio_base, 368 DeviceState *plic, bool link_up) 369 { 370 DeviceState *dev; 371 MemoryRegion *ecam_alias, *ecam_reg; 372 MemoryRegion *mmio_alias, *mmio_reg; 373 qemu_irq irq; 374 int i; 375 376 dev = qdev_create(NULL, TYPE_GPEX_HOST); 377 378 qdev_init_nofail(dev); 379 380 ecam_alias = g_new0(MemoryRegion, 1); 381 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 382 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 383 ecam_reg, 0, ecam_size); 384 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 385 386 mmio_alias = g_new0(MemoryRegion, 1); 387 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 388 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 389 mmio_reg, mmio_base, mmio_size); 390 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 391 392 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 393 394 for (i = 0; i < GPEX_NUM_IRQS; i++) { 395 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); 396 397 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 398 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 399 } 400 401 return dev; 402 } 403 404 static void riscv_virt_board_init(MachineState *machine) 405 { 406 const struct MemmapEntry *memmap = virt_memmap; 407 408 RISCVVirtState *s = g_new0(RISCVVirtState, 1); 409 MemoryRegion *system_memory = get_system_memory(); 410 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 411 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 412 char *plic_hart_config; 413 size_t plic_hart_config_len; 414 int i; 415 void *fdt; 416 417 /* Initialize SOC */ 418 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 419 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 420 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", 421 &error_abort); 422 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 423 &error_abort); 424 object_property_set_bool(OBJECT(&s->soc), true, "realized", 425 &error_abort); 426 427 /* register system main memory (actual RAM) */ 428 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", 429 machine->ram_size, &error_fatal); 430 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 431 main_mem); 432 433 /* create device tree */ 434 fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 435 436 /* boot rom */ 437 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 438 memmap[VIRT_MROM].size, &error_fatal); 439 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 440 mask_rom); 441 442 if (machine->kernel_filename) { 443 uint64_t kernel_entry = load_kernel(machine->kernel_filename); 444 445 if (machine->initrd_filename) { 446 hwaddr start; 447 hwaddr end = load_initrd(machine->initrd_filename, 448 machine->ram_size, kernel_entry, 449 &start); 450 qemu_fdt_setprop_cell(fdt, "/chosen", 451 "linux,initrd-start", start); 452 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 453 end); 454 } 455 } 456 457 /* reset vector */ 458 uint32_t reset_vec[8] = { 459 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 460 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 461 0xf1402573, /* csrr a0, mhartid */ 462 #if defined(TARGET_RISCV32) 463 0x0182a283, /* lw t0, 24(t0) */ 464 #elif defined(TARGET_RISCV64) 465 0x0182b283, /* ld t0, 24(t0) */ 466 #endif 467 0x00028067, /* jr t0 */ 468 0x00000000, 469 memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].base */ 470 0x00000000, 471 /* dtb: */ 472 }; 473 474 /* copy in the reset vector in little_endian byte order */ 475 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 476 reset_vec[i] = cpu_to_le32(reset_vec[i]); 477 } 478 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 479 memmap[VIRT_MROM].base, &address_space_memory); 480 481 /* copy in the device tree */ 482 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 483 memmap[VIRT_MROM].size - sizeof(reset_vec)) { 484 error_report("not enough space to store device-tree"); 485 exit(1); 486 } 487 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 488 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 489 memmap[VIRT_MROM].base + sizeof(reset_vec), 490 &address_space_memory); 491 492 /* create PLIC hart topology configuration string */ 493 plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus; 494 plic_hart_config = g_malloc0(plic_hart_config_len); 495 for (i = 0; i < smp_cpus; i++) { 496 if (i != 0) { 497 strncat(plic_hart_config, ",", plic_hart_config_len); 498 } 499 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len); 500 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); 501 } 502 503 /* MMIO */ 504 s->plic = sifive_plic_create(memmap[VIRT_PLIC].base, 505 plic_hart_config, 506 VIRT_PLIC_NUM_SOURCES, 507 VIRT_PLIC_NUM_PRIORITIES, 508 VIRT_PLIC_PRIORITY_BASE, 509 VIRT_PLIC_PENDING_BASE, 510 VIRT_PLIC_ENABLE_BASE, 511 VIRT_PLIC_ENABLE_STRIDE, 512 VIRT_PLIC_CONTEXT_BASE, 513 VIRT_PLIC_CONTEXT_STRIDE, 514 memmap[VIRT_PLIC].size); 515 sifive_clint_create(memmap[VIRT_CLINT].base, 516 memmap[VIRT_CLINT].size, smp_cpus, 517 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 518 sifive_test_create(memmap[VIRT_TEST].base); 519 520 for (i = 0; i < VIRTIO_COUNT; i++) { 521 sysbus_create_simple("virtio-mmio", 522 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 523 qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i)); 524 } 525 526 gpex_pcie_init(system_memory, 527 memmap[VIRT_PCIE_ECAM].base, 528 memmap[VIRT_PCIE_ECAM].size, 529 memmap[VIRT_PCIE_MMIO].base, 530 memmap[VIRT_PCIE_MMIO].size, 531 memmap[VIRT_PCIE_PIO].base, 532 DEVICE(s->plic), true); 533 534 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 535 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, 536 serial_hd(0), DEVICE_LITTLE_ENDIAN); 537 538 g_free(plic_hart_config); 539 } 540 541 static void riscv_virt_board_machine_init(MachineClass *mc) 542 { 543 mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)"; 544 mc->init = riscv_virt_board_init; 545 mc->max_cpus = 8; /* hardcoded limit in BBL */ 546 mc->default_cpu_type = VIRT_CPU; 547 } 548 549 DEFINE_MACHINE("virt", riscv_virt_board_machine_init) 550