1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "kvm/kvm_riscv.h" 39 #include "hw/firmware/smbios.h" 40 #include "hw/intc/riscv_aclint.h" 41 #include "hw/intc/riscv_aplic.h" 42 #include "hw/intc/sifive_plic.h" 43 #include "hw/misc/sifive_test.h" 44 #include "hw/platform-bus.h" 45 #include "chardev/char.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/sysemu.h" 48 #include "sysemu/tcg.h" 49 #include "sysemu/kvm.h" 50 #include "sysemu/tpm.h" 51 #include "sysemu/qtest.h" 52 #include "hw/pci/pci.h" 53 #include "hw/pci-host/gpex.h" 54 #include "hw/display/ramfb.h" 55 #include "hw/acpi/aml-build.h" 56 #include "qapi/qapi-visit-common.h" 57 #include "hw/virtio/virtio-iommu.h" 58 59 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 60 static bool virt_use_kvm_aia(RISCVVirtState *s) 61 { 62 return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 63 } 64 65 static bool virt_aclint_allowed(void) 66 { 67 return tcg_enabled() || qtest_enabled(); 68 } 69 70 static const MemMapEntry virt_memmap[] = { 71 [VIRT_DEBUG] = { 0x0, 0x100 }, 72 [VIRT_MROM] = { 0x1000, 0xf000 }, 73 [VIRT_TEST] = { 0x100000, 0x1000 }, 74 [VIRT_RTC] = { 0x101000, 0x1000 }, 75 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 76 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 77 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 78 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 79 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 80 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 81 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 82 [VIRT_UART0] = { 0x10000000, 0x100 }, 83 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 84 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 85 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 86 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 87 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 88 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 89 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 90 [VIRT_DRAM] = { 0x80000000, 0x0 }, 91 }; 92 93 /* PCIe high mmio is fixed for RV32 */ 94 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 95 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 96 97 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 98 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 99 100 static MemMapEntry virt_high_pcie_memmap; 101 102 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 103 104 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 105 const char *name, 106 const char *alias_prop_name) 107 { 108 /* 109 * Create a single flash device. We use the same parameters as 110 * the flash devices on the ARM virt board. 111 */ 112 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 113 114 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 115 qdev_prop_set_uint8(dev, "width", 4); 116 qdev_prop_set_uint8(dev, "device-width", 2); 117 qdev_prop_set_bit(dev, "big-endian", false); 118 qdev_prop_set_uint16(dev, "id0", 0x89); 119 qdev_prop_set_uint16(dev, "id1", 0x18); 120 qdev_prop_set_uint16(dev, "id2", 0x00); 121 qdev_prop_set_uint16(dev, "id3", 0x00); 122 qdev_prop_set_string(dev, "name", name); 123 124 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 125 object_property_add_alias(OBJECT(s), alias_prop_name, 126 OBJECT(dev), "drive"); 127 128 return PFLASH_CFI01(dev); 129 } 130 131 static void virt_flash_create(RISCVVirtState *s) 132 { 133 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 134 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 135 } 136 137 static void virt_flash_map1(PFlashCFI01 *flash, 138 hwaddr base, hwaddr size, 139 MemoryRegion *sysmem) 140 { 141 DeviceState *dev = DEVICE(flash); 142 143 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 144 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 145 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 146 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 147 148 memory_region_add_subregion(sysmem, base, 149 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 150 0)); 151 } 152 153 static void virt_flash_map(RISCVVirtState *s, 154 MemoryRegion *sysmem) 155 { 156 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 157 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 158 159 virt_flash_map1(s->flash[0], flashbase, flashsize, 160 sysmem); 161 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 162 sysmem); 163 } 164 165 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 166 uint32_t irqchip_phandle) 167 { 168 int pin, dev; 169 uint32_t irq_map_stride = 0; 170 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 171 FDT_MAX_INT_MAP_WIDTH] = {}; 172 uint32_t *irq_map = full_irq_map; 173 174 /* This code creates a standard swizzle of interrupts such that 175 * each device's first interrupt is based on it's PCI_SLOT number. 176 * (See pci_swizzle_map_irq_fn()) 177 * 178 * We only need one entry per interrupt in the table (not one per 179 * possible slot) seeing the interrupt-map-mask will allow the table 180 * to wrap to any number of devices. 181 */ 182 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 183 int devfn = dev * 0x8; 184 185 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 186 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 187 int i = 0; 188 189 /* Fill PCI address cells */ 190 irq_map[i] = cpu_to_be32(devfn << 8); 191 i += FDT_PCI_ADDR_CELLS; 192 193 /* Fill PCI Interrupt cells */ 194 irq_map[i] = cpu_to_be32(pin + 1); 195 i += FDT_PCI_INT_CELLS; 196 197 /* Fill interrupt controller phandle and cells */ 198 irq_map[i++] = cpu_to_be32(irqchip_phandle); 199 irq_map[i++] = cpu_to_be32(irq_nr); 200 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 201 irq_map[i++] = cpu_to_be32(0x4); 202 } 203 204 if (!irq_map_stride) { 205 irq_map_stride = i; 206 } 207 irq_map += irq_map_stride; 208 } 209 } 210 211 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 212 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 213 irq_map_stride * sizeof(uint32_t)); 214 215 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 216 0x1800, 0, 0, 0x7); 217 } 218 219 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 220 char *clust_name, uint32_t *phandle, 221 uint32_t *intc_phandles) 222 { 223 int cpu; 224 uint32_t cpu_phandle; 225 MachineState *ms = MACHINE(s); 226 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 227 uint8_t satp_mode_max; 228 229 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 230 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 231 g_autofree char *cpu_name = NULL; 232 g_autofree char *core_name = NULL; 233 g_autofree char *intc_name = NULL; 234 g_autofree char *sv_name = NULL; 235 236 cpu_phandle = (*phandle)++; 237 238 cpu_name = g_strdup_printf("/cpus/cpu@%d", 239 s->soc[socket].hartid_base + cpu); 240 qemu_fdt_add_subnode(ms->fdt, cpu_name); 241 242 if (cpu_ptr->cfg.satp_mode.supported != 0) { 243 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 244 sv_name = g_strdup_printf("riscv,%s", 245 satp_mode_str(satp_mode_max, is_32_bit)); 246 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 247 } 248 249 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); 250 251 if (cpu_ptr->cfg.ext_zicbom) { 252 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 253 cpu_ptr->cfg.cbom_blocksize); 254 } 255 256 if (cpu_ptr->cfg.ext_zicboz) { 257 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 258 cpu_ptr->cfg.cboz_blocksize); 259 } 260 261 if (cpu_ptr->cfg.ext_zicbop) { 262 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 263 cpu_ptr->cfg.cbop_blocksize); 264 } 265 266 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 267 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 268 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 269 s->soc[socket].hartid_base + cpu); 270 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 271 riscv_socket_fdt_write_id(ms, cpu_name, socket); 272 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 273 274 intc_phandles[cpu] = (*phandle)++; 275 276 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 277 qemu_fdt_add_subnode(ms->fdt, intc_name); 278 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 279 intc_phandles[cpu]); 280 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 281 "riscv,cpu-intc"); 282 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 283 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 284 285 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 286 qemu_fdt_add_subnode(ms->fdt, core_name); 287 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 288 } 289 } 290 291 static void create_fdt_socket_memory(RISCVVirtState *s, 292 const MemMapEntry *memmap, int socket) 293 { 294 g_autofree char *mem_name = NULL; 295 uint64_t addr, size; 296 MachineState *ms = MACHINE(s); 297 298 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 299 size = riscv_socket_mem_size(ms, socket); 300 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 301 qemu_fdt_add_subnode(ms->fdt, mem_name); 302 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 303 addr >> 32, addr, size >> 32, size); 304 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 305 riscv_socket_fdt_write_id(ms, mem_name, socket); 306 } 307 308 static void create_fdt_socket_clint(RISCVVirtState *s, 309 const MemMapEntry *memmap, int socket, 310 uint32_t *intc_phandles) 311 { 312 int cpu; 313 g_autofree char *clint_name = NULL; 314 g_autofree uint32_t *clint_cells = NULL; 315 unsigned long clint_addr; 316 MachineState *ms = MACHINE(s); 317 static const char * const clint_compat[2] = { 318 "sifive,clint0", "riscv,clint0" 319 }; 320 321 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 322 323 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 324 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 325 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 326 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 327 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 328 } 329 330 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 331 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 332 qemu_fdt_add_subnode(ms->fdt, clint_name); 333 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 334 (char **)&clint_compat, 335 ARRAY_SIZE(clint_compat)); 336 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 337 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 338 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 339 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 340 riscv_socket_fdt_write_id(ms, clint_name, socket); 341 } 342 343 static void create_fdt_socket_aclint(RISCVVirtState *s, 344 const MemMapEntry *memmap, int socket, 345 uint32_t *intc_phandles) 346 { 347 int cpu; 348 char *name; 349 unsigned long addr, size; 350 uint32_t aclint_cells_size; 351 g_autofree uint32_t *aclint_mswi_cells = NULL; 352 g_autofree uint32_t *aclint_sswi_cells = NULL; 353 g_autofree uint32_t *aclint_mtimer_cells = NULL; 354 MachineState *ms = MACHINE(s); 355 356 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 357 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 358 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 359 360 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 361 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 362 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 363 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 364 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 365 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 366 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 367 } 368 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 369 370 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 371 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 372 name = g_strdup_printf("/soc/mswi@%lx", addr); 373 qemu_fdt_add_subnode(ms->fdt, name); 374 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 375 "riscv,aclint-mswi"); 376 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 377 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 378 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 379 aclint_mswi_cells, aclint_cells_size); 380 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 381 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 382 riscv_socket_fdt_write_id(ms, name, socket); 383 g_free(name); 384 } 385 386 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 387 addr = memmap[VIRT_CLINT].base + 388 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 389 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 390 } else { 391 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 392 (memmap[VIRT_CLINT].size * socket); 393 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 394 } 395 name = g_strdup_printf("/soc/mtimer@%lx", addr); 396 qemu_fdt_add_subnode(ms->fdt, name); 397 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 398 "riscv,aclint-mtimer"); 399 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 400 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 401 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 402 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 403 0x0, RISCV_ACLINT_DEFAULT_MTIME); 404 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 405 aclint_mtimer_cells, aclint_cells_size); 406 riscv_socket_fdt_write_id(ms, name, socket); 407 g_free(name); 408 409 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 410 addr = memmap[VIRT_ACLINT_SSWI].base + 411 (memmap[VIRT_ACLINT_SSWI].size * socket); 412 name = g_strdup_printf("/soc/sswi@%lx", addr); 413 qemu_fdt_add_subnode(ms->fdt, name); 414 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 415 "riscv,aclint-sswi"); 416 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 417 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 418 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 419 aclint_sswi_cells, aclint_cells_size); 420 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 421 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 422 riscv_socket_fdt_write_id(ms, name, socket); 423 g_free(name); 424 } 425 } 426 427 static void create_fdt_socket_plic(RISCVVirtState *s, 428 const MemMapEntry *memmap, int socket, 429 uint32_t *phandle, uint32_t *intc_phandles, 430 uint32_t *plic_phandles) 431 { 432 int cpu; 433 g_autofree char *plic_name = NULL; 434 g_autofree uint32_t *plic_cells; 435 unsigned long plic_addr; 436 MachineState *ms = MACHINE(s); 437 static const char * const plic_compat[2] = { 438 "sifive,plic-1.0.0", "riscv,plic0" 439 }; 440 441 plic_phandles[socket] = (*phandle)++; 442 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 443 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 444 qemu_fdt_add_subnode(ms->fdt, plic_name); 445 qemu_fdt_setprop_cell(ms->fdt, plic_name, 446 "#interrupt-cells", FDT_PLIC_INT_CELLS); 447 qemu_fdt_setprop_cell(ms->fdt, plic_name, 448 "#address-cells", FDT_PLIC_ADDR_CELLS); 449 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 450 (char **)&plic_compat, 451 ARRAY_SIZE(plic_compat)); 452 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 453 454 if (kvm_enabled()) { 455 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 456 457 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 458 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 459 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 460 } 461 462 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 463 plic_cells, 464 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 465 } else { 466 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 467 468 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 469 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 470 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 471 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 472 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 473 } 474 475 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 476 plic_cells, 477 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 478 } 479 480 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 481 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 482 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 483 VIRT_IRQCHIP_NUM_SOURCES - 1); 484 riscv_socket_fdt_write_id(ms, plic_name, socket); 485 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 486 plic_phandles[socket]); 487 488 if (!socket) { 489 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 490 memmap[VIRT_PLATFORM_BUS].base, 491 memmap[VIRT_PLATFORM_BUS].size, 492 VIRT_PLATFORM_BUS_IRQ); 493 } 494 } 495 496 uint32_t imsic_num_bits(uint32_t count) 497 { 498 uint32_t ret = 0; 499 500 while (BIT(ret) < count) { 501 ret++; 502 } 503 504 return ret; 505 } 506 507 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 508 uint32_t *intc_phandles, uint32_t msi_phandle, 509 bool m_mode, uint32_t imsic_guest_bits) 510 { 511 int cpu, socket; 512 g_autofree char *imsic_name = NULL; 513 MachineState *ms = MACHINE(s); 514 int socket_count = riscv_socket_count(ms); 515 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 516 g_autofree uint32_t *imsic_cells = NULL; 517 g_autofree uint32_t *imsic_regs = NULL; 518 static const char * const imsic_compat[2] = { 519 "qemu,imsics", "riscv,imsics" 520 }; 521 522 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 523 imsic_regs = g_new0(uint32_t, socket_count * 4); 524 525 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 526 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 527 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 528 } 529 530 imsic_max_hart_per_socket = 0; 531 for (socket = 0; socket < socket_count; socket++) { 532 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 533 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 534 s->soc[socket].num_harts; 535 imsic_regs[socket * 4 + 0] = 0; 536 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 537 imsic_regs[socket * 4 + 2] = 0; 538 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 539 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 540 imsic_max_hart_per_socket = s->soc[socket].num_harts; 541 } 542 } 543 544 imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx", 545 (unsigned long)base_addr); 546 qemu_fdt_add_subnode(ms->fdt, imsic_name); 547 qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", 548 (char **)&imsic_compat, 549 ARRAY_SIZE(imsic_compat)); 550 551 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 552 FDT_IMSIC_INT_CELLS); 553 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 554 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 555 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#msi-cells", 0); 556 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 557 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 558 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 559 socket_count * sizeof(uint32_t) * 4); 560 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 561 VIRT_IRQCHIP_NUM_MSIS); 562 563 if (imsic_guest_bits) { 564 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 565 imsic_guest_bits); 566 } 567 568 if (socket_count > 1) { 569 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 570 imsic_num_bits(imsic_max_hart_per_socket)); 571 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 572 imsic_num_bits(socket_count)); 573 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 574 IMSIC_MMIO_GROUP_MIN_SHIFT); 575 } 576 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 577 } 578 579 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 580 uint32_t *phandle, uint32_t *intc_phandles, 581 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 582 { 583 *msi_m_phandle = (*phandle)++; 584 *msi_s_phandle = (*phandle)++; 585 586 if (!kvm_enabled()) { 587 /* M-level IMSIC node */ 588 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 589 *msi_m_phandle, true, 0); 590 } 591 592 /* S-level IMSIC node */ 593 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 594 *msi_s_phandle, false, 595 imsic_num_bits(s->aia_guests + 1)); 596 597 } 598 599 /* Caller must free string after use */ 600 static char *fdt_get_aplic_nodename(unsigned long aplic_addr) 601 { 602 return g_strdup_printf("/soc/interrupt-controller@%lx", aplic_addr); 603 } 604 605 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 606 unsigned long aplic_addr, uint32_t aplic_size, 607 uint32_t msi_phandle, 608 uint32_t *intc_phandles, 609 uint32_t aplic_phandle, 610 uint32_t aplic_child_phandle, 611 bool m_mode, int num_harts) 612 { 613 int cpu; 614 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 615 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 616 MachineState *ms = MACHINE(s); 617 static const char * const aplic_compat[2] = { 618 "qemu,aplic", "riscv,aplic" 619 }; 620 621 for (cpu = 0; cpu < num_harts; cpu++) { 622 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 623 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 624 } 625 626 qemu_fdt_add_subnode(ms->fdt, aplic_name); 627 qemu_fdt_setprop_string_array(ms->fdt, aplic_name, "compatible", 628 (char **)&aplic_compat, 629 ARRAY_SIZE(aplic_compat)); 630 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells", 631 FDT_APLIC_ADDR_CELLS); 632 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 633 "#interrupt-cells", FDT_APLIC_INT_CELLS); 634 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 635 636 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 637 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 638 aplic_cells, num_harts * sizeof(uint32_t) * 2); 639 } else { 640 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 641 } 642 643 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 644 0x0, aplic_addr, 0x0, aplic_size); 645 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 646 VIRT_IRQCHIP_NUM_SOURCES); 647 648 if (aplic_child_phandle) { 649 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 650 aplic_child_phandle); 651 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation", 652 aplic_child_phandle, 0x1, 653 VIRT_IRQCHIP_NUM_SOURCES); 654 } 655 656 riscv_socket_fdt_write_id(ms, aplic_name, socket); 657 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 658 } 659 660 static void create_fdt_socket_aplic(RISCVVirtState *s, 661 const MemMapEntry *memmap, int socket, 662 uint32_t msi_m_phandle, 663 uint32_t msi_s_phandle, 664 uint32_t *phandle, 665 uint32_t *intc_phandles, 666 uint32_t *aplic_phandles, 667 int num_harts) 668 { 669 unsigned long aplic_addr; 670 MachineState *ms = MACHINE(s); 671 uint32_t aplic_m_phandle, aplic_s_phandle; 672 673 aplic_m_phandle = (*phandle)++; 674 aplic_s_phandle = (*phandle)++; 675 676 if (!kvm_enabled()) { 677 /* M-level APLIC node */ 678 aplic_addr = memmap[VIRT_APLIC_M].base + 679 (memmap[VIRT_APLIC_M].size * socket); 680 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 681 msi_m_phandle, intc_phandles, 682 aplic_m_phandle, aplic_s_phandle, 683 true, num_harts); 684 } 685 686 /* S-level APLIC node */ 687 aplic_addr = memmap[VIRT_APLIC_S].base + 688 (memmap[VIRT_APLIC_S].size * socket); 689 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 690 msi_s_phandle, intc_phandles, 691 aplic_s_phandle, 0, 692 false, num_harts); 693 694 if (!socket) { 695 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 696 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 697 memmap[VIRT_PLATFORM_BUS].base, 698 memmap[VIRT_PLATFORM_BUS].size, 699 VIRT_PLATFORM_BUS_IRQ); 700 } 701 702 aplic_phandles[socket] = aplic_s_phandle; 703 } 704 705 static void create_fdt_pmu(RISCVVirtState *s) 706 { 707 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 708 MachineState *ms = MACHINE(s); 709 RISCVCPU hart = s->soc[0].harts[0]; 710 711 qemu_fdt_add_subnode(ms->fdt, pmu_name); 712 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 713 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 714 } 715 716 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 717 uint32_t *phandle, 718 uint32_t *irq_mmio_phandle, 719 uint32_t *irq_pcie_phandle, 720 uint32_t *irq_virtio_phandle, 721 uint32_t *msi_pcie_phandle) 722 { 723 int socket, phandle_pos; 724 MachineState *ms = MACHINE(s); 725 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 726 uint32_t xplic_phandles[MAX_NODES]; 727 g_autofree uint32_t *intc_phandles = NULL; 728 int socket_count = riscv_socket_count(ms); 729 730 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 731 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 732 kvm_enabled() ? 733 kvm_riscv_get_timebase_frequency(first_cpu) : 734 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 735 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 736 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 737 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 738 739 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 740 741 phandle_pos = ms->smp.cpus; 742 for (socket = (socket_count - 1); socket >= 0; socket--) { 743 g_autofree char *clust_name = NULL; 744 phandle_pos -= s->soc[socket].num_harts; 745 746 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 747 qemu_fdt_add_subnode(ms->fdt, clust_name); 748 749 create_fdt_socket_cpus(s, socket, clust_name, phandle, 750 &intc_phandles[phandle_pos]); 751 752 create_fdt_socket_memory(s, memmap, socket); 753 754 if (virt_aclint_allowed() && s->have_aclint) { 755 create_fdt_socket_aclint(s, memmap, socket, 756 &intc_phandles[phandle_pos]); 757 } else if (tcg_enabled()) { 758 create_fdt_socket_clint(s, memmap, socket, 759 &intc_phandles[phandle_pos]); 760 } 761 } 762 763 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 764 create_fdt_imsic(s, memmap, phandle, intc_phandles, 765 &msi_m_phandle, &msi_s_phandle); 766 *msi_pcie_phandle = msi_s_phandle; 767 } 768 769 /* KVM AIA only has one APLIC instance */ 770 if (kvm_enabled() && virt_use_kvm_aia(s)) { 771 create_fdt_socket_aplic(s, memmap, 0, 772 msi_m_phandle, msi_s_phandle, phandle, 773 &intc_phandles[0], xplic_phandles, 774 ms->smp.cpus); 775 } else { 776 phandle_pos = ms->smp.cpus; 777 for (socket = (socket_count - 1); socket >= 0; socket--) { 778 phandle_pos -= s->soc[socket].num_harts; 779 780 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 781 create_fdt_socket_plic(s, memmap, socket, phandle, 782 &intc_phandles[phandle_pos], 783 xplic_phandles); 784 } else { 785 create_fdt_socket_aplic(s, memmap, socket, 786 msi_m_phandle, msi_s_phandle, phandle, 787 &intc_phandles[phandle_pos], 788 xplic_phandles, 789 s->soc[socket].num_harts); 790 } 791 } 792 } 793 794 if (kvm_enabled() && virt_use_kvm_aia(s)) { 795 *irq_mmio_phandle = xplic_phandles[0]; 796 *irq_virtio_phandle = xplic_phandles[0]; 797 *irq_pcie_phandle = xplic_phandles[0]; 798 } else { 799 for (socket = 0; socket < socket_count; socket++) { 800 if (socket == 0) { 801 *irq_mmio_phandle = xplic_phandles[socket]; 802 *irq_virtio_phandle = xplic_phandles[socket]; 803 *irq_pcie_phandle = xplic_phandles[socket]; 804 } 805 if (socket == 1) { 806 *irq_virtio_phandle = xplic_phandles[socket]; 807 *irq_pcie_phandle = xplic_phandles[socket]; 808 } 809 if (socket == 2) { 810 *irq_pcie_phandle = xplic_phandles[socket]; 811 } 812 } 813 } 814 815 riscv_socket_fdt_write_distance_matrix(ms); 816 } 817 818 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 819 uint32_t irq_virtio_phandle) 820 { 821 int i; 822 MachineState *ms = MACHINE(s); 823 824 for (i = 0; i < VIRTIO_COUNT; i++) { 825 g_autofree char *name = g_strdup_printf("/soc/virtio_mmio@%lx", 826 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 827 828 qemu_fdt_add_subnode(ms->fdt, name); 829 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 830 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 831 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 832 0x0, memmap[VIRT_VIRTIO].size); 833 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 834 irq_virtio_phandle); 835 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 836 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 837 VIRTIO_IRQ + i); 838 } else { 839 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 840 VIRTIO_IRQ + i, 0x4); 841 } 842 } 843 } 844 845 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 846 uint32_t irq_pcie_phandle, 847 uint32_t msi_pcie_phandle) 848 { 849 g_autofree char *name = NULL; 850 MachineState *ms = MACHINE(s); 851 852 name = g_strdup_printf("/soc/pci@%lx", 853 (long) memmap[VIRT_PCIE_ECAM].base); 854 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 855 FDT_PCI_ADDR_CELLS); 856 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 857 FDT_PCI_INT_CELLS); 858 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 859 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 860 "pci-host-ecam-generic"); 861 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 862 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 863 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 864 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 865 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 866 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 867 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 868 } 869 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 870 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 871 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 872 1, FDT_PCI_RANGE_IOPORT, 2, 0, 873 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 874 1, FDT_PCI_RANGE_MMIO, 875 2, memmap[VIRT_PCIE_MMIO].base, 876 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 877 1, FDT_PCI_RANGE_MMIO_64BIT, 878 2, virt_high_pcie_memmap.base, 879 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 880 881 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 882 } 883 884 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 885 uint32_t *phandle) 886 { 887 char *name; 888 uint32_t test_phandle; 889 MachineState *ms = MACHINE(s); 890 891 test_phandle = (*phandle)++; 892 name = g_strdup_printf("/soc/test@%lx", 893 (long)memmap[VIRT_TEST].base); 894 qemu_fdt_add_subnode(ms->fdt, name); 895 { 896 static const char * const compat[3] = { 897 "sifive,test1", "sifive,test0", "syscon" 898 }; 899 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 900 (char **)&compat, ARRAY_SIZE(compat)); 901 } 902 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 903 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 904 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 905 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 906 g_free(name); 907 908 name = g_strdup_printf("/reboot"); 909 qemu_fdt_add_subnode(ms->fdt, name); 910 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 911 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 912 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 913 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 914 g_free(name); 915 916 name = g_strdup_printf("/poweroff"); 917 qemu_fdt_add_subnode(ms->fdt, name); 918 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 919 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 920 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 921 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 922 g_free(name); 923 } 924 925 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 926 uint32_t irq_mmio_phandle) 927 { 928 g_autofree char *name = NULL; 929 MachineState *ms = MACHINE(s); 930 931 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 932 qemu_fdt_add_subnode(ms->fdt, name); 933 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 934 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 935 0x0, memmap[VIRT_UART0].base, 936 0x0, memmap[VIRT_UART0].size); 937 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 938 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 939 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 940 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 941 } else { 942 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 943 } 944 945 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 946 } 947 948 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 949 uint32_t irq_mmio_phandle) 950 { 951 g_autofree char *name = NULL; 952 MachineState *ms = MACHINE(s); 953 954 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 955 qemu_fdt_add_subnode(ms->fdt, name); 956 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 957 "google,goldfish-rtc"); 958 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 959 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 960 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 961 irq_mmio_phandle); 962 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 963 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 964 } else { 965 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 966 } 967 } 968 969 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 970 { 971 MachineState *ms = MACHINE(s); 972 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 973 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 974 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 975 976 qemu_fdt_add_subnode(ms->fdt, name); 977 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 978 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 979 2, flashbase, 2, flashsize, 980 2, flashbase + flashsize, 2, flashsize); 981 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 982 } 983 984 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 985 { 986 MachineState *ms = MACHINE(s); 987 hwaddr base = memmap[VIRT_FW_CFG].base; 988 hwaddr size = memmap[VIRT_FW_CFG].size; 989 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 990 991 qemu_fdt_add_subnode(ms->fdt, nodename); 992 qemu_fdt_setprop_string(ms->fdt, nodename, 993 "compatible", "qemu,fw-cfg-mmio"); 994 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 995 2, base, 2, size); 996 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 997 } 998 999 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) 1000 { 1001 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1002 void *fdt = MACHINE(s)->fdt; 1003 uint32_t iommu_phandle; 1004 g_autofree char *iommu_node = NULL; 1005 g_autofree char *pci_node = NULL; 1006 1007 pci_node = g_strdup_printf("/soc/pci@%lx", 1008 (long) virt_memmap[VIRT_PCIE_ECAM].base); 1009 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, 1010 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1011 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1012 1013 qemu_fdt_add_subnode(fdt, iommu_node); 1014 1015 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat)); 1016 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 1017 1, bdf << 8, 1, 0, 1, 0, 1018 1, 0, 1, 0); 1019 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1020 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1021 1022 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1023 0, iommu_phandle, 0, bdf, 1024 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1025 } 1026 1027 static void finalize_fdt(RISCVVirtState *s) 1028 { 1029 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1030 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1031 1032 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 1033 &irq_pcie_phandle, &irq_virtio_phandle, 1034 &msi_pcie_phandle); 1035 1036 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 1037 1038 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); 1039 1040 create_fdt_reset(s, virt_memmap, &phandle); 1041 1042 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 1043 1044 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 1045 } 1046 1047 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1048 { 1049 MachineState *ms = MACHINE(s); 1050 uint8_t rng_seed[32]; 1051 g_autofree char *name = NULL; 1052 1053 ms->fdt = create_device_tree(&s->fdt_size); 1054 if (!ms->fdt) { 1055 error_report("create_device_tree() failed"); 1056 exit(1); 1057 } 1058 1059 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1060 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1061 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1062 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1063 1064 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1065 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1066 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1067 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1068 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1069 1070 /* 1071 * The "/soc/pci@..." node is needed for PCIE hotplugs 1072 * that might happen before finalize_fdt(). 1073 */ 1074 name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); 1075 qemu_fdt_add_subnode(ms->fdt, name); 1076 1077 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1078 1079 /* Pass seed to RNG */ 1080 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1081 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1082 rng_seed, sizeof(rng_seed)); 1083 1084 create_fdt_flash(s, memmap); 1085 create_fdt_fw_cfg(s, memmap); 1086 create_fdt_pmu(s); 1087 } 1088 1089 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1090 DeviceState *irqchip, 1091 RISCVVirtState *s) 1092 { 1093 DeviceState *dev; 1094 MemoryRegion *ecam_alias, *ecam_reg; 1095 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1096 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1097 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1098 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1099 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1100 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1101 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1102 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1103 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1104 qemu_irq irq; 1105 int i; 1106 1107 dev = qdev_new(TYPE_GPEX_HOST); 1108 1109 /* Set GPEX object properties for the virt machine */ 1110 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, 1111 ecam_base, NULL); 1112 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, 1113 ecam_size, NULL); 1114 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1115 PCI_HOST_BELOW_4G_MMIO_BASE, 1116 mmio_base, NULL); 1117 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, 1118 mmio_size, NULL); 1119 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1120 PCI_HOST_ABOVE_4G_MMIO_BASE, 1121 high_mmio_base, NULL); 1122 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1123 high_mmio_size, NULL); 1124 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, 1125 pio_base, NULL); 1126 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, 1127 pio_size, NULL); 1128 1129 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1130 1131 ecam_alias = g_new0(MemoryRegion, 1); 1132 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1133 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1134 ecam_reg, 0, ecam_size); 1135 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1136 1137 mmio_alias = g_new0(MemoryRegion, 1); 1138 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1139 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1140 mmio_reg, mmio_base, mmio_size); 1141 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1142 1143 /* Map high MMIO space */ 1144 high_mmio_alias = g_new0(MemoryRegion, 1); 1145 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1146 mmio_reg, high_mmio_base, high_mmio_size); 1147 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1148 high_mmio_alias); 1149 1150 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1151 1152 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1153 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1154 1155 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1156 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1157 } 1158 1159 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; 1160 return dev; 1161 } 1162 1163 static FWCfgState *create_fw_cfg(const MachineState *ms) 1164 { 1165 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1166 FWCfgState *fw_cfg; 1167 1168 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1169 &address_space_memory); 1170 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1171 1172 return fw_cfg; 1173 } 1174 1175 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1176 int base_hartid, int hart_count) 1177 { 1178 DeviceState *ret; 1179 g_autofree char *plic_hart_config = NULL; 1180 1181 /* Per-socket PLIC hart topology configuration string */ 1182 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1183 1184 /* Per-socket PLIC */ 1185 ret = sifive_plic_create( 1186 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1187 plic_hart_config, hart_count, base_hartid, 1188 VIRT_IRQCHIP_NUM_SOURCES, 1189 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1190 VIRT_PLIC_PRIORITY_BASE, 1191 VIRT_PLIC_PENDING_BASE, 1192 VIRT_PLIC_ENABLE_BASE, 1193 VIRT_PLIC_ENABLE_STRIDE, 1194 VIRT_PLIC_CONTEXT_BASE, 1195 VIRT_PLIC_CONTEXT_STRIDE, 1196 memmap[VIRT_PLIC].size); 1197 1198 return ret; 1199 } 1200 1201 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1202 const MemMapEntry *memmap, int socket, 1203 int base_hartid, int hart_count) 1204 { 1205 int i; 1206 hwaddr addr; 1207 uint32_t guest_bits; 1208 DeviceState *aplic_s = NULL; 1209 DeviceState *aplic_m = NULL; 1210 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1211 1212 if (msimode) { 1213 if (!kvm_enabled()) { 1214 /* Per-socket M-level IMSICs */ 1215 addr = memmap[VIRT_IMSIC_M].base + 1216 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1217 for (i = 0; i < hart_count; i++) { 1218 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1219 base_hartid + i, true, 1, 1220 VIRT_IRQCHIP_NUM_MSIS); 1221 } 1222 } 1223 1224 /* Per-socket S-level IMSICs */ 1225 guest_bits = imsic_num_bits(aia_guests + 1); 1226 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1227 for (i = 0; i < hart_count; i++) { 1228 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1229 base_hartid + i, false, 1 + aia_guests, 1230 VIRT_IRQCHIP_NUM_MSIS); 1231 } 1232 } 1233 1234 if (!kvm_enabled()) { 1235 /* Per-socket M-level APLIC */ 1236 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1237 socket * memmap[VIRT_APLIC_M].size, 1238 memmap[VIRT_APLIC_M].size, 1239 (msimode) ? 0 : base_hartid, 1240 (msimode) ? 0 : hart_count, 1241 VIRT_IRQCHIP_NUM_SOURCES, 1242 VIRT_IRQCHIP_NUM_PRIO_BITS, 1243 msimode, true, NULL); 1244 } 1245 1246 /* Per-socket S-level APLIC */ 1247 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1248 socket * memmap[VIRT_APLIC_S].size, 1249 memmap[VIRT_APLIC_S].size, 1250 (msimode) ? 0 : base_hartid, 1251 (msimode) ? 0 : hart_count, 1252 VIRT_IRQCHIP_NUM_SOURCES, 1253 VIRT_IRQCHIP_NUM_PRIO_BITS, 1254 msimode, false, aplic_m); 1255 1256 return kvm_enabled() ? aplic_s : aplic_m; 1257 } 1258 1259 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1260 { 1261 DeviceState *dev; 1262 SysBusDevice *sysbus; 1263 const MemMapEntry *memmap = virt_memmap; 1264 int i; 1265 MemoryRegion *sysmem = get_system_memory(); 1266 1267 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1268 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1269 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1270 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1271 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1272 s->platform_bus_dev = dev; 1273 1274 sysbus = SYS_BUS_DEVICE(dev); 1275 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1276 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1277 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1278 } 1279 1280 memory_region_add_subregion(sysmem, 1281 memmap[VIRT_PLATFORM_BUS].base, 1282 sysbus_mmio_get_region(sysbus, 0)); 1283 } 1284 1285 static void virt_build_smbios(RISCVVirtState *s) 1286 { 1287 MachineClass *mc = MACHINE_GET_CLASS(s); 1288 MachineState *ms = MACHINE(s); 1289 uint8_t *smbios_tables, *smbios_anchor; 1290 size_t smbios_tables_len, smbios_anchor_len; 1291 struct smbios_phys_mem_area mem_array; 1292 const char *product = "QEMU Virtual Machine"; 1293 1294 if (kvm_enabled()) { 1295 product = "KVM Virtual Machine"; 1296 } 1297 1298 smbios_set_defaults("QEMU", product, mc->name); 1299 1300 if (riscv_is_32bit(&s->soc[0])) { 1301 smbios_set_default_processor_family(0x200); 1302 } else { 1303 smbios_set_default_processor_family(0x201); 1304 } 1305 1306 /* build the array of physical mem area from base_memmap */ 1307 mem_array.address = s->memmap[VIRT_DRAM].base; 1308 mem_array.length = ms->ram_size; 1309 1310 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 1311 &mem_array, 1, 1312 &smbios_tables, &smbios_tables_len, 1313 &smbios_anchor, &smbios_anchor_len, 1314 &error_fatal); 1315 1316 if (smbios_anchor) { 1317 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables", 1318 smbios_tables, smbios_tables_len); 1319 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor", 1320 smbios_anchor, smbios_anchor_len); 1321 } 1322 } 1323 1324 static void virt_machine_done(Notifier *notifier, void *data) 1325 { 1326 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1327 machine_done); 1328 const MemMapEntry *memmap = virt_memmap; 1329 MachineState *machine = MACHINE(s); 1330 target_ulong start_addr = memmap[VIRT_DRAM].base; 1331 target_ulong firmware_end_addr, kernel_start_addr; 1332 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1333 uint64_t fdt_load_addr; 1334 uint64_t kernel_entry = 0; 1335 BlockBackend *pflash_blk0; 1336 1337 /* 1338 * An user provided dtb must include everything, including 1339 * dynamic sysbus devices. Our FDT needs to be finalized. 1340 */ 1341 if (machine->dtb == NULL) { 1342 finalize_fdt(s); 1343 } 1344 1345 /* 1346 * Only direct boot kernel is currently supported for KVM VM, 1347 * so the "-bios" parameter is not supported when KVM is enabled. 1348 */ 1349 if (kvm_enabled()) { 1350 if (machine->firmware) { 1351 if (strcmp(machine->firmware, "none")) { 1352 error_report("Machine mode firmware is not supported in " 1353 "combination with KVM."); 1354 exit(1); 1355 } 1356 } else { 1357 machine->firmware = g_strdup("none"); 1358 } 1359 } 1360 1361 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1362 start_addr, NULL); 1363 1364 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1365 if (pflash_blk0) { 1366 if (machine->firmware && !strcmp(machine->firmware, "none") && 1367 !kvm_enabled()) { 1368 /* 1369 * Pflash was supplied but bios is none and not KVM guest, 1370 * let's overwrite the address we jump to after reset to 1371 * the base of the flash. 1372 */ 1373 start_addr = virt_memmap[VIRT_FLASH].base; 1374 } else { 1375 /* 1376 * Pflash was supplied but either KVM guest or bios is not none. 1377 * In this case, base of the flash would contain S-mode payload. 1378 */ 1379 riscv_setup_firmware_boot(machine); 1380 kernel_entry = virt_memmap[VIRT_FLASH].base; 1381 } 1382 } 1383 1384 if (machine->kernel_filename && !kernel_entry) { 1385 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1386 firmware_end_addr); 1387 1388 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1389 kernel_start_addr, true, NULL); 1390 } 1391 1392 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1393 memmap[VIRT_DRAM].size, 1394 machine); 1395 riscv_load_fdt(fdt_load_addr, machine->fdt); 1396 1397 /* load the reset vector */ 1398 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1399 virt_memmap[VIRT_MROM].base, 1400 virt_memmap[VIRT_MROM].size, kernel_entry, 1401 fdt_load_addr); 1402 1403 /* 1404 * Only direct boot kernel is currently supported for KVM VM, 1405 * So here setup kernel start address and fdt address. 1406 * TODO:Support firmware loading and integrate to TCG start 1407 */ 1408 if (kvm_enabled()) { 1409 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1410 } 1411 1412 virt_build_smbios(s); 1413 1414 if (virt_is_acpi_enabled(s)) { 1415 virt_acpi_setup(s); 1416 } 1417 } 1418 1419 static void virt_machine_init(MachineState *machine) 1420 { 1421 const MemMapEntry *memmap = virt_memmap; 1422 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1423 MemoryRegion *system_memory = get_system_memory(); 1424 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1425 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1426 int i, base_hartid, hart_count; 1427 int socket_count = riscv_socket_count(machine); 1428 1429 /* Check socket count limit */ 1430 if (VIRT_SOCKETS_MAX < socket_count) { 1431 error_report("number of sockets/nodes should be less than %d", 1432 VIRT_SOCKETS_MAX); 1433 exit(1); 1434 } 1435 1436 if (!virt_aclint_allowed() && s->have_aclint) { 1437 error_report("'aclint' is only available with TCG acceleration"); 1438 exit(1); 1439 } 1440 1441 /* Initialize sockets */ 1442 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1443 for (i = 0; i < socket_count; i++) { 1444 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1445 1446 if (!riscv_socket_check_hartids(machine, i)) { 1447 error_report("discontinuous hartids in socket%d", i); 1448 exit(1); 1449 } 1450 1451 base_hartid = riscv_socket_first_hartid(machine, i); 1452 if (base_hartid < 0) { 1453 error_report("can't find hartid base for socket%d", i); 1454 exit(1); 1455 } 1456 1457 hart_count = riscv_socket_hart_count(machine, i); 1458 if (hart_count < 0) { 1459 error_report("can't find hart count for socket%d", i); 1460 exit(1); 1461 } 1462 1463 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1464 TYPE_RISCV_HART_ARRAY); 1465 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1466 machine->cpu_type, &error_abort); 1467 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1468 base_hartid, &error_abort); 1469 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1470 hart_count, &error_abort); 1471 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1472 1473 if (virt_aclint_allowed() && s->have_aclint) { 1474 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1475 /* Per-socket ACLINT MTIMER */ 1476 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1477 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1478 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1479 base_hartid, hart_count, 1480 RISCV_ACLINT_DEFAULT_MTIMECMP, 1481 RISCV_ACLINT_DEFAULT_MTIME, 1482 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1483 } else { 1484 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1485 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1486 i * memmap[VIRT_CLINT].size, 1487 base_hartid, hart_count, false); 1488 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1489 i * memmap[VIRT_CLINT].size + 1490 RISCV_ACLINT_SWI_SIZE, 1491 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1492 base_hartid, hart_count, 1493 RISCV_ACLINT_DEFAULT_MTIMECMP, 1494 RISCV_ACLINT_DEFAULT_MTIME, 1495 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1496 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1497 i * memmap[VIRT_ACLINT_SSWI].size, 1498 base_hartid, hart_count, true); 1499 } 1500 } else if (tcg_enabled()) { 1501 /* Per-socket SiFive CLINT */ 1502 riscv_aclint_swi_create( 1503 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1504 base_hartid, hart_count, false); 1505 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1506 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1507 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1508 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1509 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1510 } 1511 1512 /* Per-socket interrupt controller */ 1513 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1514 s->irqchip[i] = virt_create_plic(memmap, i, 1515 base_hartid, hart_count); 1516 } else { 1517 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1518 memmap, i, base_hartid, 1519 hart_count); 1520 } 1521 1522 /* Try to use different IRQCHIP instance based device type */ 1523 if (i == 0) { 1524 mmio_irqchip = s->irqchip[i]; 1525 virtio_irqchip = s->irqchip[i]; 1526 pcie_irqchip = s->irqchip[i]; 1527 } 1528 if (i == 1) { 1529 virtio_irqchip = s->irqchip[i]; 1530 pcie_irqchip = s->irqchip[i]; 1531 } 1532 if (i == 2) { 1533 pcie_irqchip = s->irqchip[i]; 1534 } 1535 } 1536 1537 if (kvm_enabled() && virt_use_kvm_aia(s)) { 1538 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1539 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1540 memmap[VIRT_APLIC_S].base, 1541 memmap[VIRT_IMSIC_S].base, 1542 s->aia_guests); 1543 } 1544 1545 if (riscv_is_32bit(&s->soc[0])) { 1546 #if HOST_LONG_BITS == 64 1547 /* limit RAM size in a 32-bit system */ 1548 if (machine->ram_size > 10 * GiB) { 1549 machine->ram_size = 10 * GiB; 1550 error_report("Limiting RAM size to 10 GiB"); 1551 } 1552 #endif 1553 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1554 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1555 } else { 1556 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1557 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1558 virt_high_pcie_memmap.base = 1559 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1560 } 1561 1562 s->memmap = virt_memmap; 1563 1564 /* register system main memory (actual RAM) */ 1565 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1566 machine->ram); 1567 1568 /* boot rom */ 1569 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1570 memmap[VIRT_MROM].size, &error_fatal); 1571 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1572 mask_rom); 1573 1574 /* 1575 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1576 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1577 */ 1578 s->fw_cfg = create_fw_cfg(machine); 1579 rom_set_fw(s->fw_cfg); 1580 1581 /* SiFive Test MMIO device */ 1582 sifive_test_create(memmap[VIRT_TEST].base); 1583 1584 /* VirtIO MMIO devices */ 1585 for (i = 0; i < VIRTIO_COUNT; i++) { 1586 sysbus_create_simple("virtio-mmio", 1587 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1588 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1589 } 1590 1591 gpex_pcie_init(system_memory, pcie_irqchip, s); 1592 1593 create_platform_bus(s, mmio_irqchip); 1594 1595 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1596 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1597 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1598 1599 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1600 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1601 1602 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1603 /* Map legacy -drive if=pflash to machine properties */ 1604 pflash_cfi01_legacy_drive(s->flash[i], 1605 drive_get(IF_PFLASH, 0, i)); 1606 } 1607 virt_flash_map(s, system_memory); 1608 1609 /* load/create device tree */ 1610 if (machine->dtb) { 1611 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1612 if (!machine->fdt) { 1613 error_report("load_device_tree() failed"); 1614 exit(1); 1615 } 1616 } else { 1617 create_fdt(s, memmap); 1618 } 1619 1620 s->machine_done.notify = virt_machine_done; 1621 qemu_add_machine_init_done_notifier(&s->machine_done); 1622 } 1623 1624 static void virt_machine_instance_init(Object *obj) 1625 { 1626 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1627 1628 virt_flash_create(s); 1629 1630 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1631 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1632 s->acpi = ON_OFF_AUTO_AUTO; 1633 } 1634 1635 static char *virt_get_aia_guests(Object *obj, Error **errp) 1636 { 1637 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1638 1639 return g_strdup_printf("%d", s->aia_guests); 1640 } 1641 1642 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1643 { 1644 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1645 1646 s->aia_guests = atoi(val); 1647 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1648 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1649 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1650 VIRT_IRQCHIP_MAX_GUESTS); 1651 } 1652 } 1653 1654 static char *virt_get_aia(Object *obj, Error **errp) 1655 { 1656 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1657 const char *val; 1658 1659 switch (s->aia_type) { 1660 case VIRT_AIA_TYPE_APLIC: 1661 val = "aplic"; 1662 break; 1663 case VIRT_AIA_TYPE_APLIC_IMSIC: 1664 val = "aplic-imsic"; 1665 break; 1666 default: 1667 val = "none"; 1668 break; 1669 }; 1670 1671 return g_strdup(val); 1672 } 1673 1674 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1675 { 1676 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1677 1678 if (!strcmp(val, "none")) { 1679 s->aia_type = VIRT_AIA_TYPE_NONE; 1680 } else if (!strcmp(val, "aplic")) { 1681 s->aia_type = VIRT_AIA_TYPE_APLIC; 1682 } else if (!strcmp(val, "aplic-imsic")) { 1683 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1684 } else { 1685 error_setg(errp, "Invalid AIA interrupt controller type"); 1686 error_append_hint(errp, "Valid values are none, aplic, and " 1687 "aplic-imsic.\n"); 1688 } 1689 } 1690 1691 static bool virt_get_aclint(Object *obj, Error **errp) 1692 { 1693 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1694 1695 return s->have_aclint; 1696 } 1697 1698 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1699 { 1700 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1701 1702 s->have_aclint = value; 1703 } 1704 1705 bool virt_is_acpi_enabled(RISCVVirtState *s) 1706 { 1707 return s->acpi != ON_OFF_AUTO_OFF; 1708 } 1709 1710 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1711 void *opaque, Error **errp) 1712 { 1713 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1714 OnOffAuto acpi = s->acpi; 1715 1716 visit_type_OnOffAuto(v, name, &acpi, errp); 1717 } 1718 1719 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1720 void *opaque, Error **errp) 1721 { 1722 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1723 1724 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1725 } 1726 1727 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1728 DeviceState *dev) 1729 { 1730 MachineClass *mc = MACHINE_GET_CLASS(machine); 1731 1732 if (device_is_dynamic_sysbus(mc, dev) || 1733 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1734 return HOTPLUG_HANDLER(machine); 1735 } 1736 return NULL; 1737 } 1738 1739 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1740 DeviceState *dev, Error **errp) 1741 { 1742 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1743 1744 if (s->platform_bus_dev) { 1745 MachineClass *mc = MACHINE_GET_CLASS(s); 1746 1747 if (device_is_dynamic_sysbus(mc, dev)) { 1748 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1749 SYS_BUS_DEVICE(dev)); 1750 } 1751 } 1752 1753 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1754 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1755 } 1756 } 1757 1758 static void virt_machine_class_init(ObjectClass *oc, void *data) 1759 { 1760 MachineClass *mc = MACHINE_CLASS(oc); 1761 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1762 1763 mc->desc = "RISC-V VirtIO board"; 1764 mc->init = virt_machine_init; 1765 mc->max_cpus = VIRT_CPUS_MAX; 1766 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1767 mc->block_default_type = IF_VIRTIO; 1768 mc->no_cdrom = 1; 1769 mc->pci_allow_0_address = true; 1770 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1771 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1772 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1773 mc->numa_mem_supported = true; 1774 /* platform instead of architectural choice */ 1775 mc->cpu_cluster_has_numa_boundary = true; 1776 mc->default_ram_id = "riscv_virt_board.ram"; 1777 assert(!mc->get_hotplug_handler); 1778 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1779 1780 hc->plug = virt_machine_device_plug_cb; 1781 1782 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1783 #ifdef CONFIG_TPM 1784 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1785 #endif 1786 1787 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1788 virt_set_aclint); 1789 object_class_property_set_description(oc, "aclint", 1790 "(TCG only) Set on/off to " 1791 "enable/disable emulating " 1792 "ACLINT devices"); 1793 1794 object_class_property_add_str(oc, "aia", virt_get_aia, 1795 virt_set_aia); 1796 object_class_property_set_description(oc, "aia", 1797 "Set type of AIA interrupt " 1798 "controller. Valid values are " 1799 "none, aplic, and aplic-imsic."); 1800 1801 object_class_property_add_str(oc, "aia-guests", 1802 virt_get_aia_guests, 1803 virt_set_aia_guests); 1804 { 1805 g_autofree char *str = 1806 g_strdup_printf("Set number of guest MMIO pages for AIA IMSIC. " 1807 "Valid value should be between 0 and %d.", 1808 VIRT_IRQCHIP_MAX_GUESTS); 1809 object_class_property_set_description(oc, "aia-guests", str); 1810 } 1811 1812 object_class_property_add(oc, "acpi", "OnOffAuto", 1813 virt_get_acpi, virt_set_acpi, 1814 NULL, NULL); 1815 object_class_property_set_description(oc, "acpi", 1816 "Enable ACPI"); 1817 } 1818 1819 static const TypeInfo virt_machine_typeinfo = { 1820 .name = MACHINE_TYPE_NAME("virt"), 1821 .parent = TYPE_MACHINE, 1822 .class_init = virt_machine_class_init, 1823 .instance_init = virt_machine_instance_init, 1824 .instance_size = sizeof(RISCVVirtState), 1825 .interfaces = (InterfaceInfo[]) { 1826 { TYPE_HOTPLUG_HANDLER }, 1827 { } 1828 }, 1829 }; 1830 1831 static void virt_machine_init_register_types(void) 1832 { 1833 type_register_static(&virt_machine_typeinfo); 1834 } 1835 1836 type_init(virt_machine_init_register_types) 1837