1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "kvm/kvm_riscv.h" 39 #include "hw/intc/riscv_aclint.h" 40 #include "hw/intc/riscv_aplic.h" 41 #include "hw/intc/sifive_plic.h" 42 #include "hw/misc/sifive_test.h" 43 #include "hw/platform-bus.h" 44 #include "chardev/char.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/tcg.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/tpm.h" 50 #include "hw/pci/pci.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/display/ramfb.h" 53 #include "hw/acpi/aml-build.h" 54 #include "qapi/qapi-visit-common.h" 55 56 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 57 static bool virt_use_kvm_aia(RISCVVirtState *s) 58 { 59 return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 60 } 61 62 static const MemMapEntry virt_memmap[] = { 63 [VIRT_DEBUG] = { 0x0, 0x100 }, 64 [VIRT_MROM] = { 0x1000, 0xf000 }, 65 [VIRT_TEST] = { 0x100000, 0x1000 }, 66 [VIRT_RTC] = { 0x101000, 0x1000 }, 67 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 68 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 69 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 70 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 71 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 72 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 73 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 74 [VIRT_UART0] = { 0x10000000, 0x100 }, 75 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 76 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 77 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 78 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 79 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 80 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 81 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 82 [VIRT_DRAM] = { 0x80000000, 0x0 }, 83 }; 84 85 /* PCIe high mmio is fixed for RV32 */ 86 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 87 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 88 89 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 90 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 91 92 static MemMapEntry virt_high_pcie_memmap; 93 94 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 95 96 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 97 const char *name, 98 const char *alias_prop_name) 99 { 100 /* 101 * Create a single flash device. We use the same parameters as 102 * the flash devices on the ARM virt board. 103 */ 104 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 105 106 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 107 qdev_prop_set_uint8(dev, "width", 4); 108 qdev_prop_set_uint8(dev, "device-width", 2); 109 qdev_prop_set_bit(dev, "big-endian", false); 110 qdev_prop_set_uint16(dev, "id0", 0x89); 111 qdev_prop_set_uint16(dev, "id1", 0x18); 112 qdev_prop_set_uint16(dev, "id2", 0x00); 113 qdev_prop_set_uint16(dev, "id3", 0x00); 114 qdev_prop_set_string(dev, "name", name); 115 116 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 117 object_property_add_alias(OBJECT(s), alias_prop_name, 118 OBJECT(dev), "drive"); 119 120 return PFLASH_CFI01(dev); 121 } 122 123 static void virt_flash_create(RISCVVirtState *s) 124 { 125 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 126 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 127 } 128 129 static void virt_flash_map1(PFlashCFI01 *flash, 130 hwaddr base, hwaddr size, 131 MemoryRegion *sysmem) 132 { 133 DeviceState *dev = DEVICE(flash); 134 135 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 136 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 137 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 138 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 139 140 memory_region_add_subregion(sysmem, base, 141 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 142 0)); 143 } 144 145 static void virt_flash_map(RISCVVirtState *s, 146 MemoryRegion *sysmem) 147 { 148 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 149 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 150 151 virt_flash_map1(s->flash[0], flashbase, flashsize, 152 sysmem); 153 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 154 sysmem); 155 } 156 157 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 158 uint32_t irqchip_phandle) 159 { 160 int pin, dev; 161 uint32_t irq_map_stride = 0; 162 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 163 FDT_MAX_INT_MAP_WIDTH] = {}; 164 uint32_t *irq_map = full_irq_map; 165 166 /* This code creates a standard swizzle of interrupts such that 167 * each device's first interrupt is based on it's PCI_SLOT number. 168 * (See pci_swizzle_map_irq_fn()) 169 * 170 * We only need one entry per interrupt in the table (not one per 171 * possible slot) seeing the interrupt-map-mask will allow the table 172 * to wrap to any number of devices. 173 */ 174 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 175 int devfn = dev * 0x8; 176 177 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 178 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 179 int i = 0; 180 181 /* Fill PCI address cells */ 182 irq_map[i] = cpu_to_be32(devfn << 8); 183 i += FDT_PCI_ADDR_CELLS; 184 185 /* Fill PCI Interrupt cells */ 186 irq_map[i] = cpu_to_be32(pin + 1); 187 i += FDT_PCI_INT_CELLS; 188 189 /* Fill interrupt controller phandle and cells */ 190 irq_map[i++] = cpu_to_be32(irqchip_phandle); 191 irq_map[i++] = cpu_to_be32(irq_nr); 192 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 193 irq_map[i++] = cpu_to_be32(0x4); 194 } 195 196 if (!irq_map_stride) { 197 irq_map_stride = i; 198 } 199 irq_map += irq_map_stride; 200 } 201 } 202 203 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 204 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 205 irq_map_stride * sizeof(uint32_t)); 206 207 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 208 0x1800, 0, 0, 0x7); 209 } 210 211 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 212 char *clust_name, uint32_t *phandle, 213 uint32_t *intc_phandles) 214 { 215 int cpu; 216 uint32_t cpu_phandle; 217 MachineState *ms = MACHINE(s); 218 char *name, *cpu_name, *core_name, *intc_name, *sv_name; 219 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 220 uint8_t satp_mode_max; 221 222 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 223 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 224 225 cpu_phandle = (*phandle)++; 226 227 cpu_name = g_strdup_printf("/cpus/cpu@%d", 228 s->soc[socket].hartid_base + cpu); 229 qemu_fdt_add_subnode(ms->fdt, cpu_name); 230 231 if (cpu_ptr->cfg.satp_mode.supported != 0) { 232 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 233 sv_name = g_strdup_printf("riscv,%s", 234 satp_mode_str(satp_mode_max, is_32_bit)); 235 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 236 g_free(sv_name); 237 } 238 239 name = riscv_isa_string(cpu_ptr); 240 qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); 241 g_free(name); 242 243 if (cpu_ptr->cfg.ext_zicbom) { 244 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 245 cpu_ptr->cfg.cbom_blocksize); 246 } 247 248 if (cpu_ptr->cfg.ext_zicboz) { 249 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 250 cpu_ptr->cfg.cboz_blocksize); 251 } 252 253 if (cpu_ptr->cfg.ext_zicbop) { 254 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 255 cpu_ptr->cfg.cbop_blocksize); 256 } 257 258 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 259 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 260 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 261 s->soc[socket].hartid_base + cpu); 262 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 263 riscv_socket_fdt_write_id(ms, cpu_name, socket); 264 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 265 266 intc_phandles[cpu] = (*phandle)++; 267 268 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 269 qemu_fdt_add_subnode(ms->fdt, intc_name); 270 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 271 intc_phandles[cpu]); 272 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 273 "riscv,cpu-intc"); 274 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 275 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 276 277 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 278 qemu_fdt_add_subnode(ms->fdt, core_name); 279 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 280 281 g_free(core_name); 282 g_free(intc_name); 283 g_free(cpu_name); 284 } 285 } 286 287 static void create_fdt_socket_memory(RISCVVirtState *s, 288 const MemMapEntry *memmap, int socket) 289 { 290 char *mem_name; 291 uint64_t addr, size; 292 MachineState *ms = MACHINE(s); 293 294 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 295 size = riscv_socket_mem_size(ms, socket); 296 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 297 qemu_fdt_add_subnode(ms->fdt, mem_name); 298 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 299 addr >> 32, addr, size >> 32, size); 300 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 301 riscv_socket_fdt_write_id(ms, mem_name, socket); 302 g_free(mem_name); 303 } 304 305 static void create_fdt_socket_clint(RISCVVirtState *s, 306 const MemMapEntry *memmap, int socket, 307 uint32_t *intc_phandles) 308 { 309 int cpu; 310 char *clint_name; 311 uint32_t *clint_cells; 312 unsigned long clint_addr; 313 MachineState *ms = MACHINE(s); 314 static const char * const clint_compat[2] = { 315 "sifive,clint0", "riscv,clint0" 316 }; 317 318 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 319 320 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 321 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 322 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 323 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 324 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 325 } 326 327 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 328 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 329 qemu_fdt_add_subnode(ms->fdt, clint_name); 330 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 331 (char **)&clint_compat, 332 ARRAY_SIZE(clint_compat)); 333 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 334 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 335 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 336 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 337 riscv_socket_fdt_write_id(ms, clint_name, socket); 338 g_free(clint_name); 339 340 g_free(clint_cells); 341 } 342 343 static void create_fdt_socket_aclint(RISCVVirtState *s, 344 const MemMapEntry *memmap, int socket, 345 uint32_t *intc_phandles) 346 { 347 int cpu; 348 char *name; 349 unsigned long addr, size; 350 uint32_t aclint_cells_size; 351 uint32_t *aclint_mswi_cells; 352 uint32_t *aclint_sswi_cells; 353 uint32_t *aclint_mtimer_cells; 354 MachineState *ms = MACHINE(s); 355 356 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 357 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 358 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 359 360 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 361 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 362 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 363 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 364 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 365 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 366 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 367 } 368 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 369 370 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 371 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 372 name = g_strdup_printf("/soc/mswi@%lx", addr); 373 qemu_fdt_add_subnode(ms->fdt, name); 374 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 375 "riscv,aclint-mswi"); 376 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 377 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 378 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 379 aclint_mswi_cells, aclint_cells_size); 380 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 381 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 382 riscv_socket_fdt_write_id(ms, name, socket); 383 g_free(name); 384 } 385 386 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 387 addr = memmap[VIRT_CLINT].base + 388 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 389 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 390 } else { 391 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 392 (memmap[VIRT_CLINT].size * socket); 393 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 394 } 395 name = g_strdup_printf("/soc/mtimer@%lx", addr); 396 qemu_fdt_add_subnode(ms->fdt, name); 397 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 398 "riscv,aclint-mtimer"); 399 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 400 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 401 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 402 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 403 0x0, RISCV_ACLINT_DEFAULT_MTIME); 404 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 405 aclint_mtimer_cells, aclint_cells_size); 406 riscv_socket_fdt_write_id(ms, name, socket); 407 g_free(name); 408 409 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 410 addr = memmap[VIRT_ACLINT_SSWI].base + 411 (memmap[VIRT_ACLINT_SSWI].size * socket); 412 name = g_strdup_printf("/soc/sswi@%lx", addr); 413 qemu_fdt_add_subnode(ms->fdt, name); 414 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 415 "riscv,aclint-sswi"); 416 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 417 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 418 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 419 aclint_sswi_cells, aclint_cells_size); 420 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 421 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 422 riscv_socket_fdt_write_id(ms, name, socket); 423 g_free(name); 424 } 425 426 g_free(aclint_mswi_cells); 427 g_free(aclint_mtimer_cells); 428 g_free(aclint_sswi_cells); 429 } 430 431 static void create_fdt_socket_plic(RISCVVirtState *s, 432 const MemMapEntry *memmap, int socket, 433 uint32_t *phandle, uint32_t *intc_phandles, 434 uint32_t *plic_phandles) 435 { 436 int cpu; 437 char *plic_name; 438 uint32_t *plic_cells; 439 unsigned long plic_addr; 440 MachineState *ms = MACHINE(s); 441 static const char * const plic_compat[2] = { 442 "sifive,plic-1.0.0", "riscv,plic0" 443 }; 444 445 plic_phandles[socket] = (*phandle)++; 446 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 447 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 448 qemu_fdt_add_subnode(ms->fdt, plic_name); 449 qemu_fdt_setprop_cell(ms->fdt, plic_name, 450 "#interrupt-cells", FDT_PLIC_INT_CELLS); 451 qemu_fdt_setprop_cell(ms->fdt, plic_name, 452 "#address-cells", FDT_PLIC_ADDR_CELLS); 453 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 454 (char **)&plic_compat, 455 ARRAY_SIZE(plic_compat)); 456 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 457 458 if (kvm_enabled()) { 459 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 460 461 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 462 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 463 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 464 } 465 466 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 467 plic_cells, 468 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 469 } else { 470 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 471 472 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 473 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 474 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 475 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 476 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 477 } 478 479 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 480 plic_cells, 481 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 482 } 483 484 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 485 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 486 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 487 VIRT_IRQCHIP_NUM_SOURCES - 1); 488 riscv_socket_fdt_write_id(ms, plic_name, socket); 489 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 490 plic_phandles[socket]); 491 492 if (!socket) { 493 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 494 memmap[VIRT_PLATFORM_BUS].base, 495 memmap[VIRT_PLATFORM_BUS].size, 496 VIRT_PLATFORM_BUS_IRQ); 497 } 498 499 g_free(plic_name); 500 501 g_free(plic_cells); 502 } 503 504 uint32_t imsic_num_bits(uint32_t count) 505 { 506 uint32_t ret = 0; 507 508 while (BIT(ret) < count) { 509 ret++; 510 } 511 512 return ret; 513 } 514 515 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 516 uint32_t *intc_phandles, uint32_t msi_phandle, 517 bool m_mode, uint32_t imsic_guest_bits) 518 { 519 int cpu, socket; 520 char *imsic_name; 521 MachineState *ms = MACHINE(s); 522 int socket_count = riscv_socket_count(ms); 523 uint32_t imsic_max_hart_per_socket; 524 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 525 526 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 527 imsic_regs = g_new0(uint32_t, socket_count * 4); 528 529 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 530 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 531 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 532 } 533 534 imsic_max_hart_per_socket = 0; 535 for (socket = 0; socket < socket_count; socket++) { 536 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 537 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 538 s->soc[socket].num_harts; 539 imsic_regs[socket * 4 + 0] = 0; 540 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 541 imsic_regs[socket * 4 + 2] = 0; 542 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 543 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 544 imsic_max_hart_per_socket = s->soc[socket].num_harts; 545 } 546 } 547 548 imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr); 549 qemu_fdt_add_subnode(ms->fdt, imsic_name); 550 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); 551 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 552 FDT_IMSIC_INT_CELLS); 553 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 554 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 555 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 556 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 557 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 558 socket_count * sizeof(uint32_t) * 4); 559 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 560 VIRT_IRQCHIP_NUM_MSIS); 561 562 if (imsic_guest_bits) { 563 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 564 imsic_guest_bits); 565 } 566 567 if (socket_count > 1) { 568 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 569 imsic_num_bits(imsic_max_hart_per_socket)); 570 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 571 imsic_num_bits(socket_count)); 572 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 573 IMSIC_MMIO_GROUP_MIN_SHIFT); 574 } 575 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 576 577 g_free(imsic_name); 578 g_free(imsic_regs); 579 g_free(imsic_cells); 580 } 581 582 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 583 uint32_t *phandle, uint32_t *intc_phandles, 584 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 585 { 586 *msi_m_phandle = (*phandle)++; 587 *msi_s_phandle = (*phandle)++; 588 589 if (!kvm_enabled()) { 590 /* M-level IMSIC node */ 591 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 592 *msi_m_phandle, true, 0); 593 } 594 595 /* S-level IMSIC node */ 596 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 597 *msi_s_phandle, false, 598 imsic_num_bits(s->aia_guests + 1)); 599 600 } 601 602 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 603 unsigned long aplic_addr, uint32_t aplic_size, 604 uint32_t msi_phandle, 605 uint32_t *intc_phandles, 606 uint32_t aplic_phandle, 607 uint32_t aplic_child_phandle, 608 bool m_mode, int num_harts) 609 { 610 int cpu; 611 char *aplic_name; 612 uint32_t *aplic_cells; 613 MachineState *ms = MACHINE(s); 614 615 aplic_cells = g_new0(uint32_t, num_harts * 2); 616 617 for (cpu = 0; cpu < num_harts; cpu++) { 618 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 619 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 620 } 621 622 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 623 qemu_fdt_add_subnode(ms->fdt, aplic_name); 624 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); 625 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 626 "#interrupt-cells", FDT_APLIC_INT_CELLS); 627 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 628 629 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 630 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 631 aplic_cells, num_harts * sizeof(uint32_t) * 2); 632 } else { 633 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 634 } 635 636 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 637 0x0, aplic_addr, 0x0, aplic_size); 638 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 639 VIRT_IRQCHIP_NUM_SOURCES); 640 641 if (aplic_child_phandle) { 642 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 643 aplic_child_phandle); 644 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 645 aplic_child_phandle, 0x1, 646 VIRT_IRQCHIP_NUM_SOURCES); 647 } 648 649 riscv_socket_fdt_write_id(ms, aplic_name, socket); 650 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 651 652 g_free(aplic_name); 653 g_free(aplic_cells); 654 } 655 656 static void create_fdt_socket_aplic(RISCVVirtState *s, 657 const MemMapEntry *memmap, int socket, 658 uint32_t msi_m_phandle, 659 uint32_t msi_s_phandle, 660 uint32_t *phandle, 661 uint32_t *intc_phandles, 662 uint32_t *aplic_phandles, 663 int num_harts) 664 { 665 char *aplic_name; 666 unsigned long aplic_addr; 667 MachineState *ms = MACHINE(s); 668 uint32_t aplic_m_phandle, aplic_s_phandle; 669 670 aplic_m_phandle = (*phandle)++; 671 aplic_s_phandle = (*phandle)++; 672 673 if (!kvm_enabled()) { 674 /* M-level APLIC node */ 675 aplic_addr = memmap[VIRT_APLIC_M].base + 676 (memmap[VIRT_APLIC_M].size * socket); 677 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 678 msi_m_phandle, intc_phandles, 679 aplic_m_phandle, aplic_s_phandle, 680 true, num_harts); 681 } 682 683 /* S-level APLIC node */ 684 aplic_addr = memmap[VIRT_APLIC_S].base + 685 (memmap[VIRT_APLIC_S].size * socket); 686 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 687 msi_s_phandle, intc_phandles, 688 aplic_s_phandle, 0, 689 false, num_harts); 690 691 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 692 693 if (!socket) { 694 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 695 memmap[VIRT_PLATFORM_BUS].base, 696 memmap[VIRT_PLATFORM_BUS].size, 697 VIRT_PLATFORM_BUS_IRQ); 698 } 699 700 g_free(aplic_name); 701 702 aplic_phandles[socket] = aplic_s_phandle; 703 } 704 705 static void create_fdt_pmu(RISCVVirtState *s) 706 { 707 char *pmu_name; 708 MachineState *ms = MACHINE(s); 709 RISCVCPU hart = s->soc[0].harts[0]; 710 711 pmu_name = g_strdup_printf("/pmu"); 712 qemu_fdt_add_subnode(ms->fdt, pmu_name); 713 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 714 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 715 716 g_free(pmu_name); 717 } 718 719 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 720 uint32_t *phandle, 721 uint32_t *irq_mmio_phandle, 722 uint32_t *irq_pcie_phandle, 723 uint32_t *irq_virtio_phandle, 724 uint32_t *msi_pcie_phandle) 725 { 726 char *clust_name; 727 int socket, phandle_pos; 728 MachineState *ms = MACHINE(s); 729 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 730 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 731 int socket_count = riscv_socket_count(ms); 732 733 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 734 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 735 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 736 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 737 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 738 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 739 740 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 741 742 phandle_pos = ms->smp.cpus; 743 for (socket = (socket_count - 1); socket >= 0; socket--) { 744 phandle_pos -= s->soc[socket].num_harts; 745 746 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 747 qemu_fdt_add_subnode(ms->fdt, clust_name); 748 749 create_fdt_socket_cpus(s, socket, clust_name, phandle, 750 &intc_phandles[phandle_pos]); 751 752 create_fdt_socket_memory(s, memmap, socket); 753 754 g_free(clust_name); 755 756 if (tcg_enabled()) { 757 if (s->have_aclint) { 758 create_fdt_socket_aclint(s, memmap, socket, 759 &intc_phandles[phandle_pos]); 760 } else { 761 create_fdt_socket_clint(s, memmap, socket, 762 &intc_phandles[phandle_pos]); 763 } 764 } 765 } 766 767 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 768 create_fdt_imsic(s, memmap, phandle, intc_phandles, 769 &msi_m_phandle, &msi_s_phandle); 770 *msi_pcie_phandle = msi_s_phandle; 771 } 772 773 /* KVM AIA only has one APLIC instance */ 774 if (kvm_enabled() && virt_use_kvm_aia(s)) { 775 create_fdt_socket_aplic(s, memmap, 0, 776 msi_m_phandle, msi_s_phandle, phandle, 777 &intc_phandles[0], xplic_phandles, 778 ms->smp.cpus); 779 } else { 780 phandle_pos = ms->smp.cpus; 781 for (socket = (socket_count - 1); socket >= 0; socket--) { 782 phandle_pos -= s->soc[socket].num_harts; 783 784 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 785 create_fdt_socket_plic(s, memmap, socket, phandle, 786 &intc_phandles[phandle_pos], 787 xplic_phandles); 788 } else { 789 create_fdt_socket_aplic(s, memmap, socket, 790 msi_m_phandle, msi_s_phandle, phandle, 791 &intc_phandles[phandle_pos], 792 xplic_phandles, 793 s->soc[socket].num_harts); 794 } 795 } 796 } 797 798 g_free(intc_phandles); 799 800 if (kvm_enabled() && virt_use_kvm_aia(s)) { 801 *irq_mmio_phandle = xplic_phandles[0]; 802 *irq_virtio_phandle = xplic_phandles[0]; 803 *irq_pcie_phandle = xplic_phandles[0]; 804 } else { 805 for (socket = 0; socket < socket_count; socket++) { 806 if (socket == 0) { 807 *irq_mmio_phandle = xplic_phandles[socket]; 808 *irq_virtio_phandle = xplic_phandles[socket]; 809 *irq_pcie_phandle = xplic_phandles[socket]; 810 } 811 if (socket == 1) { 812 *irq_virtio_phandle = xplic_phandles[socket]; 813 *irq_pcie_phandle = xplic_phandles[socket]; 814 } 815 if (socket == 2) { 816 *irq_pcie_phandle = xplic_phandles[socket]; 817 } 818 } 819 } 820 821 riscv_socket_fdt_write_distance_matrix(ms); 822 } 823 824 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 825 uint32_t irq_virtio_phandle) 826 { 827 int i; 828 char *name; 829 MachineState *ms = MACHINE(s); 830 831 for (i = 0; i < VIRTIO_COUNT; i++) { 832 name = g_strdup_printf("/soc/virtio_mmio@%lx", 833 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 834 qemu_fdt_add_subnode(ms->fdt, name); 835 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 836 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 837 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 838 0x0, memmap[VIRT_VIRTIO].size); 839 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 840 irq_virtio_phandle); 841 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 842 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 843 VIRTIO_IRQ + i); 844 } else { 845 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 846 VIRTIO_IRQ + i, 0x4); 847 } 848 g_free(name); 849 } 850 } 851 852 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 853 uint32_t irq_pcie_phandle, 854 uint32_t msi_pcie_phandle) 855 { 856 char *name; 857 MachineState *ms = MACHINE(s); 858 859 name = g_strdup_printf("/soc/pci@%lx", 860 (long) memmap[VIRT_PCIE_ECAM].base); 861 qemu_fdt_add_subnode(ms->fdt, name); 862 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 863 FDT_PCI_ADDR_CELLS); 864 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 865 FDT_PCI_INT_CELLS); 866 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 867 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 868 "pci-host-ecam-generic"); 869 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 870 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 871 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 872 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 873 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 874 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 875 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 876 } 877 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 878 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 879 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 880 1, FDT_PCI_RANGE_IOPORT, 2, 0, 881 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 882 1, FDT_PCI_RANGE_MMIO, 883 2, memmap[VIRT_PCIE_MMIO].base, 884 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 885 1, FDT_PCI_RANGE_MMIO_64BIT, 886 2, virt_high_pcie_memmap.base, 887 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 888 889 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 890 g_free(name); 891 } 892 893 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 894 uint32_t *phandle) 895 { 896 char *name; 897 uint32_t test_phandle; 898 MachineState *ms = MACHINE(s); 899 900 test_phandle = (*phandle)++; 901 name = g_strdup_printf("/soc/test@%lx", 902 (long)memmap[VIRT_TEST].base); 903 qemu_fdt_add_subnode(ms->fdt, name); 904 { 905 static const char * const compat[3] = { 906 "sifive,test1", "sifive,test0", "syscon" 907 }; 908 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 909 (char **)&compat, ARRAY_SIZE(compat)); 910 } 911 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 912 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 913 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 914 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 915 g_free(name); 916 917 name = g_strdup_printf("/reboot"); 918 qemu_fdt_add_subnode(ms->fdt, name); 919 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 920 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 921 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 922 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 923 g_free(name); 924 925 name = g_strdup_printf("/poweroff"); 926 qemu_fdt_add_subnode(ms->fdt, name); 927 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 928 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 929 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 930 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 931 g_free(name); 932 } 933 934 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 935 uint32_t irq_mmio_phandle) 936 { 937 char *name; 938 MachineState *ms = MACHINE(s); 939 940 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 941 qemu_fdt_add_subnode(ms->fdt, name); 942 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 943 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 944 0x0, memmap[VIRT_UART0].base, 945 0x0, memmap[VIRT_UART0].size); 946 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 947 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 948 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 949 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 950 } else { 951 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 952 } 953 954 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 955 g_free(name); 956 } 957 958 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 959 uint32_t irq_mmio_phandle) 960 { 961 char *name; 962 MachineState *ms = MACHINE(s); 963 964 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 965 qemu_fdt_add_subnode(ms->fdt, name); 966 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 967 "google,goldfish-rtc"); 968 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 969 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 970 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 971 irq_mmio_phandle); 972 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 973 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 974 } else { 975 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 976 } 977 g_free(name); 978 } 979 980 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 981 { 982 char *name; 983 MachineState *ms = MACHINE(s); 984 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 985 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 986 987 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 988 qemu_fdt_add_subnode(ms->fdt, name); 989 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 990 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 991 2, flashbase, 2, flashsize, 992 2, flashbase + flashsize, 2, flashsize); 993 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 994 g_free(name); 995 } 996 997 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 998 { 999 char *nodename; 1000 MachineState *ms = MACHINE(s); 1001 hwaddr base = memmap[VIRT_FW_CFG].base; 1002 hwaddr size = memmap[VIRT_FW_CFG].size; 1003 1004 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1005 qemu_fdt_add_subnode(ms->fdt, nodename); 1006 qemu_fdt_setprop_string(ms->fdt, nodename, 1007 "compatible", "qemu,fw-cfg-mmio"); 1008 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1009 2, base, 2, size); 1010 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1011 g_free(nodename); 1012 } 1013 1014 static void finalize_fdt(RISCVVirtState *s) 1015 { 1016 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1017 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1018 1019 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 1020 &irq_pcie_phandle, &irq_virtio_phandle, 1021 &msi_pcie_phandle); 1022 1023 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 1024 1025 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); 1026 1027 create_fdt_reset(s, virt_memmap, &phandle); 1028 1029 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 1030 1031 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 1032 } 1033 1034 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1035 { 1036 MachineState *ms = MACHINE(s); 1037 uint8_t rng_seed[32]; 1038 1039 ms->fdt = create_device_tree(&s->fdt_size); 1040 if (!ms->fdt) { 1041 error_report("create_device_tree() failed"); 1042 exit(1); 1043 } 1044 1045 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1046 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1047 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1048 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1049 1050 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1051 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1052 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1053 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1054 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1055 1056 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1057 1058 /* Pass seed to RNG */ 1059 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1060 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1061 rng_seed, sizeof(rng_seed)); 1062 1063 create_fdt_flash(s, memmap); 1064 create_fdt_fw_cfg(s, memmap); 1065 create_fdt_pmu(s); 1066 } 1067 1068 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1069 DeviceState *irqchip, 1070 RISCVVirtState *s) 1071 { 1072 DeviceState *dev; 1073 MemoryRegion *ecam_alias, *ecam_reg; 1074 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1075 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1076 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1077 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1078 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1079 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1080 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1081 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1082 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1083 qemu_irq irq; 1084 int i; 1085 1086 dev = qdev_new(TYPE_GPEX_HOST); 1087 1088 /* Set GPEX object properties for the virt machine */ 1089 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, 1090 ecam_base, NULL); 1091 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, 1092 ecam_size, NULL); 1093 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1094 PCI_HOST_BELOW_4G_MMIO_BASE, 1095 mmio_base, NULL); 1096 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, 1097 mmio_size, NULL); 1098 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1099 PCI_HOST_ABOVE_4G_MMIO_BASE, 1100 high_mmio_base, NULL); 1101 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1102 high_mmio_size, NULL); 1103 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, 1104 pio_base, NULL); 1105 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, 1106 pio_size, NULL); 1107 1108 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1109 1110 ecam_alias = g_new0(MemoryRegion, 1); 1111 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1112 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1113 ecam_reg, 0, ecam_size); 1114 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1115 1116 mmio_alias = g_new0(MemoryRegion, 1); 1117 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1118 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1119 mmio_reg, mmio_base, mmio_size); 1120 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1121 1122 /* Map high MMIO space */ 1123 high_mmio_alias = g_new0(MemoryRegion, 1); 1124 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1125 mmio_reg, high_mmio_base, high_mmio_size); 1126 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1127 high_mmio_alias); 1128 1129 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1130 1131 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1132 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1133 1134 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1135 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1136 } 1137 1138 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; 1139 return dev; 1140 } 1141 1142 static FWCfgState *create_fw_cfg(const MachineState *ms) 1143 { 1144 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1145 FWCfgState *fw_cfg; 1146 1147 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1148 &address_space_memory); 1149 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1150 1151 return fw_cfg; 1152 } 1153 1154 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1155 int base_hartid, int hart_count) 1156 { 1157 DeviceState *ret; 1158 char *plic_hart_config; 1159 1160 /* Per-socket PLIC hart topology configuration string */ 1161 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1162 1163 /* Per-socket PLIC */ 1164 ret = sifive_plic_create( 1165 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1166 plic_hart_config, hart_count, base_hartid, 1167 VIRT_IRQCHIP_NUM_SOURCES, 1168 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1169 VIRT_PLIC_PRIORITY_BASE, 1170 VIRT_PLIC_PENDING_BASE, 1171 VIRT_PLIC_ENABLE_BASE, 1172 VIRT_PLIC_ENABLE_STRIDE, 1173 VIRT_PLIC_CONTEXT_BASE, 1174 VIRT_PLIC_CONTEXT_STRIDE, 1175 memmap[VIRT_PLIC].size); 1176 1177 g_free(plic_hart_config); 1178 1179 return ret; 1180 } 1181 1182 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1183 const MemMapEntry *memmap, int socket, 1184 int base_hartid, int hart_count) 1185 { 1186 int i; 1187 hwaddr addr; 1188 uint32_t guest_bits; 1189 DeviceState *aplic_s = NULL; 1190 DeviceState *aplic_m = NULL; 1191 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1192 1193 if (msimode) { 1194 if (!kvm_enabled()) { 1195 /* Per-socket M-level IMSICs */ 1196 addr = memmap[VIRT_IMSIC_M].base + 1197 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1198 for (i = 0; i < hart_count; i++) { 1199 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1200 base_hartid + i, true, 1, 1201 VIRT_IRQCHIP_NUM_MSIS); 1202 } 1203 } 1204 1205 /* Per-socket S-level IMSICs */ 1206 guest_bits = imsic_num_bits(aia_guests + 1); 1207 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1208 for (i = 0; i < hart_count; i++) { 1209 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1210 base_hartid + i, false, 1 + aia_guests, 1211 VIRT_IRQCHIP_NUM_MSIS); 1212 } 1213 } 1214 1215 if (!kvm_enabled()) { 1216 /* Per-socket M-level APLIC */ 1217 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1218 socket * memmap[VIRT_APLIC_M].size, 1219 memmap[VIRT_APLIC_M].size, 1220 (msimode) ? 0 : base_hartid, 1221 (msimode) ? 0 : hart_count, 1222 VIRT_IRQCHIP_NUM_SOURCES, 1223 VIRT_IRQCHIP_NUM_PRIO_BITS, 1224 msimode, true, NULL); 1225 } 1226 1227 /* Per-socket S-level APLIC */ 1228 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1229 socket * memmap[VIRT_APLIC_S].size, 1230 memmap[VIRT_APLIC_S].size, 1231 (msimode) ? 0 : base_hartid, 1232 (msimode) ? 0 : hart_count, 1233 VIRT_IRQCHIP_NUM_SOURCES, 1234 VIRT_IRQCHIP_NUM_PRIO_BITS, 1235 msimode, false, aplic_m); 1236 1237 return kvm_enabled() ? aplic_s : aplic_m; 1238 } 1239 1240 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1241 { 1242 DeviceState *dev; 1243 SysBusDevice *sysbus; 1244 const MemMapEntry *memmap = virt_memmap; 1245 int i; 1246 MemoryRegion *sysmem = get_system_memory(); 1247 1248 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1249 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1250 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1251 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1252 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1253 s->platform_bus_dev = dev; 1254 1255 sysbus = SYS_BUS_DEVICE(dev); 1256 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1257 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1258 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1259 } 1260 1261 memory_region_add_subregion(sysmem, 1262 memmap[VIRT_PLATFORM_BUS].base, 1263 sysbus_mmio_get_region(sysbus, 0)); 1264 } 1265 1266 static void virt_machine_done(Notifier *notifier, void *data) 1267 { 1268 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1269 machine_done); 1270 const MemMapEntry *memmap = virt_memmap; 1271 MachineState *machine = MACHINE(s); 1272 target_ulong start_addr = memmap[VIRT_DRAM].base; 1273 target_ulong firmware_end_addr, kernel_start_addr; 1274 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1275 uint64_t fdt_load_addr; 1276 uint64_t kernel_entry = 0; 1277 BlockBackend *pflash_blk0; 1278 1279 /* 1280 * An user provided dtb must include everything, including 1281 * dynamic sysbus devices. Our FDT needs to be finalized. 1282 */ 1283 if (machine->dtb == NULL) { 1284 finalize_fdt(s); 1285 } 1286 1287 /* 1288 * Only direct boot kernel is currently supported for KVM VM, 1289 * so the "-bios" parameter is not supported when KVM is enabled. 1290 */ 1291 if (kvm_enabled()) { 1292 if (machine->firmware) { 1293 if (strcmp(machine->firmware, "none")) { 1294 error_report("Machine mode firmware is not supported in " 1295 "combination with KVM."); 1296 exit(1); 1297 } 1298 } else { 1299 machine->firmware = g_strdup("none"); 1300 } 1301 } 1302 1303 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1304 start_addr, NULL); 1305 1306 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1307 if (pflash_blk0) { 1308 if (machine->firmware && !strcmp(machine->firmware, "none") && 1309 !kvm_enabled()) { 1310 /* 1311 * Pflash was supplied but bios is none and not KVM guest, 1312 * let's overwrite the address we jump to after reset to 1313 * the base of the flash. 1314 */ 1315 start_addr = virt_memmap[VIRT_FLASH].base; 1316 } else { 1317 /* 1318 * Pflash was supplied but either KVM guest or bios is not none. 1319 * In this case, base of the flash would contain S-mode payload. 1320 */ 1321 riscv_setup_firmware_boot(machine); 1322 kernel_entry = virt_memmap[VIRT_FLASH].base; 1323 } 1324 } 1325 1326 if (machine->kernel_filename && !kernel_entry) { 1327 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1328 firmware_end_addr); 1329 1330 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1331 kernel_start_addr, true, NULL); 1332 } 1333 1334 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1335 memmap[VIRT_DRAM].size, 1336 machine); 1337 riscv_load_fdt(fdt_load_addr, machine->fdt); 1338 1339 /* load the reset vector */ 1340 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1341 virt_memmap[VIRT_MROM].base, 1342 virt_memmap[VIRT_MROM].size, kernel_entry, 1343 fdt_load_addr); 1344 1345 /* 1346 * Only direct boot kernel is currently supported for KVM VM, 1347 * So here setup kernel start address and fdt address. 1348 * TODO:Support firmware loading and integrate to TCG start 1349 */ 1350 if (kvm_enabled()) { 1351 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1352 } 1353 1354 if (virt_is_acpi_enabled(s)) { 1355 virt_acpi_setup(s); 1356 } 1357 } 1358 1359 static void virt_machine_init(MachineState *machine) 1360 { 1361 const MemMapEntry *memmap = virt_memmap; 1362 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1363 MemoryRegion *system_memory = get_system_memory(); 1364 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1365 char *soc_name; 1366 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1367 int i, base_hartid, hart_count; 1368 int socket_count = riscv_socket_count(machine); 1369 1370 /* Check socket count limit */ 1371 if (VIRT_SOCKETS_MAX < socket_count) { 1372 error_report("number of sockets/nodes should be less than %d", 1373 VIRT_SOCKETS_MAX); 1374 exit(1); 1375 } 1376 1377 if (!tcg_enabled() && s->have_aclint) { 1378 error_report("'aclint' is only available with TCG acceleration"); 1379 exit(1); 1380 } 1381 1382 /* Initialize sockets */ 1383 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1384 for (i = 0; i < socket_count; i++) { 1385 if (!riscv_socket_check_hartids(machine, i)) { 1386 error_report("discontinuous hartids in socket%d", i); 1387 exit(1); 1388 } 1389 1390 base_hartid = riscv_socket_first_hartid(machine, i); 1391 if (base_hartid < 0) { 1392 error_report("can't find hartid base for socket%d", i); 1393 exit(1); 1394 } 1395 1396 hart_count = riscv_socket_hart_count(machine, i); 1397 if (hart_count < 0) { 1398 error_report("can't find hart count for socket%d", i); 1399 exit(1); 1400 } 1401 1402 soc_name = g_strdup_printf("soc%d", i); 1403 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1404 TYPE_RISCV_HART_ARRAY); 1405 g_free(soc_name); 1406 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1407 machine->cpu_type, &error_abort); 1408 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1409 base_hartid, &error_abort); 1410 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1411 hart_count, &error_abort); 1412 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1413 1414 if (tcg_enabled()) { 1415 if (s->have_aclint) { 1416 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1417 /* Per-socket ACLINT MTIMER */ 1418 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1419 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1420 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1421 base_hartid, hart_count, 1422 RISCV_ACLINT_DEFAULT_MTIMECMP, 1423 RISCV_ACLINT_DEFAULT_MTIME, 1424 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1425 } else { 1426 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1427 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1428 i * memmap[VIRT_CLINT].size, 1429 base_hartid, hart_count, false); 1430 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1431 i * memmap[VIRT_CLINT].size + 1432 RISCV_ACLINT_SWI_SIZE, 1433 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1434 base_hartid, hart_count, 1435 RISCV_ACLINT_DEFAULT_MTIMECMP, 1436 RISCV_ACLINT_DEFAULT_MTIME, 1437 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1438 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1439 i * memmap[VIRT_ACLINT_SSWI].size, 1440 base_hartid, hart_count, true); 1441 } 1442 } else { 1443 /* Per-socket SiFive CLINT */ 1444 riscv_aclint_swi_create( 1445 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1446 base_hartid, hart_count, false); 1447 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1448 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1449 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1450 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1451 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1452 } 1453 } 1454 1455 /* Per-socket interrupt controller */ 1456 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1457 s->irqchip[i] = virt_create_plic(memmap, i, 1458 base_hartid, hart_count); 1459 } else { 1460 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1461 memmap, i, base_hartid, 1462 hart_count); 1463 } 1464 1465 /* Try to use different IRQCHIP instance based device type */ 1466 if (i == 0) { 1467 mmio_irqchip = s->irqchip[i]; 1468 virtio_irqchip = s->irqchip[i]; 1469 pcie_irqchip = s->irqchip[i]; 1470 } 1471 if (i == 1) { 1472 virtio_irqchip = s->irqchip[i]; 1473 pcie_irqchip = s->irqchip[i]; 1474 } 1475 if (i == 2) { 1476 pcie_irqchip = s->irqchip[i]; 1477 } 1478 } 1479 1480 if (kvm_enabled() && virt_use_kvm_aia(s)) { 1481 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1482 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1483 memmap[VIRT_APLIC_S].base, 1484 memmap[VIRT_IMSIC_S].base, 1485 s->aia_guests); 1486 } 1487 1488 if (riscv_is_32bit(&s->soc[0])) { 1489 #if HOST_LONG_BITS == 64 1490 /* limit RAM size in a 32-bit system */ 1491 if (machine->ram_size > 10 * GiB) { 1492 machine->ram_size = 10 * GiB; 1493 error_report("Limiting RAM size to 10 GiB"); 1494 } 1495 #endif 1496 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1497 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1498 } else { 1499 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1500 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1501 virt_high_pcie_memmap.base = 1502 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1503 } 1504 1505 s->memmap = virt_memmap; 1506 1507 /* register system main memory (actual RAM) */ 1508 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1509 machine->ram); 1510 1511 /* boot rom */ 1512 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1513 memmap[VIRT_MROM].size, &error_fatal); 1514 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1515 mask_rom); 1516 1517 /* 1518 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1519 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1520 */ 1521 s->fw_cfg = create_fw_cfg(machine); 1522 rom_set_fw(s->fw_cfg); 1523 1524 /* SiFive Test MMIO device */ 1525 sifive_test_create(memmap[VIRT_TEST].base); 1526 1527 /* VirtIO MMIO devices */ 1528 for (i = 0; i < VIRTIO_COUNT; i++) { 1529 sysbus_create_simple("virtio-mmio", 1530 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1531 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1532 } 1533 1534 gpex_pcie_init(system_memory, pcie_irqchip, s); 1535 1536 create_platform_bus(s, mmio_irqchip); 1537 1538 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1539 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1540 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1541 1542 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1543 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1544 1545 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1546 /* Map legacy -drive if=pflash to machine properties */ 1547 pflash_cfi01_legacy_drive(s->flash[i], 1548 drive_get(IF_PFLASH, 0, i)); 1549 } 1550 virt_flash_map(s, system_memory); 1551 1552 /* load/create device tree */ 1553 if (machine->dtb) { 1554 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1555 if (!machine->fdt) { 1556 error_report("load_device_tree() failed"); 1557 exit(1); 1558 } 1559 } else { 1560 create_fdt(s, memmap); 1561 } 1562 1563 s->machine_done.notify = virt_machine_done; 1564 qemu_add_machine_init_done_notifier(&s->machine_done); 1565 } 1566 1567 static void virt_machine_instance_init(Object *obj) 1568 { 1569 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1570 1571 virt_flash_create(s); 1572 1573 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1574 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1575 s->acpi = ON_OFF_AUTO_AUTO; 1576 } 1577 1578 static char *virt_get_aia_guests(Object *obj, Error **errp) 1579 { 1580 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1581 char val[32]; 1582 1583 sprintf(val, "%d", s->aia_guests); 1584 return g_strdup(val); 1585 } 1586 1587 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1588 { 1589 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1590 1591 s->aia_guests = atoi(val); 1592 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1593 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1594 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1595 VIRT_IRQCHIP_MAX_GUESTS); 1596 } 1597 } 1598 1599 static char *virt_get_aia(Object *obj, Error **errp) 1600 { 1601 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1602 const char *val; 1603 1604 switch (s->aia_type) { 1605 case VIRT_AIA_TYPE_APLIC: 1606 val = "aplic"; 1607 break; 1608 case VIRT_AIA_TYPE_APLIC_IMSIC: 1609 val = "aplic-imsic"; 1610 break; 1611 default: 1612 val = "none"; 1613 break; 1614 }; 1615 1616 return g_strdup(val); 1617 } 1618 1619 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1620 { 1621 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1622 1623 if (!strcmp(val, "none")) { 1624 s->aia_type = VIRT_AIA_TYPE_NONE; 1625 } else if (!strcmp(val, "aplic")) { 1626 s->aia_type = VIRT_AIA_TYPE_APLIC; 1627 } else if (!strcmp(val, "aplic-imsic")) { 1628 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1629 } else { 1630 error_setg(errp, "Invalid AIA interrupt controller type"); 1631 error_append_hint(errp, "Valid values are none, aplic, and " 1632 "aplic-imsic.\n"); 1633 } 1634 } 1635 1636 static bool virt_get_aclint(Object *obj, Error **errp) 1637 { 1638 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1639 1640 return s->have_aclint; 1641 } 1642 1643 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1644 { 1645 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1646 1647 s->have_aclint = value; 1648 } 1649 1650 bool virt_is_acpi_enabled(RISCVVirtState *s) 1651 { 1652 return s->acpi != ON_OFF_AUTO_OFF; 1653 } 1654 1655 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1656 void *opaque, Error **errp) 1657 { 1658 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1659 OnOffAuto acpi = s->acpi; 1660 1661 visit_type_OnOffAuto(v, name, &acpi, errp); 1662 } 1663 1664 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1665 void *opaque, Error **errp) 1666 { 1667 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1668 1669 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1670 } 1671 1672 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1673 DeviceState *dev) 1674 { 1675 MachineClass *mc = MACHINE_GET_CLASS(machine); 1676 1677 if (device_is_dynamic_sysbus(mc, dev)) { 1678 return HOTPLUG_HANDLER(machine); 1679 } 1680 return NULL; 1681 } 1682 1683 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1684 DeviceState *dev, Error **errp) 1685 { 1686 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1687 1688 if (s->platform_bus_dev) { 1689 MachineClass *mc = MACHINE_GET_CLASS(s); 1690 1691 if (device_is_dynamic_sysbus(mc, dev)) { 1692 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1693 SYS_BUS_DEVICE(dev)); 1694 } 1695 } 1696 } 1697 1698 static void virt_machine_class_init(ObjectClass *oc, void *data) 1699 { 1700 char str[128]; 1701 MachineClass *mc = MACHINE_CLASS(oc); 1702 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1703 1704 mc->desc = "RISC-V VirtIO board"; 1705 mc->init = virt_machine_init; 1706 mc->max_cpus = VIRT_CPUS_MAX; 1707 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1708 mc->pci_allow_0_address = true; 1709 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1710 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1711 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1712 mc->numa_mem_supported = true; 1713 /* platform instead of architectural choice */ 1714 mc->cpu_cluster_has_numa_boundary = true; 1715 mc->default_ram_id = "riscv_virt_board.ram"; 1716 assert(!mc->get_hotplug_handler); 1717 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1718 1719 hc->plug = virt_machine_device_plug_cb; 1720 1721 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1722 #ifdef CONFIG_TPM 1723 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1724 #endif 1725 1726 1727 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1728 virt_set_aclint); 1729 object_class_property_set_description(oc, "aclint", 1730 "(TCG only) Set on/off to " 1731 "enable/disable emulating " 1732 "ACLINT devices"); 1733 1734 object_class_property_add_str(oc, "aia", virt_get_aia, 1735 virt_set_aia); 1736 object_class_property_set_description(oc, "aia", 1737 "Set type of AIA interrupt " 1738 "controller. Valid values are " 1739 "none, aplic, and aplic-imsic."); 1740 1741 object_class_property_add_str(oc, "aia-guests", 1742 virt_get_aia_guests, 1743 virt_set_aia_guests); 1744 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1745 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1746 object_class_property_set_description(oc, "aia-guests", str); 1747 object_class_property_add(oc, "acpi", "OnOffAuto", 1748 virt_get_acpi, virt_set_acpi, 1749 NULL, NULL); 1750 object_class_property_set_description(oc, "acpi", 1751 "Enable ACPI"); 1752 } 1753 1754 static const TypeInfo virt_machine_typeinfo = { 1755 .name = MACHINE_TYPE_NAME("virt"), 1756 .parent = TYPE_MACHINE, 1757 .class_init = virt_machine_class_init, 1758 .instance_init = virt_machine_instance_init, 1759 .instance_size = sizeof(RISCVVirtState), 1760 .interfaces = (InterfaceInfo[]) { 1761 { TYPE_HOTPLUG_HANDLER }, 1762 { } 1763 }, 1764 }; 1765 1766 static void virt_machine_init_register_types(void) 1767 { 1768 type_register_static(&virt_machine_typeinfo); 1769 } 1770 1771 type_init(virt_machine_init_register_types) 1772