1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "kvm/kvm_riscv.h" 39 #include "hw/firmware/smbios.h" 40 #include "hw/intc/riscv_aclint.h" 41 #include "hw/intc/riscv_aplic.h" 42 #include "hw/intc/sifive_plic.h" 43 #include "hw/misc/sifive_test.h" 44 #include "hw/platform-bus.h" 45 #include "chardev/char.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/sysemu.h" 48 #include "sysemu/tcg.h" 49 #include "sysemu/kvm.h" 50 #include "sysemu/tpm.h" 51 #include "sysemu/qtest.h" 52 #include "hw/pci/pci.h" 53 #include "hw/pci-host/gpex.h" 54 #include "hw/display/ramfb.h" 55 #include "hw/acpi/aml-build.h" 56 #include "qapi/qapi-visit-common.h" 57 #include "hw/virtio/virtio-iommu.h" 58 59 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 60 static bool virt_use_kvm_aia(RISCVVirtState *s) 61 { 62 return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 63 } 64 65 static bool virt_aclint_allowed(void) 66 { 67 return tcg_enabled() || qtest_enabled(); 68 } 69 70 static const MemMapEntry virt_memmap[] = { 71 [VIRT_DEBUG] = { 0x0, 0x100 }, 72 [VIRT_MROM] = { 0x1000, 0xf000 }, 73 [VIRT_TEST] = { 0x100000, 0x1000 }, 74 [VIRT_RTC] = { 0x101000, 0x1000 }, 75 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 76 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 77 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 78 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 79 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 80 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 81 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 82 [VIRT_UART0] = { 0x10000000, 0x100 }, 83 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 84 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 85 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 86 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 87 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 88 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 89 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 90 [VIRT_DRAM] = { 0x80000000, 0x0 }, 91 }; 92 93 /* PCIe high mmio is fixed for RV32 */ 94 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 95 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 96 97 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 98 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 99 100 static MemMapEntry virt_high_pcie_memmap; 101 102 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 103 104 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 105 const char *name, 106 const char *alias_prop_name) 107 { 108 /* 109 * Create a single flash device. We use the same parameters as 110 * the flash devices on the ARM virt board. 111 */ 112 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 113 114 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 115 qdev_prop_set_uint8(dev, "width", 4); 116 qdev_prop_set_uint8(dev, "device-width", 2); 117 qdev_prop_set_bit(dev, "big-endian", false); 118 qdev_prop_set_uint16(dev, "id0", 0x89); 119 qdev_prop_set_uint16(dev, "id1", 0x18); 120 qdev_prop_set_uint16(dev, "id2", 0x00); 121 qdev_prop_set_uint16(dev, "id3", 0x00); 122 qdev_prop_set_string(dev, "name", name); 123 124 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 125 object_property_add_alias(OBJECT(s), alias_prop_name, 126 OBJECT(dev), "drive"); 127 128 return PFLASH_CFI01(dev); 129 } 130 131 static void virt_flash_create(RISCVVirtState *s) 132 { 133 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 134 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 135 } 136 137 static void virt_flash_map1(PFlashCFI01 *flash, 138 hwaddr base, hwaddr size, 139 MemoryRegion *sysmem) 140 { 141 DeviceState *dev = DEVICE(flash); 142 143 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 144 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 145 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 146 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 147 148 memory_region_add_subregion(sysmem, base, 149 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 150 0)); 151 } 152 153 static void virt_flash_map(RISCVVirtState *s, 154 MemoryRegion *sysmem) 155 { 156 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 157 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 158 159 virt_flash_map1(s->flash[0], flashbase, flashsize, 160 sysmem); 161 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 162 sysmem); 163 } 164 165 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 166 uint32_t irqchip_phandle) 167 { 168 int pin, dev; 169 uint32_t irq_map_stride = 0; 170 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 171 FDT_MAX_INT_MAP_WIDTH] = {}; 172 uint32_t *irq_map = full_irq_map; 173 174 /* This code creates a standard swizzle of interrupts such that 175 * each device's first interrupt is based on it's PCI_SLOT number. 176 * (See pci_swizzle_map_irq_fn()) 177 * 178 * We only need one entry per interrupt in the table (not one per 179 * possible slot) seeing the interrupt-map-mask will allow the table 180 * to wrap to any number of devices. 181 */ 182 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 183 int devfn = dev * 0x8; 184 185 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 186 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 187 int i = 0; 188 189 /* Fill PCI address cells */ 190 irq_map[i] = cpu_to_be32(devfn << 8); 191 i += FDT_PCI_ADDR_CELLS; 192 193 /* Fill PCI Interrupt cells */ 194 irq_map[i] = cpu_to_be32(pin + 1); 195 i += FDT_PCI_INT_CELLS; 196 197 /* Fill interrupt controller phandle and cells */ 198 irq_map[i++] = cpu_to_be32(irqchip_phandle); 199 irq_map[i++] = cpu_to_be32(irq_nr); 200 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 201 irq_map[i++] = cpu_to_be32(0x4); 202 } 203 204 if (!irq_map_stride) { 205 irq_map_stride = i; 206 } 207 irq_map += irq_map_stride; 208 } 209 } 210 211 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 212 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 213 irq_map_stride * sizeof(uint32_t)); 214 215 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 216 0x1800, 0, 0, 0x7); 217 } 218 219 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 220 char *clust_name, uint32_t *phandle, 221 uint32_t *intc_phandles) 222 { 223 int cpu; 224 uint32_t cpu_phandle; 225 MachineState *ms = MACHINE(s); 226 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 227 uint8_t satp_mode_max; 228 229 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 230 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 231 g_autofree char *cpu_name = NULL; 232 g_autofree char *core_name = NULL; 233 g_autofree char *intc_name = NULL; 234 g_autofree char *sv_name = NULL; 235 236 cpu_phandle = (*phandle)++; 237 238 cpu_name = g_strdup_printf("/cpus/cpu@%d", 239 s->soc[socket].hartid_base + cpu); 240 qemu_fdt_add_subnode(ms->fdt, cpu_name); 241 242 if (cpu_ptr->cfg.satp_mode.supported != 0) { 243 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 244 sv_name = g_strdup_printf("riscv,%s", 245 satp_mode_str(satp_mode_max, is_32_bit)); 246 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 247 } 248 249 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); 250 251 if (cpu_ptr->cfg.ext_zicbom) { 252 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 253 cpu_ptr->cfg.cbom_blocksize); 254 } 255 256 if (cpu_ptr->cfg.ext_zicboz) { 257 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 258 cpu_ptr->cfg.cboz_blocksize); 259 } 260 261 if (cpu_ptr->cfg.ext_zicbop) { 262 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 263 cpu_ptr->cfg.cbop_blocksize); 264 } 265 266 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 267 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 268 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 269 s->soc[socket].hartid_base + cpu); 270 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 271 riscv_socket_fdt_write_id(ms, cpu_name, socket); 272 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 273 274 intc_phandles[cpu] = (*phandle)++; 275 276 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 277 qemu_fdt_add_subnode(ms->fdt, intc_name); 278 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 279 intc_phandles[cpu]); 280 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 281 "riscv,cpu-intc"); 282 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 283 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 284 285 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 286 qemu_fdt_add_subnode(ms->fdt, core_name); 287 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 288 } 289 } 290 291 static void create_fdt_socket_memory(RISCVVirtState *s, 292 const MemMapEntry *memmap, int socket) 293 { 294 g_autofree char *mem_name = NULL; 295 uint64_t addr, size; 296 MachineState *ms = MACHINE(s); 297 298 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 299 size = riscv_socket_mem_size(ms, socket); 300 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 301 qemu_fdt_add_subnode(ms->fdt, mem_name); 302 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 303 addr >> 32, addr, size >> 32, size); 304 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 305 riscv_socket_fdt_write_id(ms, mem_name, socket); 306 } 307 308 static void create_fdt_socket_clint(RISCVVirtState *s, 309 const MemMapEntry *memmap, int socket, 310 uint32_t *intc_phandles) 311 { 312 int cpu; 313 g_autofree char *clint_name = NULL; 314 g_autofree uint32_t *clint_cells = NULL; 315 unsigned long clint_addr; 316 MachineState *ms = MACHINE(s); 317 static const char * const clint_compat[2] = { 318 "sifive,clint0", "riscv,clint0" 319 }; 320 321 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 322 323 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 324 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 325 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 326 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 327 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 328 } 329 330 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 331 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 332 qemu_fdt_add_subnode(ms->fdt, clint_name); 333 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 334 (char **)&clint_compat, 335 ARRAY_SIZE(clint_compat)); 336 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 337 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 338 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 339 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 340 riscv_socket_fdt_write_id(ms, clint_name, socket); 341 } 342 343 static void create_fdt_socket_aclint(RISCVVirtState *s, 344 const MemMapEntry *memmap, int socket, 345 uint32_t *intc_phandles) 346 { 347 int cpu; 348 char *name; 349 unsigned long addr, size; 350 uint32_t aclint_cells_size; 351 g_autofree uint32_t *aclint_mswi_cells = NULL; 352 g_autofree uint32_t *aclint_sswi_cells = NULL; 353 g_autofree uint32_t *aclint_mtimer_cells = NULL; 354 MachineState *ms = MACHINE(s); 355 356 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 357 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 358 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 359 360 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 361 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 362 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 363 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 364 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 365 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 366 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 367 } 368 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 369 370 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 371 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 372 name = g_strdup_printf("/soc/mswi@%lx", addr); 373 qemu_fdt_add_subnode(ms->fdt, name); 374 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 375 "riscv,aclint-mswi"); 376 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 377 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 378 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 379 aclint_mswi_cells, aclint_cells_size); 380 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 381 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 382 riscv_socket_fdt_write_id(ms, name, socket); 383 g_free(name); 384 } 385 386 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 387 addr = memmap[VIRT_CLINT].base + 388 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 389 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 390 } else { 391 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 392 (memmap[VIRT_CLINT].size * socket); 393 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 394 } 395 name = g_strdup_printf("/soc/mtimer@%lx", addr); 396 qemu_fdt_add_subnode(ms->fdt, name); 397 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 398 "riscv,aclint-mtimer"); 399 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 400 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 401 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 402 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 403 0x0, RISCV_ACLINT_DEFAULT_MTIME); 404 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 405 aclint_mtimer_cells, aclint_cells_size); 406 riscv_socket_fdt_write_id(ms, name, socket); 407 g_free(name); 408 409 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 410 addr = memmap[VIRT_ACLINT_SSWI].base + 411 (memmap[VIRT_ACLINT_SSWI].size * socket); 412 name = g_strdup_printf("/soc/sswi@%lx", addr); 413 qemu_fdt_add_subnode(ms->fdt, name); 414 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 415 "riscv,aclint-sswi"); 416 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 417 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 418 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 419 aclint_sswi_cells, aclint_cells_size); 420 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 421 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 422 riscv_socket_fdt_write_id(ms, name, socket); 423 g_free(name); 424 } 425 } 426 427 static void create_fdt_socket_plic(RISCVVirtState *s, 428 const MemMapEntry *memmap, int socket, 429 uint32_t *phandle, uint32_t *intc_phandles, 430 uint32_t *plic_phandles) 431 { 432 int cpu; 433 g_autofree char *plic_name = NULL; 434 g_autofree uint32_t *plic_cells; 435 unsigned long plic_addr; 436 MachineState *ms = MACHINE(s); 437 static const char * const plic_compat[2] = { 438 "sifive,plic-1.0.0", "riscv,plic0" 439 }; 440 441 plic_phandles[socket] = (*phandle)++; 442 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 443 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 444 qemu_fdt_add_subnode(ms->fdt, plic_name); 445 qemu_fdt_setprop_cell(ms->fdt, plic_name, 446 "#interrupt-cells", FDT_PLIC_INT_CELLS); 447 qemu_fdt_setprop_cell(ms->fdt, plic_name, 448 "#address-cells", FDT_PLIC_ADDR_CELLS); 449 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 450 (char **)&plic_compat, 451 ARRAY_SIZE(plic_compat)); 452 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 453 454 if (kvm_enabled()) { 455 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 456 457 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 458 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 459 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 460 } 461 462 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 463 plic_cells, 464 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 465 } else { 466 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 467 468 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 469 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 470 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 471 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 472 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 473 } 474 475 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 476 plic_cells, 477 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 478 } 479 480 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 481 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 482 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 483 VIRT_IRQCHIP_NUM_SOURCES - 1); 484 riscv_socket_fdt_write_id(ms, plic_name, socket); 485 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 486 plic_phandles[socket]); 487 488 if (!socket) { 489 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 490 memmap[VIRT_PLATFORM_BUS].base, 491 memmap[VIRT_PLATFORM_BUS].size, 492 VIRT_PLATFORM_BUS_IRQ); 493 } 494 } 495 496 uint32_t imsic_num_bits(uint32_t count) 497 { 498 uint32_t ret = 0; 499 500 while (BIT(ret) < count) { 501 ret++; 502 } 503 504 return ret; 505 } 506 507 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 508 uint32_t *intc_phandles, uint32_t msi_phandle, 509 bool m_mode, uint32_t imsic_guest_bits) 510 { 511 int cpu, socket; 512 g_autofree char *imsic_name = NULL; 513 MachineState *ms = MACHINE(s); 514 int socket_count = riscv_socket_count(ms); 515 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 516 g_autofree uint32_t *imsic_cells = NULL; 517 g_autofree uint32_t *imsic_regs = NULL; 518 519 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 520 imsic_regs = g_new0(uint32_t, socket_count * 4); 521 522 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 523 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 524 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 525 } 526 527 imsic_max_hart_per_socket = 0; 528 for (socket = 0; socket < socket_count; socket++) { 529 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 530 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 531 s->soc[socket].num_harts; 532 imsic_regs[socket * 4 + 0] = 0; 533 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 534 imsic_regs[socket * 4 + 2] = 0; 535 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 536 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 537 imsic_max_hart_per_socket = s->soc[socket].num_harts; 538 } 539 } 540 541 imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr); 542 qemu_fdt_add_subnode(ms->fdt, imsic_name); 543 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); 544 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 545 FDT_IMSIC_INT_CELLS); 546 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 547 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 548 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 549 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 550 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 551 socket_count * sizeof(uint32_t) * 4); 552 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 553 VIRT_IRQCHIP_NUM_MSIS); 554 555 if (imsic_guest_bits) { 556 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 557 imsic_guest_bits); 558 } 559 560 if (socket_count > 1) { 561 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 562 imsic_num_bits(imsic_max_hart_per_socket)); 563 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 564 imsic_num_bits(socket_count)); 565 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 566 IMSIC_MMIO_GROUP_MIN_SHIFT); 567 } 568 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 569 } 570 571 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 572 uint32_t *phandle, uint32_t *intc_phandles, 573 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 574 { 575 *msi_m_phandle = (*phandle)++; 576 *msi_s_phandle = (*phandle)++; 577 578 if (!kvm_enabled()) { 579 /* M-level IMSIC node */ 580 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 581 *msi_m_phandle, true, 0); 582 } 583 584 /* S-level IMSIC node */ 585 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 586 *msi_s_phandle, false, 587 imsic_num_bits(s->aia_guests + 1)); 588 589 } 590 591 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 592 unsigned long aplic_addr, uint32_t aplic_size, 593 uint32_t msi_phandle, 594 uint32_t *intc_phandles, 595 uint32_t aplic_phandle, 596 uint32_t aplic_child_phandle, 597 bool m_mode, int num_harts) 598 { 599 int cpu; 600 g_autofree char *aplic_name = NULL; 601 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 602 MachineState *ms = MACHINE(s); 603 604 for (cpu = 0; cpu < num_harts; cpu++) { 605 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 606 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 607 } 608 609 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 610 qemu_fdt_add_subnode(ms->fdt, aplic_name); 611 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); 612 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 613 "#interrupt-cells", FDT_APLIC_INT_CELLS); 614 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 615 616 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 617 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 618 aplic_cells, num_harts * sizeof(uint32_t) * 2); 619 } else { 620 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 621 } 622 623 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 624 0x0, aplic_addr, 0x0, aplic_size); 625 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 626 VIRT_IRQCHIP_NUM_SOURCES); 627 628 if (aplic_child_phandle) { 629 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 630 aplic_child_phandle); 631 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 632 aplic_child_phandle, 0x1, 633 VIRT_IRQCHIP_NUM_SOURCES); 634 } 635 636 riscv_socket_fdt_write_id(ms, aplic_name, socket); 637 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 638 } 639 640 static void create_fdt_socket_aplic(RISCVVirtState *s, 641 const MemMapEntry *memmap, int socket, 642 uint32_t msi_m_phandle, 643 uint32_t msi_s_phandle, 644 uint32_t *phandle, 645 uint32_t *intc_phandles, 646 uint32_t *aplic_phandles, 647 int num_harts) 648 { 649 g_autofree char *aplic_name = NULL; 650 unsigned long aplic_addr; 651 MachineState *ms = MACHINE(s); 652 uint32_t aplic_m_phandle, aplic_s_phandle; 653 654 aplic_m_phandle = (*phandle)++; 655 aplic_s_phandle = (*phandle)++; 656 657 if (!kvm_enabled()) { 658 /* M-level APLIC node */ 659 aplic_addr = memmap[VIRT_APLIC_M].base + 660 (memmap[VIRT_APLIC_M].size * socket); 661 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 662 msi_m_phandle, intc_phandles, 663 aplic_m_phandle, aplic_s_phandle, 664 true, num_harts); 665 } 666 667 /* S-level APLIC node */ 668 aplic_addr = memmap[VIRT_APLIC_S].base + 669 (memmap[VIRT_APLIC_S].size * socket); 670 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 671 msi_s_phandle, intc_phandles, 672 aplic_s_phandle, 0, 673 false, num_harts); 674 675 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 676 677 if (!socket) { 678 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 679 memmap[VIRT_PLATFORM_BUS].base, 680 memmap[VIRT_PLATFORM_BUS].size, 681 VIRT_PLATFORM_BUS_IRQ); 682 } 683 684 aplic_phandles[socket] = aplic_s_phandle; 685 } 686 687 static void create_fdt_pmu(RISCVVirtState *s) 688 { 689 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 690 MachineState *ms = MACHINE(s); 691 RISCVCPU hart = s->soc[0].harts[0]; 692 693 qemu_fdt_add_subnode(ms->fdt, pmu_name); 694 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 695 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 696 } 697 698 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 699 uint32_t *phandle, 700 uint32_t *irq_mmio_phandle, 701 uint32_t *irq_pcie_phandle, 702 uint32_t *irq_virtio_phandle, 703 uint32_t *msi_pcie_phandle) 704 { 705 int socket, phandle_pos; 706 MachineState *ms = MACHINE(s); 707 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 708 uint32_t xplic_phandles[MAX_NODES]; 709 g_autofree uint32_t *intc_phandles = NULL; 710 int socket_count = riscv_socket_count(ms); 711 712 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 713 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 714 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 715 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 716 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 717 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 718 719 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 720 721 phandle_pos = ms->smp.cpus; 722 for (socket = (socket_count - 1); socket >= 0; socket--) { 723 g_autofree char *clust_name = NULL; 724 phandle_pos -= s->soc[socket].num_harts; 725 726 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 727 qemu_fdt_add_subnode(ms->fdt, clust_name); 728 729 create_fdt_socket_cpus(s, socket, clust_name, phandle, 730 &intc_phandles[phandle_pos]); 731 732 create_fdt_socket_memory(s, memmap, socket); 733 734 if (virt_aclint_allowed() && s->have_aclint) { 735 create_fdt_socket_aclint(s, memmap, socket, 736 &intc_phandles[phandle_pos]); 737 } else if (tcg_enabled()) { 738 create_fdt_socket_clint(s, memmap, socket, 739 &intc_phandles[phandle_pos]); 740 } 741 } 742 743 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 744 create_fdt_imsic(s, memmap, phandle, intc_phandles, 745 &msi_m_phandle, &msi_s_phandle); 746 *msi_pcie_phandle = msi_s_phandle; 747 } 748 749 /* KVM AIA only has one APLIC instance */ 750 if (kvm_enabled() && virt_use_kvm_aia(s)) { 751 create_fdt_socket_aplic(s, memmap, 0, 752 msi_m_phandle, msi_s_phandle, phandle, 753 &intc_phandles[0], xplic_phandles, 754 ms->smp.cpus); 755 } else { 756 phandle_pos = ms->smp.cpus; 757 for (socket = (socket_count - 1); socket >= 0; socket--) { 758 phandle_pos -= s->soc[socket].num_harts; 759 760 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 761 create_fdt_socket_plic(s, memmap, socket, phandle, 762 &intc_phandles[phandle_pos], 763 xplic_phandles); 764 } else { 765 create_fdt_socket_aplic(s, memmap, socket, 766 msi_m_phandle, msi_s_phandle, phandle, 767 &intc_phandles[phandle_pos], 768 xplic_phandles, 769 s->soc[socket].num_harts); 770 } 771 } 772 } 773 774 if (kvm_enabled() && virt_use_kvm_aia(s)) { 775 *irq_mmio_phandle = xplic_phandles[0]; 776 *irq_virtio_phandle = xplic_phandles[0]; 777 *irq_pcie_phandle = xplic_phandles[0]; 778 } else { 779 for (socket = 0; socket < socket_count; socket++) { 780 if (socket == 0) { 781 *irq_mmio_phandle = xplic_phandles[socket]; 782 *irq_virtio_phandle = xplic_phandles[socket]; 783 *irq_pcie_phandle = xplic_phandles[socket]; 784 } 785 if (socket == 1) { 786 *irq_virtio_phandle = xplic_phandles[socket]; 787 *irq_pcie_phandle = xplic_phandles[socket]; 788 } 789 if (socket == 2) { 790 *irq_pcie_phandle = xplic_phandles[socket]; 791 } 792 } 793 } 794 795 riscv_socket_fdt_write_distance_matrix(ms); 796 } 797 798 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 799 uint32_t irq_virtio_phandle) 800 { 801 int i; 802 MachineState *ms = MACHINE(s); 803 804 for (i = 0; i < VIRTIO_COUNT; i++) { 805 g_autofree char *name = g_strdup_printf("/soc/virtio_mmio@%lx", 806 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 807 808 qemu_fdt_add_subnode(ms->fdt, name); 809 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 810 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 811 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 812 0x0, memmap[VIRT_VIRTIO].size); 813 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 814 irq_virtio_phandle); 815 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 816 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 817 VIRTIO_IRQ + i); 818 } else { 819 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 820 VIRTIO_IRQ + i, 0x4); 821 } 822 } 823 } 824 825 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 826 uint32_t irq_pcie_phandle, 827 uint32_t msi_pcie_phandle) 828 { 829 g_autofree char *name = NULL; 830 MachineState *ms = MACHINE(s); 831 832 name = g_strdup_printf("/soc/pci@%lx", 833 (long) memmap[VIRT_PCIE_ECAM].base); 834 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 835 FDT_PCI_ADDR_CELLS); 836 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 837 FDT_PCI_INT_CELLS); 838 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 839 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 840 "pci-host-ecam-generic"); 841 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 842 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 843 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 844 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 845 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 846 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 847 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 848 } 849 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 850 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 851 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 852 1, FDT_PCI_RANGE_IOPORT, 2, 0, 853 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 854 1, FDT_PCI_RANGE_MMIO, 855 2, memmap[VIRT_PCIE_MMIO].base, 856 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 857 1, FDT_PCI_RANGE_MMIO_64BIT, 858 2, virt_high_pcie_memmap.base, 859 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 860 861 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 862 } 863 864 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 865 uint32_t *phandle) 866 { 867 char *name; 868 uint32_t test_phandle; 869 MachineState *ms = MACHINE(s); 870 871 test_phandle = (*phandle)++; 872 name = g_strdup_printf("/soc/test@%lx", 873 (long)memmap[VIRT_TEST].base); 874 qemu_fdt_add_subnode(ms->fdt, name); 875 { 876 static const char * const compat[3] = { 877 "sifive,test1", "sifive,test0", "syscon" 878 }; 879 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 880 (char **)&compat, ARRAY_SIZE(compat)); 881 } 882 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 883 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 884 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 885 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 886 g_free(name); 887 888 name = g_strdup_printf("/reboot"); 889 qemu_fdt_add_subnode(ms->fdt, name); 890 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 891 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 892 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 893 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 894 g_free(name); 895 896 name = g_strdup_printf("/poweroff"); 897 qemu_fdt_add_subnode(ms->fdt, name); 898 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 899 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 900 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 901 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 902 g_free(name); 903 } 904 905 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 906 uint32_t irq_mmio_phandle) 907 { 908 g_autofree char *name = NULL; 909 MachineState *ms = MACHINE(s); 910 911 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 912 qemu_fdt_add_subnode(ms->fdt, name); 913 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 914 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 915 0x0, memmap[VIRT_UART0].base, 916 0x0, memmap[VIRT_UART0].size); 917 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 918 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 919 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 920 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 921 } else { 922 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 923 } 924 925 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 926 } 927 928 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 929 uint32_t irq_mmio_phandle) 930 { 931 g_autofree char *name = NULL; 932 MachineState *ms = MACHINE(s); 933 934 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 935 qemu_fdt_add_subnode(ms->fdt, name); 936 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 937 "google,goldfish-rtc"); 938 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 939 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 940 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 941 irq_mmio_phandle); 942 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 943 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 944 } else { 945 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 946 } 947 } 948 949 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 950 { 951 MachineState *ms = MACHINE(s); 952 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 953 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 954 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 955 956 qemu_fdt_add_subnode(ms->fdt, name); 957 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 958 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 959 2, flashbase, 2, flashsize, 960 2, flashbase + flashsize, 2, flashsize); 961 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 962 } 963 964 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 965 { 966 MachineState *ms = MACHINE(s); 967 hwaddr base = memmap[VIRT_FW_CFG].base; 968 hwaddr size = memmap[VIRT_FW_CFG].size; 969 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 970 971 qemu_fdt_add_subnode(ms->fdt, nodename); 972 qemu_fdt_setprop_string(ms->fdt, nodename, 973 "compatible", "qemu,fw-cfg-mmio"); 974 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 975 2, base, 2, size); 976 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 977 } 978 979 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) 980 { 981 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 982 void *fdt = MACHINE(s)->fdt; 983 uint32_t iommu_phandle; 984 g_autofree char *iommu_node = NULL; 985 g_autofree char *pci_node = NULL; 986 987 pci_node = g_strdup_printf("/soc/pci@%lx", 988 (long) virt_memmap[VIRT_PCIE_ECAM].base); 989 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, 990 PCI_SLOT(bdf), PCI_FUNC(bdf)); 991 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 992 993 qemu_fdt_add_subnode(fdt, iommu_node); 994 995 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat)); 996 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 997 1, bdf << 8, 1, 0, 1, 0, 998 1, 0, 1, 0); 999 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1000 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1001 1002 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1003 0, iommu_phandle, 0, bdf, 1004 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1005 } 1006 1007 static void finalize_fdt(RISCVVirtState *s) 1008 { 1009 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1010 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1011 1012 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 1013 &irq_pcie_phandle, &irq_virtio_phandle, 1014 &msi_pcie_phandle); 1015 1016 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 1017 1018 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); 1019 1020 create_fdt_reset(s, virt_memmap, &phandle); 1021 1022 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 1023 1024 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 1025 } 1026 1027 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1028 { 1029 MachineState *ms = MACHINE(s); 1030 uint8_t rng_seed[32]; 1031 g_autofree char *name = NULL; 1032 1033 ms->fdt = create_device_tree(&s->fdt_size); 1034 if (!ms->fdt) { 1035 error_report("create_device_tree() failed"); 1036 exit(1); 1037 } 1038 1039 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1040 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1041 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1042 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1043 1044 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1045 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1046 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1047 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1048 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1049 1050 /* 1051 * The "/soc/pci@..." node is needed for PCIE hotplugs 1052 * that might happen before finalize_fdt(). 1053 */ 1054 name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); 1055 qemu_fdt_add_subnode(ms->fdt, name); 1056 1057 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1058 1059 /* Pass seed to RNG */ 1060 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1061 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1062 rng_seed, sizeof(rng_seed)); 1063 1064 create_fdt_flash(s, memmap); 1065 create_fdt_fw_cfg(s, memmap); 1066 create_fdt_pmu(s); 1067 } 1068 1069 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1070 DeviceState *irqchip, 1071 RISCVVirtState *s) 1072 { 1073 DeviceState *dev; 1074 MemoryRegion *ecam_alias, *ecam_reg; 1075 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1076 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1077 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1078 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1079 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1080 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1081 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1082 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1083 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1084 qemu_irq irq; 1085 int i; 1086 1087 dev = qdev_new(TYPE_GPEX_HOST); 1088 1089 /* Set GPEX object properties for the virt machine */ 1090 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, 1091 ecam_base, NULL); 1092 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, 1093 ecam_size, NULL); 1094 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1095 PCI_HOST_BELOW_4G_MMIO_BASE, 1096 mmio_base, NULL); 1097 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, 1098 mmio_size, NULL); 1099 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1100 PCI_HOST_ABOVE_4G_MMIO_BASE, 1101 high_mmio_base, NULL); 1102 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1103 high_mmio_size, NULL); 1104 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, 1105 pio_base, NULL); 1106 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, 1107 pio_size, NULL); 1108 1109 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1110 1111 ecam_alias = g_new0(MemoryRegion, 1); 1112 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1113 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1114 ecam_reg, 0, ecam_size); 1115 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1116 1117 mmio_alias = g_new0(MemoryRegion, 1); 1118 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1119 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1120 mmio_reg, mmio_base, mmio_size); 1121 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1122 1123 /* Map high MMIO space */ 1124 high_mmio_alias = g_new0(MemoryRegion, 1); 1125 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1126 mmio_reg, high_mmio_base, high_mmio_size); 1127 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1128 high_mmio_alias); 1129 1130 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1131 1132 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1133 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1134 1135 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1136 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1137 } 1138 1139 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; 1140 return dev; 1141 } 1142 1143 static FWCfgState *create_fw_cfg(const MachineState *ms) 1144 { 1145 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1146 FWCfgState *fw_cfg; 1147 1148 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1149 &address_space_memory); 1150 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1151 1152 return fw_cfg; 1153 } 1154 1155 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1156 int base_hartid, int hart_count) 1157 { 1158 DeviceState *ret; 1159 g_autofree char *plic_hart_config = NULL; 1160 1161 /* Per-socket PLIC hart topology configuration string */ 1162 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1163 1164 /* Per-socket PLIC */ 1165 ret = sifive_plic_create( 1166 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1167 plic_hart_config, hart_count, base_hartid, 1168 VIRT_IRQCHIP_NUM_SOURCES, 1169 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1170 VIRT_PLIC_PRIORITY_BASE, 1171 VIRT_PLIC_PENDING_BASE, 1172 VIRT_PLIC_ENABLE_BASE, 1173 VIRT_PLIC_ENABLE_STRIDE, 1174 VIRT_PLIC_CONTEXT_BASE, 1175 VIRT_PLIC_CONTEXT_STRIDE, 1176 memmap[VIRT_PLIC].size); 1177 1178 return ret; 1179 } 1180 1181 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1182 const MemMapEntry *memmap, int socket, 1183 int base_hartid, int hart_count) 1184 { 1185 int i; 1186 hwaddr addr; 1187 uint32_t guest_bits; 1188 DeviceState *aplic_s = NULL; 1189 DeviceState *aplic_m = NULL; 1190 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1191 1192 if (msimode) { 1193 if (!kvm_enabled()) { 1194 /* Per-socket M-level IMSICs */ 1195 addr = memmap[VIRT_IMSIC_M].base + 1196 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1197 for (i = 0; i < hart_count; i++) { 1198 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1199 base_hartid + i, true, 1, 1200 VIRT_IRQCHIP_NUM_MSIS); 1201 } 1202 } 1203 1204 /* Per-socket S-level IMSICs */ 1205 guest_bits = imsic_num_bits(aia_guests + 1); 1206 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1207 for (i = 0; i < hart_count; i++) { 1208 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1209 base_hartid + i, false, 1 + aia_guests, 1210 VIRT_IRQCHIP_NUM_MSIS); 1211 } 1212 } 1213 1214 if (!kvm_enabled()) { 1215 /* Per-socket M-level APLIC */ 1216 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1217 socket * memmap[VIRT_APLIC_M].size, 1218 memmap[VIRT_APLIC_M].size, 1219 (msimode) ? 0 : base_hartid, 1220 (msimode) ? 0 : hart_count, 1221 VIRT_IRQCHIP_NUM_SOURCES, 1222 VIRT_IRQCHIP_NUM_PRIO_BITS, 1223 msimode, true, NULL); 1224 } 1225 1226 /* Per-socket S-level APLIC */ 1227 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1228 socket * memmap[VIRT_APLIC_S].size, 1229 memmap[VIRT_APLIC_S].size, 1230 (msimode) ? 0 : base_hartid, 1231 (msimode) ? 0 : hart_count, 1232 VIRT_IRQCHIP_NUM_SOURCES, 1233 VIRT_IRQCHIP_NUM_PRIO_BITS, 1234 msimode, false, aplic_m); 1235 1236 return kvm_enabled() ? aplic_s : aplic_m; 1237 } 1238 1239 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1240 { 1241 DeviceState *dev; 1242 SysBusDevice *sysbus; 1243 const MemMapEntry *memmap = virt_memmap; 1244 int i; 1245 MemoryRegion *sysmem = get_system_memory(); 1246 1247 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1248 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1249 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1250 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1251 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1252 s->platform_bus_dev = dev; 1253 1254 sysbus = SYS_BUS_DEVICE(dev); 1255 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1256 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1257 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1258 } 1259 1260 memory_region_add_subregion(sysmem, 1261 memmap[VIRT_PLATFORM_BUS].base, 1262 sysbus_mmio_get_region(sysbus, 0)); 1263 } 1264 1265 static void virt_build_smbios(RISCVVirtState *s) 1266 { 1267 MachineClass *mc = MACHINE_GET_CLASS(s); 1268 MachineState *ms = MACHINE(s); 1269 uint8_t *smbios_tables, *smbios_anchor; 1270 size_t smbios_tables_len, smbios_anchor_len; 1271 struct smbios_phys_mem_area mem_array; 1272 const char *product = "QEMU Virtual Machine"; 1273 1274 if (kvm_enabled()) { 1275 product = "KVM Virtual Machine"; 1276 } 1277 1278 smbios_set_defaults("QEMU", product, mc->name, false, 1279 true, SMBIOS_ENTRY_POINT_TYPE_64); 1280 1281 if (riscv_is_32bit(&s->soc[0])) { 1282 smbios_set_default_processor_family(0x200); 1283 } else { 1284 smbios_set_default_processor_family(0x201); 1285 } 1286 1287 /* build the array of physical mem area from base_memmap */ 1288 mem_array.address = s->memmap[VIRT_DRAM].base; 1289 mem_array.length = ms->ram_size; 1290 1291 smbios_get_tables(ms, &mem_array, 1, 1292 &smbios_tables, &smbios_tables_len, 1293 &smbios_anchor, &smbios_anchor_len, 1294 &error_fatal); 1295 1296 if (smbios_anchor) { 1297 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables", 1298 smbios_tables, smbios_tables_len); 1299 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor", 1300 smbios_anchor, smbios_anchor_len); 1301 } 1302 } 1303 1304 static void virt_machine_done(Notifier *notifier, void *data) 1305 { 1306 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1307 machine_done); 1308 const MemMapEntry *memmap = virt_memmap; 1309 MachineState *machine = MACHINE(s); 1310 target_ulong start_addr = memmap[VIRT_DRAM].base; 1311 target_ulong firmware_end_addr, kernel_start_addr; 1312 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1313 uint64_t fdt_load_addr; 1314 uint64_t kernel_entry = 0; 1315 BlockBackend *pflash_blk0; 1316 1317 /* 1318 * An user provided dtb must include everything, including 1319 * dynamic sysbus devices. Our FDT needs to be finalized. 1320 */ 1321 if (machine->dtb == NULL) { 1322 finalize_fdt(s); 1323 } 1324 1325 /* 1326 * Only direct boot kernel is currently supported for KVM VM, 1327 * so the "-bios" parameter is not supported when KVM is enabled. 1328 */ 1329 if (kvm_enabled()) { 1330 if (machine->firmware) { 1331 if (strcmp(machine->firmware, "none")) { 1332 error_report("Machine mode firmware is not supported in " 1333 "combination with KVM."); 1334 exit(1); 1335 } 1336 } else { 1337 machine->firmware = g_strdup("none"); 1338 } 1339 } 1340 1341 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1342 start_addr, NULL); 1343 1344 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1345 if (pflash_blk0) { 1346 if (machine->firmware && !strcmp(machine->firmware, "none") && 1347 !kvm_enabled()) { 1348 /* 1349 * Pflash was supplied but bios is none and not KVM guest, 1350 * let's overwrite the address we jump to after reset to 1351 * the base of the flash. 1352 */ 1353 start_addr = virt_memmap[VIRT_FLASH].base; 1354 } else { 1355 /* 1356 * Pflash was supplied but either KVM guest or bios is not none. 1357 * In this case, base of the flash would contain S-mode payload. 1358 */ 1359 riscv_setup_firmware_boot(machine); 1360 kernel_entry = virt_memmap[VIRT_FLASH].base; 1361 } 1362 } 1363 1364 if (machine->kernel_filename && !kernel_entry) { 1365 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1366 firmware_end_addr); 1367 1368 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1369 kernel_start_addr, true, NULL); 1370 } 1371 1372 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1373 memmap[VIRT_DRAM].size, 1374 machine); 1375 riscv_load_fdt(fdt_load_addr, machine->fdt); 1376 1377 /* load the reset vector */ 1378 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1379 virt_memmap[VIRT_MROM].base, 1380 virt_memmap[VIRT_MROM].size, kernel_entry, 1381 fdt_load_addr); 1382 1383 /* 1384 * Only direct boot kernel is currently supported for KVM VM, 1385 * So here setup kernel start address and fdt address. 1386 * TODO:Support firmware loading and integrate to TCG start 1387 */ 1388 if (kvm_enabled()) { 1389 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1390 } 1391 1392 virt_build_smbios(s); 1393 1394 if (virt_is_acpi_enabled(s)) { 1395 virt_acpi_setup(s); 1396 } 1397 } 1398 1399 static void virt_machine_init(MachineState *machine) 1400 { 1401 const MemMapEntry *memmap = virt_memmap; 1402 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1403 MemoryRegion *system_memory = get_system_memory(); 1404 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1405 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1406 int i, base_hartid, hart_count; 1407 int socket_count = riscv_socket_count(machine); 1408 1409 /* Check socket count limit */ 1410 if (VIRT_SOCKETS_MAX < socket_count) { 1411 error_report("number of sockets/nodes should be less than %d", 1412 VIRT_SOCKETS_MAX); 1413 exit(1); 1414 } 1415 1416 if (!virt_aclint_allowed() && s->have_aclint) { 1417 error_report("'aclint' is only available with TCG acceleration"); 1418 exit(1); 1419 } 1420 1421 /* Initialize sockets */ 1422 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1423 for (i = 0; i < socket_count; i++) { 1424 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1425 1426 if (!riscv_socket_check_hartids(machine, i)) { 1427 error_report("discontinuous hartids in socket%d", i); 1428 exit(1); 1429 } 1430 1431 base_hartid = riscv_socket_first_hartid(machine, i); 1432 if (base_hartid < 0) { 1433 error_report("can't find hartid base for socket%d", i); 1434 exit(1); 1435 } 1436 1437 hart_count = riscv_socket_hart_count(machine, i); 1438 if (hart_count < 0) { 1439 error_report("can't find hart count for socket%d", i); 1440 exit(1); 1441 } 1442 1443 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1444 TYPE_RISCV_HART_ARRAY); 1445 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1446 machine->cpu_type, &error_abort); 1447 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1448 base_hartid, &error_abort); 1449 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1450 hart_count, &error_abort); 1451 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1452 1453 if (virt_aclint_allowed() && s->have_aclint) { 1454 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1455 /* Per-socket ACLINT MTIMER */ 1456 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1457 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1458 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1459 base_hartid, hart_count, 1460 RISCV_ACLINT_DEFAULT_MTIMECMP, 1461 RISCV_ACLINT_DEFAULT_MTIME, 1462 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1463 } else { 1464 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1465 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1466 i * memmap[VIRT_CLINT].size, 1467 base_hartid, hart_count, false); 1468 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1469 i * memmap[VIRT_CLINT].size + 1470 RISCV_ACLINT_SWI_SIZE, 1471 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1472 base_hartid, hart_count, 1473 RISCV_ACLINT_DEFAULT_MTIMECMP, 1474 RISCV_ACLINT_DEFAULT_MTIME, 1475 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1476 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1477 i * memmap[VIRT_ACLINT_SSWI].size, 1478 base_hartid, hart_count, true); 1479 } 1480 } else if (tcg_enabled()) { 1481 /* Per-socket SiFive CLINT */ 1482 riscv_aclint_swi_create( 1483 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1484 base_hartid, hart_count, false); 1485 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1486 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1487 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1488 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1489 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1490 } 1491 1492 /* Per-socket interrupt controller */ 1493 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1494 s->irqchip[i] = virt_create_plic(memmap, i, 1495 base_hartid, hart_count); 1496 } else { 1497 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1498 memmap, i, base_hartid, 1499 hart_count); 1500 } 1501 1502 /* Try to use different IRQCHIP instance based device type */ 1503 if (i == 0) { 1504 mmio_irqchip = s->irqchip[i]; 1505 virtio_irqchip = s->irqchip[i]; 1506 pcie_irqchip = s->irqchip[i]; 1507 } 1508 if (i == 1) { 1509 virtio_irqchip = s->irqchip[i]; 1510 pcie_irqchip = s->irqchip[i]; 1511 } 1512 if (i == 2) { 1513 pcie_irqchip = s->irqchip[i]; 1514 } 1515 } 1516 1517 if (kvm_enabled() && virt_use_kvm_aia(s)) { 1518 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1519 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1520 memmap[VIRT_APLIC_S].base, 1521 memmap[VIRT_IMSIC_S].base, 1522 s->aia_guests); 1523 } 1524 1525 if (riscv_is_32bit(&s->soc[0])) { 1526 #if HOST_LONG_BITS == 64 1527 /* limit RAM size in a 32-bit system */ 1528 if (machine->ram_size > 10 * GiB) { 1529 machine->ram_size = 10 * GiB; 1530 error_report("Limiting RAM size to 10 GiB"); 1531 } 1532 #endif 1533 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1534 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1535 } else { 1536 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1537 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1538 virt_high_pcie_memmap.base = 1539 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1540 } 1541 1542 s->memmap = virt_memmap; 1543 1544 /* register system main memory (actual RAM) */ 1545 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1546 machine->ram); 1547 1548 /* boot rom */ 1549 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1550 memmap[VIRT_MROM].size, &error_fatal); 1551 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1552 mask_rom); 1553 1554 /* 1555 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1556 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1557 */ 1558 s->fw_cfg = create_fw_cfg(machine); 1559 rom_set_fw(s->fw_cfg); 1560 1561 /* SiFive Test MMIO device */ 1562 sifive_test_create(memmap[VIRT_TEST].base); 1563 1564 /* VirtIO MMIO devices */ 1565 for (i = 0; i < VIRTIO_COUNT; i++) { 1566 sysbus_create_simple("virtio-mmio", 1567 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1568 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1569 } 1570 1571 gpex_pcie_init(system_memory, pcie_irqchip, s); 1572 1573 create_platform_bus(s, mmio_irqchip); 1574 1575 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1576 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1577 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1578 1579 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1580 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1581 1582 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1583 /* Map legacy -drive if=pflash to machine properties */ 1584 pflash_cfi01_legacy_drive(s->flash[i], 1585 drive_get(IF_PFLASH, 0, i)); 1586 } 1587 virt_flash_map(s, system_memory); 1588 1589 /* load/create device tree */ 1590 if (machine->dtb) { 1591 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1592 if (!machine->fdt) { 1593 error_report("load_device_tree() failed"); 1594 exit(1); 1595 } 1596 } else { 1597 create_fdt(s, memmap); 1598 } 1599 1600 s->machine_done.notify = virt_machine_done; 1601 qemu_add_machine_init_done_notifier(&s->machine_done); 1602 } 1603 1604 static void virt_machine_instance_init(Object *obj) 1605 { 1606 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1607 1608 virt_flash_create(s); 1609 1610 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1611 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1612 s->acpi = ON_OFF_AUTO_AUTO; 1613 } 1614 1615 static char *virt_get_aia_guests(Object *obj, Error **errp) 1616 { 1617 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1618 char val[32]; 1619 1620 sprintf(val, "%d", s->aia_guests); 1621 return g_strdup(val); 1622 } 1623 1624 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1625 { 1626 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1627 1628 s->aia_guests = atoi(val); 1629 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1630 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1631 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1632 VIRT_IRQCHIP_MAX_GUESTS); 1633 } 1634 } 1635 1636 static char *virt_get_aia(Object *obj, Error **errp) 1637 { 1638 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1639 const char *val; 1640 1641 switch (s->aia_type) { 1642 case VIRT_AIA_TYPE_APLIC: 1643 val = "aplic"; 1644 break; 1645 case VIRT_AIA_TYPE_APLIC_IMSIC: 1646 val = "aplic-imsic"; 1647 break; 1648 default: 1649 val = "none"; 1650 break; 1651 }; 1652 1653 return g_strdup(val); 1654 } 1655 1656 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1657 { 1658 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1659 1660 if (!strcmp(val, "none")) { 1661 s->aia_type = VIRT_AIA_TYPE_NONE; 1662 } else if (!strcmp(val, "aplic")) { 1663 s->aia_type = VIRT_AIA_TYPE_APLIC; 1664 } else if (!strcmp(val, "aplic-imsic")) { 1665 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1666 } else { 1667 error_setg(errp, "Invalid AIA interrupt controller type"); 1668 error_append_hint(errp, "Valid values are none, aplic, and " 1669 "aplic-imsic.\n"); 1670 } 1671 } 1672 1673 static bool virt_get_aclint(Object *obj, Error **errp) 1674 { 1675 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1676 1677 return s->have_aclint; 1678 } 1679 1680 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1681 { 1682 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1683 1684 s->have_aclint = value; 1685 } 1686 1687 bool virt_is_acpi_enabled(RISCVVirtState *s) 1688 { 1689 return s->acpi != ON_OFF_AUTO_OFF; 1690 } 1691 1692 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1693 void *opaque, Error **errp) 1694 { 1695 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1696 OnOffAuto acpi = s->acpi; 1697 1698 visit_type_OnOffAuto(v, name, &acpi, errp); 1699 } 1700 1701 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1702 void *opaque, Error **errp) 1703 { 1704 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1705 1706 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1707 } 1708 1709 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1710 DeviceState *dev) 1711 { 1712 MachineClass *mc = MACHINE_GET_CLASS(machine); 1713 1714 if (device_is_dynamic_sysbus(mc, dev) || 1715 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1716 return HOTPLUG_HANDLER(machine); 1717 } 1718 return NULL; 1719 } 1720 1721 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1722 DeviceState *dev, Error **errp) 1723 { 1724 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1725 1726 if (s->platform_bus_dev) { 1727 MachineClass *mc = MACHINE_GET_CLASS(s); 1728 1729 if (device_is_dynamic_sysbus(mc, dev)) { 1730 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1731 SYS_BUS_DEVICE(dev)); 1732 } 1733 } 1734 1735 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1736 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1737 } 1738 } 1739 1740 static void virt_machine_class_init(ObjectClass *oc, void *data) 1741 { 1742 char str[128]; 1743 MachineClass *mc = MACHINE_CLASS(oc); 1744 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1745 1746 mc->desc = "RISC-V VirtIO board"; 1747 mc->init = virt_machine_init; 1748 mc->max_cpus = VIRT_CPUS_MAX; 1749 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1750 mc->pci_allow_0_address = true; 1751 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1752 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1753 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1754 mc->numa_mem_supported = true; 1755 /* platform instead of architectural choice */ 1756 mc->cpu_cluster_has_numa_boundary = true; 1757 mc->default_ram_id = "riscv_virt_board.ram"; 1758 assert(!mc->get_hotplug_handler); 1759 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1760 1761 hc->plug = virt_machine_device_plug_cb; 1762 1763 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1764 #ifdef CONFIG_TPM 1765 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1766 #endif 1767 1768 1769 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1770 virt_set_aclint); 1771 object_class_property_set_description(oc, "aclint", 1772 "(TCG only) Set on/off to " 1773 "enable/disable emulating " 1774 "ACLINT devices"); 1775 1776 object_class_property_add_str(oc, "aia", virt_get_aia, 1777 virt_set_aia); 1778 object_class_property_set_description(oc, "aia", 1779 "Set type of AIA interrupt " 1780 "controller. Valid values are " 1781 "none, aplic, and aplic-imsic."); 1782 1783 object_class_property_add_str(oc, "aia-guests", 1784 virt_get_aia_guests, 1785 virt_set_aia_guests); 1786 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1787 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1788 object_class_property_set_description(oc, "aia-guests", str); 1789 object_class_property_add(oc, "acpi", "OnOffAuto", 1790 virt_get_acpi, virt_set_acpi, 1791 NULL, NULL); 1792 object_class_property_set_description(oc, "acpi", 1793 "Enable ACPI"); 1794 } 1795 1796 static const TypeInfo virt_machine_typeinfo = { 1797 .name = MACHINE_TYPE_NAME("virt"), 1798 .parent = TYPE_MACHINE, 1799 .class_init = virt_machine_class_init, 1800 .instance_init = virt_machine_instance_init, 1801 .instance_size = sizeof(RISCVVirtState), 1802 .interfaces = (InterfaceInfo[]) { 1803 { TYPE_HOTPLUG_HANDLER }, 1804 { } 1805 }, 1806 }; 1807 1808 static void virt_machine_init_register_types(void) 1809 { 1810 type_register_static(&virt_machine_typeinfo); 1811 } 1812 1813 type_init(virt_machine_init_register_types) 1814