1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/log.h" 24 #include "qemu/error-report.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/char/serial.h" 30 #include "target/riscv/cpu.h" 31 #include "hw/riscv/riscv_hart.h" 32 #include "hw/riscv/sifive_plic.h" 33 #include "hw/riscv/sifive_clint.h" 34 #include "hw/riscv/sifive_test.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "chardev/char.h" 38 #include "sysemu/arch_init.h" 39 #include "sysemu/device_tree.h" 40 #include "sysemu/sysemu.h" 41 #include "exec/address-spaces.h" 42 #include "hw/pci/pci.h" 43 #include "hw/pci-host/gpex.h" 44 45 #include <libfdt.h> 46 47 #if defined(TARGET_RISCV32) 48 # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin" 49 #else 50 # define BIOS_FILENAME "opensbi-riscv64-virt-fw_jump.bin" 51 #endif 52 53 static const struct MemmapEntry { 54 hwaddr base; 55 hwaddr size; 56 } virt_memmap[] = { 57 [VIRT_DEBUG] = { 0x0, 0x100 }, 58 [VIRT_MROM] = { 0x1000, 0x11000 }, 59 [VIRT_TEST] = { 0x100000, 0x1000 }, 60 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 61 [VIRT_PLIC] = { 0xc000000, 0x4000000 }, 62 [VIRT_UART0] = { 0x10000000, 0x100 }, 63 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 64 [VIRT_DRAM] = { 0x80000000, 0x0 }, 65 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 66 [VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 }, 67 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 68 }; 69 70 static void create_pcie_irq_map(void *fdt, char *nodename, 71 uint32_t plic_phandle) 72 { 73 int pin, dev; 74 uint32_t 75 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; 76 uint32_t *irq_map = full_irq_map; 77 78 /* This code creates a standard swizzle of interrupts such that 79 * each device's first interrupt is based on it's PCI_SLOT number. 80 * (See pci_swizzle_map_irq_fn()) 81 * 82 * We only need one entry per interrupt in the table (not one per 83 * possible slot) seeing the interrupt-map-mask will allow the table 84 * to wrap to any number of devices. 85 */ 86 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 87 int devfn = dev * 0x8; 88 89 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 90 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 91 int i = 0; 92 93 irq_map[i] = cpu_to_be32(devfn << 8); 94 95 i += FDT_PCI_ADDR_CELLS; 96 irq_map[i] = cpu_to_be32(pin + 1); 97 98 i += FDT_PCI_INT_CELLS; 99 irq_map[i++] = cpu_to_be32(plic_phandle); 100 101 i += FDT_PLIC_ADDR_CELLS; 102 irq_map[i] = cpu_to_be32(irq_nr); 103 104 irq_map += FDT_INT_MAP_WIDTH; 105 } 106 } 107 108 qemu_fdt_setprop(fdt, nodename, "interrupt-map", 109 full_irq_map, sizeof(full_irq_map)); 110 111 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 112 0x1800, 0, 0, 0x7); 113 } 114 115 static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, 116 uint64_t mem_size, const char *cmdline) 117 { 118 void *fdt; 119 int cpu; 120 uint32_t *cells; 121 char *nodename; 122 uint32_t plic_phandle, phandle = 1; 123 int i; 124 125 fdt = s->fdt = create_device_tree(&s->fdt_size); 126 if (!fdt) { 127 error_report("create_device_tree() failed"); 128 exit(1); 129 } 130 131 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); 132 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); 133 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 134 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 135 136 qemu_fdt_add_subnode(fdt, "/soc"); 137 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 138 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 139 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 140 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 141 142 nodename = g_strdup_printf("/memory@%lx", 143 (long)memmap[VIRT_DRAM].base); 144 qemu_fdt_add_subnode(fdt, nodename); 145 qemu_fdt_setprop_cells(fdt, nodename, "reg", 146 memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base, 147 mem_size >> 32, mem_size); 148 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 149 g_free(nodename); 150 151 qemu_fdt_add_subnode(fdt, "/cpus"); 152 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 153 SIFIVE_CLINT_TIMEBASE_FREQ); 154 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 155 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 156 157 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { 158 int cpu_phandle = phandle++; 159 int intc_phandle; 160 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 161 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 162 char *isa = riscv_isa_string(&s->soc.harts[cpu]); 163 qemu_fdt_add_subnode(fdt, nodename); 164 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 165 VIRT_CLOCK_FREQ); 166 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 167 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 168 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 169 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 170 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 171 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 172 qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); 173 intc_phandle = phandle++; 174 qemu_fdt_add_subnode(fdt, intc); 175 qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle); 176 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 177 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 178 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 179 g_free(isa); 180 g_free(intc); 181 g_free(nodename); 182 } 183 184 /* Add cpu-topology node */ 185 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 186 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0"); 187 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { 188 char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d", 189 cpu); 190 char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 191 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename); 192 qemu_fdt_add_subnode(fdt, core_nodename); 193 qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle); 194 g_free(core_nodename); 195 g_free(cpu_nodename); 196 } 197 198 cells = g_new0(uint32_t, s->soc.num_harts * 4); 199 for (cpu = 0; cpu < s->soc.num_harts; cpu++) { 200 nodename = 201 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 202 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 203 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 204 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 205 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 206 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 207 g_free(nodename); 208 } 209 nodename = g_strdup_printf("/soc/clint@%lx", 210 (long)memmap[VIRT_CLINT].base); 211 qemu_fdt_add_subnode(fdt, nodename); 212 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 213 qemu_fdt_setprop_cells(fdt, nodename, "reg", 214 0x0, memmap[VIRT_CLINT].base, 215 0x0, memmap[VIRT_CLINT].size); 216 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 217 cells, s->soc.num_harts * sizeof(uint32_t) * 4); 218 g_free(cells); 219 g_free(nodename); 220 221 plic_phandle = phandle++; 222 cells = g_new0(uint32_t, s->soc.num_harts * 4); 223 for (cpu = 0; cpu < s->soc.num_harts; cpu++) { 224 nodename = 225 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 226 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 227 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 228 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 229 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 230 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 231 g_free(nodename); 232 } 233 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 234 (long)memmap[VIRT_PLIC].base); 235 qemu_fdt_add_subnode(fdt, nodename); 236 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 237 FDT_PLIC_ADDR_CELLS); 238 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 239 FDT_PLIC_INT_CELLS); 240 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 241 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 242 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 243 cells, s->soc.num_harts * sizeof(uint32_t) * 4); 244 qemu_fdt_setprop_cells(fdt, nodename, "reg", 245 0x0, memmap[VIRT_PLIC].base, 246 0x0, memmap[VIRT_PLIC].size); 247 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); 248 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 249 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 250 g_free(cells); 251 g_free(nodename); 252 253 for (i = 0; i < VIRTIO_COUNT; i++) { 254 nodename = g_strdup_printf("/virtio_mmio@%lx", 255 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 256 qemu_fdt_add_subnode(fdt, nodename); 257 qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio"); 258 qemu_fdt_setprop_cells(fdt, nodename, "reg", 259 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 260 0x0, memmap[VIRT_VIRTIO].size); 261 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 262 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i); 263 g_free(nodename); 264 } 265 266 nodename = g_strdup_printf("/soc/pci@%lx", 267 (long) memmap[VIRT_PCIE_ECAM].base); 268 qemu_fdt_add_subnode(fdt, nodename); 269 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 270 FDT_PCI_ADDR_CELLS); 271 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 272 FDT_PCI_INT_CELLS); 273 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2); 274 qemu_fdt_setprop_string(fdt, nodename, "compatible", 275 "pci-host-ecam-generic"); 276 qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); 277 qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0); 278 qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0, 279 memmap[VIRT_PCIE_ECAM].size / 280 PCIE_MMCFG_SIZE_MIN - 1); 281 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); 282 qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base, 283 0, memmap[VIRT_PCIE_ECAM].size); 284 qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges", 285 1, FDT_PCI_RANGE_IOPORT, 2, 0, 286 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 287 1, FDT_PCI_RANGE_MMIO, 288 2, memmap[VIRT_PCIE_MMIO].base, 289 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); 290 create_pcie_irq_map(fdt, nodename, plic_phandle); 291 g_free(nodename); 292 293 nodename = g_strdup_printf("/test@%lx", 294 (long)memmap[VIRT_TEST].base); 295 qemu_fdt_add_subnode(fdt, nodename); 296 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0"); 297 qemu_fdt_setprop_cells(fdt, nodename, "reg", 298 0x0, memmap[VIRT_TEST].base, 299 0x0, memmap[VIRT_TEST].size); 300 g_free(nodename); 301 302 nodename = g_strdup_printf("/uart@%lx", 303 (long)memmap[VIRT_UART0].base); 304 qemu_fdt_add_subnode(fdt, nodename); 305 qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a"); 306 qemu_fdt_setprop_cells(fdt, nodename, "reg", 307 0x0, memmap[VIRT_UART0].base, 308 0x0, memmap[VIRT_UART0].size); 309 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); 310 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 311 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ); 312 313 qemu_fdt_add_subnode(fdt, "/chosen"); 314 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 315 if (cmdline) { 316 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 317 } 318 g_free(nodename); 319 } 320 321 322 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 323 hwaddr ecam_base, hwaddr ecam_size, 324 hwaddr mmio_base, hwaddr mmio_size, 325 hwaddr pio_base, 326 DeviceState *plic, bool link_up) 327 { 328 DeviceState *dev; 329 MemoryRegion *ecam_alias, *ecam_reg; 330 MemoryRegion *mmio_alias, *mmio_reg; 331 qemu_irq irq; 332 int i; 333 334 dev = qdev_create(NULL, TYPE_GPEX_HOST); 335 336 qdev_init_nofail(dev); 337 338 ecam_alias = g_new0(MemoryRegion, 1); 339 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 340 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 341 ecam_reg, 0, ecam_size); 342 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 343 344 mmio_alias = g_new0(MemoryRegion, 1); 345 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 346 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 347 mmio_reg, mmio_base, mmio_size); 348 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 349 350 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 351 352 for (i = 0; i < GPEX_NUM_IRQS; i++) { 353 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); 354 355 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 356 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 357 } 358 359 return dev; 360 } 361 362 static void riscv_virt_board_init(MachineState *machine) 363 { 364 const struct MemmapEntry *memmap = virt_memmap; 365 366 RISCVVirtState *s = g_new0(RISCVVirtState, 1); 367 MemoryRegion *system_memory = get_system_memory(); 368 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 369 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 370 char *plic_hart_config; 371 size_t plic_hart_config_len; 372 int i; 373 unsigned int smp_cpus = machine->smp.cpus; 374 375 /* Initialize SOC */ 376 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 377 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 378 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", 379 &error_abort); 380 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 381 &error_abort); 382 object_property_set_bool(OBJECT(&s->soc), true, "realized", 383 &error_abort); 384 385 /* register system main memory (actual RAM) */ 386 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", 387 machine->ram_size, &error_fatal); 388 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 389 main_mem); 390 391 /* create device tree */ 392 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 393 394 /* boot rom */ 395 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 396 memmap[VIRT_MROM].size, &error_fatal); 397 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 398 mask_rom); 399 400 riscv_find_and_load_firmware(machine, BIOS_FILENAME, 401 memmap[VIRT_DRAM].base); 402 403 if (machine->kernel_filename) { 404 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); 405 406 if (machine->initrd_filename) { 407 hwaddr start; 408 hwaddr end = riscv_load_initrd(machine->initrd_filename, 409 machine->ram_size, kernel_entry, 410 &start); 411 qemu_fdt_setprop_cell(s->fdt, "/chosen", 412 "linux,initrd-start", start); 413 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 414 end); 415 } 416 } 417 418 /* reset vector */ 419 uint32_t reset_vec[8] = { 420 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 421 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 422 0xf1402573, /* csrr a0, mhartid */ 423 #if defined(TARGET_RISCV32) 424 0x0182a283, /* lw t0, 24(t0) */ 425 #elif defined(TARGET_RISCV64) 426 0x0182b283, /* ld t0, 24(t0) */ 427 #endif 428 0x00028067, /* jr t0 */ 429 0x00000000, 430 memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].base */ 431 0x00000000, 432 /* dtb: */ 433 }; 434 435 /* copy in the reset vector in little_endian byte order */ 436 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 437 reset_vec[i] = cpu_to_le32(reset_vec[i]); 438 } 439 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 440 memmap[VIRT_MROM].base, &address_space_memory); 441 442 /* copy in the device tree */ 443 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 444 memmap[VIRT_MROM].size - sizeof(reset_vec)) { 445 error_report("not enough space to store device-tree"); 446 exit(1); 447 } 448 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 449 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 450 memmap[VIRT_MROM].base + sizeof(reset_vec), 451 &address_space_memory); 452 453 /* create PLIC hart topology configuration string */ 454 plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus; 455 plic_hart_config = g_malloc0(plic_hart_config_len); 456 for (i = 0; i < smp_cpus; i++) { 457 if (i != 0) { 458 strncat(plic_hart_config, ",", plic_hart_config_len); 459 } 460 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len); 461 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); 462 } 463 464 /* MMIO */ 465 s->plic = sifive_plic_create(memmap[VIRT_PLIC].base, 466 plic_hart_config, 467 VIRT_PLIC_NUM_SOURCES, 468 VIRT_PLIC_NUM_PRIORITIES, 469 VIRT_PLIC_PRIORITY_BASE, 470 VIRT_PLIC_PENDING_BASE, 471 VIRT_PLIC_ENABLE_BASE, 472 VIRT_PLIC_ENABLE_STRIDE, 473 VIRT_PLIC_CONTEXT_BASE, 474 VIRT_PLIC_CONTEXT_STRIDE, 475 memmap[VIRT_PLIC].size); 476 sifive_clint_create(memmap[VIRT_CLINT].base, 477 memmap[VIRT_CLINT].size, smp_cpus, 478 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 479 sifive_test_create(memmap[VIRT_TEST].base); 480 481 for (i = 0; i < VIRTIO_COUNT; i++) { 482 sysbus_create_simple("virtio-mmio", 483 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 484 qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i)); 485 } 486 487 gpex_pcie_init(system_memory, 488 memmap[VIRT_PCIE_ECAM].base, 489 memmap[VIRT_PCIE_ECAM].size, 490 memmap[VIRT_PCIE_MMIO].base, 491 memmap[VIRT_PCIE_MMIO].size, 492 memmap[VIRT_PCIE_PIO].base, 493 DEVICE(s->plic), true); 494 495 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 496 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, 497 serial_hd(0), DEVICE_LITTLE_ENDIAN); 498 499 g_free(plic_hart_config); 500 } 501 502 static void riscv_virt_board_machine_init(MachineClass *mc) 503 { 504 mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)"; 505 mc->init = riscv_virt_board_init; 506 mc->max_cpus = 8; /* hardcoded limit in BBL */ 507 mc->default_cpu_type = VIRT_CPU; 508 } 509 510 DEFINE_MACHINE("virt", riscv_virt_board_machine_init) 511