1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "hw/riscv/riscv_hart.h" 34 #include "hw/riscv/virt.h" 35 #include "hw/riscv/boot.h" 36 #include "hw/riscv/numa.h" 37 #include "hw/intc/riscv_aclint.h" 38 #include "hw/intc/riscv_aplic.h" 39 #include "hw/intc/riscv_imsic.h" 40 #include "hw/intc/sifive_plic.h" 41 #include "hw/misc/sifive_test.h" 42 #include "hw/platform-bus.h" 43 #include "chardev/char.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/sysemu.h" 46 #include "sysemu/kvm.h" 47 #include "sysemu/tpm.h" 48 #include "hw/pci/pci.h" 49 #include "hw/pci-host/gpex.h" 50 #include "hw/display/ramfb.h" 51 52 /* 53 * The virt machine physical address space used by some of the devices 54 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 55 * number of CPUs, and number of IMSIC guest files. 56 * 57 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 58 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 59 * of virt machine physical address space. 60 */ 61 62 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 63 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 64 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 65 #error "Can't accomodate single IMSIC group in address space" 66 #endif 67 68 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 69 VIRT_IMSIC_GROUP_MAX_SIZE) 70 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 71 #error "Can't accomodate all IMSIC groups in address space" 72 #endif 73 74 static const MemMapEntry virt_memmap[] = { 75 [VIRT_DEBUG] = { 0x0, 0x100 }, 76 [VIRT_MROM] = { 0x1000, 0xf000 }, 77 [VIRT_TEST] = { 0x100000, 0x1000 }, 78 [VIRT_RTC] = { 0x101000, 0x1000 }, 79 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 80 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 81 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 82 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 83 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 84 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 85 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 86 [VIRT_UART0] = { 0x10000000, 0x100 }, 87 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 88 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 89 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 90 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 91 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 92 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 93 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 94 [VIRT_DRAM] = { 0x80000000, 0x0 }, 95 }; 96 97 /* PCIe high mmio is fixed for RV32 */ 98 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 99 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 100 101 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 102 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 103 104 static MemMapEntry virt_high_pcie_memmap; 105 106 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 107 108 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 109 const char *name, 110 const char *alias_prop_name) 111 { 112 /* 113 * Create a single flash device. We use the same parameters as 114 * the flash devices on the ARM virt board. 115 */ 116 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 117 118 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 119 qdev_prop_set_uint8(dev, "width", 4); 120 qdev_prop_set_uint8(dev, "device-width", 2); 121 qdev_prop_set_bit(dev, "big-endian", false); 122 qdev_prop_set_uint16(dev, "id0", 0x89); 123 qdev_prop_set_uint16(dev, "id1", 0x18); 124 qdev_prop_set_uint16(dev, "id2", 0x00); 125 qdev_prop_set_uint16(dev, "id3", 0x00); 126 qdev_prop_set_string(dev, "name", name); 127 128 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 129 object_property_add_alias(OBJECT(s), alias_prop_name, 130 OBJECT(dev), "drive"); 131 132 return PFLASH_CFI01(dev); 133 } 134 135 static void virt_flash_create(RISCVVirtState *s) 136 { 137 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 138 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 139 } 140 141 static void virt_flash_map1(PFlashCFI01 *flash, 142 hwaddr base, hwaddr size, 143 MemoryRegion *sysmem) 144 { 145 DeviceState *dev = DEVICE(flash); 146 147 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 148 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 149 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 150 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 151 152 memory_region_add_subregion(sysmem, base, 153 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 154 0)); 155 } 156 157 static void virt_flash_map(RISCVVirtState *s, 158 MemoryRegion *sysmem) 159 { 160 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 161 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 162 163 virt_flash_map1(s->flash[0], flashbase, flashsize, 164 sysmem); 165 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 166 sysmem); 167 } 168 169 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 170 uint32_t irqchip_phandle) 171 { 172 int pin, dev; 173 uint32_t irq_map_stride = 0; 174 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 175 FDT_MAX_INT_MAP_WIDTH] = {}; 176 uint32_t *irq_map = full_irq_map; 177 178 /* This code creates a standard swizzle of interrupts such that 179 * each device's first interrupt is based on it's PCI_SLOT number. 180 * (See pci_swizzle_map_irq_fn()) 181 * 182 * We only need one entry per interrupt in the table (not one per 183 * possible slot) seeing the interrupt-map-mask will allow the table 184 * to wrap to any number of devices. 185 */ 186 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 187 int devfn = dev * 0x8; 188 189 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 190 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 191 int i = 0; 192 193 /* Fill PCI address cells */ 194 irq_map[i] = cpu_to_be32(devfn << 8); 195 i += FDT_PCI_ADDR_CELLS; 196 197 /* Fill PCI Interrupt cells */ 198 irq_map[i] = cpu_to_be32(pin + 1); 199 i += FDT_PCI_INT_CELLS; 200 201 /* Fill interrupt controller phandle and cells */ 202 irq_map[i++] = cpu_to_be32(irqchip_phandle); 203 irq_map[i++] = cpu_to_be32(irq_nr); 204 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 205 irq_map[i++] = cpu_to_be32(0x4); 206 } 207 208 if (!irq_map_stride) { 209 irq_map_stride = i; 210 } 211 irq_map += irq_map_stride; 212 } 213 } 214 215 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 216 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 217 irq_map_stride * sizeof(uint32_t)); 218 219 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 220 0x1800, 0, 0, 0x7); 221 } 222 223 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 224 char *clust_name, uint32_t *phandle, 225 bool is_32_bit, uint32_t *intc_phandles) 226 { 227 int cpu; 228 uint32_t cpu_phandle; 229 MachineState *mc = MACHINE(s); 230 char *name, *cpu_name, *core_name, *intc_name; 231 232 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 233 cpu_phandle = (*phandle)++; 234 235 cpu_name = g_strdup_printf("/cpus/cpu@%d", 236 s->soc[socket].hartid_base + cpu); 237 qemu_fdt_add_subnode(mc->fdt, cpu_name); 238 if (riscv_feature(&s->soc[socket].harts[cpu].env, 239 RISCV_FEATURE_MMU)) { 240 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 241 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 242 } else { 243 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 244 "riscv,none"); 245 } 246 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 247 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); 248 g_free(name); 249 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); 250 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); 251 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", 252 s->soc[socket].hartid_base + cpu); 253 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); 254 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); 255 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); 256 257 intc_phandles[cpu] = (*phandle)++; 258 259 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 260 qemu_fdt_add_subnode(mc->fdt, intc_name); 261 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", 262 intc_phandles[cpu]); 263 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", 264 "riscv,cpu-intc"); 265 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); 266 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); 267 268 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 269 qemu_fdt_add_subnode(mc->fdt, core_name); 270 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); 271 272 g_free(core_name); 273 g_free(intc_name); 274 g_free(cpu_name); 275 } 276 } 277 278 static void create_fdt_socket_memory(RISCVVirtState *s, 279 const MemMapEntry *memmap, int socket) 280 { 281 char *mem_name; 282 uint64_t addr, size; 283 MachineState *mc = MACHINE(s); 284 285 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 286 size = riscv_socket_mem_size(mc, socket); 287 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 288 qemu_fdt_add_subnode(mc->fdt, mem_name); 289 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", 290 addr >> 32, addr, size >> 32, size); 291 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); 292 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); 293 g_free(mem_name); 294 } 295 296 static void create_fdt_socket_clint(RISCVVirtState *s, 297 const MemMapEntry *memmap, int socket, 298 uint32_t *intc_phandles) 299 { 300 int cpu; 301 char *clint_name; 302 uint32_t *clint_cells; 303 unsigned long clint_addr; 304 MachineState *mc = MACHINE(s); 305 static const char * const clint_compat[2] = { 306 "sifive,clint0", "riscv,clint0" 307 }; 308 309 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 310 311 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 312 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 313 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 314 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 315 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 316 } 317 318 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 319 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 320 qemu_fdt_add_subnode(mc->fdt, clint_name); 321 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", 322 (char **)&clint_compat, 323 ARRAY_SIZE(clint_compat)); 324 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", 325 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 326 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", 327 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 328 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); 329 g_free(clint_name); 330 331 g_free(clint_cells); 332 } 333 334 static void create_fdt_socket_aclint(RISCVVirtState *s, 335 const MemMapEntry *memmap, int socket, 336 uint32_t *intc_phandles) 337 { 338 int cpu; 339 char *name; 340 unsigned long addr, size; 341 uint32_t aclint_cells_size; 342 uint32_t *aclint_mswi_cells; 343 uint32_t *aclint_sswi_cells; 344 uint32_t *aclint_mtimer_cells; 345 MachineState *mc = MACHINE(s); 346 347 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 348 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 349 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 350 351 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 352 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 353 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 354 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 355 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 356 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 357 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 358 } 359 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 360 361 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 362 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 363 name = g_strdup_printf("/soc/mswi@%lx", addr); 364 qemu_fdt_add_subnode(mc->fdt, name); 365 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 366 "riscv,aclint-mswi"); 367 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 368 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 369 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 370 aclint_mswi_cells, aclint_cells_size); 371 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 372 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 373 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 374 g_free(name); 375 } 376 377 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 378 addr = memmap[VIRT_CLINT].base + 379 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 380 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 381 } else { 382 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 383 (memmap[VIRT_CLINT].size * socket); 384 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 385 } 386 name = g_strdup_printf("/soc/mtimer@%lx", addr); 387 qemu_fdt_add_subnode(mc->fdt, name); 388 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 389 "riscv,aclint-mtimer"); 390 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 391 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 392 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 393 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 394 0x0, RISCV_ACLINT_DEFAULT_MTIME); 395 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 396 aclint_mtimer_cells, aclint_cells_size); 397 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 398 g_free(name); 399 400 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 401 addr = memmap[VIRT_ACLINT_SSWI].base + 402 (memmap[VIRT_ACLINT_SSWI].size * socket); 403 name = g_strdup_printf("/soc/sswi@%lx", addr); 404 qemu_fdt_add_subnode(mc->fdt, name); 405 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 406 "riscv,aclint-sswi"); 407 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 408 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 409 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 410 aclint_sswi_cells, aclint_cells_size); 411 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 412 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 413 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 414 g_free(name); 415 } 416 417 g_free(aclint_mswi_cells); 418 g_free(aclint_mtimer_cells); 419 g_free(aclint_sswi_cells); 420 } 421 422 static void create_fdt_socket_plic(RISCVVirtState *s, 423 const MemMapEntry *memmap, int socket, 424 uint32_t *phandle, uint32_t *intc_phandles, 425 uint32_t *plic_phandles) 426 { 427 int cpu; 428 char *plic_name; 429 uint32_t *plic_cells; 430 unsigned long plic_addr; 431 MachineState *mc = MACHINE(s); 432 static const char * const plic_compat[2] = { 433 "sifive,plic-1.0.0", "riscv,plic0" 434 }; 435 436 if (kvm_enabled()) { 437 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 438 } else { 439 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 440 } 441 442 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 443 if (kvm_enabled()) { 444 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 445 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 446 } else { 447 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 448 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 449 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 450 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 451 } 452 } 453 454 plic_phandles[socket] = (*phandle)++; 455 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 456 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 457 qemu_fdt_add_subnode(mc->fdt, plic_name); 458 qemu_fdt_setprop_cell(mc->fdt, plic_name, 459 "#interrupt-cells", FDT_PLIC_INT_CELLS); 460 qemu_fdt_setprop_cell(mc->fdt, plic_name, 461 "#address-cells", FDT_PLIC_ADDR_CELLS); 462 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", 463 (char **)&plic_compat, 464 ARRAY_SIZE(plic_compat)); 465 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); 466 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", 467 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 468 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", 469 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 470 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 471 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); 472 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", 473 plic_phandles[socket]); 474 475 if (!socket) { 476 platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, 477 memmap[VIRT_PLATFORM_BUS].base, 478 memmap[VIRT_PLATFORM_BUS].size, 479 VIRT_PLATFORM_BUS_IRQ); 480 } 481 482 g_free(plic_name); 483 484 g_free(plic_cells); 485 } 486 487 static uint32_t imsic_num_bits(uint32_t count) 488 { 489 uint32_t ret = 0; 490 491 while (BIT(ret) < count) { 492 ret++; 493 } 494 495 return ret; 496 } 497 498 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 499 uint32_t *phandle, uint32_t *intc_phandles, 500 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 501 { 502 int cpu, socket; 503 char *imsic_name; 504 MachineState *mc = MACHINE(s); 505 uint32_t imsic_max_hart_per_socket, imsic_guest_bits; 506 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 507 508 *msi_m_phandle = (*phandle)++; 509 *msi_s_phandle = (*phandle)++; 510 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); 511 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); 512 513 /* M-level IMSIC node */ 514 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 515 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 516 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 517 } 518 imsic_max_hart_per_socket = 0; 519 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 520 imsic_addr = memmap[VIRT_IMSIC_M].base + 521 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 522 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; 523 imsic_regs[socket * 4 + 0] = 0; 524 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 525 imsic_regs[socket * 4 + 2] = 0; 526 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 527 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 528 imsic_max_hart_per_socket = s->soc[socket].num_harts; 529 } 530 } 531 imsic_name = g_strdup_printf("/soc/imsics@%lx", 532 (unsigned long)memmap[VIRT_IMSIC_M].base); 533 qemu_fdt_add_subnode(mc->fdt, imsic_name); 534 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 535 "riscv,imsics"); 536 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 537 FDT_IMSIC_INT_CELLS); 538 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 539 NULL, 0); 540 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 541 NULL, 0); 542 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 543 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 544 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 545 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 546 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 547 VIRT_IRQCHIP_NUM_MSIS); 548 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 549 VIRT_IRQCHIP_IPI_MSI); 550 if (riscv_socket_count(mc) > 1) { 551 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 552 imsic_num_bits(imsic_max_hart_per_socket)); 553 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 554 imsic_num_bits(riscv_socket_count(mc))); 555 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 556 IMSIC_MMIO_GROUP_MIN_SHIFT); 557 } 558 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); 559 560 g_free(imsic_name); 561 562 /* S-level IMSIC node */ 563 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 564 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 565 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 566 } 567 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); 568 imsic_max_hart_per_socket = 0; 569 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 570 imsic_addr = memmap[VIRT_IMSIC_S].base + 571 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 572 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 573 s->soc[socket].num_harts; 574 imsic_regs[socket * 4 + 0] = 0; 575 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 576 imsic_regs[socket * 4 + 2] = 0; 577 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 578 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 579 imsic_max_hart_per_socket = s->soc[socket].num_harts; 580 } 581 } 582 imsic_name = g_strdup_printf("/soc/imsics@%lx", 583 (unsigned long)memmap[VIRT_IMSIC_S].base); 584 qemu_fdt_add_subnode(mc->fdt, imsic_name); 585 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 586 "riscv,imsics"); 587 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 588 FDT_IMSIC_INT_CELLS); 589 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 590 NULL, 0); 591 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 592 NULL, 0); 593 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 594 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 595 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 596 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 597 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 598 VIRT_IRQCHIP_NUM_MSIS); 599 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 600 VIRT_IRQCHIP_IPI_MSI); 601 if (imsic_guest_bits) { 602 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", 603 imsic_guest_bits); 604 } 605 if (riscv_socket_count(mc) > 1) { 606 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 607 imsic_num_bits(imsic_max_hart_per_socket)); 608 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 609 imsic_num_bits(riscv_socket_count(mc))); 610 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 611 IMSIC_MMIO_GROUP_MIN_SHIFT); 612 } 613 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); 614 g_free(imsic_name); 615 616 g_free(imsic_regs); 617 g_free(imsic_cells); 618 } 619 620 static void create_fdt_socket_aplic(RISCVVirtState *s, 621 const MemMapEntry *memmap, int socket, 622 uint32_t msi_m_phandle, 623 uint32_t msi_s_phandle, 624 uint32_t *phandle, 625 uint32_t *intc_phandles, 626 uint32_t *aplic_phandles) 627 { 628 int cpu; 629 char *aplic_name; 630 uint32_t *aplic_cells; 631 unsigned long aplic_addr; 632 MachineState *mc = MACHINE(s); 633 uint32_t aplic_m_phandle, aplic_s_phandle; 634 635 aplic_m_phandle = (*phandle)++; 636 aplic_s_phandle = (*phandle)++; 637 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 638 639 /* M-level APLIC node */ 640 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 641 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 642 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 643 } 644 aplic_addr = memmap[VIRT_APLIC_M].base + 645 (memmap[VIRT_APLIC_M].size * socket); 646 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 647 qemu_fdt_add_subnode(mc->fdt, aplic_name); 648 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 649 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 650 "#interrupt-cells", FDT_APLIC_INT_CELLS); 651 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 652 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 653 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 654 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 655 } else { 656 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 657 msi_m_phandle); 658 } 659 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 660 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); 661 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 662 VIRT_IRQCHIP_NUM_SOURCES); 663 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", 664 aplic_s_phandle); 665 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", 666 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); 667 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 668 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); 669 g_free(aplic_name); 670 671 /* S-level APLIC node */ 672 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 673 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 674 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 675 } 676 aplic_addr = memmap[VIRT_APLIC_S].base + 677 (memmap[VIRT_APLIC_S].size * socket); 678 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 679 qemu_fdt_add_subnode(mc->fdt, aplic_name); 680 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 681 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 682 "#interrupt-cells", FDT_APLIC_INT_CELLS); 683 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 684 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 685 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 686 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 687 } else { 688 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 689 msi_s_phandle); 690 } 691 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 692 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); 693 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 694 VIRT_IRQCHIP_NUM_SOURCES); 695 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 696 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); 697 698 if (!socket) { 699 platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, 700 memmap[VIRT_PLATFORM_BUS].base, 701 memmap[VIRT_PLATFORM_BUS].size, 702 VIRT_PLATFORM_BUS_IRQ); 703 } 704 705 g_free(aplic_name); 706 707 g_free(aplic_cells); 708 aplic_phandles[socket] = aplic_s_phandle; 709 } 710 711 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 712 bool is_32_bit, uint32_t *phandle, 713 uint32_t *irq_mmio_phandle, 714 uint32_t *irq_pcie_phandle, 715 uint32_t *irq_virtio_phandle, 716 uint32_t *msi_pcie_phandle) 717 { 718 char *clust_name; 719 int socket, phandle_pos; 720 MachineState *mc = MACHINE(s); 721 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 722 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 723 724 qemu_fdt_add_subnode(mc->fdt, "/cpus"); 725 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", 726 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 727 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); 728 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); 729 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); 730 731 intc_phandles = g_new0(uint32_t, mc->smp.cpus); 732 733 phandle_pos = mc->smp.cpus; 734 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 735 phandle_pos -= s->soc[socket].num_harts; 736 737 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 738 qemu_fdt_add_subnode(mc->fdt, clust_name); 739 740 create_fdt_socket_cpus(s, socket, clust_name, phandle, 741 is_32_bit, &intc_phandles[phandle_pos]); 742 743 create_fdt_socket_memory(s, memmap, socket); 744 745 g_free(clust_name); 746 747 if (!kvm_enabled()) { 748 if (s->have_aclint) { 749 create_fdt_socket_aclint(s, memmap, socket, 750 &intc_phandles[phandle_pos]); 751 } else { 752 create_fdt_socket_clint(s, memmap, socket, 753 &intc_phandles[phandle_pos]); 754 } 755 } 756 } 757 758 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 759 create_fdt_imsic(s, memmap, phandle, intc_phandles, 760 &msi_m_phandle, &msi_s_phandle); 761 *msi_pcie_phandle = msi_s_phandle; 762 } 763 764 phandle_pos = mc->smp.cpus; 765 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 766 phandle_pos -= s->soc[socket].num_harts; 767 768 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 769 create_fdt_socket_plic(s, memmap, socket, phandle, 770 &intc_phandles[phandle_pos], xplic_phandles); 771 } else { 772 create_fdt_socket_aplic(s, memmap, socket, 773 msi_m_phandle, msi_s_phandle, phandle, 774 &intc_phandles[phandle_pos], xplic_phandles); 775 } 776 } 777 778 g_free(intc_phandles); 779 780 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 781 if (socket == 0) { 782 *irq_mmio_phandle = xplic_phandles[socket]; 783 *irq_virtio_phandle = xplic_phandles[socket]; 784 *irq_pcie_phandle = xplic_phandles[socket]; 785 } 786 if (socket == 1) { 787 *irq_virtio_phandle = xplic_phandles[socket]; 788 *irq_pcie_phandle = xplic_phandles[socket]; 789 } 790 if (socket == 2) { 791 *irq_pcie_phandle = xplic_phandles[socket]; 792 } 793 } 794 795 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); 796 } 797 798 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 799 uint32_t irq_virtio_phandle) 800 { 801 int i; 802 char *name; 803 MachineState *mc = MACHINE(s); 804 805 for (i = 0; i < VIRTIO_COUNT; i++) { 806 name = g_strdup_printf("/soc/virtio_mmio@%lx", 807 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 808 qemu_fdt_add_subnode(mc->fdt, name); 809 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); 810 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 811 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 812 0x0, memmap[VIRT_VIRTIO].size); 813 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 814 irq_virtio_phandle); 815 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 816 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", 817 VIRTIO_IRQ + i); 818 } else { 819 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", 820 VIRTIO_IRQ + i, 0x4); 821 } 822 g_free(name); 823 } 824 } 825 826 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 827 uint32_t irq_pcie_phandle, 828 uint32_t msi_pcie_phandle) 829 { 830 char *name; 831 MachineState *mc = MACHINE(s); 832 833 name = g_strdup_printf("/soc/pci@%lx", 834 (long) memmap[VIRT_PCIE_ECAM].base); 835 qemu_fdt_add_subnode(mc->fdt, name); 836 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", 837 FDT_PCI_ADDR_CELLS); 838 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 839 FDT_PCI_INT_CELLS); 840 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); 841 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 842 "pci-host-ecam-generic"); 843 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); 844 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); 845 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, 846 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 847 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); 848 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 849 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); 850 } 851 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, 852 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 853 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", 854 1, FDT_PCI_RANGE_IOPORT, 2, 0, 855 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 856 1, FDT_PCI_RANGE_MMIO, 857 2, memmap[VIRT_PCIE_MMIO].base, 858 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 859 1, FDT_PCI_RANGE_MMIO_64BIT, 860 2, virt_high_pcie_memmap.base, 861 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 862 863 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); 864 g_free(name); 865 } 866 867 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 868 uint32_t *phandle) 869 { 870 char *name; 871 uint32_t test_phandle; 872 MachineState *mc = MACHINE(s); 873 874 test_phandle = (*phandle)++; 875 name = g_strdup_printf("/soc/test@%lx", 876 (long)memmap[VIRT_TEST].base); 877 qemu_fdt_add_subnode(mc->fdt, name); 878 { 879 static const char * const compat[3] = { 880 "sifive,test1", "sifive,test0", "syscon" 881 }; 882 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", 883 (char **)&compat, ARRAY_SIZE(compat)); 884 } 885 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 886 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 887 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); 888 test_phandle = qemu_fdt_get_phandle(mc->fdt, name); 889 g_free(name); 890 891 name = g_strdup_printf("/reboot"); 892 qemu_fdt_add_subnode(mc->fdt, name); 893 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); 894 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 895 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 896 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); 897 g_free(name); 898 899 name = g_strdup_printf("/poweroff"); 900 qemu_fdt_add_subnode(mc->fdt, name); 901 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); 902 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 903 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 904 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); 905 g_free(name); 906 } 907 908 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 909 uint32_t irq_mmio_phandle) 910 { 911 char *name; 912 MachineState *mc = MACHINE(s); 913 914 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 915 qemu_fdt_add_subnode(mc->fdt, name); 916 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); 917 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 918 0x0, memmap[VIRT_UART0].base, 919 0x0, memmap[VIRT_UART0].size); 920 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); 921 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); 922 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 923 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); 924 } else { 925 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); 926 } 927 928 qemu_fdt_add_subnode(mc->fdt, "/chosen"); 929 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); 930 g_free(name); 931 } 932 933 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 934 uint32_t irq_mmio_phandle) 935 { 936 char *name; 937 MachineState *mc = MACHINE(s); 938 939 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 940 qemu_fdt_add_subnode(mc->fdt, name); 941 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 942 "google,goldfish-rtc"); 943 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 944 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 945 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 946 irq_mmio_phandle); 947 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 948 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); 949 } else { 950 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); 951 } 952 g_free(name); 953 } 954 955 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 956 { 957 char *name; 958 MachineState *mc = MACHINE(s); 959 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 960 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 961 962 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 963 qemu_fdt_add_subnode(mc->fdt, name); 964 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 965 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 966 2, flashbase, 2, flashsize, 967 2, flashbase + flashsize, 2, flashsize); 968 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 969 g_free(name); 970 } 971 972 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 973 { 974 char *nodename; 975 MachineState *mc = MACHINE(s); 976 hwaddr base = memmap[VIRT_FW_CFG].base; 977 hwaddr size = memmap[VIRT_FW_CFG].size; 978 979 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 980 qemu_fdt_add_subnode(mc->fdt, nodename); 981 qemu_fdt_setprop_string(mc->fdt, nodename, 982 "compatible", "qemu,fw-cfg-mmio"); 983 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 984 2, base, 2, size); 985 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 986 g_free(nodename); 987 } 988 989 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 990 uint64_t mem_size, const char *cmdline, bool is_32_bit) 991 { 992 MachineState *mc = MACHINE(s); 993 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 994 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 995 uint8_t rng_seed[32]; 996 997 if (mc->dtb) { 998 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 999 if (!mc->fdt) { 1000 error_report("load_device_tree() failed"); 1001 exit(1); 1002 } 1003 goto update_bootargs; 1004 } else { 1005 mc->fdt = create_device_tree(&s->fdt_size); 1006 if (!mc->fdt) { 1007 error_report("create_device_tree() failed"); 1008 exit(1); 1009 } 1010 } 1011 1012 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); 1013 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); 1014 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); 1015 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); 1016 1017 qemu_fdt_add_subnode(mc->fdt, "/soc"); 1018 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); 1019 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); 1020 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); 1021 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); 1022 1023 create_fdt_sockets(s, memmap, is_32_bit, &phandle, 1024 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, 1025 &msi_pcie_phandle); 1026 1027 create_fdt_virtio(s, memmap, irq_virtio_phandle); 1028 1029 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); 1030 1031 create_fdt_reset(s, memmap, &phandle); 1032 1033 create_fdt_uart(s, memmap, irq_mmio_phandle); 1034 1035 create_fdt_rtc(s, memmap, irq_mmio_phandle); 1036 1037 create_fdt_flash(s, memmap); 1038 create_fdt_fw_cfg(s, memmap); 1039 1040 update_bootargs: 1041 if (cmdline && *cmdline) { 1042 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); 1043 } 1044 1045 /* Pass seed to RNG */ 1046 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1047 qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); 1048 } 1049 1050 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1051 hwaddr ecam_base, hwaddr ecam_size, 1052 hwaddr mmio_base, hwaddr mmio_size, 1053 hwaddr high_mmio_base, 1054 hwaddr high_mmio_size, 1055 hwaddr pio_base, 1056 DeviceState *irqchip) 1057 { 1058 DeviceState *dev; 1059 MemoryRegion *ecam_alias, *ecam_reg; 1060 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1061 qemu_irq irq; 1062 int i; 1063 1064 dev = qdev_new(TYPE_GPEX_HOST); 1065 1066 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1067 1068 ecam_alias = g_new0(MemoryRegion, 1); 1069 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1070 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1071 ecam_reg, 0, ecam_size); 1072 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1073 1074 mmio_alias = g_new0(MemoryRegion, 1); 1075 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1076 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1077 mmio_reg, mmio_base, mmio_size); 1078 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1079 1080 /* Map high MMIO space */ 1081 high_mmio_alias = g_new0(MemoryRegion, 1); 1082 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1083 mmio_reg, high_mmio_base, high_mmio_size); 1084 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1085 high_mmio_alias); 1086 1087 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1088 1089 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1090 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1091 1092 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1093 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1094 } 1095 1096 return dev; 1097 } 1098 1099 static FWCfgState *create_fw_cfg(const MachineState *mc) 1100 { 1101 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1102 FWCfgState *fw_cfg; 1103 1104 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1105 &address_space_memory); 1106 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 1107 1108 return fw_cfg; 1109 } 1110 1111 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1112 int base_hartid, int hart_count) 1113 { 1114 DeviceState *ret; 1115 char *plic_hart_config; 1116 1117 /* Per-socket PLIC hart topology configuration string */ 1118 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1119 1120 /* Per-socket PLIC */ 1121 ret = sifive_plic_create( 1122 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1123 plic_hart_config, hart_count, base_hartid, 1124 VIRT_IRQCHIP_NUM_SOURCES, 1125 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1126 VIRT_PLIC_PRIORITY_BASE, 1127 VIRT_PLIC_PENDING_BASE, 1128 VIRT_PLIC_ENABLE_BASE, 1129 VIRT_PLIC_ENABLE_STRIDE, 1130 VIRT_PLIC_CONTEXT_BASE, 1131 VIRT_PLIC_CONTEXT_STRIDE, 1132 memmap[VIRT_PLIC].size); 1133 1134 g_free(plic_hart_config); 1135 1136 return ret; 1137 } 1138 1139 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1140 const MemMapEntry *memmap, int socket, 1141 int base_hartid, int hart_count) 1142 { 1143 int i; 1144 hwaddr addr; 1145 uint32_t guest_bits; 1146 DeviceState *aplic_m; 1147 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; 1148 1149 if (msimode) { 1150 /* Per-socket M-level IMSICs */ 1151 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1152 for (i = 0; i < hart_count; i++) { 1153 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1154 base_hartid + i, true, 1, 1155 VIRT_IRQCHIP_NUM_MSIS); 1156 } 1157 1158 /* Per-socket S-level IMSICs */ 1159 guest_bits = imsic_num_bits(aia_guests + 1); 1160 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1161 for (i = 0; i < hart_count; i++) { 1162 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1163 base_hartid + i, false, 1 + aia_guests, 1164 VIRT_IRQCHIP_NUM_MSIS); 1165 } 1166 } 1167 1168 /* Per-socket M-level APLIC */ 1169 aplic_m = riscv_aplic_create( 1170 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, 1171 memmap[VIRT_APLIC_M].size, 1172 (msimode) ? 0 : base_hartid, 1173 (msimode) ? 0 : hart_count, 1174 VIRT_IRQCHIP_NUM_SOURCES, 1175 VIRT_IRQCHIP_NUM_PRIO_BITS, 1176 msimode, true, NULL); 1177 1178 if (aplic_m) { 1179 /* Per-socket S-level APLIC */ 1180 riscv_aplic_create( 1181 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, 1182 memmap[VIRT_APLIC_S].size, 1183 (msimode) ? 0 : base_hartid, 1184 (msimode) ? 0 : hart_count, 1185 VIRT_IRQCHIP_NUM_SOURCES, 1186 VIRT_IRQCHIP_NUM_PRIO_BITS, 1187 msimode, false, aplic_m); 1188 } 1189 1190 return aplic_m; 1191 } 1192 1193 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1194 { 1195 DeviceState *dev; 1196 SysBusDevice *sysbus; 1197 const MemMapEntry *memmap = virt_memmap; 1198 int i; 1199 MemoryRegion *sysmem = get_system_memory(); 1200 1201 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1202 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1203 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1204 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1205 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1206 s->platform_bus_dev = dev; 1207 1208 sysbus = SYS_BUS_DEVICE(dev); 1209 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1210 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1211 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1212 } 1213 1214 memory_region_add_subregion(sysmem, 1215 memmap[VIRT_PLATFORM_BUS].base, 1216 sysbus_mmio_get_region(sysbus, 0)); 1217 } 1218 1219 static void virt_machine_done(Notifier *notifier, void *data) 1220 { 1221 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1222 machine_done); 1223 const MemMapEntry *memmap = virt_memmap; 1224 MachineState *machine = MACHINE(s); 1225 target_ulong start_addr = memmap[VIRT_DRAM].base; 1226 target_ulong firmware_end_addr, kernel_start_addr; 1227 uint32_t fdt_load_addr; 1228 uint64_t kernel_entry; 1229 1230 /* 1231 * Only direct boot kernel is currently supported for KVM VM, 1232 * so the "-bios" parameter is not supported when KVM is enabled. 1233 */ 1234 if (kvm_enabled()) { 1235 if (machine->firmware) { 1236 if (strcmp(machine->firmware, "none")) { 1237 error_report("Machine mode firmware is not supported in " 1238 "combination with KVM."); 1239 exit(1); 1240 } 1241 } else { 1242 machine->firmware = g_strdup("none"); 1243 } 1244 } 1245 1246 if (riscv_is_32bit(&s->soc[0])) { 1247 firmware_end_addr = riscv_find_and_load_firmware(machine, 1248 RISCV32_BIOS_BIN, start_addr, NULL); 1249 } else { 1250 firmware_end_addr = riscv_find_and_load_firmware(machine, 1251 RISCV64_BIOS_BIN, start_addr, NULL); 1252 } 1253 1254 if (machine->kernel_filename) { 1255 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1256 firmware_end_addr); 1257 1258 kernel_entry = riscv_load_kernel(machine->kernel_filename, 1259 kernel_start_addr, NULL); 1260 1261 if (machine->initrd_filename) { 1262 hwaddr start; 1263 hwaddr end = riscv_load_initrd(machine->initrd_filename, 1264 machine->ram_size, kernel_entry, 1265 &start); 1266 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 1267 "linux,initrd-start", start); 1268 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 1269 end); 1270 } 1271 } else { 1272 /* 1273 * If dynamic firmware is used, it doesn't know where is the next mode 1274 * if kernel argument is not set. 1275 */ 1276 kernel_entry = 0; 1277 } 1278 1279 if (drive_get(IF_PFLASH, 0, 0)) { 1280 /* 1281 * Pflash was supplied, let's overwrite the address we jump to after 1282 * reset to the base of the flash. 1283 */ 1284 start_addr = virt_memmap[VIRT_FLASH].base; 1285 } 1286 1287 /* 1288 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 1289 * tree cannot be altered and we get FDT_ERR_NOSPACE. 1290 */ 1291 s->fw_cfg = create_fw_cfg(machine); 1292 rom_set_fw(s->fw_cfg); 1293 1294 /* Compute the fdt load address in dram */ 1295 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 1296 machine->ram_size, machine->fdt); 1297 /* load the reset vector */ 1298 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1299 virt_memmap[VIRT_MROM].base, 1300 virt_memmap[VIRT_MROM].size, kernel_entry, 1301 fdt_load_addr); 1302 1303 /* 1304 * Only direct boot kernel is currently supported for KVM VM, 1305 * So here setup kernel start address and fdt address. 1306 * TODO:Support firmware loading and integrate to TCG start 1307 */ 1308 if (kvm_enabled()) { 1309 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1310 } 1311 } 1312 1313 static void virt_machine_init(MachineState *machine) 1314 { 1315 const MemMapEntry *memmap = virt_memmap; 1316 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1317 MemoryRegion *system_memory = get_system_memory(); 1318 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1319 char *soc_name; 1320 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1321 int i, base_hartid, hart_count; 1322 1323 /* Check socket count limit */ 1324 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 1325 error_report("number of sockets/nodes should be less than %d", 1326 VIRT_SOCKETS_MAX); 1327 exit(1); 1328 } 1329 1330 /* Initialize sockets */ 1331 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1332 for (i = 0; i < riscv_socket_count(machine); i++) { 1333 if (!riscv_socket_check_hartids(machine, i)) { 1334 error_report("discontinuous hartids in socket%d", i); 1335 exit(1); 1336 } 1337 1338 base_hartid = riscv_socket_first_hartid(machine, i); 1339 if (base_hartid < 0) { 1340 error_report("can't find hartid base for socket%d", i); 1341 exit(1); 1342 } 1343 1344 hart_count = riscv_socket_hart_count(machine, i); 1345 if (hart_count < 0) { 1346 error_report("can't find hart count for socket%d", i); 1347 exit(1); 1348 } 1349 1350 soc_name = g_strdup_printf("soc%d", i); 1351 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1352 TYPE_RISCV_HART_ARRAY); 1353 g_free(soc_name); 1354 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1355 machine->cpu_type, &error_abort); 1356 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1357 base_hartid, &error_abort); 1358 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1359 hart_count, &error_abort); 1360 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1361 1362 if (!kvm_enabled()) { 1363 if (s->have_aclint) { 1364 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1365 /* Per-socket ACLINT MTIMER */ 1366 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1367 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1368 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1369 base_hartid, hart_count, 1370 RISCV_ACLINT_DEFAULT_MTIMECMP, 1371 RISCV_ACLINT_DEFAULT_MTIME, 1372 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1373 } else { 1374 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1375 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1376 i * memmap[VIRT_CLINT].size, 1377 base_hartid, hart_count, false); 1378 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1379 i * memmap[VIRT_CLINT].size + 1380 RISCV_ACLINT_SWI_SIZE, 1381 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1382 base_hartid, hart_count, 1383 RISCV_ACLINT_DEFAULT_MTIMECMP, 1384 RISCV_ACLINT_DEFAULT_MTIME, 1385 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1386 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1387 i * memmap[VIRT_ACLINT_SSWI].size, 1388 base_hartid, hart_count, true); 1389 } 1390 } else { 1391 /* Per-socket SiFive CLINT */ 1392 riscv_aclint_swi_create( 1393 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1394 base_hartid, hart_count, false); 1395 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1396 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1397 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1398 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1399 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1400 } 1401 } 1402 1403 /* Per-socket interrupt controller */ 1404 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1405 s->irqchip[i] = virt_create_plic(memmap, i, 1406 base_hartid, hart_count); 1407 } else { 1408 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1409 memmap, i, base_hartid, 1410 hart_count); 1411 } 1412 1413 /* Try to use different IRQCHIP instance based device type */ 1414 if (i == 0) { 1415 mmio_irqchip = s->irqchip[i]; 1416 virtio_irqchip = s->irqchip[i]; 1417 pcie_irqchip = s->irqchip[i]; 1418 } 1419 if (i == 1) { 1420 virtio_irqchip = s->irqchip[i]; 1421 pcie_irqchip = s->irqchip[i]; 1422 } 1423 if (i == 2) { 1424 pcie_irqchip = s->irqchip[i]; 1425 } 1426 } 1427 1428 if (riscv_is_32bit(&s->soc[0])) { 1429 #if HOST_LONG_BITS == 64 1430 /* limit RAM size in a 32-bit system */ 1431 if (machine->ram_size > 10 * GiB) { 1432 machine->ram_size = 10 * GiB; 1433 error_report("Limiting RAM size to 10 GiB"); 1434 } 1435 #endif 1436 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1437 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1438 } else { 1439 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1440 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1441 virt_high_pcie_memmap.base = 1442 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1443 } 1444 1445 /* register system main memory (actual RAM) */ 1446 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1447 machine->ram); 1448 1449 /* boot rom */ 1450 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1451 memmap[VIRT_MROM].size, &error_fatal); 1452 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1453 mask_rom); 1454 1455 /* SiFive Test MMIO device */ 1456 sifive_test_create(memmap[VIRT_TEST].base); 1457 1458 /* VirtIO MMIO devices */ 1459 for (i = 0; i < VIRTIO_COUNT; i++) { 1460 sysbus_create_simple("virtio-mmio", 1461 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1462 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); 1463 } 1464 1465 gpex_pcie_init(system_memory, 1466 memmap[VIRT_PCIE_ECAM].base, 1467 memmap[VIRT_PCIE_ECAM].size, 1468 memmap[VIRT_PCIE_MMIO].base, 1469 memmap[VIRT_PCIE_MMIO].size, 1470 virt_high_pcie_memmap.base, 1471 virt_high_pcie_memmap.size, 1472 memmap[VIRT_PCIE_PIO].base, 1473 DEVICE(pcie_irqchip)); 1474 1475 create_platform_bus(s, DEVICE(mmio_irqchip)); 1476 1477 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1478 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, 1479 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1480 1481 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1482 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); 1483 1484 virt_flash_create(s); 1485 1486 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1487 /* Map legacy -drive if=pflash to machine properties */ 1488 pflash_cfi01_legacy_drive(s->flash[i], 1489 drive_get(IF_PFLASH, 0, i)); 1490 } 1491 virt_flash_map(s, system_memory); 1492 1493 /* create device tree */ 1494 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 1495 riscv_is_32bit(&s->soc[0])); 1496 1497 s->machine_done.notify = virt_machine_done; 1498 qemu_add_machine_init_done_notifier(&s->machine_done); 1499 } 1500 1501 static void virt_machine_instance_init(Object *obj) 1502 { 1503 } 1504 1505 static char *virt_get_aia_guests(Object *obj, Error **errp) 1506 { 1507 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1508 char val[32]; 1509 1510 sprintf(val, "%d", s->aia_guests); 1511 return g_strdup(val); 1512 } 1513 1514 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1515 { 1516 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1517 1518 s->aia_guests = atoi(val); 1519 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1520 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1521 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1522 VIRT_IRQCHIP_MAX_GUESTS); 1523 } 1524 } 1525 1526 static char *virt_get_aia(Object *obj, Error **errp) 1527 { 1528 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1529 const char *val; 1530 1531 switch (s->aia_type) { 1532 case VIRT_AIA_TYPE_APLIC: 1533 val = "aplic"; 1534 break; 1535 case VIRT_AIA_TYPE_APLIC_IMSIC: 1536 val = "aplic-imsic"; 1537 break; 1538 default: 1539 val = "none"; 1540 break; 1541 }; 1542 1543 return g_strdup(val); 1544 } 1545 1546 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1547 { 1548 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1549 1550 if (!strcmp(val, "none")) { 1551 s->aia_type = VIRT_AIA_TYPE_NONE; 1552 } else if (!strcmp(val, "aplic")) { 1553 s->aia_type = VIRT_AIA_TYPE_APLIC; 1554 } else if (!strcmp(val, "aplic-imsic")) { 1555 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1556 } else { 1557 error_setg(errp, "Invalid AIA interrupt controller type"); 1558 error_append_hint(errp, "Valid values are none, aplic, and " 1559 "aplic-imsic.\n"); 1560 } 1561 } 1562 1563 static bool virt_get_aclint(Object *obj, Error **errp) 1564 { 1565 MachineState *ms = MACHINE(obj); 1566 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1567 1568 return s->have_aclint; 1569 } 1570 1571 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1572 { 1573 MachineState *ms = MACHINE(obj); 1574 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1575 1576 s->have_aclint = value; 1577 } 1578 1579 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1580 DeviceState *dev) 1581 { 1582 MachineClass *mc = MACHINE_GET_CLASS(machine); 1583 1584 if (device_is_dynamic_sysbus(mc, dev)) { 1585 return HOTPLUG_HANDLER(machine); 1586 } 1587 return NULL; 1588 } 1589 1590 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1591 DeviceState *dev, Error **errp) 1592 { 1593 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1594 1595 if (s->platform_bus_dev) { 1596 MachineClass *mc = MACHINE_GET_CLASS(s); 1597 1598 if (device_is_dynamic_sysbus(mc, dev)) { 1599 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1600 SYS_BUS_DEVICE(dev)); 1601 } 1602 } 1603 } 1604 1605 static void virt_machine_class_init(ObjectClass *oc, void *data) 1606 { 1607 char str[128]; 1608 MachineClass *mc = MACHINE_CLASS(oc); 1609 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1610 1611 mc->desc = "RISC-V VirtIO board"; 1612 mc->init = virt_machine_init; 1613 mc->max_cpus = VIRT_CPUS_MAX; 1614 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1615 mc->pci_allow_0_address = true; 1616 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1617 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1618 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1619 mc->numa_mem_supported = true; 1620 mc->default_ram_id = "riscv_virt_board.ram"; 1621 assert(!mc->get_hotplug_handler); 1622 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1623 1624 hc->plug = virt_machine_device_plug_cb; 1625 1626 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1627 #ifdef CONFIG_TPM 1628 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1629 #endif 1630 1631 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1632 virt_set_aclint); 1633 object_class_property_set_description(oc, "aclint", 1634 "Set on/off to enable/disable " 1635 "emulating ACLINT devices"); 1636 1637 object_class_property_add_str(oc, "aia", virt_get_aia, 1638 virt_set_aia); 1639 object_class_property_set_description(oc, "aia", 1640 "Set type of AIA interrupt " 1641 "conttoller. Valid values are " 1642 "none, aplic, and aplic-imsic."); 1643 1644 object_class_property_add_str(oc, "aia-guests", 1645 virt_get_aia_guests, 1646 virt_set_aia_guests); 1647 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1648 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1649 object_class_property_set_description(oc, "aia-guests", str); 1650 } 1651 1652 static const TypeInfo virt_machine_typeinfo = { 1653 .name = MACHINE_TYPE_NAME("virt"), 1654 .parent = TYPE_MACHINE, 1655 .class_init = virt_machine_class_init, 1656 .instance_init = virt_machine_instance_init, 1657 .instance_size = sizeof(RISCVVirtState), 1658 .interfaces = (InterfaceInfo[]) { 1659 { TYPE_HOTPLUG_HANDLER }, 1660 { } 1661 }, 1662 }; 1663 1664 static void virt_machine_init_register_types(void) 1665 { 1666 type_register_static(&virt_machine_typeinfo); 1667 } 1668 1669 type_init(virt_machine_init_register_types) 1670