xref: /openbmc/qemu/hw/riscv/virt.c (revision d5938f29)
1 /*
2  * QEMU RISC-V VirtIO Board
3  *
4  * Copyright (c) 2017 SiFive, Inc.
5  *
6  * RISC-V machine with 16550a UART and VirtIO MMIO
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2 or later, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/log.h"
24 #include "qemu/error-report.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/char/serial.h"
30 #include "target/riscv/cpu.h"
31 #include "hw/riscv/riscv_hart.h"
32 #include "hw/riscv/sifive_plic.h"
33 #include "hw/riscv/sifive_clint.h"
34 #include "hw/riscv/sifive_test.h"
35 #include "hw/riscv/virt.h"
36 #include "hw/riscv/boot.h"
37 #include "chardev/char.h"
38 #include "sysemu/arch_init.h"
39 #include "sysemu/device_tree.h"
40 #include "exec/address-spaces.h"
41 #include "hw/pci/pci.h"
42 #include "hw/pci-host/gpex.h"
43 
44 #include <libfdt.h>
45 
46 #if defined(TARGET_RISCV32)
47 # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
48 #else
49 # define BIOS_FILENAME "opensbi-riscv64-virt-fw_jump.bin"
50 #endif
51 
52 static const struct MemmapEntry {
53     hwaddr base;
54     hwaddr size;
55 } virt_memmap[] = {
56     [VIRT_DEBUG] =       {        0x0,         0x100 },
57     [VIRT_MROM] =        {     0x1000,       0x11000 },
58     [VIRT_TEST] =        {   0x100000,        0x1000 },
59     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
60     [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
61     [VIRT_UART0] =       { 0x10000000,         0x100 },
62     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
63     [VIRT_DRAM] =        { 0x80000000,           0x0 },
64     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
65     [VIRT_PCIE_PIO] =    { 0x03000000,    0x00010000 },
66     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
67 };
68 
69 static void create_pcie_irq_map(void *fdt, char *nodename,
70                                 uint32_t plic_phandle)
71 {
72     int pin, dev;
73     uint32_t
74         full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
75     uint32_t *irq_map = full_irq_map;
76 
77     /* This code creates a standard swizzle of interrupts such that
78      * each device's first interrupt is based on it's PCI_SLOT number.
79      * (See pci_swizzle_map_irq_fn())
80      *
81      * We only need one entry per interrupt in the table (not one per
82      * possible slot) seeing the interrupt-map-mask will allow the table
83      * to wrap to any number of devices.
84      */
85     for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
86         int devfn = dev * 0x8;
87 
88         for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
89             int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
90             int i = 0;
91 
92             irq_map[i] = cpu_to_be32(devfn << 8);
93 
94             i += FDT_PCI_ADDR_CELLS;
95             irq_map[i] = cpu_to_be32(pin + 1);
96 
97             i += FDT_PCI_INT_CELLS;
98             irq_map[i++] = cpu_to_be32(plic_phandle);
99 
100             i += FDT_PLIC_ADDR_CELLS;
101             irq_map[i] = cpu_to_be32(irq_nr);
102 
103             irq_map += FDT_INT_MAP_WIDTH;
104         }
105     }
106 
107     qemu_fdt_setprop(fdt, nodename, "interrupt-map",
108                      full_irq_map, sizeof(full_irq_map));
109 
110     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
111                            0x1800, 0, 0, 0x7);
112 }
113 
114 static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
115     uint64_t mem_size, const char *cmdline)
116 {
117     void *fdt;
118     int cpu;
119     uint32_t *cells;
120     char *nodename;
121     uint32_t plic_phandle, phandle = 1;
122     int i;
123 
124     fdt = s->fdt = create_device_tree(&s->fdt_size);
125     if (!fdt) {
126         error_report("create_device_tree() failed");
127         exit(1);
128     }
129 
130     qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
131     qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
132     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
133     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
134 
135     qemu_fdt_add_subnode(fdt, "/soc");
136     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
137     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
138     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
139     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
140 
141     nodename = g_strdup_printf("/memory@%lx",
142         (long)memmap[VIRT_DRAM].base);
143     qemu_fdt_add_subnode(fdt, nodename);
144     qemu_fdt_setprop_cells(fdt, nodename, "reg",
145         memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
146         mem_size >> 32, mem_size);
147     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
148     g_free(nodename);
149 
150     qemu_fdt_add_subnode(fdt, "/cpus");
151     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
152                           SIFIVE_CLINT_TIMEBASE_FREQ);
153     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
154     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
155 
156     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
157         int cpu_phandle = phandle++;
158         int intc_phandle;
159         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
160         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
161         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
162         qemu_fdt_add_subnode(fdt, nodename);
163         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
164                               VIRT_CLOCK_FREQ);
165         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
166         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
167         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
168         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
169         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
170         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
171         qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
172         qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle);
173         intc_phandle = phandle++;
174         qemu_fdt_add_subnode(fdt, intc);
175         qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
176         qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle);
177         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
178         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
179         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
180         g_free(isa);
181         g_free(intc);
182         g_free(nodename);
183     }
184 
185     /* Add cpu-topology node */
186     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
187     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
188     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
189         char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
190                                               cpu);
191         char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
192         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
193         qemu_fdt_add_subnode(fdt, core_nodename);
194         qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
195         g_free(core_nodename);
196         g_free(cpu_nodename);
197     }
198 
199     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
200     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
201         nodename =
202             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
203         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
204         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
205         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
206         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
207         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
208         g_free(nodename);
209     }
210     nodename = g_strdup_printf("/soc/clint@%lx",
211         (long)memmap[VIRT_CLINT].base);
212     qemu_fdt_add_subnode(fdt, nodename);
213     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
214     qemu_fdt_setprop_cells(fdt, nodename, "reg",
215         0x0, memmap[VIRT_CLINT].base,
216         0x0, memmap[VIRT_CLINT].size);
217     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
218         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
219     g_free(cells);
220     g_free(nodename);
221 
222     plic_phandle = phandle++;
223     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
224     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
225         nodename =
226             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
227         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
228         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
229         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
230         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
231         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
232         g_free(nodename);
233     }
234     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
235         (long)memmap[VIRT_PLIC].base);
236     qemu_fdt_add_subnode(fdt, nodename);
237     qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
238                            FDT_PLIC_ADDR_CELLS);
239     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
240                           FDT_PLIC_INT_CELLS);
241     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
242     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
243     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
244         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
245     qemu_fdt_setprop_cells(fdt, nodename, "reg",
246         0x0, memmap[VIRT_PLIC].base,
247         0x0, memmap[VIRT_PLIC].size);
248     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
249     qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
250     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
251     qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
252     qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
253     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
254     g_free(cells);
255     g_free(nodename);
256 
257     for (i = 0; i < VIRTIO_COUNT; i++) {
258         nodename = g_strdup_printf("/virtio_mmio@%lx",
259             (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
260         qemu_fdt_add_subnode(fdt, nodename);
261         qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
262         qemu_fdt_setprop_cells(fdt, nodename, "reg",
263             0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
264             0x0, memmap[VIRT_VIRTIO].size);
265         qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
266         qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
267         g_free(nodename);
268     }
269 
270     nodename = g_strdup_printf("/soc/pci@%lx",
271         (long) memmap[VIRT_PCIE_ECAM].base);
272     qemu_fdt_add_subnode(fdt, nodename);
273     qemu_fdt_setprop_cells(fdt, nodename, "#address-cells",
274                            FDT_PCI_ADDR_CELLS);
275     qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells",
276                            FDT_PCI_INT_CELLS);
277     qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
278     qemu_fdt_setprop_string(fdt, nodename, "compatible",
279                             "pci-host-ecam-generic");
280     qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
281     qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
282     qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
283                            memmap[VIRT_PCIE_ECAM].size /
284                                PCIE_MMCFG_SIZE_MIN - 1);
285     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
286     qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
287                            0, memmap[VIRT_PCIE_ECAM].size);
288     qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
289         1, FDT_PCI_RANGE_IOPORT, 2, 0,
290         2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
291         1, FDT_PCI_RANGE_MMIO,
292         2, memmap[VIRT_PCIE_MMIO].base,
293         2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
294     create_pcie_irq_map(fdt, nodename, plic_phandle);
295     g_free(nodename);
296 
297     nodename = g_strdup_printf("/test@%lx",
298         (long)memmap[VIRT_TEST].base);
299     qemu_fdt_add_subnode(fdt, nodename);
300     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
301     qemu_fdt_setprop_cells(fdt, nodename, "reg",
302         0x0, memmap[VIRT_TEST].base,
303         0x0, memmap[VIRT_TEST].size);
304     g_free(nodename);
305 
306     nodename = g_strdup_printf("/uart@%lx",
307         (long)memmap[VIRT_UART0].base);
308     qemu_fdt_add_subnode(fdt, nodename);
309     qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
310     qemu_fdt_setprop_cells(fdt, nodename, "reg",
311         0x0, memmap[VIRT_UART0].base,
312         0x0, memmap[VIRT_UART0].size);
313     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
314         qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
315         qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);
316 
317     qemu_fdt_add_subnode(fdt, "/chosen");
318     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
319     if (cmdline) {
320         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
321     }
322     g_free(nodename);
323 
324     return fdt;
325 }
326 
327 
328 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
329                                           hwaddr ecam_base, hwaddr ecam_size,
330                                           hwaddr mmio_base, hwaddr mmio_size,
331                                           hwaddr pio_base,
332                                           DeviceState *plic, bool link_up)
333 {
334     DeviceState *dev;
335     MemoryRegion *ecam_alias, *ecam_reg;
336     MemoryRegion *mmio_alias, *mmio_reg;
337     qemu_irq irq;
338     int i;
339 
340     dev = qdev_create(NULL, TYPE_GPEX_HOST);
341 
342     qdev_init_nofail(dev);
343 
344     ecam_alias = g_new0(MemoryRegion, 1);
345     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
346     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
347                              ecam_reg, 0, ecam_size);
348     memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
349 
350     mmio_alias = g_new0(MemoryRegion, 1);
351     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
352     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
353                              mmio_reg, mmio_base, mmio_size);
354     memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
355 
356     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
357 
358     for (i = 0; i < GPEX_NUM_IRQS; i++) {
359         irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
360 
361         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
362         gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
363     }
364 
365     return dev;
366 }
367 
368 static void riscv_virt_board_init(MachineState *machine)
369 {
370     const struct MemmapEntry *memmap = virt_memmap;
371 
372     RISCVVirtState *s = g_new0(RISCVVirtState, 1);
373     MemoryRegion *system_memory = get_system_memory();
374     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
375     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
376     char *plic_hart_config;
377     size_t plic_hart_config_len;
378     int i;
379     unsigned int smp_cpus = machine->smp.cpus;
380     void *fdt;
381 
382     /* Initialize SOC */
383     object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
384                             TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
385     object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
386                             &error_abort);
387     object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
388                             &error_abort);
389     object_property_set_bool(OBJECT(&s->soc), true, "realized",
390                             &error_abort);
391 
392     /* register system main memory (actual RAM) */
393     memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
394                            machine->ram_size, &error_fatal);
395     memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
396         main_mem);
397 
398     /* create device tree */
399     fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
400 
401     /* boot rom */
402     memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
403                            memmap[VIRT_MROM].size, &error_fatal);
404     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
405                                 mask_rom);
406 
407     riscv_find_and_load_firmware(machine, BIOS_FILENAME,
408                                  memmap[VIRT_DRAM].base);
409 
410     if (machine->kernel_filename) {
411         uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
412 
413         if (machine->initrd_filename) {
414             hwaddr start;
415             hwaddr end = riscv_load_initrd(machine->initrd_filename,
416                                            machine->ram_size, kernel_entry,
417                                            &start);
418             qemu_fdt_setprop_cell(fdt, "/chosen",
419                                   "linux,initrd-start", start);
420             qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
421                                   end);
422         }
423     }
424 
425     /* reset vector */
426     uint32_t reset_vec[8] = {
427         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
428         0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
429         0xf1402573,                  /*     csrr   a0, mhartid  */
430 #if defined(TARGET_RISCV32)
431         0x0182a283,                  /*     lw     t0, 24(t0) */
432 #elif defined(TARGET_RISCV64)
433         0x0182b283,                  /*     ld     t0, 24(t0) */
434 #endif
435         0x00028067,                  /*     jr     t0 */
436         0x00000000,
437         memmap[VIRT_DRAM].base,      /* start: .dword memmap[VIRT_DRAM].base */
438         0x00000000,
439                                      /* dtb: */
440     };
441 
442     /* copy in the reset vector in little_endian byte order */
443     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
444         reset_vec[i] = cpu_to_le32(reset_vec[i]);
445     }
446     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
447                           memmap[VIRT_MROM].base, &address_space_memory);
448 
449     /* copy in the device tree */
450     if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
451             memmap[VIRT_MROM].size - sizeof(reset_vec)) {
452         error_report("not enough space to store device-tree");
453         exit(1);
454     }
455     qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
456     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
457                           memmap[VIRT_MROM].base + sizeof(reset_vec),
458                           &address_space_memory);
459 
460     /* create PLIC hart topology configuration string */
461     plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
462     plic_hart_config = g_malloc0(plic_hart_config_len);
463     for (i = 0; i < smp_cpus; i++) {
464         if (i != 0) {
465             strncat(plic_hart_config, ",", plic_hart_config_len);
466         }
467         strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
468         plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
469     }
470 
471     /* MMIO */
472     s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
473         plic_hart_config,
474         VIRT_PLIC_NUM_SOURCES,
475         VIRT_PLIC_NUM_PRIORITIES,
476         VIRT_PLIC_PRIORITY_BASE,
477         VIRT_PLIC_PENDING_BASE,
478         VIRT_PLIC_ENABLE_BASE,
479         VIRT_PLIC_ENABLE_STRIDE,
480         VIRT_PLIC_CONTEXT_BASE,
481         VIRT_PLIC_CONTEXT_STRIDE,
482         memmap[VIRT_PLIC].size);
483     sifive_clint_create(memmap[VIRT_CLINT].base,
484         memmap[VIRT_CLINT].size, smp_cpus,
485         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
486     sifive_test_create(memmap[VIRT_TEST].base);
487 
488     for (i = 0; i < VIRTIO_COUNT; i++) {
489         sysbus_create_simple("virtio-mmio",
490             memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
491             qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
492     }
493 
494     gpex_pcie_init(system_memory,
495                          memmap[VIRT_PCIE_ECAM].base,
496                          memmap[VIRT_PCIE_ECAM].size,
497                          memmap[VIRT_PCIE_MMIO].base,
498                          memmap[VIRT_PCIE_MMIO].size,
499                          memmap[VIRT_PCIE_PIO].base,
500                          DEVICE(s->plic), true);
501 
502     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
503         0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
504         serial_hd(0), DEVICE_LITTLE_ENDIAN);
505 
506     g_free(plic_hart_config);
507 }
508 
509 static void riscv_virt_board_machine_init(MachineClass *mc)
510 {
511     mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
512     mc->init = riscv_virt_board_init;
513     mc->max_cpus = 8; /* hardcoded limit in BBL */
514     mc->default_cpu_type = VIRT_CPU;
515 }
516 
517 DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
518