1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/log.h" 24 #include "qemu/error-report.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/riscv/riscv_hart.h" 33 #include "hw/riscv/virt.h" 34 #include "hw/riscv/boot.h" 35 #include "hw/riscv/numa.h" 36 #include "hw/intc/sifive_clint.h" 37 #include "hw/intc/sifive_plic.h" 38 #include "hw/misc/sifive_test.h" 39 #include "chardev/char.h" 40 #include "sysemu/arch_init.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/sysemu.h" 43 #include "hw/pci/pci.h" 44 #include "hw/pci-host/gpex.h" 45 46 #if defined(TARGET_RISCV32) 47 # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" 48 #else 49 # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" 50 #endif 51 52 static const struct MemmapEntry { 53 hwaddr base; 54 hwaddr size; 55 } virt_memmap[] = { 56 [VIRT_DEBUG] = { 0x0, 0x100 }, 57 [VIRT_MROM] = { 0x1000, 0xf000 }, 58 [VIRT_TEST] = { 0x100000, 0x1000 }, 59 [VIRT_RTC] = { 0x101000, 0x1000 }, 60 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 61 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 62 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 63 [VIRT_UART0] = { 0x10000000, 0x100 }, 64 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 65 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 66 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 67 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 68 [VIRT_DRAM] = { 0x80000000, 0x0 }, 69 }; 70 71 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 72 73 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 74 const char *name, 75 const char *alias_prop_name) 76 { 77 /* 78 * Create a single flash device. We use the same parameters as 79 * the flash devices on the ARM virt board. 80 */ 81 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 82 83 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 84 qdev_prop_set_uint8(dev, "width", 4); 85 qdev_prop_set_uint8(dev, "device-width", 2); 86 qdev_prop_set_bit(dev, "big-endian", false); 87 qdev_prop_set_uint16(dev, "id0", 0x89); 88 qdev_prop_set_uint16(dev, "id1", 0x18); 89 qdev_prop_set_uint16(dev, "id2", 0x00); 90 qdev_prop_set_uint16(dev, "id3", 0x00); 91 qdev_prop_set_string(dev, "name", name); 92 93 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 94 object_property_add_alias(OBJECT(s), alias_prop_name, 95 OBJECT(dev), "drive"); 96 97 return PFLASH_CFI01(dev); 98 } 99 100 static void virt_flash_create(RISCVVirtState *s) 101 { 102 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 103 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 104 } 105 106 static void virt_flash_map1(PFlashCFI01 *flash, 107 hwaddr base, hwaddr size, 108 MemoryRegion *sysmem) 109 { 110 DeviceState *dev = DEVICE(flash); 111 112 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 113 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 114 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 115 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 116 117 memory_region_add_subregion(sysmem, base, 118 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 119 0)); 120 } 121 122 static void virt_flash_map(RISCVVirtState *s, 123 MemoryRegion *sysmem) 124 { 125 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 126 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 127 128 virt_flash_map1(s->flash[0], flashbase, flashsize, 129 sysmem); 130 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 131 sysmem); 132 } 133 134 static void create_pcie_irq_map(void *fdt, char *nodename, 135 uint32_t plic_phandle) 136 { 137 int pin, dev; 138 uint32_t 139 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; 140 uint32_t *irq_map = full_irq_map; 141 142 /* This code creates a standard swizzle of interrupts such that 143 * each device's first interrupt is based on it's PCI_SLOT number. 144 * (See pci_swizzle_map_irq_fn()) 145 * 146 * We only need one entry per interrupt in the table (not one per 147 * possible slot) seeing the interrupt-map-mask will allow the table 148 * to wrap to any number of devices. 149 */ 150 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 151 int devfn = dev * 0x8; 152 153 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 154 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 155 int i = 0; 156 157 irq_map[i] = cpu_to_be32(devfn << 8); 158 159 i += FDT_PCI_ADDR_CELLS; 160 irq_map[i] = cpu_to_be32(pin + 1); 161 162 i += FDT_PCI_INT_CELLS; 163 irq_map[i++] = cpu_to_be32(plic_phandle); 164 165 i += FDT_PLIC_ADDR_CELLS; 166 irq_map[i] = cpu_to_be32(irq_nr); 167 168 irq_map += FDT_INT_MAP_WIDTH; 169 } 170 } 171 172 qemu_fdt_setprop(fdt, nodename, "interrupt-map", 173 full_irq_map, sizeof(full_irq_map)); 174 175 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 176 0x1800, 0, 0, 0x7); 177 } 178 179 static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, 180 uint64_t mem_size, const char *cmdline) 181 { 182 void *fdt; 183 int i, cpu, socket; 184 MachineState *mc = MACHINE(s); 185 uint64_t addr, size; 186 uint32_t *clint_cells, *plic_cells; 187 unsigned long clint_addr, plic_addr; 188 uint32_t plic_phandle[MAX_NODES]; 189 uint32_t cpu_phandle, intc_phandle, test_phandle; 190 uint32_t phandle = 1, plic_mmio_phandle = 1; 191 uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; 192 char *mem_name, *cpu_name, *core_name, *intc_name; 193 char *name, *clint_name, *plic_name, *clust_name; 194 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 195 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 196 197 if (mc->dtb) { 198 fdt = s->fdt = load_device_tree(mc->dtb, &s->fdt_size); 199 if (!fdt) { 200 error_report("load_device_tree() failed"); 201 exit(1); 202 } 203 goto update_bootargs; 204 } else { 205 fdt = s->fdt = create_device_tree(&s->fdt_size); 206 if (!fdt) { 207 error_report("create_device_tree() failed"); 208 exit(1); 209 } 210 } 211 212 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); 213 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); 214 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 215 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 216 217 qemu_fdt_add_subnode(fdt, "/soc"); 218 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 219 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 220 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 221 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 222 223 qemu_fdt_add_subnode(fdt, "/cpus"); 224 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 225 SIFIVE_CLINT_TIMEBASE_FREQ); 226 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 227 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 228 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 229 230 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 231 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 232 qemu_fdt_add_subnode(fdt, clust_name); 233 234 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 235 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 236 237 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 238 cpu_phandle = phandle++; 239 240 cpu_name = g_strdup_printf("/cpus/cpu@%d", 241 s->soc[socket].hartid_base + cpu); 242 qemu_fdt_add_subnode(fdt, cpu_name); 243 #if defined(TARGET_RISCV32) 244 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 245 #else 246 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 247 #endif 248 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 249 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 250 g_free(name); 251 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 252 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 253 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 254 s->soc[socket].hartid_base + cpu); 255 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 256 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 257 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 258 259 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 260 qemu_fdt_add_subnode(fdt, intc_name); 261 intc_phandle = phandle++; 262 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 263 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 264 "riscv,cpu-intc"); 265 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 266 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 267 268 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 269 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 270 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 271 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 272 273 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 274 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 275 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 276 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 277 278 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 279 qemu_fdt_add_subnode(fdt, core_name); 280 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 281 282 g_free(core_name); 283 g_free(intc_name); 284 g_free(cpu_name); 285 } 286 287 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 288 size = riscv_socket_mem_size(mc, socket); 289 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 290 qemu_fdt_add_subnode(fdt, mem_name); 291 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 292 addr >> 32, addr, size >> 32, size); 293 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 294 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 295 g_free(mem_name); 296 297 clint_addr = memmap[VIRT_CLINT].base + 298 (memmap[VIRT_CLINT].size * socket); 299 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 300 qemu_fdt_add_subnode(fdt, clint_name); 301 qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); 302 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 303 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 304 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 305 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 306 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 307 g_free(clint_name); 308 309 plic_phandle[socket] = phandle++; 310 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 311 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 312 qemu_fdt_add_subnode(fdt, plic_name); 313 qemu_fdt_setprop_cell(fdt, plic_name, 314 "#address-cells", FDT_PLIC_ADDR_CELLS); 315 qemu_fdt_setprop_cell(fdt, plic_name, 316 "#interrupt-cells", FDT_PLIC_INT_CELLS); 317 qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); 318 qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); 319 qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", 320 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 321 qemu_fdt_setprop_cells(fdt, plic_name, "reg", 322 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 323 qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 324 riscv_socket_fdt_write_id(mc, fdt, plic_name, socket); 325 qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]); 326 g_free(plic_name); 327 328 g_free(clint_cells); 329 g_free(plic_cells); 330 g_free(clust_name); 331 } 332 333 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 334 if (socket == 0) { 335 plic_mmio_phandle = plic_phandle[socket]; 336 plic_virtio_phandle = plic_phandle[socket]; 337 plic_pcie_phandle = plic_phandle[socket]; 338 } 339 if (socket == 1) { 340 plic_virtio_phandle = plic_phandle[socket]; 341 plic_pcie_phandle = plic_phandle[socket]; 342 } 343 if (socket == 2) { 344 plic_pcie_phandle = plic_phandle[socket]; 345 } 346 } 347 348 riscv_socket_fdt_write_distance_matrix(mc, fdt); 349 350 for (i = 0; i < VIRTIO_COUNT; i++) { 351 name = g_strdup_printf("/soc/virtio_mmio@%lx", 352 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 353 qemu_fdt_add_subnode(fdt, name); 354 qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); 355 qemu_fdt_setprop_cells(fdt, name, "reg", 356 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 357 0x0, memmap[VIRT_VIRTIO].size); 358 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", 359 plic_virtio_phandle); 360 qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); 361 g_free(name); 362 } 363 364 name = g_strdup_printf("/soc/pci@%lx", 365 (long) memmap[VIRT_PCIE_ECAM].base); 366 qemu_fdt_add_subnode(fdt, name); 367 qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); 368 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); 369 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); 370 qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); 371 qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); 372 qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); 373 qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, 374 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 375 qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); 376 qemu_fdt_setprop_cells(fdt, name, "reg", 0, 377 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 378 qemu_fdt_setprop_sized_cells(fdt, name, "ranges", 379 1, FDT_PCI_RANGE_IOPORT, 2, 0, 380 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 381 1, FDT_PCI_RANGE_MMIO, 382 2, memmap[VIRT_PCIE_MMIO].base, 383 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); 384 create_pcie_irq_map(fdt, name, plic_pcie_phandle); 385 g_free(name); 386 387 test_phandle = phandle++; 388 name = g_strdup_printf("/soc/test@%lx", 389 (long)memmap[VIRT_TEST].base); 390 qemu_fdt_add_subnode(fdt, name); 391 { 392 const char compat[] = "sifive,test1\0sifive,test0\0syscon"; 393 qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat)); 394 } 395 qemu_fdt_setprop_cells(fdt, name, "reg", 396 0x0, memmap[VIRT_TEST].base, 397 0x0, memmap[VIRT_TEST].size); 398 qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); 399 test_phandle = qemu_fdt_get_phandle(fdt, name); 400 g_free(name); 401 402 name = g_strdup_printf("/soc/reboot"); 403 qemu_fdt_add_subnode(fdt, name); 404 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); 405 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 406 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 407 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); 408 g_free(name); 409 410 name = g_strdup_printf("/soc/poweroff"); 411 qemu_fdt_add_subnode(fdt, name); 412 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); 413 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 414 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 415 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); 416 g_free(name); 417 418 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 419 qemu_fdt_add_subnode(fdt, name); 420 qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); 421 qemu_fdt_setprop_cells(fdt, name, "reg", 422 0x0, memmap[VIRT_UART0].base, 423 0x0, memmap[VIRT_UART0].size); 424 qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); 425 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 426 qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); 427 428 qemu_fdt_add_subnode(fdt, "/chosen"); 429 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); 430 g_free(name); 431 432 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 433 qemu_fdt_add_subnode(fdt, name); 434 qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); 435 qemu_fdt_setprop_cells(fdt, name, "reg", 436 0x0, memmap[VIRT_RTC].base, 437 0x0, memmap[VIRT_RTC].size); 438 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 439 qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); 440 g_free(name); 441 442 name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); 443 qemu_fdt_add_subnode(s->fdt, name); 444 qemu_fdt_setprop_string(s->fdt, name, "compatible", "cfi-flash"); 445 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 446 2, flashbase, 2, flashsize, 447 2, flashbase + flashsize, 2, flashsize); 448 qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4); 449 g_free(name); 450 451 update_bootargs: 452 if (cmdline) { 453 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 454 } 455 } 456 457 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 458 hwaddr ecam_base, hwaddr ecam_size, 459 hwaddr mmio_base, hwaddr mmio_size, 460 hwaddr pio_base, 461 DeviceState *plic, bool link_up) 462 { 463 DeviceState *dev; 464 MemoryRegion *ecam_alias, *ecam_reg; 465 MemoryRegion *mmio_alias, *mmio_reg; 466 qemu_irq irq; 467 int i; 468 469 dev = qdev_new(TYPE_GPEX_HOST); 470 471 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 472 473 ecam_alias = g_new0(MemoryRegion, 1); 474 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 475 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 476 ecam_reg, 0, ecam_size); 477 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 478 479 mmio_alias = g_new0(MemoryRegion, 1); 480 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 481 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 482 mmio_reg, mmio_base, mmio_size); 483 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 484 485 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 486 487 for (i = 0; i < GPEX_NUM_IRQS; i++) { 488 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); 489 490 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 491 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 492 } 493 494 return dev; 495 } 496 497 static void virt_machine_init(MachineState *machine) 498 { 499 const struct MemmapEntry *memmap = virt_memmap; 500 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 501 MemoryRegion *system_memory = get_system_memory(); 502 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 503 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 504 char *plic_hart_config, *soc_name; 505 size_t plic_hart_config_len; 506 target_ulong start_addr = memmap[VIRT_DRAM].base; 507 target_ulong firmware_end_addr, kernel_start_addr; 508 uint32_t fdt_load_addr; 509 uint64_t kernel_entry; 510 DeviceState *mmio_plic, *virtio_plic, *pcie_plic; 511 int i, j, base_hartid, hart_count; 512 513 /* Check socket count limit */ 514 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 515 error_report("number of sockets/nodes should be less than %d", 516 VIRT_SOCKETS_MAX); 517 exit(1); 518 } 519 520 /* Initialize sockets */ 521 mmio_plic = virtio_plic = pcie_plic = NULL; 522 for (i = 0; i < riscv_socket_count(machine); i++) { 523 if (!riscv_socket_check_hartids(machine, i)) { 524 error_report("discontinuous hartids in socket%d", i); 525 exit(1); 526 } 527 528 base_hartid = riscv_socket_first_hartid(machine, i); 529 if (base_hartid < 0) { 530 error_report("can't find hartid base for socket%d", i); 531 exit(1); 532 } 533 534 hart_count = riscv_socket_hart_count(machine, i); 535 if (hart_count < 0) { 536 error_report("can't find hart count for socket%d", i); 537 exit(1); 538 } 539 540 soc_name = g_strdup_printf("soc%d", i); 541 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 542 TYPE_RISCV_HART_ARRAY); 543 g_free(soc_name); 544 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 545 machine->cpu_type, &error_abort); 546 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 547 base_hartid, &error_abort); 548 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 549 hart_count, &error_abort); 550 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 551 552 /* Per-socket CLINT */ 553 sifive_clint_create( 554 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 555 memmap[VIRT_CLINT].size, base_hartid, hart_count, 556 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 557 SIFIVE_CLINT_TIMEBASE_FREQ, true); 558 559 /* Per-socket PLIC hart topology configuration string */ 560 plic_hart_config_len = 561 (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count; 562 plic_hart_config = g_malloc0(plic_hart_config_len); 563 for (j = 0; j < hart_count; j++) { 564 if (j != 0) { 565 strncat(plic_hart_config, ",", plic_hart_config_len); 566 } 567 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, 568 plic_hart_config_len); 569 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); 570 } 571 572 /* Per-socket PLIC */ 573 s->plic[i] = sifive_plic_create( 574 memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, 575 plic_hart_config, base_hartid, 576 VIRT_PLIC_NUM_SOURCES, 577 VIRT_PLIC_NUM_PRIORITIES, 578 VIRT_PLIC_PRIORITY_BASE, 579 VIRT_PLIC_PENDING_BASE, 580 VIRT_PLIC_ENABLE_BASE, 581 VIRT_PLIC_ENABLE_STRIDE, 582 VIRT_PLIC_CONTEXT_BASE, 583 VIRT_PLIC_CONTEXT_STRIDE, 584 memmap[VIRT_PLIC].size); 585 g_free(plic_hart_config); 586 587 /* Try to use different PLIC instance based device type */ 588 if (i == 0) { 589 mmio_plic = s->plic[i]; 590 virtio_plic = s->plic[i]; 591 pcie_plic = s->plic[i]; 592 } 593 if (i == 1) { 594 virtio_plic = s->plic[i]; 595 pcie_plic = s->plic[i]; 596 } 597 if (i == 2) { 598 pcie_plic = s->plic[i]; 599 } 600 } 601 602 /* register system main memory (actual RAM) */ 603 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", 604 machine->ram_size, &error_fatal); 605 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 606 main_mem); 607 608 /* create device tree */ 609 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 610 611 /* boot rom */ 612 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 613 memmap[VIRT_MROM].size, &error_fatal); 614 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 615 mask_rom); 616 617 firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, 618 start_addr, NULL); 619 620 if (machine->kernel_filename) { 621 kernel_start_addr = riscv_calc_kernel_start_addr(machine, 622 firmware_end_addr); 623 624 kernel_entry = riscv_load_kernel(machine->kernel_filename, 625 kernel_start_addr, NULL); 626 627 if (machine->initrd_filename) { 628 hwaddr start; 629 hwaddr end = riscv_load_initrd(machine->initrd_filename, 630 machine->ram_size, kernel_entry, 631 &start); 632 qemu_fdt_setprop_cell(s->fdt, "/chosen", 633 "linux,initrd-start", start); 634 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 635 end); 636 } 637 } else { 638 /* 639 * If dynamic firmware is used, it doesn't know where is the next mode 640 * if kernel argument is not set. 641 */ 642 kernel_entry = 0; 643 } 644 645 if (drive_get(IF_PFLASH, 0, 0)) { 646 /* 647 * Pflash was supplied, let's overwrite the address we jump to after 648 * reset to the base of the flash. 649 */ 650 start_addr = virt_memmap[VIRT_FLASH].base; 651 } 652 653 /* Compute the fdt load address in dram */ 654 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 655 machine->ram_size, s->fdt); 656 /* load the reset vector */ 657 riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, 658 virt_memmap[VIRT_MROM].size, kernel_entry, 659 fdt_load_addr, s->fdt); 660 661 /* SiFive Test MMIO device */ 662 sifive_test_create(memmap[VIRT_TEST].base); 663 664 /* VirtIO MMIO devices */ 665 for (i = 0; i < VIRTIO_COUNT; i++) { 666 sysbus_create_simple("virtio-mmio", 667 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 668 qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); 669 } 670 671 gpex_pcie_init(system_memory, 672 memmap[VIRT_PCIE_ECAM].base, 673 memmap[VIRT_PCIE_ECAM].size, 674 memmap[VIRT_PCIE_MMIO].base, 675 memmap[VIRT_PCIE_MMIO].size, 676 memmap[VIRT_PCIE_PIO].base, 677 DEVICE(pcie_plic), true); 678 679 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 680 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, 681 serial_hd(0), DEVICE_LITTLE_ENDIAN); 682 683 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 684 qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); 685 686 virt_flash_create(s); 687 688 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 689 /* Map legacy -drive if=pflash to machine properties */ 690 pflash_cfi01_legacy_drive(s->flash[i], 691 drive_get(IF_PFLASH, 0, i)); 692 } 693 virt_flash_map(s, system_memory); 694 } 695 696 static void virt_machine_instance_init(Object *obj) 697 { 698 } 699 700 static void virt_machine_class_init(ObjectClass *oc, void *data) 701 { 702 MachineClass *mc = MACHINE_CLASS(oc); 703 704 mc->desc = "RISC-V VirtIO board"; 705 mc->init = virt_machine_init; 706 mc->max_cpus = VIRT_CPUS_MAX; 707 mc->default_cpu_type = VIRT_CPU; 708 mc->pci_allow_0_address = true; 709 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 710 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 711 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 712 mc->numa_mem_supported = true; 713 } 714 715 static const TypeInfo virt_machine_typeinfo = { 716 .name = MACHINE_TYPE_NAME("virt"), 717 .parent = TYPE_MACHINE, 718 .class_init = virt_machine_class_init, 719 .instance_init = virt_machine_instance_init, 720 .instance_size = sizeof(RISCVVirtState), 721 }; 722 723 static void virt_machine_init_register_types(void) 724 { 725 type_register_static(&virt_machine_typeinfo); 726 } 727 728 type_init(virt_machine_init_register_types) 729