1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "kvm/kvm_riscv.h" 39 #include "hw/firmware/smbios.h" 40 #include "hw/intc/riscv_aclint.h" 41 #include "hw/intc/riscv_aplic.h" 42 #include "hw/intc/sifive_plic.h" 43 #include "hw/misc/sifive_test.h" 44 #include "hw/platform-bus.h" 45 #include "chardev/char.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/sysemu.h" 48 #include "sysemu/tcg.h" 49 #include "sysemu/kvm.h" 50 #include "sysemu/tpm.h" 51 #include "sysemu/qtest.h" 52 #include "hw/pci/pci.h" 53 #include "hw/pci-host/gpex.h" 54 #include "hw/display/ramfb.h" 55 #include "hw/acpi/aml-build.h" 56 #include "qapi/qapi-visit-common.h" 57 #include "hw/virtio/virtio-iommu.h" 58 59 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 60 static bool virt_use_kvm_aia(RISCVVirtState *s) 61 { 62 return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 63 } 64 65 static bool virt_aclint_allowed(void) 66 { 67 return tcg_enabled() || qtest_enabled(); 68 } 69 70 static const MemMapEntry virt_memmap[] = { 71 [VIRT_DEBUG] = { 0x0, 0x100 }, 72 [VIRT_MROM] = { 0x1000, 0xf000 }, 73 [VIRT_TEST] = { 0x100000, 0x1000 }, 74 [VIRT_RTC] = { 0x101000, 0x1000 }, 75 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 76 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 77 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 78 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 79 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 80 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 81 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 82 [VIRT_UART0] = { 0x10000000, 0x100 }, 83 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 84 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 85 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 86 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 87 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 88 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 89 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 90 [VIRT_DRAM] = { 0x80000000, 0x0 }, 91 }; 92 93 /* PCIe high mmio is fixed for RV32 */ 94 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 95 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 96 97 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 98 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 99 100 static MemMapEntry virt_high_pcie_memmap; 101 102 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 103 104 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 105 const char *name, 106 const char *alias_prop_name) 107 { 108 /* 109 * Create a single flash device. We use the same parameters as 110 * the flash devices on the ARM virt board. 111 */ 112 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 113 114 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 115 qdev_prop_set_uint8(dev, "width", 4); 116 qdev_prop_set_uint8(dev, "device-width", 2); 117 qdev_prop_set_bit(dev, "big-endian", false); 118 qdev_prop_set_uint16(dev, "id0", 0x89); 119 qdev_prop_set_uint16(dev, "id1", 0x18); 120 qdev_prop_set_uint16(dev, "id2", 0x00); 121 qdev_prop_set_uint16(dev, "id3", 0x00); 122 qdev_prop_set_string(dev, "name", name); 123 124 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 125 object_property_add_alias(OBJECT(s), alias_prop_name, 126 OBJECT(dev), "drive"); 127 128 return PFLASH_CFI01(dev); 129 } 130 131 static void virt_flash_create(RISCVVirtState *s) 132 { 133 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 134 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 135 } 136 137 static void virt_flash_map1(PFlashCFI01 *flash, 138 hwaddr base, hwaddr size, 139 MemoryRegion *sysmem) 140 { 141 DeviceState *dev = DEVICE(flash); 142 143 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 144 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 145 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 146 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 147 148 memory_region_add_subregion(sysmem, base, 149 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 150 0)); 151 } 152 153 static void virt_flash_map(RISCVVirtState *s, 154 MemoryRegion *sysmem) 155 { 156 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 157 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 158 159 virt_flash_map1(s->flash[0], flashbase, flashsize, 160 sysmem); 161 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 162 sysmem); 163 } 164 165 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 166 uint32_t irqchip_phandle) 167 { 168 int pin, dev; 169 uint32_t irq_map_stride = 0; 170 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 171 FDT_MAX_INT_MAP_WIDTH] = {}; 172 uint32_t *irq_map = full_irq_map; 173 174 /* This code creates a standard swizzle of interrupts such that 175 * each device's first interrupt is based on it's PCI_SLOT number. 176 * (See pci_swizzle_map_irq_fn()) 177 * 178 * We only need one entry per interrupt in the table (not one per 179 * possible slot) seeing the interrupt-map-mask will allow the table 180 * to wrap to any number of devices. 181 */ 182 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 183 int devfn = dev * 0x8; 184 185 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 186 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 187 int i = 0; 188 189 /* Fill PCI address cells */ 190 irq_map[i] = cpu_to_be32(devfn << 8); 191 i += FDT_PCI_ADDR_CELLS; 192 193 /* Fill PCI Interrupt cells */ 194 irq_map[i] = cpu_to_be32(pin + 1); 195 i += FDT_PCI_INT_CELLS; 196 197 /* Fill interrupt controller phandle and cells */ 198 irq_map[i++] = cpu_to_be32(irqchip_phandle); 199 irq_map[i++] = cpu_to_be32(irq_nr); 200 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 201 irq_map[i++] = cpu_to_be32(0x4); 202 } 203 204 if (!irq_map_stride) { 205 irq_map_stride = i; 206 } 207 irq_map += irq_map_stride; 208 } 209 } 210 211 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 212 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 213 irq_map_stride * sizeof(uint32_t)); 214 215 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 216 0x1800, 0, 0, 0x7); 217 } 218 219 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 220 char *clust_name, uint32_t *phandle, 221 uint32_t *intc_phandles) 222 { 223 int cpu; 224 uint32_t cpu_phandle; 225 MachineState *ms = MACHINE(s); 226 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 227 uint8_t satp_mode_max; 228 229 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 230 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 231 g_autofree char *cpu_name = NULL; 232 g_autofree char *core_name = NULL; 233 g_autofree char *intc_name = NULL; 234 g_autofree char *sv_name = NULL; 235 236 cpu_phandle = (*phandle)++; 237 238 cpu_name = g_strdup_printf("/cpus/cpu@%d", 239 s->soc[socket].hartid_base + cpu); 240 qemu_fdt_add_subnode(ms->fdt, cpu_name); 241 242 if (cpu_ptr->cfg.satp_mode.supported != 0) { 243 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 244 sv_name = g_strdup_printf("riscv,%s", 245 satp_mode_str(satp_mode_max, is_32_bit)); 246 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 247 } 248 249 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); 250 251 if (cpu_ptr->cfg.ext_zicbom) { 252 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 253 cpu_ptr->cfg.cbom_blocksize); 254 } 255 256 if (cpu_ptr->cfg.ext_zicboz) { 257 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 258 cpu_ptr->cfg.cboz_blocksize); 259 } 260 261 if (cpu_ptr->cfg.ext_zicbop) { 262 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 263 cpu_ptr->cfg.cbop_blocksize); 264 } 265 266 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 267 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 268 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 269 s->soc[socket].hartid_base + cpu); 270 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 271 riscv_socket_fdt_write_id(ms, cpu_name, socket); 272 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 273 274 intc_phandles[cpu] = (*phandle)++; 275 276 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 277 qemu_fdt_add_subnode(ms->fdt, intc_name); 278 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 279 intc_phandles[cpu]); 280 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 281 "riscv,cpu-intc"); 282 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 283 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 284 285 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 286 qemu_fdt_add_subnode(ms->fdt, core_name); 287 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 288 } 289 } 290 291 static void create_fdt_socket_memory(RISCVVirtState *s, 292 const MemMapEntry *memmap, int socket) 293 { 294 g_autofree char *mem_name = NULL; 295 uint64_t addr, size; 296 MachineState *ms = MACHINE(s); 297 298 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 299 size = riscv_socket_mem_size(ms, socket); 300 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 301 qemu_fdt_add_subnode(ms->fdt, mem_name); 302 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 303 addr >> 32, addr, size >> 32, size); 304 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 305 riscv_socket_fdt_write_id(ms, mem_name, socket); 306 } 307 308 static void create_fdt_socket_clint(RISCVVirtState *s, 309 const MemMapEntry *memmap, int socket, 310 uint32_t *intc_phandles) 311 { 312 int cpu; 313 g_autofree char *clint_name = NULL; 314 g_autofree uint32_t *clint_cells = NULL; 315 unsigned long clint_addr; 316 MachineState *ms = MACHINE(s); 317 static const char * const clint_compat[2] = { 318 "sifive,clint0", "riscv,clint0" 319 }; 320 321 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 322 323 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 324 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 325 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 326 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 327 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 328 } 329 330 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 331 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 332 qemu_fdt_add_subnode(ms->fdt, clint_name); 333 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 334 (char **)&clint_compat, 335 ARRAY_SIZE(clint_compat)); 336 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 337 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 338 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 339 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 340 riscv_socket_fdt_write_id(ms, clint_name, socket); 341 } 342 343 static void create_fdt_socket_aclint(RISCVVirtState *s, 344 const MemMapEntry *memmap, int socket, 345 uint32_t *intc_phandles) 346 { 347 int cpu; 348 char *name; 349 unsigned long addr, size; 350 uint32_t aclint_cells_size; 351 g_autofree uint32_t *aclint_mswi_cells = NULL; 352 g_autofree uint32_t *aclint_sswi_cells = NULL; 353 g_autofree uint32_t *aclint_mtimer_cells = NULL; 354 MachineState *ms = MACHINE(s); 355 356 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 357 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 358 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 359 360 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 361 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 362 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 363 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 364 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 365 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 366 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 367 } 368 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 369 370 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 371 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 372 name = g_strdup_printf("/soc/mswi@%lx", addr); 373 qemu_fdt_add_subnode(ms->fdt, name); 374 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 375 "riscv,aclint-mswi"); 376 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 377 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 378 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 379 aclint_mswi_cells, aclint_cells_size); 380 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 381 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 382 riscv_socket_fdt_write_id(ms, name, socket); 383 g_free(name); 384 } 385 386 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 387 addr = memmap[VIRT_CLINT].base + 388 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 389 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 390 } else { 391 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 392 (memmap[VIRT_CLINT].size * socket); 393 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 394 } 395 name = g_strdup_printf("/soc/mtimer@%lx", addr); 396 qemu_fdt_add_subnode(ms->fdt, name); 397 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 398 "riscv,aclint-mtimer"); 399 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 400 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 401 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 402 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 403 0x0, RISCV_ACLINT_DEFAULT_MTIME); 404 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 405 aclint_mtimer_cells, aclint_cells_size); 406 riscv_socket_fdt_write_id(ms, name, socket); 407 g_free(name); 408 409 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 410 addr = memmap[VIRT_ACLINT_SSWI].base + 411 (memmap[VIRT_ACLINT_SSWI].size * socket); 412 name = g_strdup_printf("/soc/sswi@%lx", addr); 413 qemu_fdt_add_subnode(ms->fdt, name); 414 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 415 "riscv,aclint-sswi"); 416 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 417 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 418 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 419 aclint_sswi_cells, aclint_cells_size); 420 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 421 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 422 riscv_socket_fdt_write_id(ms, name, socket); 423 g_free(name); 424 } 425 } 426 427 static void create_fdt_socket_plic(RISCVVirtState *s, 428 const MemMapEntry *memmap, int socket, 429 uint32_t *phandle, uint32_t *intc_phandles, 430 uint32_t *plic_phandles) 431 { 432 int cpu; 433 g_autofree char *plic_name = NULL; 434 g_autofree uint32_t *plic_cells; 435 unsigned long plic_addr; 436 MachineState *ms = MACHINE(s); 437 static const char * const plic_compat[2] = { 438 "sifive,plic-1.0.0", "riscv,plic0" 439 }; 440 441 plic_phandles[socket] = (*phandle)++; 442 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 443 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 444 qemu_fdt_add_subnode(ms->fdt, plic_name); 445 qemu_fdt_setprop_cell(ms->fdt, plic_name, 446 "#interrupt-cells", FDT_PLIC_INT_CELLS); 447 qemu_fdt_setprop_cell(ms->fdt, plic_name, 448 "#address-cells", FDT_PLIC_ADDR_CELLS); 449 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 450 (char **)&plic_compat, 451 ARRAY_SIZE(plic_compat)); 452 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 453 454 if (kvm_enabled()) { 455 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 456 457 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 458 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 459 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 460 } 461 462 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 463 plic_cells, 464 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 465 } else { 466 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 467 468 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 469 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 470 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 471 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 472 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 473 } 474 475 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 476 plic_cells, 477 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 478 } 479 480 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 481 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 482 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 483 VIRT_IRQCHIP_NUM_SOURCES - 1); 484 riscv_socket_fdt_write_id(ms, plic_name, socket); 485 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 486 plic_phandles[socket]); 487 488 if (!socket) { 489 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 490 memmap[VIRT_PLATFORM_BUS].base, 491 memmap[VIRT_PLATFORM_BUS].size, 492 VIRT_PLATFORM_BUS_IRQ); 493 } 494 } 495 496 uint32_t imsic_num_bits(uint32_t count) 497 { 498 uint32_t ret = 0; 499 500 while (BIT(ret) < count) { 501 ret++; 502 } 503 504 return ret; 505 } 506 507 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 508 uint32_t *intc_phandles, uint32_t msi_phandle, 509 bool m_mode, uint32_t imsic_guest_bits) 510 { 511 int cpu, socket; 512 g_autofree char *imsic_name = NULL; 513 MachineState *ms = MACHINE(s); 514 int socket_count = riscv_socket_count(ms); 515 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 516 g_autofree uint32_t *imsic_cells = NULL; 517 g_autofree uint32_t *imsic_regs = NULL; 518 static const char * const imsic_compat[2] = { 519 "qemu,imsics", "riscv,imsics" 520 }; 521 522 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 523 imsic_regs = g_new0(uint32_t, socket_count * 4); 524 525 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 526 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 527 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 528 } 529 530 imsic_max_hart_per_socket = 0; 531 for (socket = 0; socket < socket_count; socket++) { 532 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 533 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 534 s->soc[socket].num_harts; 535 imsic_regs[socket * 4 + 0] = 0; 536 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 537 imsic_regs[socket * 4 + 2] = 0; 538 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 539 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 540 imsic_max_hart_per_socket = s->soc[socket].num_harts; 541 } 542 } 543 544 imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx", 545 (unsigned long)base_addr); 546 qemu_fdt_add_subnode(ms->fdt, imsic_name); 547 qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", 548 (char **)&imsic_compat, 549 ARRAY_SIZE(imsic_compat)); 550 551 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 552 FDT_IMSIC_INT_CELLS); 553 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 554 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 555 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#msi-cells", 0); 556 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 557 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 558 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 559 socket_count * sizeof(uint32_t) * 4); 560 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 561 VIRT_IRQCHIP_NUM_MSIS); 562 563 if (imsic_guest_bits) { 564 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 565 imsic_guest_bits); 566 } 567 568 if (socket_count > 1) { 569 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 570 imsic_num_bits(imsic_max_hart_per_socket)); 571 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 572 imsic_num_bits(socket_count)); 573 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 574 IMSIC_MMIO_GROUP_MIN_SHIFT); 575 } 576 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 577 } 578 579 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 580 uint32_t *phandle, uint32_t *intc_phandles, 581 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 582 { 583 *msi_m_phandle = (*phandle)++; 584 *msi_s_phandle = (*phandle)++; 585 586 if (!kvm_enabled()) { 587 /* M-level IMSIC node */ 588 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 589 *msi_m_phandle, true, 0); 590 } 591 592 /* S-level IMSIC node */ 593 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 594 *msi_s_phandle, false, 595 imsic_num_bits(s->aia_guests + 1)); 596 597 } 598 599 /* Caller must free string after use */ 600 static char *fdt_get_aplic_nodename(unsigned long aplic_addr) 601 { 602 return g_strdup_printf("/soc/interrupt-controller@%lx", aplic_addr); 603 } 604 605 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 606 unsigned long aplic_addr, uint32_t aplic_size, 607 uint32_t msi_phandle, 608 uint32_t *intc_phandles, 609 uint32_t aplic_phandle, 610 uint32_t aplic_child_phandle, 611 bool m_mode, int num_harts) 612 { 613 int cpu; 614 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 615 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 616 MachineState *ms = MACHINE(s); 617 static const char * const aplic_compat[2] = { 618 "qemu,aplic", "riscv,aplic" 619 }; 620 621 for (cpu = 0; cpu < num_harts; cpu++) { 622 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 623 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 624 } 625 626 qemu_fdt_add_subnode(ms->fdt, aplic_name); 627 qemu_fdt_setprop_string_array(ms->fdt, aplic_name, "compatible", 628 (char **)&aplic_compat, 629 ARRAY_SIZE(aplic_compat)); 630 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells", 631 FDT_APLIC_ADDR_CELLS); 632 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 633 "#interrupt-cells", FDT_APLIC_INT_CELLS); 634 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 635 636 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 637 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 638 aplic_cells, num_harts * sizeof(uint32_t) * 2); 639 } else { 640 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 641 } 642 643 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 644 0x0, aplic_addr, 0x0, aplic_size); 645 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 646 VIRT_IRQCHIP_NUM_SOURCES); 647 648 if (aplic_child_phandle) { 649 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 650 aplic_child_phandle); 651 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation", 652 aplic_child_phandle, 0x1, 653 VIRT_IRQCHIP_NUM_SOURCES); 654 /* 655 * DEPRECATED_9.1: Compat property kept temporarily 656 * to allow old firmwares to work with AIA. Do *not* 657 * use 'riscv,delegate' in new code: use 658 * 'riscv,delegation' instead. 659 */ 660 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 661 aplic_child_phandle, 0x1, 662 VIRT_IRQCHIP_NUM_SOURCES); 663 } 664 665 riscv_socket_fdt_write_id(ms, aplic_name, socket); 666 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 667 } 668 669 static void create_fdt_socket_aplic(RISCVVirtState *s, 670 const MemMapEntry *memmap, int socket, 671 uint32_t msi_m_phandle, 672 uint32_t msi_s_phandle, 673 uint32_t *phandle, 674 uint32_t *intc_phandles, 675 uint32_t *aplic_phandles, 676 int num_harts) 677 { 678 unsigned long aplic_addr; 679 MachineState *ms = MACHINE(s); 680 uint32_t aplic_m_phandle, aplic_s_phandle; 681 682 aplic_m_phandle = (*phandle)++; 683 aplic_s_phandle = (*phandle)++; 684 685 if (!kvm_enabled()) { 686 /* M-level APLIC node */ 687 aplic_addr = memmap[VIRT_APLIC_M].base + 688 (memmap[VIRT_APLIC_M].size * socket); 689 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 690 msi_m_phandle, intc_phandles, 691 aplic_m_phandle, aplic_s_phandle, 692 true, num_harts); 693 } 694 695 /* S-level APLIC node */ 696 aplic_addr = memmap[VIRT_APLIC_S].base + 697 (memmap[VIRT_APLIC_S].size * socket); 698 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 699 msi_s_phandle, intc_phandles, 700 aplic_s_phandle, 0, 701 false, num_harts); 702 703 if (!socket) { 704 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 705 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 706 memmap[VIRT_PLATFORM_BUS].base, 707 memmap[VIRT_PLATFORM_BUS].size, 708 VIRT_PLATFORM_BUS_IRQ); 709 } 710 711 aplic_phandles[socket] = aplic_s_phandle; 712 } 713 714 static void create_fdt_pmu(RISCVVirtState *s) 715 { 716 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 717 MachineState *ms = MACHINE(s); 718 RISCVCPU hart = s->soc[0].harts[0]; 719 720 qemu_fdt_add_subnode(ms->fdt, pmu_name); 721 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 722 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 723 } 724 725 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 726 uint32_t *phandle, 727 uint32_t *irq_mmio_phandle, 728 uint32_t *irq_pcie_phandle, 729 uint32_t *irq_virtio_phandle, 730 uint32_t *msi_pcie_phandle) 731 { 732 int socket, phandle_pos; 733 MachineState *ms = MACHINE(s); 734 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 735 uint32_t xplic_phandles[MAX_NODES]; 736 g_autofree uint32_t *intc_phandles = NULL; 737 int socket_count = riscv_socket_count(ms); 738 739 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 740 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 741 kvm_enabled() ? 742 kvm_riscv_get_timebase_frequency(first_cpu) : 743 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 744 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 745 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 746 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 747 748 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 749 750 phandle_pos = ms->smp.cpus; 751 for (socket = (socket_count - 1); socket >= 0; socket--) { 752 g_autofree char *clust_name = NULL; 753 phandle_pos -= s->soc[socket].num_harts; 754 755 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 756 qemu_fdt_add_subnode(ms->fdt, clust_name); 757 758 create_fdt_socket_cpus(s, socket, clust_name, phandle, 759 &intc_phandles[phandle_pos]); 760 761 create_fdt_socket_memory(s, memmap, socket); 762 763 if (virt_aclint_allowed() && s->have_aclint) { 764 create_fdt_socket_aclint(s, memmap, socket, 765 &intc_phandles[phandle_pos]); 766 } else if (tcg_enabled()) { 767 create_fdt_socket_clint(s, memmap, socket, 768 &intc_phandles[phandle_pos]); 769 } 770 } 771 772 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 773 create_fdt_imsic(s, memmap, phandle, intc_phandles, 774 &msi_m_phandle, &msi_s_phandle); 775 *msi_pcie_phandle = msi_s_phandle; 776 } 777 778 /* KVM AIA only has one APLIC instance */ 779 if (kvm_enabled() && virt_use_kvm_aia(s)) { 780 create_fdt_socket_aplic(s, memmap, 0, 781 msi_m_phandle, msi_s_phandle, phandle, 782 &intc_phandles[0], xplic_phandles, 783 ms->smp.cpus); 784 } else { 785 phandle_pos = ms->smp.cpus; 786 for (socket = (socket_count - 1); socket >= 0; socket--) { 787 phandle_pos -= s->soc[socket].num_harts; 788 789 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 790 create_fdt_socket_plic(s, memmap, socket, phandle, 791 &intc_phandles[phandle_pos], 792 xplic_phandles); 793 } else { 794 create_fdt_socket_aplic(s, memmap, socket, 795 msi_m_phandle, msi_s_phandle, phandle, 796 &intc_phandles[phandle_pos], 797 xplic_phandles, 798 s->soc[socket].num_harts); 799 } 800 } 801 } 802 803 if (kvm_enabled() && virt_use_kvm_aia(s)) { 804 *irq_mmio_phandle = xplic_phandles[0]; 805 *irq_virtio_phandle = xplic_phandles[0]; 806 *irq_pcie_phandle = xplic_phandles[0]; 807 } else { 808 for (socket = 0; socket < socket_count; socket++) { 809 if (socket == 0) { 810 *irq_mmio_phandle = xplic_phandles[socket]; 811 *irq_virtio_phandle = xplic_phandles[socket]; 812 *irq_pcie_phandle = xplic_phandles[socket]; 813 } 814 if (socket == 1) { 815 *irq_virtio_phandle = xplic_phandles[socket]; 816 *irq_pcie_phandle = xplic_phandles[socket]; 817 } 818 if (socket == 2) { 819 *irq_pcie_phandle = xplic_phandles[socket]; 820 } 821 } 822 } 823 824 riscv_socket_fdt_write_distance_matrix(ms); 825 } 826 827 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 828 uint32_t irq_virtio_phandle) 829 { 830 int i; 831 MachineState *ms = MACHINE(s); 832 833 for (i = 0; i < VIRTIO_COUNT; i++) { 834 g_autofree char *name = g_strdup_printf("/soc/virtio_mmio@%lx", 835 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 836 837 qemu_fdt_add_subnode(ms->fdt, name); 838 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 839 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 840 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 841 0x0, memmap[VIRT_VIRTIO].size); 842 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 843 irq_virtio_phandle); 844 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 845 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 846 VIRTIO_IRQ + i); 847 } else { 848 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 849 VIRTIO_IRQ + i, 0x4); 850 } 851 } 852 } 853 854 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 855 uint32_t irq_pcie_phandle, 856 uint32_t msi_pcie_phandle) 857 { 858 g_autofree char *name = NULL; 859 MachineState *ms = MACHINE(s); 860 861 name = g_strdup_printf("/soc/pci@%lx", 862 (long) memmap[VIRT_PCIE_ECAM].base); 863 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 864 FDT_PCI_ADDR_CELLS); 865 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 866 FDT_PCI_INT_CELLS); 867 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 868 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 869 "pci-host-ecam-generic"); 870 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 871 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 872 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 873 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 874 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 875 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 876 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 877 } 878 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 879 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 880 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 881 1, FDT_PCI_RANGE_IOPORT, 2, 0, 882 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 883 1, FDT_PCI_RANGE_MMIO, 884 2, memmap[VIRT_PCIE_MMIO].base, 885 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 886 1, FDT_PCI_RANGE_MMIO_64BIT, 887 2, virt_high_pcie_memmap.base, 888 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 889 890 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 891 } 892 893 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 894 uint32_t *phandle) 895 { 896 char *name; 897 uint32_t test_phandle; 898 MachineState *ms = MACHINE(s); 899 900 test_phandle = (*phandle)++; 901 name = g_strdup_printf("/soc/test@%lx", 902 (long)memmap[VIRT_TEST].base); 903 qemu_fdt_add_subnode(ms->fdt, name); 904 { 905 static const char * const compat[3] = { 906 "sifive,test1", "sifive,test0", "syscon" 907 }; 908 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 909 (char **)&compat, ARRAY_SIZE(compat)); 910 } 911 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 912 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 913 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 914 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 915 g_free(name); 916 917 name = g_strdup_printf("/reboot"); 918 qemu_fdt_add_subnode(ms->fdt, name); 919 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 920 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 921 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 922 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 923 g_free(name); 924 925 name = g_strdup_printf("/poweroff"); 926 qemu_fdt_add_subnode(ms->fdt, name); 927 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 928 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 929 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 930 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 931 g_free(name); 932 } 933 934 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 935 uint32_t irq_mmio_phandle) 936 { 937 g_autofree char *name = NULL; 938 MachineState *ms = MACHINE(s); 939 940 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 941 qemu_fdt_add_subnode(ms->fdt, name); 942 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 943 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 944 0x0, memmap[VIRT_UART0].base, 945 0x0, memmap[VIRT_UART0].size); 946 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 947 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 948 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 949 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 950 } else { 951 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 952 } 953 954 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 955 } 956 957 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 958 uint32_t irq_mmio_phandle) 959 { 960 g_autofree char *name = NULL; 961 MachineState *ms = MACHINE(s); 962 963 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 964 qemu_fdt_add_subnode(ms->fdt, name); 965 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 966 "google,goldfish-rtc"); 967 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 968 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 969 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 970 irq_mmio_phandle); 971 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 972 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 973 } else { 974 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 975 } 976 } 977 978 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 979 { 980 MachineState *ms = MACHINE(s); 981 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 982 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 983 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 984 985 qemu_fdt_add_subnode(ms->fdt, name); 986 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 987 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 988 2, flashbase, 2, flashsize, 989 2, flashbase + flashsize, 2, flashsize); 990 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 991 } 992 993 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 994 { 995 MachineState *ms = MACHINE(s); 996 hwaddr base = memmap[VIRT_FW_CFG].base; 997 hwaddr size = memmap[VIRT_FW_CFG].size; 998 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 999 1000 qemu_fdt_add_subnode(ms->fdt, nodename); 1001 qemu_fdt_setprop_string(ms->fdt, nodename, 1002 "compatible", "qemu,fw-cfg-mmio"); 1003 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1004 2, base, 2, size); 1005 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1006 } 1007 1008 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) 1009 { 1010 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1011 void *fdt = MACHINE(s)->fdt; 1012 uint32_t iommu_phandle; 1013 g_autofree char *iommu_node = NULL; 1014 g_autofree char *pci_node = NULL; 1015 1016 pci_node = g_strdup_printf("/soc/pci@%lx", 1017 (long) virt_memmap[VIRT_PCIE_ECAM].base); 1018 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, 1019 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1020 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1021 1022 qemu_fdt_add_subnode(fdt, iommu_node); 1023 1024 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat)); 1025 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 1026 1, bdf << 8, 1, 0, 1, 0, 1027 1, 0, 1, 0); 1028 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1029 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1030 1031 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1032 0, iommu_phandle, 0, bdf, 1033 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1034 } 1035 1036 static void finalize_fdt(RISCVVirtState *s) 1037 { 1038 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1039 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1040 1041 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 1042 &irq_pcie_phandle, &irq_virtio_phandle, 1043 &msi_pcie_phandle); 1044 1045 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 1046 1047 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); 1048 1049 create_fdt_reset(s, virt_memmap, &phandle); 1050 1051 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 1052 1053 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 1054 } 1055 1056 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1057 { 1058 MachineState *ms = MACHINE(s); 1059 uint8_t rng_seed[32]; 1060 g_autofree char *name = NULL; 1061 1062 ms->fdt = create_device_tree(&s->fdt_size); 1063 if (!ms->fdt) { 1064 error_report("create_device_tree() failed"); 1065 exit(1); 1066 } 1067 1068 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1069 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1070 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1071 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1072 1073 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1074 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1075 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1076 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1077 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1078 1079 /* 1080 * The "/soc/pci@..." node is needed for PCIE hotplugs 1081 * that might happen before finalize_fdt(). 1082 */ 1083 name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); 1084 qemu_fdt_add_subnode(ms->fdt, name); 1085 1086 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1087 1088 /* Pass seed to RNG */ 1089 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1090 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1091 rng_seed, sizeof(rng_seed)); 1092 1093 create_fdt_flash(s, memmap); 1094 create_fdt_fw_cfg(s, memmap); 1095 create_fdt_pmu(s); 1096 } 1097 1098 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1099 DeviceState *irqchip, 1100 RISCVVirtState *s) 1101 { 1102 DeviceState *dev; 1103 MemoryRegion *ecam_alias, *ecam_reg; 1104 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1105 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1106 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1107 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1108 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1109 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1110 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1111 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1112 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1113 qemu_irq irq; 1114 int i; 1115 1116 dev = qdev_new(TYPE_GPEX_HOST); 1117 1118 /* Set GPEX object properties for the virt machine */ 1119 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, 1120 ecam_base, NULL); 1121 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, 1122 ecam_size, NULL); 1123 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1124 PCI_HOST_BELOW_4G_MMIO_BASE, 1125 mmio_base, NULL); 1126 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, 1127 mmio_size, NULL); 1128 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1129 PCI_HOST_ABOVE_4G_MMIO_BASE, 1130 high_mmio_base, NULL); 1131 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1132 high_mmio_size, NULL); 1133 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, 1134 pio_base, NULL); 1135 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, 1136 pio_size, NULL); 1137 1138 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1139 1140 ecam_alias = g_new0(MemoryRegion, 1); 1141 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1142 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1143 ecam_reg, 0, ecam_size); 1144 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1145 1146 mmio_alias = g_new0(MemoryRegion, 1); 1147 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1148 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1149 mmio_reg, mmio_base, mmio_size); 1150 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1151 1152 /* Map high MMIO space */ 1153 high_mmio_alias = g_new0(MemoryRegion, 1); 1154 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1155 mmio_reg, high_mmio_base, high_mmio_size); 1156 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1157 high_mmio_alias); 1158 1159 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1160 1161 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1162 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1163 1164 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1165 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1166 } 1167 1168 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; 1169 return dev; 1170 } 1171 1172 static FWCfgState *create_fw_cfg(const MachineState *ms) 1173 { 1174 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1175 FWCfgState *fw_cfg; 1176 1177 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1178 &address_space_memory); 1179 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1180 1181 return fw_cfg; 1182 } 1183 1184 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1185 int base_hartid, int hart_count) 1186 { 1187 DeviceState *ret; 1188 g_autofree char *plic_hart_config = NULL; 1189 1190 /* Per-socket PLIC hart topology configuration string */ 1191 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1192 1193 /* Per-socket PLIC */ 1194 ret = sifive_plic_create( 1195 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1196 plic_hart_config, hart_count, base_hartid, 1197 VIRT_IRQCHIP_NUM_SOURCES, 1198 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1199 VIRT_PLIC_PRIORITY_BASE, 1200 VIRT_PLIC_PENDING_BASE, 1201 VIRT_PLIC_ENABLE_BASE, 1202 VIRT_PLIC_ENABLE_STRIDE, 1203 VIRT_PLIC_CONTEXT_BASE, 1204 VIRT_PLIC_CONTEXT_STRIDE, 1205 memmap[VIRT_PLIC].size); 1206 1207 return ret; 1208 } 1209 1210 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1211 const MemMapEntry *memmap, int socket, 1212 int base_hartid, int hart_count) 1213 { 1214 int i; 1215 hwaddr addr; 1216 uint32_t guest_bits; 1217 DeviceState *aplic_s = NULL; 1218 DeviceState *aplic_m = NULL; 1219 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1220 1221 if (msimode) { 1222 if (!kvm_enabled()) { 1223 /* Per-socket M-level IMSICs */ 1224 addr = memmap[VIRT_IMSIC_M].base + 1225 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1226 for (i = 0; i < hart_count; i++) { 1227 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1228 base_hartid + i, true, 1, 1229 VIRT_IRQCHIP_NUM_MSIS); 1230 } 1231 } 1232 1233 /* Per-socket S-level IMSICs */ 1234 guest_bits = imsic_num_bits(aia_guests + 1); 1235 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1236 for (i = 0; i < hart_count; i++) { 1237 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1238 base_hartid + i, false, 1 + aia_guests, 1239 VIRT_IRQCHIP_NUM_MSIS); 1240 } 1241 } 1242 1243 if (!kvm_enabled()) { 1244 /* Per-socket M-level APLIC */ 1245 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1246 socket * memmap[VIRT_APLIC_M].size, 1247 memmap[VIRT_APLIC_M].size, 1248 (msimode) ? 0 : base_hartid, 1249 (msimode) ? 0 : hart_count, 1250 VIRT_IRQCHIP_NUM_SOURCES, 1251 VIRT_IRQCHIP_NUM_PRIO_BITS, 1252 msimode, true, NULL); 1253 } 1254 1255 /* Per-socket S-level APLIC */ 1256 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1257 socket * memmap[VIRT_APLIC_S].size, 1258 memmap[VIRT_APLIC_S].size, 1259 (msimode) ? 0 : base_hartid, 1260 (msimode) ? 0 : hart_count, 1261 VIRT_IRQCHIP_NUM_SOURCES, 1262 VIRT_IRQCHIP_NUM_PRIO_BITS, 1263 msimode, false, aplic_m); 1264 1265 return kvm_enabled() ? aplic_s : aplic_m; 1266 } 1267 1268 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1269 { 1270 DeviceState *dev; 1271 SysBusDevice *sysbus; 1272 const MemMapEntry *memmap = virt_memmap; 1273 int i; 1274 MemoryRegion *sysmem = get_system_memory(); 1275 1276 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1277 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1278 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1279 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1280 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1281 s->platform_bus_dev = dev; 1282 1283 sysbus = SYS_BUS_DEVICE(dev); 1284 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1285 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1286 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1287 } 1288 1289 memory_region_add_subregion(sysmem, 1290 memmap[VIRT_PLATFORM_BUS].base, 1291 sysbus_mmio_get_region(sysbus, 0)); 1292 } 1293 1294 static void virt_build_smbios(RISCVVirtState *s) 1295 { 1296 MachineClass *mc = MACHINE_GET_CLASS(s); 1297 MachineState *ms = MACHINE(s); 1298 uint8_t *smbios_tables, *smbios_anchor; 1299 size_t smbios_tables_len, smbios_anchor_len; 1300 struct smbios_phys_mem_area mem_array; 1301 const char *product = "QEMU Virtual Machine"; 1302 1303 if (kvm_enabled()) { 1304 product = "KVM Virtual Machine"; 1305 } 1306 1307 smbios_set_defaults("QEMU", product, mc->name); 1308 1309 if (riscv_is_32bit(&s->soc[0])) { 1310 smbios_set_default_processor_family(0x200); 1311 } else { 1312 smbios_set_default_processor_family(0x201); 1313 } 1314 1315 /* build the array of physical mem area from base_memmap */ 1316 mem_array.address = s->memmap[VIRT_DRAM].base; 1317 mem_array.length = ms->ram_size; 1318 1319 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 1320 &mem_array, 1, 1321 &smbios_tables, &smbios_tables_len, 1322 &smbios_anchor, &smbios_anchor_len, 1323 &error_fatal); 1324 1325 if (smbios_anchor) { 1326 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables", 1327 smbios_tables, smbios_tables_len); 1328 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor", 1329 smbios_anchor, smbios_anchor_len); 1330 } 1331 } 1332 1333 static void virt_machine_done(Notifier *notifier, void *data) 1334 { 1335 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1336 machine_done); 1337 const MemMapEntry *memmap = virt_memmap; 1338 MachineState *machine = MACHINE(s); 1339 target_ulong start_addr = memmap[VIRT_DRAM].base; 1340 target_ulong firmware_end_addr, kernel_start_addr; 1341 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1342 uint64_t fdt_load_addr; 1343 uint64_t kernel_entry = 0; 1344 BlockBackend *pflash_blk0; 1345 1346 /* 1347 * An user provided dtb must include everything, including 1348 * dynamic sysbus devices. Our FDT needs to be finalized. 1349 */ 1350 if (machine->dtb == NULL) { 1351 finalize_fdt(s); 1352 } 1353 1354 /* 1355 * Only direct boot kernel is currently supported for KVM VM, 1356 * so the "-bios" parameter is not supported when KVM is enabled. 1357 */ 1358 if (kvm_enabled()) { 1359 if (machine->firmware) { 1360 if (strcmp(machine->firmware, "none")) { 1361 error_report("Machine mode firmware is not supported in " 1362 "combination with KVM."); 1363 exit(1); 1364 } 1365 } else { 1366 machine->firmware = g_strdup("none"); 1367 } 1368 } 1369 1370 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1371 start_addr, NULL); 1372 1373 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1374 if (pflash_blk0) { 1375 if (machine->firmware && !strcmp(machine->firmware, "none") && 1376 !kvm_enabled()) { 1377 /* 1378 * Pflash was supplied but bios is none and not KVM guest, 1379 * let's overwrite the address we jump to after reset to 1380 * the base of the flash. 1381 */ 1382 start_addr = virt_memmap[VIRT_FLASH].base; 1383 } else { 1384 /* 1385 * Pflash was supplied but either KVM guest or bios is not none. 1386 * In this case, base of the flash would contain S-mode payload. 1387 */ 1388 riscv_setup_firmware_boot(machine); 1389 kernel_entry = virt_memmap[VIRT_FLASH].base; 1390 } 1391 } 1392 1393 if (machine->kernel_filename && !kernel_entry) { 1394 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1395 firmware_end_addr); 1396 1397 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1398 kernel_start_addr, true, NULL); 1399 } 1400 1401 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1402 memmap[VIRT_DRAM].size, 1403 machine); 1404 riscv_load_fdt(fdt_load_addr, machine->fdt); 1405 1406 /* load the reset vector */ 1407 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1408 virt_memmap[VIRT_MROM].base, 1409 virt_memmap[VIRT_MROM].size, kernel_entry, 1410 fdt_load_addr); 1411 1412 /* 1413 * Only direct boot kernel is currently supported for KVM VM, 1414 * So here setup kernel start address and fdt address. 1415 * TODO:Support firmware loading and integrate to TCG start 1416 */ 1417 if (kvm_enabled()) { 1418 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1419 } 1420 1421 virt_build_smbios(s); 1422 1423 if (virt_is_acpi_enabled(s)) { 1424 virt_acpi_setup(s); 1425 } 1426 } 1427 1428 static void virt_machine_init(MachineState *machine) 1429 { 1430 const MemMapEntry *memmap = virt_memmap; 1431 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1432 MemoryRegion *system_memory = get_system_memory(); 1433 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1434 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1435 int i, base_hartid, hart_count; 1436 int socket_count = riscv_socket_count(machine); 1437 1438 /* Check socket count limit */ 1439 if (VIRT_SOCKETS_MAX < socket_count) { 1440 error_report("number of sockets/nodes should be less than %d", 1441 VIRT_SOCKETS_MAX); 1442 exit(1); 1443 } 1444 1445 if (!virt_aclint_allowed() && s->have_aclint) { 1446 error_report("'aclint' is only available with TCG acceleration"); 1447 exit(1); 1448 } 1449 1450 /* Initialize sockets */ 1451 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1452 for (i = 0; i < socket_count; i++) { 1453 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1454 1455 if (!riscv_socket_check_hartids(machine, i)) { 1456 error_report("discontinuous hartids in socket%d", i); 1457 exit(1); 1458 } 1459 1460 base_hartid = riscv_socket_first_hartid(machine, i); 1461 if (base_hartid < 0) { 1462 error_report("can't find hartid base for socket%d", i); 1463 exit(1); 1464 } 1465 1466 hart_count = riscv_socket_hart_count(machine, i); 1467 if (hart_count < 0) { 1468 error_report("can't find hart count for socket%d", i); 1469 exit(1); 1470 } 1471 1472 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1473 TYPE_RISCV_HART_ARRAY); 1474 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1475 machine->cpu_type, &error_abort); 1476 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1477 base_hartid, &error_abort); 1478 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1479 hart_count, &error_abort); 1480 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1481 1482 if (virt_aclint_allowed() && s->have_aclint) { 1483 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1484 /* Per-socket ACLINT MTIMER */ 1485 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1486 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1487 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1488 base_hartid, hart_count, 1489 RISCV_ACLINT_DEFAULT_MTIMECMP, 1490 RISCV_ACLINT_DEFAULT_MTIME, 1491 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1492 } else { 1493 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1494 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1495 i * memmap[VIRT_CLINT].size, 1496 base_hartid, hart_count, false); 1497 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1498 i * memmap[VIRT_CLINT].size + 1499 RISCV_ACLINT_SWI_SIZE, 1500 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1501 base_hartid, hart_count, 1502 RISCV_ACLINT_DEFAULT_MTIMECMP, 1503 RISCV_ACLINT_DEFAULT_MTIME, 1504 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1505 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1506 i * memmap[VIRT_ACLINT_SSWI].size, 1507 base_hartid, hart_count, true); 1508 } 1509 } else if (tcg_enabled()) { 1510 /* Per-socket SiFive CLINT */ 1511 riscv_aclint_swi_create( 1512 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1513 base_hartid, hart_count, false); 1514 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1515 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1516 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1517 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1518 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1519 } 1520 1521 /* Per-socket interrupt controller */ 1522 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1523 s->irqchip[i] = virt_create_plic(memmap, i, 1524 base_hartid, hart_count); 1525 } else { 1526 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1527 memmap, i, base_hartid, 1528 hart_count); 1529 } 1530 1531 /* Try to use different IRQCHIP instance based device type */ 1532 if (i == 0) { 1533 mmio_irqchip = s->irqchip[i]; 1534 virtio_irqchip = s->irqchip[i]; 1535 pcie_irqchip = s->irqchip[i]; 1536 } 1537 if (i == 1) { 1538 virtio_irqchip = s->irqchip[i]; 1539 pcie_irqchip = s->irqchip[i]; 1540 } 1541 if (i == 2) { 1542 pcie_irqchip = s->irqchip[i]; 1543 } 1544 } 1545 1546 if (kvm_enabled() && virt_use_kvm_aia(s)) { 1547 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1548 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1549 memmap[VIRT_APLIC_S].base, 1550 memmap[VIRT_IMSIC_S].base, 1551 s->aia_guests); 1552 } 1553 1554 if (riscv_is_32bit(&s->soc[0])) { 1555 #if HOST_LONG_BITS == 64 1556 /* limit RAM size in a 32-bit system */ 1557 if (machine->ram_size > 10 * GiB) { 1558 machine->ram_size = 10 * GiB; 1559 error_report("Limiting RAM size to 10 GiB"); 1560 } 1561 #endif 1562 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1563 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1564 } else { 1565 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1566 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1567 virt_high_pcie_memmap.base = 1568 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1569 } 1570 1571 s->memmap = virt_memmap; 1572 1573 /* register system main memory (actual RAM) */ 1574 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1575 machine->ram); 1576 1577 /* boot rom */ 1578 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1579 memmap[VIRT_MROM].size, &error_fatal); 1580 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1581 mask_rom); 1582 1583 /* 1584 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1585 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1586 */ 1587 s->fw_cfg = create_fw_cfg(machine); 1588 rom_set_fw(s->fw_cfg); 1589 1590 /* SiFive Test MMIO device */ 1591 sifive_test_create(memmap[VIRT_TEST].base); 1592 1593 /* VirtIO MMIO devices */ 1594 for (i = 0; i < VIRTIO_COUNT; i++) { 1595 sysbus_create_simple("virtio-mmio", 1596 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1597 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1598 } 1599 1600 gpex_pcie_init(system_memory, pcie_irqchip, s); 1601 1602 create_platform_bus(s, mmio_irqchip); 1603 1604 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1605 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1606 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1607 1608 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1609 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1610 1611 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1612 /* Map legacy -drive if=pflash to machine properties */ 1613 pflash_cfi01_legacy_drive(s->flash[i], 1614 drive_get(IF_PFLASH, 0, i)); 1615 } 1616 virt_flash_map(s, system_memory); 1617 1618 /* load/create device tree */ 1619 if (machine->dtb) { 1620 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1621 if (!machine->fdt) { 1622 error_report("load_device_tree() failed"); 1623 exit(1); 1624 } 1625 } else { 1626 create_fdt(s, memmap); 1627 } 1628 1629 s->machine_done.notify = virt_machine_done; 1630 qemu_add_machine_init_done_notifier(&s->machine_done); 1631 } 1632 1633 static void virt_machine_instance_init(Object *obj) 1634 { 1635 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1636 1637 virt_flash_create(s); 1638 1639 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1640 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1641 s->acpi = ON_OFF_AUTO_AUTO; 1642 } 1643 1644 static char *virt_get_aia_guests(Object *obj, Error **errp) 1645 { 1646 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1647 1648 return g_strdup_printf("%d", s->aia_guests); 1649 } 1650 1651 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1652 { 1653 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1654 1655 s->aia_guests = atoi(val); 1656 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1657 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1658 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1659 VIRT_IRQCHIP_MAX_GUESTS); 1660 } 1661 } 1662 1663 static char *virt_get_aia(Object *obj, Error **errp) 1664 { 1665 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1666 const char *val; 1667 1668 switch (s->aia_type) { 1669 case VIRT_AIA_TYPE_APLIC: 1670 val = "aplic"; 1671 break; 1672 case VIRT_AIA_TYPE_APLIC_IMSIC: 1673 val = "aplic-imsic"; 1674 break; 1675 default: 1676 val = "none"; 1677 break; 1678 }; 1679 1680 return g_strdup(val); 1681 } 1682 1683 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1684 { 1685 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1686 1687 if (!strcmp(val, "none")) { 1688 s->aia_type = VIRT_AIA_TYPE_NONE; 1689 } else if (!strcmp(val, "aplic")) { 1690 s->aia_type = VIRT_AIA_TYPE_APLIC; 1691 } else if (!strcmp(val, "aplic-imsic")) { 1692 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1693 } else { 1694 error_setg(errp, "Invalid AIA interrupt controller type"); 1695 error_append_hint(errp, "Valid values are none, aplic, and " 1696 "aplic-imsic.\n"); 1697 } 1698 } 1699 1700 static bool virt_get_aclint(Object *obj, Error **errp) 1701 { 1702 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1703 1704 return s->have_aclint; 1705 } 1706 1707 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1708 { 1709 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1710 1711 s->have_aclint = value; 1712 } 1713 1714 bool virt_is_acpi_enabled(RISCVVirtState *s) 1715 { 1716 return s->acpi != ON_OFF_AUTO_OFF; 1717 } 1718 1719 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1720 void *opaque, Error **errp) 1721 { 1722 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1723 OnOffAuto acpi = s->acpi; 1724 1725 visit_type_OnOffAuto(v, name, &acpi, errp); 1726 } 1727 1728 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1729 void *opaque, Error **errp) 1730 { 1731 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1732 1733 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1734 } 1735 1736 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1737 DeviceState *dev) 1738 { 1739 MachineClass *mc = MACHINE_GET_CLASS(machine); 1740 1741 if (device_is_dynamic_sysbus(mc, dev) || 1742 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1743 return HOTPLUG_HANDLER(machine); 1744 } 1745 return NULL; 1746 } 1747 1748 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1749 DeviceState *dev, Error **errp) 1750 { 1751 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1752 1753 if (s->platform_bus_dev) { 1754 MachineClass *mc = MACHINE_GET_CLASS(s); 1755 1756 if (device_is_dynamic_sysbus(mc, dev)) { 1757 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1758 SYS_BUS_DEVICE(dev)); 1759 } 1760 } 1761 1762 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1763 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1764 } 1765 } 1766 1767 static void virt_machine_class_init(ObjectClass *oc, void *data) 1768 { 1769 MachineClass *mc = MACHINE_CLASS(oc); 1770 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1771 1772 mc->desc = "RISC-V VirtIO board"; 1773 mc->init = virt_machine_init; 1774 mc->max_cpus = VIRT_CPUS_MAX; 1775 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1776 mc->block_default_type = IF_VIRTIO; 1777 mc->no_cdrom = 1; 1778 mc->pci_allow_0_address = true; 1779 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1780 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1781 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1782 mc->numa_mem_supported = true; 1783 /* platform instead of architectural choice */ 1784 mc->cpu_cluster_has_numa_boundary = true; 1785 mc->default_ram_id = "riscv_virt_board.ram"; 1786 assert(!mc->get_hotplug_handler); 1787 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1788 1789 hc->plug = virt_machine_device_plug_cb; 1790 1791 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1792 #ifdef CONFIG_TPM 1793 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1794 #endif 1795 1796 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1797 virt_set_aclint); 1798 object_class_property_set_description(oc, "aclint", 1799 "(TCG only) Set on/off to " 1800 "enable/disable emulating " 1801 "ACLINT devices"); 1802 1803 object_class_property_add_str(oc, "aia", virt_get_aia, 1804 virt_set_aia); 1805 object_class_property_set_description(oc, "aia", 1806 "Set type of AIA interrupt " 1807 "controller. Valid values are " 1808 "none, aplic, and aplic-imsic."); 1809 1810 object_class_property_add_str(oc, "aia-guests", 1811 virt_get_aia_guests, 1812 virt_set_aia_guests); 1813 { 1814 g_autofree char *str = 1815 g_strdup_printf("Set number of guest MMIO pages for AIA IMSIC. " 1816 "Valid value should be between 0 and %d.", 1817 VIRT_IRQCHIP_MAX_GUESTS); 1818 object_class_property_set_description(oc, "aia-guests", str); 1819 } 1820 1821 object_class_property_add(oc, "acpi", "OnOffAuto", 1822 virt_get_acpi, virt_set_acpi, 1823 NULL, NULL); 1824 object_class_property_set_description(oc, "acpi", 1825 "Enable ACPI"); 1826 } 1827 1828 static const TypeInfo virt_machine_typeinfo = { 1829 .name = MACHINE_TYPE_NAME("virt"), 1830 .parent = TYPE_MACHINE, 1831 .class_init = virt_machine_class_init, 1832 .instance_init = virt_machine_instance_init, 1833 .instance_size = sizeof(RISCVVirtState), 1834 .interfaces = (InterfaceInfo[]) { 1835 { TYPE_HOTPLUG_HANDLER }, 1836 { } 1837 }, 1838 }; 1839 1840 static void virt_machine_init_register_types(void) 1841 { 1842 type_register_static(&virt_machine_typeinfo); 1843 } 1844 1845 type_init(virt_machine_init_register_types) 1846