1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "hw/intc/riscv_aclint.h" 39 #include "hw/intc/riscv_aplic.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "hw/intc/sifive_plic.h" 42 #include "hw/misc/sifive_test.h" 43 #include "hw/platform-bus.h" 44 #include "chardev/char.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/tpm.h" 49 #include "hw/pci/pci.h" 50 #include "hw/pci-host/gpex.h" 51 #include "hw/display/ramfb.h" 52 53 /* 54 * The virt machine physical address space used by some of the devices 55 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 56 * number of CPUs, and number of IMSIC guest files. 57 * 58 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 59 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 60 * of virt machine physical address space. 61 */ 62 63 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 64 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 65 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 66 #error "Can't accomodate single IMSIC group in address space" 67 #endif 68 69 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 70 VIRT_IMSIC_GROUP_MAX_SIZE) 71 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 72 #error "Can't accomodate all IMSIC groups in address space" 73 #endif 74 75 static const MemMapEntry virt_memmap[] = { 76 [VIRT_DEBUG] = { 0x0, 0x100 }, 77 [VIRT_MROM] = { 0x1000, 0xf000 }, 78 [VIRT_TEST] = { 0x100000, 0x1000 }, 79 [VIRT_RTC] = { 0x101000, 0x1000 }, 80 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 81 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 82 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 83 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 84 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 85 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 86 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 87 [VIRT_UART0] = { 0x10000000, 0x100 }, 88 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 89 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 90 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 91 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 92 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 93 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 94 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 95 [VIRT_DRAM] = { 0x80000000, 0x0 }, 96 }; 97 98 /* PCIe high mmio is fixed for RV32 */ 99 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 100 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 101 102 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 103 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 104 105 static MemMapEntry virt_high_pcie_memmap; 106 107 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 108 109 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 110 const char *name, 111 const char *alias_prop_name) 112 { 113 /* 114 * Create a single flash device. We use the same parameters as 115 * the flash devices on the ARM virt board. 116 */ 117 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 118 119 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 120 qdev_prop_set_uint8(dev, "width", 4); 121 qdev_prop_set_uint8(dev, "device-width", 2); 122 qdev_prop_set_bit(dev, "big-endian", false); 123 qdev_prop_set_uint16(dev, "id0", 0x89); 124 qdev_prop_set_uint16(dev, "id1", 0x18); 125 qdev_prop_set_uint16(dev, "id2", 0x00); 126 qdev_prop_set_uint16(dev, "id3", 0x00); 127 qdev_prop_set_string(dev, "name", name); 128 129 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 130 object_property_add_alias(OBJECT(s), alias_prop_name, 131 OBJECT(dev), "drive"); 132 133 return PFLASH_CFI01(dev); 134 } 135 136 static void virt_flash_create(RISCVVirtState *s) 137 { 138 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 139 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 140 } 141 142 static void virt_flash_map1(PFlashCFI01 *flash, 143 hwaddr base, hwaddr size, 144 MemoryRegion *sysmem) 145 { 146 DeviceState *dev = DEVICE(flash); 147 148 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 149 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 150 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 151 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 152 153 memory_region_add_subregion(sysmem, base, 154 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 155 0)); 156 } 157 158 static void virt_flash_map(RISCVVirtState *s, 159 MemoryRegion *sysmem) 160 { 161 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 162 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 163 164 virt_flash_map1(s->flash[0], flashbase, flashsize, 165 sysmem); 166 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 167 sysmem); 168 } 169 170 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 171 uint32_t irqchip_phandle) 172 { 173 int pin, dev; 174 uint32_t irq_map_stride = 0; 175 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 176 FDT_MAX_INT_MAP_WIDTH] = {}; 177 uint32_t *irq_map = full_irq_map; 178 179 /* This code creates a standard swizzle of interrupts such that 180 * each device's first interrupt is based on it's PCI_SLOT number. 181 * (See pci_swizzle_map_irq_fn()) 182 * 183 * We only need one entry per interrupt in the table (not one per 184 * possible slot) seeing the interrupt-map-mask will allow the table 185 * to wrap to any number of devices. 186 */ 187 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 188 int devfn = dev * 0x8; 189 190 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 191 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 192 int i = 0; 193 194 /* Fill PCI address cells */ 195 irq_map[i] = cpu_to_be32(devfn << 8); 196 i += FDT_PCI_ADDR_CELLS; 197 198 /* Fill PCI Interrupt cells */ 199 irq_map[i] = cpu_to_be32(pin + 1); 200 i += FDT_PCI_INT_CELLS; 201 202 /* Fill interrupt controller phandle and cells */ 203 irq_map[i++] = cpu_to_be32(irqchip_phandle); 204 irq_map[i++] = cpu_to_be32(irq_nr); 205 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 206 irq_map[i++] = cpu_to_be32(0x4); 207 } 208 209 if (!irq_map_stride) { 210 irq_map_stride = i; 211 } 212 irq_map += irq_map_stride; 213 } 214 } 215 216 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 217 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 218 irq_map_stride * sizeof(uint32_t)); 219 220 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 221 0x1800, 0, 0, 0x7); 222 } 223 224 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 225 char *clust_name, uint32_t *phandle, 226 bool is_32_bit, uint32_t *intc_phandles) 227 { 228 int cpu; 229 uint32_t cpu_phandle; 230 MachineState *mc = MACHINE(s); 231 char *name, *cpu_name, *core_name, *intc_name; 232 233 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 234 cpu_phandle = (*phandle)++; 235 236 cpu_name = g_strdup_printf("/cpus/cpu@%d", 237 s->soc[socket].hartid_base + cpu); 238 qemu_fdt_add_subnode(mc->fdt, cpu_name); 239 if (riscv_feature(&s->soc[socket].harts[cpu].env, 240 RISCV_FEATURE_MMU)) { 241 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 242 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 243 } else { 244 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 245 "riscv,none"); 246 } 247 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 248 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); 249 g_free(name); 250 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); 251 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); 252 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", 253 s->soc[socket].hartid_base + cpu); 254 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); 255 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); 256 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); 257 258 intc_phandles[cpu] = (*phandle)++; 259 260 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 261 qemu_fdt_add_subnode(mc->fdt, intc_name); 262 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", 263 intc_phandles[cpu]); 264 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", 265 "riscv,cpu-intc"); 266 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); 267 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); 268 269 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 270 qemu_fdt_add_subnode(mc->fdt, core_name); 271 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); 272 273 g_free(core_name); 274 g_free(intc_name); 275 g_free(cpu_name); 276 } 277 } 278 279 static void create_fdt_socket_memory(RISCVVirtState *s, 280 const MemMapEntry *memmap, int socket) 281 { 282 char *mem_name; 283 uint64_t addr, size; 284 MachineState *mc = MACHINE(s); 285 286 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 287 size = riscv_socket_mem_size(mc, socket); 288 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 289 qemu_fdt_add_subnode(mc->fdt, mem_name); 290 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", 291 addr >> 32, addr, size >> 32, size); 292 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); 293 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); 294 g_free(mem_name); 295 } 296 297 static void create_fdt_socket_clint(RISCVVirtState *s, 298 const MemMapEntry *memmap, int socket, 299 uint32_t *intc_phandles) 300 { 301 int cpu; 302 char *clint_name; 303 uint32_t *clint_cells; 304 unsigned long clint_addr; 305 MachineState *mc = MACHINE(s); 306 static const char * const clint_compat[2] = { 307 "sifive,clint0", "riscv,clint0" 308 }; 309 310 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 311 312 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 313 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 314 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 315 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 316 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 317 } 318 319 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 320 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 321 qemu_fdt_add_subnode(mc->fdt, clint_name); 322 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", 323 (char **)&clint_compat, 324 ARRAY_SIZE(clint_compat)); 325 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", 326 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 327 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", 328 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 329 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); 330 g_free(clint_name); 331 332 g_free(clint_cells); 333 } 334 335 static void create_fdt_socket_aclint(RISCVVirtState *s, 336 const MemMapEntry *memmap, int socket, 337 uint32_t *intc_phandles) 338 { 339 int cpu; 340 char *name; 341 unsigned long addr, size; 342 uint32_t aclint_cells_size; 343 uint32_t *aclint_mswi_cells; 344 uint32_t *aclint_sswi_cells; 345 uint32_t *aclint_mtimer_cells; 346 MachineState *mc = MACHINE(s); 347 348 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 349 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 350 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 351 352 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 353 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 354 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 355 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 356 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 357 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 358 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 359 } 360 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 361 362 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 363 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 364 name = g_strdup_printf("/soc/mswi@%lx", addr); 365 qemu_fdt_add_subnode(mc->fdt, name); 366 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 367 "riscv,aclint-mswi"); 368 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 369 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 370 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 371 aclint_mswi_cells, aclint_cells_size); 372 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 373 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 374 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 375 g_free(name); 376 } 377 378 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 379 addr = memmap[VIRT_CLINT].base + 380 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 381 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 382 } else { 383 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 384 (memmap[VIRT_CLINT].size * socket); 385 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 386 } 387 name = g_strdup_printf("/soc/mtimer@%lx", addr); 388 qemu_fdt_add_subnode(mc->fdt, name); 389 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 390 "riscv,aclint-mtimer"); 391 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 392 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 393 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 394 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 395 0x0, RISCV_ACLINT_DEFAULT_MTIME); 396 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 397 aclint_mtimer_cells, aclint_cells_size); 398 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 399 g_free(name); 400 401 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 402 addr = memmap[VIRT_ACLINT_SSWI].base + 403 (memmap[VIRT_ACLINT_SSWI].size * socket); 404 name = g_strdup_printf("/soc/sswi@%lx", addr); 405 qemu_fdt_add_subnode(mc->fdt, name); 406 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 407 "riscv,aclint-sswi"); 408 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 409 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 410 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 411 aclint_sswi_cells, aclint_cells_size); 412 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 413 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 414 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 415 g_free(name); 416 } 417 418 g_free(aclint_mswi_cells); 419 g_free(aclint_mtimer_cells); 420 g_free(aclint_sswi_cells); 421 } 422 423 static void create_fdt_socket_plic(RISCVVirtState *s, 424 const MemMapEntry *memmap, int socket, 425 uint32_t *phandle, uint32_t *intc_phandles, 426 uint32_t *plic_phandles) 427 { 428 int cpu; 429 char *plic_name; 430 uint32_t *plic_cells; 431 unsigned long plic_addr; 432 MachineState *mc = MACHINE(s); 433 static const char * const plic_compat[2] = { 434 "sifive,plic-1.0.0", "riscv,plic0" 435 }; 436 437 if (kvm_enabled()) { 438 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 439 } else { 440 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 441 } 442 443 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 444 if (kvm_enabled()) { 445 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 446 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 447 } else { 448 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 449 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 450 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 451 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 452 } 453 } 454 455 plic_phandles[socket] = (*phandle)++; 456 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 457 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 458 qemu_fdt_add_subnode(mc->fdt, plic_name); 459 qemu_fdt_setprop_cell(mc->fdt, plic_name, 460 "#interrupt-cells", FDT_PLIC_INT_CELLS); 461 qemu_fdt_setprop_cell(mc->fdt, plic_name, 462 "#address-cells", FDT_PLIC_ADDR_CELLS); 463 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", 464 (char **)&plic_compat, 465 ARRAY_SIZE(plic_compat)); 466 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); 467 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", 468 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 469 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", 470 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 471 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 472 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); 473 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", 474 plic_phandles[socket]); 475 476 if (!socket) { 477 platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, 478 memmap[VIRT_PLATFORM_BUS].base, 479 memmap[VIRT_PLATFORM_BUS].size, 480 VIRT_PLATFORM_BUS_IRQ); 481 } 482 483 g_free(plic_name); 484 485 g_free(plic_cells); 486 } 487 488 static uint32_t imsic_num_bits(uint32_t count) 489 { 490 uint32_t ret = 0; 491 492 while (BIT(ret) < count) { 493 ret++; 494 } 495 496 return ret; 497 } 498 499 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 500 uint32_t *phandle, uint32_t *intc_phandles, 501 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 502 { 503 int cpu, socket; 504 char *imsic_name; 505 MachineState *mc = MACHINE(s); 506 uint32_t imsic_max_hart_per_socket, imsic_guest_bits; 507 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 508 509 *msi_m_phandle = (*phandle)++; 510 *msi_s_phandle = (*phandle)++; 511 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); 512 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); 513 514 /* M-level IMSIC node */ 515 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 516 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 517 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 518 } 519 imsic_max_hart_per_socket = 0; 520 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 521 imsic_addr = memmap[VIRT_IMSIC_M].base + 522 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 523 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; 524 imsic_regs[socket * 4 + 0] = 0; 525 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 526 imsic_regs[socket * 4 + 2] = 0; 527 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 528 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 529 imsic_max_hart_per_socket = s->soc[socket].num_harts; 530 } 531 } 532 imsic_name = g_strdup_printf("/soc/imsics@%lx", 533 (unsigned long)memmap[VIRT_IMSIC_M].base); 534 qemu_fdt_add_subnode(mc->fdt, imsic_name); 535 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 536 "riscv,imsics"); 537 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 538 FDT_IMSIC_INT_CELLS); 539 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 540 NULL, 0); 541 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 542 NULL, 0); 543 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 544 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 545 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 546 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 547 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 548 VIRT_IRQCHIP_NUM_MSIS); 549 if (riscv_socket_count(mc) > 1) { 550 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 551 imsic_num_bits(imsic_max_hart_per_socket)); 552 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 553 imsic_num_bits(riscv_socket_count(mc))); 554 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 555 IMSIC_MMIO_GROUP_MIN_SHIFT); 556 } 557 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); 558 559 g_free(imsic_name); 560 561 /* S-level IMSIC node */ 562 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 563 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 564 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 565 } 566 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); 567 imsic_max_hart_per_socket = 0; 568 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 569 imsic_addr = memmap[VIRT_IMSIC_S].base + 570 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 571 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 572 s->soc[socket].num_harts; 573 imsic_regs[socket * 4 + 0] = 0; 574 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 575 imsic_regs[socket * 4 + 2] = 0; 576 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 577 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 578 imsic_max_hart_per_socket = s->soc[socket].num_harts; 579 } 580 } 581 imsic_name = g_strdup_printf("/soc/imsics@%lx", 582 (unsigned long)memmap[VIRT_IMSIC_S].base); 583 qemu_fdt_add_subnode(mc->fdt, imsic_name); 584 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 585 "riscv,imsics"); 586 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 587 FDT_IMSIC_INT_CELLS); 588 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 589 NULL, 0); 590 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 591 NULL, 0); 592 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 593 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 594 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 595 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 596 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 597 VIRT_IRQCHIP_NUM_MSIS); 598 if (imsic_guest_bits) { 599 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", 600 imsic_guest_bits); 601 } 602 if (riscv_socket_count(mc) > 1) { 603 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 604 imsic_num_bits(imsic_max_hart_per_socket)); 605 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 606 imsic_num_bits(riscv_socket_count(mc))); 607 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 608 IMSIC_MMIO_GROUP_MIN_SHIFT); 609 } 610 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); 611 g_free(imsic_name); 612 613 g_free(imsic_regs); 614 g_free(imsic_cells); 615 } 616 617 static void create_fdt_socket_aplic(RISCVVirtState *s, 618 const MemMapEntry *memmap, int socket, 619 uint32_t msi_m_phandle, 620 uint32_t msi_s_phandle, 621 uint32_t *phandle, 622 uint32_t *intc_phandles, 623 uint32_t *aplic_phandles) 624 { 625 int cpu; 626 char *aplic_name; 627 uint32_t *aplic_cells; 628 unsigned long aplic_addr; 629 MachineState *mc = MACHINE(s); 630 uint32_t aplic_m_phandle, aplic_s_phandle; 631 632 aplic_m_phandle = (*phandle)++; 633 aplic_s_phandle = (*phandle)++; 634 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 635 636 /* M-level APLIC node */ 637 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 638 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 639 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 640 } 641 aplic_addr = memmap[VIRT_APLIC_M].base + 642 (memmap[VIRT_APLIC_M].size * socket); 643 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 644 qemu_fdt_add_subnode(mc->fdt, aplic_name); 645 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 646 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 647 "#interrupt-cells", FDT_APLIC_INT_CELLS); 648 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 649 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 650 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 651 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 652 } else { 653 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 654 msi_m_phandle); 655 } 656 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 657 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); 658 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 659 VIRT_IRQCHIP_NUM_SOURCES); 660 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", 661 aplic_s_phandle); 662 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", 663 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); 664 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 665 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); 666 g_free(aplic_name); 667 668 /* S-level APLIC node */ 669 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 670 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 671 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 672 } 673 aplic_addr = memmap[VIRT_APLIC_S].base + 674 (memmap[VIRT_APLIC_S].size * socket); 675 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 676 qemu_fdt_add_subnode(mc->fdt, aplic_name); 677 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 678 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 679 "#interrupt-cells", FDT_APLIC_INT_CELLS); 680 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 681 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 682 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 683 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 684 } else { 685 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 686 msi_s_phandle); 687 } 688 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 689 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); 690 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 691 VIRT_IRQCHIP_NUM_SOURCES); 692 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 693 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); 694 695 if (!socket) { 696 platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, 697 memmap[VIRT_PLATFORM_BUS].base, 698 memmap[VIRT_PLATFORM_BUS].size, 699 VIRT_PLATFORM_BUS_IRQ); 700 } 701 702 g_free(aplic_name); 703 704 g_free(aplic_cells); 705 aplic_phandles[socket] = aplic_s_phandle; 706 } 707 708 static void create_fdt_pmu(RISCVVirtState *s) 709 { 710 char *pmu_name; 711 MachineState *mc = MACHINE(s); 712 RISCVCPU hart = s->soc[0].harts[0]; 713 714 pmu_name = g_strdup_printf("/soc/pmu"); 715 qemu_fdt_add_subnode(mc->fdt, pmu_name); 716 qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); 717 riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); 718 719 g_free(pmu_name); 720 } 721 722 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 723 bool is_32_bit, uint32_t *phandle, 724 uint32_t *irq_mmio_phandle, 725 uint32_t *irq_pcie_phandle, 726 uint32_t *irq_virtio_phandle, 727 uint32_t *msi_pcie_phandle) 728 { 729 char *clust_name; 730 int socket, phandle_pos; 731 MachineState *mc = MACHINE(s); 732 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 733 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 734 735 qemu_fdt_add_subnode(mc->fdt, "/cpus"); 736 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", 737 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 738 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); 739 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); 740 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); 741 742 intc_phandles = g_new0(uint32_t, mc->smp.cpus); 743 744 phandle_pos = mc->smp.cpus; 745 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 746 phandle_pos -= s->soc[socket].num_harts; 747 748 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 749 qemu_fdt_add_subnode(mc->fdt, clust_name); 750 751 create_fdt_socket_cpus(s, socket, clust_name, phandle, 752 is_32_bit, &intc_phandles[phandle_pos]); 753 754 create_fdt_socket_memory(s, memmap, socket); 755 756 g_free(clust_name); 757 758 if (!kvm_enabled()) { 759 if (s->have_aclint) { 760 create_fdt_socket_aclint(s, memmap, socket, 761 &intc_phandles[phandle_pos]); 762 } else { 763 create_fdt_socket_clint(s, memmap, socket, 764 &intc_phandles[phandle_pos]); 765 } 766 } 767 } 768 769 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 770 create_fdt_imsic(s, memmap, phandle, intc_phandles, 771 &msi_m_phandle, &msi_s_phandle); 772 *msi_pcie_phandle = msi_s_phandle; 773 } 774 775 phandle_pos = mc->smp.cpus; 776 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 777 phandle_pos -= s->soc[socket].num_harts; 778 779 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 780 create_fdt_socket_plic(s, memmap, socket, phandle, 781 &intc_phandles[phandle_pos], xplic_phandles); 782 } else { 783 create_fdt_socket_aplic(s, memmap, socket, 784 msi_m_phandle, msi_s_phandle, phandle, 785 &intc_phandles[phandle_pos], xplic_phandles); 786 } 787 } 788 789 g_free(intc_phandles); 790 791 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 792 if (socket == 0) { 793 *irq_mmio_phandle = xplic_phandles[socket]; 794 *irq_virtio_phandle = xplic_phandles[socket]; 795 *irq_pcie_phandle = xplic_phandles[socket]; 796 } 797 if (socket == 1) { 798 *irq_virtio_phandle = xplic_phandles[socket]; 799 *irq_pcie_phandle = xplic_phandles[socket]; 800 } 801 if (socket == 2) { 802 *irq_pcie_phandle = xplic_phandles[socket]; 803 } 804 } 805 806 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); 807 } 808 809 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 810 uint32_t irq_virtio_phandle) 811 { 812 int i; 813 char *name; 814 MachineState *mc = MACHINE(s); 815 816 for (i = 0; i < VIRTIO_COUNT; i++) { 817 name = g_strdup_printf("/soc/virtio_mmio@%lx", 818 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 819 qemu_fdt_add_subnode(mc->fdt, name); 820 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); 821 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 822 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 823 0x0, memmap[VIRT_VIRTIO].size); 824 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 825 irq_virtio_phandle); 826 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 827 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", 828 VIRTIO_IRQ + i); 829 } else { 830 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", 831 VIRTIO_IRQ + i, 0x4); 832 } 833 g_free(name); 834 } 835 } 836 837 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 838 uint32_t irq_pcie_phandle, 839 uint32_t msi_pcie_phandle) 840 { 841 char *name; 842 MachineState *mc = MACHINE(s); 843 844 name = g_strdup_printf("/soc/pci@%lx", 845 (long) memmap[VIRT_PCIE_ECAM].base); 846 qemu_fdt_add_subnode(mc->fdt, name); 847 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", 848 FDT_PCI_ADDR_CELLS); 849 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 850 FDT_PCI_INT_CELLS); 851 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); 852 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 853 "pci-host-ecam-generic"); 854 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); 855 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); 856 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, 857 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 858 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); 859 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 860 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); 861 } 862 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, 863 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 864 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", 865 1, FDT_PCI_RANGE_IOPORT, 2, 0, 866 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 867 1, FDT_PCI_RANGE_MMIO, 868 2, memmap[VIRT_PCIE_MMIO].base, 869 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 870 1, FDT_PCI_RANGE_MMIO_64BIT, 871 2, virt_high_pcie_memmap.base, 872 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 873 874 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); 875 g_free(name); 876 } 877 878 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 879 uint32_t *phandle) 880 { 881 char *name; 882 uint32_t test_phandle; 883 MachineState *mc = MACHINE(s); 884 885 test_phandle = (*phandle)++; 886 name = g_strdup_printf("/soc/test@%lx", 887 (long)memmap[VIRT_TEST].base); 888 qemu_fdt_add_subnode(mc->fdt, name); 889 { 890 static const char * const compat[3] = { 891 "sifive,test1", "sifive,test0", "syscon" 892 }; 893 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", 894 (char **)&compat, ARRAY_SIZE(compat)); 895 } 896 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 897 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 898 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); 899 test_phandle = qemu_fdt_get_phandle(mc->fdt, name); 900 g_free(name); 901 902 name = g_strdup_printf("/reboot"); 903 qemu_fdt_add_subnode(mc->fdt, name); 904 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); 905 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 906 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 907 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); 908 g_free(name); 909 910 name = g_strdup_printf("/poweroff"); 911 qemu_fdt_add_subnode(mc->fdt, name); 912 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); 913 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 914 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 915 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); 916 g_free(name); 917 } 918 919 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 920 uint32_t irq_mmio_phandle) 921 { 922 char *name; 923 MachineState *mc = MACHINE(s); 924 925 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 926 qemu_fdt_add_subnode(mc->fdt, name); 927 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); 928 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 929 0x0, memmap[VIRT_UART0].base, 930 0x0, memmap[VIRT_UART0].size); 931 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); 932 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); 933 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 934 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); 935 } else { 936 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); 937 } 938 939 qemu_fdt_add_subnode(mc->fdt, "/chosen"); 940 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); 941 g_free(name); 942 } 943 944 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 945 uint32_t irq_mmio_phandle) 946 { 947 char *name; 948 MachineState *mc = MACHINE(s); 949 950 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 951 qemu_fdt_add_subnode(mc->fdt, name); 952 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 953 "google,goldfish-rtc"); 954 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 955 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 956 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 957 irq_mmio_phandle); 958 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 959 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); 960 } else { 961 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); 962 } 963 g_free(name); 964 } 965 966 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 967 { 968 char *name; 969 MachineState *mc = MACHINE(s); 970 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 971 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 972 973 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 974 qemu_fdt_add_subnode(mc->fdt, name); 975 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 976 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 977 2, flashbase, 2, flashsize, 978 2, flashbase + flashsize, 2, flashsize); 979 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 980 g_free(name); 981 } 982 983 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 984 { 985 char *nodename; 986 MachineState *mc = MACHINE(s); 987 hwaddr base = memmap[VIRT_FW_CFG].base; 988 hwaddr size = memmap[VIRT_FW_CFG].size; 989 990 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 991 qemu_fdt_add_subnode(mc->fdt, nodename); 992 qemu_fdt_setprop_string(mc->fdt, nodename, 993 "compatible", "qemu,fw-cfg-mmio"); 994 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 995 2, base, 2, size); 996 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 997 g_free(nodename); 998 } 999 1000 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 1001 uint64_t mem_size, const char *cmdline, bool is_32_bit) 1002 { 1003 MachineState *mc = MACHINE(s); 1004 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1005 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1006 uint8_t rng_seed[32]; 1007 1008 if (mc->dtb) { 1009 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 1010 if (!mc->fdt) { 1011 error_report("load_device_tree() failed"); 1012 exit(1); 1013 } 1014 goto update_bootargs; 1015 } else { 1016 mc->fdt = create_device_tree(&s->fdt_size); 1017 if (!mc->fdt) { 1018 error_report("create_device_tree() failed"); 1019 exit(1); 1020 } 1021 } 1022 1023 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); 1024 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); 1025 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); 1026 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); 1027 1028 qemu_fdt_add_subnode(mc->fdt, "/soc"); 1029 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); 1030 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); 1031 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); 1032 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); 1033 1034 create_fdt_sockets(s, memmap, is_32_bit, &phandle, 1035 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, 1036 &msi_pcie_phandle); 1037 1038 create_fdt_virtio(s, memmap, irq_virtio_phandle); 1039 1040 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); 1041 1042 create_fdt_reset(s, memmap, &phandle); 1043 1044 create_fdt_uart(s, memmap, irq_mmio_phandle); 1045 1046 create_fdt_rtc(s, memmap, irq_mmio_phandle); 1047 1048 create_fdt_flash(s, memmap); 1049 create_fdt_fw_cfg(s, memmap); 1050 create_fdt_pmu(s); 1051 1052 update_bootargs: 1053 if (cmdline && *cmdline) { 1054 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); 1055 } 1056 1057 /* Pass seed to RNG */ 1058 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1059 qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); 1060 } 1061 1062 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1063 hwaddr ecam_base, hwaddr ecam_size, 1064 hwaddr mmio_base, hwaddr mmio_size, 1065 hwaddr high_mmio_base, 1066 hwaddr high_mmio_size, 1067 hwaddr pio_base, 1068 DeviceState *irqchip) 1069 { 1070 DeviceState *dev; 1071 MemoryRegion *ecam_alias, *ecam_reg; 1072 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1073 qemu_irq irq; 1074 int i; 1075 1076 dev = qdev_new(TYPE_GPEX_HOST); 1077 1078 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1079 1080 ecam_alias = g_new0(MemoryRegion, 1); 1081 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1082 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1083 ecam_reg, 0, ecam_size); 1084 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1085 1086 mmio_alias = g_new0(MemoryRegion, 1); 1087 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1088 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1089 mmio_reg, mmio_base, mmio_size); 1090 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1091 1092 /* Map high MMIO space */ 1093 high_mmio_alias = g_new0(MemoryRegion, 1); 1094 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1095 mmio_reg, high_mmio_base, high_mmio_size); 1096 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1097 high_mmio_alias); 1098 1099 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1100 1101 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1102 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1103 1104 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1105 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1106 } 1107 1108 return dev; 1109 } 1110 1111 static FWCfgState *create_fw_cfg(const MachineState *mc) 1112 { 1113 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1114 FWCfgState *fw_cfg; 1115 1116 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1117 &address_space_memory); 1118 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 1119 1120 return fw_cfg; 1121 } 1122 1123 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1124 int base_hartid, int hart_count) 1125 { 1126 DeviceState *ret; 1127 char *plic_hart_config; 1128 1129 /* Per-socket PLIC hart topology configuration string */ 1130 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1131 1132 /* Per-socket PLIC */ 1133 ret = sifive_plic_create( 1134 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1135 plic_hart_config, hart_count, base_hartid, 1136 VIRT_IRQCHIP_NUM_SOURCES, 1137 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1138 VIRT_PLIC_PRIORITY_BASE, 1139 VIRT_PLIC_PENDING_BASE, 1140 VIRT_PLIC_ENABLE_BASE, 1141 VIRT_PLIC_ENABLE_STRIDE, 1142 VIRT_PLIC_CONTEXT_BASE, 1143 VIRT_PLIC_CONTEXT_STRIDE, 1144 memmap[VIRT_PLIC].size); 1145 1146 g_free(plic_hart_config); 1147 1148 return ret; 1149 } 1150 1151 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1152 const MemMapEntry *memmap, int socket, 1153 int base_hartid, int hart_count) 1154 { 1155 int i; 1156 hwaddr addr; 1157 uint32_t guest_bits; 1158 DeviceState *aplic_m; 1159 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; 1160 1161 if (msimode) { 1162 /* Per-socket M-level IMSICs */ 1163 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1164 for (i = 0; i < hart_count; i++) { 1165 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1166 base_hartid + i, true, 1, 1167 VIRT_IRQCHIP_NUM_MSIS); 1168 } 1169 1170 /* Per-socket S-level IMSICs */ 1171 guest_bits = imsic_num_bits(aia_guests + 1); 1172 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1173 for (i = 0; i < hart_count; i++) { 1174 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1175 base_hartid + i, false, 1 + aia_guests, 1176 VIRT_IRQCHIP_NUM_MSIS); 1177 } 1178 } 1179 1180 /* Per-socket M-level APLIC */ 1181 aplic_m = riscv_aplic_create( 1182 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, 1183 memmap[VIRT_APLIC_M].size, 1184 (msimode) ? 0 : base_hartid, 1185 (msimode) ? 0 : hart_count, 1186 VIRT_IRQCHIP_NUM_SOURCES, 1187 VIRT_IRQCHIP_NUM_PRIO_BITS, 1188 msimode, true, NULL); 1189 1190 if (aplic_m) { 1191 /* Per-socket S-level APLIC */ 1192 riscv_aplic_create( 1193 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, 1194 memmap[VIRT_APLIC_S].size, 1195 (msimode) ? 0 : base_hartid, 1196 (msimode) ? 0 : hart_count, 1197 VIRT_IRQCHIP_NUM_SOURCES, 1198 VIRT_IRQCHIP_NUM_PRIO_BITS, 1199 msimode, false, aplic_m); 1200 } 1201 1202 return aplic_m; 1203 } 1204 1205 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1206 { 1207 DeviceState *dev; 1208 SysBusDevice *sysbus; 1209 const MemMapEntry *memmap = virt_memmap; 1210 int i; 1211 MemoryRegion *sysmem = get_system_memory(); 1212 1213 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1214 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1215 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1216 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1217 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1218 s->platform_bus_dev = dev; 1219 1220 sysbus = SYS_BUS_DEVICE(dev); 1221 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1222 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1223 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1224 } 1225 1226 memory_region_add_subregion(sysmem, 1227 memmap[VIRT_PLATFORM_BUS].base, 1228 sysbus_mmio_get_region(sysbus, 0)); 1229 } 1230 1231 static void virt_machine_done(Notifier *notifier, void *data) 1232 { 1233 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1234 machine_done); 1235 const MemMapEntry *memmap = virt_memmap; 1236 MachineState *machine = MACHINE(s); 1237 target_ulong start_addr = memmap[VIRT_DRAM].base; 1238 target_ulong firmware_end_addr, kernel_start_addr; 1239 uint32_t fdt_load_addr; 1240 uint64_t kernel_entry; 1241 1242 /* 1243 * Only direct boot kernel is currently supported for KVM VM, 1244 * so the "-bios" parameter is not supported when KVM is enabled. 1245 */ 1246 if (kvm_enabled()) { 1247 if (machine->firmware) { 1248 if (strcmp(machine->firmware, "none")) { 1249 error_report("Machine mode firmware is not supported in " 1250 "combination with KVM."); 1251 exit(1); 1252 } 1253 } else { 1254 machine->firmware = g_strdup("none"); 1255 } 1256 } 1257 1258 if (riscv_is_32bit(&s->soc[0])) { 1259 firmware_end_addr = riscv_find_and_load_firmware(machine, 1260 RISCV32_BIOS_BIN, start_addr, NULL); 1261 } else { 1262 firmware_end_addr = riscv_find_and_load_firmware(machine, 1263 RISCV64_BIOS_BIN, start_addr, NULL); 1264 } 1265 1266 /* 1267 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 1268 * tree cannot be altered and we get FDT_ERR_NOSPACE. 1269 */ 1270 s->fw_cfg = create_fw_cfg(machine); 1271 rom_set_fw(s->fw_cfg); 1272 1273 if (drive_get(IF_PFLASH, 0, 1)) { 1274 /* 1275 * S-mode FW like EDK2 will be kept in second plash (unit 1). 1276 * When both kernel, initrd and pflash options are provided in the 1277 * command line, the kernel and initrd will be copied to the fw_cfg 1278 * table and opensbi will jump to the flash address which is the 1279 * entry point of S-mode FW. It is the job of the S-mode FW to load 1280 * the kernel and initrd using fw_cfg table. 1281 * 1282 * If only pflash is given but not -kernel, then it is the job of 1283 * of the S-mode firmware to locate and load the kernel. 1284 * In either case, the next_addr for opensbi will be the flash address. 1285 */ 1286 riscv_setup_firmware_boot(machine); 1287 kernel_entry = virt_memmap[VIRT_FLASH].base + 1288 virt_memmap[VIRT_FLASH].size / 2; 1289 } else if (machine->kernel_filename) { 1290 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1291 firmware_end_addr); 1292 1293 kernel_entry = riscv_load_kernel(machine->kernel_filename, 1294 kernel_start_addr, NULL); 1295 1296 if (machine->initrd_filename) { 1297 hwaddr start; 1298 hwaddr end = riscv_load_initrd(machine->initrd_filename, 1299 machine->ram_size, kernel_entry, 1300 &start); 1301 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 1302 "linux,initrd-start", start); 1303 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 1304 end); 1305 } 1306 } else { 1307 /* 1308 * If dynamic firmware is used, it doesn't know where is the next mode 1309 * if kernel argument is not set. 1310 */ 1311 kernel_entry = 0; 1312 } 1313 1314 if (drive_get(IF_PFLASH, 0, 0)) { 1315 /* 1316 * Pflash was supplied, let's overwrite the address we jump to after 1317 * reset to the base of the flash. 1318 */ 1319 start_addr = virt_memmap[VIRT_FLASH].base; 1320 } 1321 1322 /* Compute the fdt load address in dram */ 1323 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 1324 machine->ram_size, machine->fdt); 1325 /* load the reset vector */ 1326 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1327 virt_memmap[VIRT_MROM].base, 1328 virt_memmap[VIRT_MROM].size, kernel_entry, 1329 fdt_load_addr); 1330 1331 /* 1332 * Only direct boot kernel is currently supported for KVM VM, 1333 * So here setup kernel start address and fdt address. 1334 * TODO:Support firmware loading and integrate to TCG start 1335 */ 1336 if (kvm_enabled()) { 1337 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1338 } 1339 } 1340 1341 static void virt_machine_init(MachineState *machine) 1342 { 1343 const MemMapEntry *memmap = virt_memmap; 1344 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1345 MemoryRegion *system_memory = get_system_memory(); 1346 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1347 char *soc_name; 1348 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1349 int i, base_hartid, hart_count; 1350 1351 /* Check socket count limit */ 1352 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 1353 error_report("number of sockets/nodes should be less than %d", 1354 VIRT_SOCKETS_MAX); 1355 exit(1); 1356 } 1357 1358 /* Initialize sockets */ 1359 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1360 for (i = 0; i < riscv_socket_count(machine); i++) { 1361 if (!riscv_socket_check_hartids(machine, i)) { 1362 error_report("discontinuous hartids in socket%d", i); 1363 exit(1); 1364 } 1365 1366 base_hartid = riscv_socket_first_hartid(machine, i); 1367 if (base_hartid < 0) { 1368 error_report("can't find hartid base for socket%d", i); 1369 exit(1); 1370 } 1371 1372 hart_count = riscv_socket_hart_count(machine, i); 1373 if (hart_count < 0) { 1374 error_report("can't find hart count for socket%d", i); 1375 exit(1); 1376 } 1377 1378 soc_name = g_strdup_printf("soc%d", i); 1379 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1380 TYPE_RISCV_HART_ARRAY); 1381 g_free(soc_name); 1382 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1383 machine->cpu_type, &error_abort); 1384 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1385 base_hartid, &error_abort); 1386 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1387 hart_count, &error_abort); 1388 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1389 1390 if (!kvm_enabled()) { 1391 if (s->have_aclint) { 1392 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1393 /* Per-socket ACLINT MTIMER */ 1394 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1395 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1396 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1397 base_hartid, hart_count, 1398 RISCV_ACLINT_DEFAULT_MTIMECMP, 1399 RISCV_ACLINT_DEFAULT_MTIME, 1400 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1401 } else { 1402 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1403 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1404 i * memmap[VIRT_CLINT].size, 1405 base_hartid, hart_count, false); 1406 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1407 i * memmap[VIRT_CLINT].size + 1408 RISCV_ACLINT_SWI_SIZE, 1409 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1410 base_hartid, hart_count, 1411 RISCV_ACLINT_DEFAULT_MTIMECMP, 1412 RISCV_ACLINT_DEFAULT_MTIME, 1413 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1414 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1415 i * memmap[VIRT_ACLINT_SSWI].size, 1416 base_hartid, hart_count, true); 1417 } 1418 } else { 1419 /* Per-socket SiFive CLINT */ 1420 riscv_aclint_swi_create( 1421 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1422 base_hartid, hart_count, false); 1423 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1424 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1425 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1426 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1427 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1428 } 1429 } 1430 1431 /* Per-socket interrupt controller */ 1432 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1433 s->irqchip[i] = virt_create_plic(memmap, i, 1434 base_hartid, hart_count); 1435 } else { 1436 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1437 memmap, i, base_hartid, 1438 hart_count); 1439 } 1440 1441 /* Try to use different IRQCHIP instance based device type */ 1442 if (i == 0) { 1443 mmio_irqchip = s->irqchip[i]; 1444 virtio_irqchip = s->irqchip[i]; 1445 pcie_irqchip = s->irqchip[i]; 1446 } 1447 if (i == 1) { 1448 virtio_irqchip = s->irqchip[i]; 1449 pcie_irqchip = s->irqchip[i]; 1450 } 1451 if (i == 2) { 1452 pcie_irqchip = s->irqchip[i]; 1453 } 1454 } 1455 1456 if (riscv_is_32bit(&s->soc[0])) { 1457 #if HOST_LONG_BITS == 64 1458 /* limit RAM size in a 32-bit system */ 1459 if (machine->ram_size > 10 * GiB) { 1460 machine->ram_size = 10 * GiB; 1461 error_report("Limiting RAM size to 10 GiB"); 1462 } 1463 #endif 1464 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1465 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1466 } else { 1467 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1468 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1469 virt_high_pcie_memmap.base = 1470 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1471 } 1472 1473 /* register system main memory (actual RAM) */ 1474 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1475 machine->ram); 1476 1477 /* boot rom */ 1478 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1479 memmap[VIRT_MROM].size, &error_fatal); 1480 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1481 mask_rom); 1482 1483 /* SiFive Test MMIO device */ 1484 sifive_test_create(memmap[VIRT_TEST].base); 1485 1486 /* VirtIO MMIO devices */ 1487 for (i = 0; i < VIRTIO_COUNT; i++) { 1488 sysbus_create_simple("virtio-mmio", 1489 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1490 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); 1491 } 1492 1493 gpex_pcie_init(system_memory, 1494 memmap[VIRT_PCIE_ECAM].base, 1495 memmap[VIRT_PCIE_ECAM].size, 1496 memmap[VIRT_PCIE_MMIO].base, 1497 memmap[VIRT_PCIE_MMIO].size, 1498 virt_high_pcie_memmap.base, 1499 virt_high_pcie_memmap.size, 1500 memmap[VIRT_PCIE_PIO].base, 1501 DEVICE(pcie_irqchip)); 1502 1503 create_platform_bus(s, DEVICE(mmio_irqchip)); 1504 1505 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1506 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, 1507 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1508 1509 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1510 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); 1511 1512 virt_flash_create(s); 1513 1514 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1515 /* Map legacy -drive if=pflash to machine properties */ 1516 pflash_cfi01_legacy_drive(s->flash[i], 1517 drive_get(IF_PFLASH, 0, i)); 1518 } 1519 virt_flash_map(s, system_memory); 1520 1521 /* create device tree */ 1522 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 1523 riscv_is_32bit(&s->soc[0])); 1524 1525 s->machine_done.notify = virt_machine_done; 1526 qemu_add_machine_init_done_notifier(&s->machine_done); 1527 } 1528 1529 static void virt_machine_instance_init(Object *obj) 1530 { 1531 } 1532 1533 static char *virt_get_aia_guests(Object *obj, Error **errp) 1534 { 1535 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1536 char val[32]; 1537 1538 sprintf(val, "%d", s->aia_guests); 1539 return g_strdup(val); 1540 } 1541 1542 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1543 { 1544 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1545 1546 s->aia_guests = atoi(val); 1547 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1548 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1549 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1550 VIRT_IRQCHIP_MAX_GUESTS); 1551 } 1552 } 1553 1554 static char *virt_get_aia(Object *obj, Error **errp) 1555 { 1556 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1557 const char *val; 1558 1559 switch (s->aia_type) { 1560 case VIRT_AIA_TYPE_APLIC: 1561 val = "aplic"; 1562 break; 1563 case VIRT_AIA_TYPE_APLIC_IMSIC: 1564 val = "aplic-imsic"; 1565 break; 1566 default: 1567 val = "none"; 1568 break; 1569 }; 1570 1571 return g_strdup(val); 1572 } 1573 1574 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1575 { 1576 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1577 1578 if (!strcmp(val, "none")) { 1579 s->aia_type = VIRT_AIA_TYPE_NONE; 1580 } else if (!strcmp(val, "aplic")) { 1581 s->aia_type = VIRT_AIA_TYPE_APLIC; 1582 } else if (!strcmp(val, "aplic-imsic")) { 1583 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1584 } else { 1585 error_setg(errp, "Invalid AIA interrupt controller type"); 1586 error_append_hint(errp, "Valid values are none, aplic, and " 1587 "aplic-imsic.\n"); 1588 } 1589 } 1590 1591 static bool virt_get_aclint(Object *obj, Error **errp) 1592 { 1593 MachineState *ms = MACHINE(obj); 1594 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1595 1596 return s->have_aclint; 1597 } 1598 1599 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1600 { 1601 MachineState *ms = MACHINE(obj); 1602 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1603 1604 s->have_aclint = value; 1605 } 1606 1607 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1608 DeviceState *dev) 1609 { 1610 MachineClass *mc = MACHINE_GET_CLASS(machine); 1611 1612 if (device_is_dynamic_sysbus(mc, dev)) { 1613 return HOTPLUG_HANDLER(machine); 1614 } 1615 return NULL; 1616 } 1617 1618 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1619 DeviceState *dev, Error **errp) 1620 { 1621 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1622 1623 if (s->platform_bus_dev) { 1624 MachineClass *mc = MACHINE_GET_CLASS(s); 1625 1626 if (device_is_dynamic_sysbus(mc, dev)) { 1627 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1628 SYS_BUS_DEVICE(dev)); 1629 } 1630 } 1631 } 1632 1633 static void virt_machine_class_init(ObjectClass *oc, void *data) 1634 { 1635 char str[128]; 1636 MachineClass *mc = MACHINE_CLASS(oc); 1637 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1638 1639 mc->desc = "RISC-V VirtIO board"; 1640 mc->init = virt_machine_init; 1641 mc->max_cpus = VIRT_CPUS_MAX; 1642 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1643 mc->pci_allow_0_address = true; 1644 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1645 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1646 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1647 mc->numa_mem_supported = true; 1648 mc->default_ram_id = "riscv_virt_board.ram"; 1649 assert(!mc->get_hotplug_handler); 1650 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1651 1652 hc->plug = virt_machine_device_plug_cb; 1653 1654 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1655 #ifdef CONFIG_TPM 1656 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1657 #endif 1658 1659 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1660 virt_set_aclint); 1661 object_class_property_set_description(oc, "aclint", 1662 "Set on/off to enable/disable " 1663 "emulating ACLINT devices"); 1664 1665 object_class_property_add_str(oc, "aia", virt_get_aia, 1666 virt_set_aia); 1667 object_class_property_set_description(oc, "aia", 1668 "Set type of AIA interrupt " 1669 "conttoller. Valid values are " 1670 "none, aplic, and aplic-imsic."); 1671 1672 object_class_property_add_str(oc, "aia-guests", 1673 virt_get_aia_guests, 1674 virt_set_aia_guests); 1675 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1676 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1677 object_class_property_set_description(oc, "aia-guests", str); 1678 } 1679 1680 static const TypeInfo virt_machine_typeinfo = { 1681 .name = MACHINE_TYPE_NAME("virt"), 1682 .parent = TYPE_MACHINE, 1683 .class_init = virt_machine_class_init, 1684 .instance_init = virt_machine_instance_init, 1685 .instance_size = sizeof(RISCVVirtState), 1686 .interfaces = (InterfaceInfo[]) { 1687 { TYPE_HOTPLUG_HANDLER }, 1688 { } 1689 }, 1690 }; 1691 1692 static void virt_machine_init_register_types(void) 1693 { 1694 type_register_static(&virt_machine_typeinfo); 1695 } 1696 1697 type_init(virt_machine_init_register_types) 1698