1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial-mm.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/iommu.h" 36 #include "hw/riscv/riscv-iommu-bits.h" 37 #include "hw/riscv/virt.h" 38 #include "hw/riscv/boot.h" 39 #include "hw/riscv/numa.h" 40 #include "kvm/kvm_riscv.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/intc/riscv_aclint.h" 43 #include "hw/intc/riscv_aplic.h" 44 #include "hw/intc/sifive_plic.h" 45 #include "hw/misc/sifive_test.h" 46 #include "hw/platform-bus.h" 47 #include "chardev/char.h" 48 #include "system/device_tree.h" 49 #include "system/system.h" 50 #include "system/tcg.h" 51 #include "system/kvm.h" 52 #include "system/tpm.h" 53 #include "system/qtest.h" 54 #include "hw/pci/pci.h" 55 #include "hw/pci-host/gpex.h" 56 #include "hw/display/ramfb.h" 57 #include "hw/acpi/aml-build.h" 58 #include "qapi/qapi-visit-common.h" 59 #include "hw/virtio/virtio-iommu.h" 60 #include "hw/uefi/var-service-api.h" 61 62 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 63 static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type) 64 { 65 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 66 67 return riscv_is_kvm_aia_aplic_imsic(msimode); 68 } 69 70 static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type) 71 { 72 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 73 74 return riscv_use_emulated_aplic(msimode); 75 } 76 77 static bool virt_aclint_allowed(void) 78 { 79 return tcg_enabled() || qtest_enabled(); 80 } 81 82 static const MemMapEntry virt_memmap[] = { 83 [VIRT_DEBUG] = { 0x0, 0x100 }, 84 [VIRT_MROM] = { 0x1000, 0xf000 }, 85 [VIRT_TEST] = { 0x100000, 0x1000 }, 86 [VIRT_RTC] = { 0x101000, 0x1000 }, 87 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 88 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 89 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 90 [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 }, 91 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 92 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 93 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 94 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 95 [VIRT_UART0] = { 0x10000000, 0x100 }, 96 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 97 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 98 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 99 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 100 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 101 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 102 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 103 [VIRT_DRAM] = { 0x80000000, 0x0 }, 104 }; 105 106 /* PCIe high mmio is fixed for RV32 */ 107 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 108 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 109 110 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 111 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 112 113 static MemMapEntry virt_high_pcie_memmap; 114 115 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 116 117 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 118 const char *name, 119 const char *alias_prop_name) 120 { 121 /* 122 * Create a single flash device. We use the same parameters as 123 * the flash devices on the ARM virt board. 124 */ 125 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 126 127 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 128 qdev_prop_set_uint8(dev, "width", 4); 129 qdev_prop_set_uint8(dev, "device-width", 2); 130 qdev_prop_set_bit(dev, "big-endian", false); 131 qdev_prop_set_uint16(dev, "id0", 0x89); 132 qdev_prop_set_uint16(dev, "id1", 0x18); 133 qdev_prop_set_uint16(dev, "id2", 0x00); 134 qdev_prop_set_uint16(dev, "id3", 0x00); 135 qdev_prop_set_string(dev, "name", name); 136 137 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 138 object_property_add_alias(OBJECT(s), alias_prop_name, 139 OBJECT(dev), "drive"); 140 141 return PFLASH_CFI01(dev); 142 } 143 144 static void virt_flash_create(RISCVVirtState *s) 145 { 146 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 147 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 148 } 149 150 static void virt_flash_map1(PFlashCFI01 *flash, 151 hwaddr base, hwaddr size, 152 MemoryRegion *sysmem) 153 { 154 DeviceState *dev = DEVICE(flash); 155 156 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 157 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 158 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 159 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 160 161 memory_region_add_subregion(sysmem, base, 162 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 163 0)); 164 } 165 166 static void virt_flash_map(RISCVVirtState *s, 167 MemoryRegion *sysmem) 168 { 169 hwaddr flashsize = s->memmap[VIRT_FLASH].size / 2; 170 hwaddr flashbase = s->memmap[VIRT_FLASH].base; 171 172 virt_flash_map1(s->flash[0], flashbase, flashsize, 173 sysmem); 174 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 175 sysmem); 176 } 177 178 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 179 uint32_t irqchip_phandle) 180 { 181 int pin, dev; 182 uint32_t irq_map_stride = 0; 183 uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * 184 FDT_MAX_INT_MAP_WIDTH] = {}; 185 uint32_t *irq_map = full_irq_map; 186 187 /* This code creates a standard swizzle of interrupts such that 188 * each device's first interrupt is based on it's PCI_SLOT number. 189 * (See pci_swizzle_map_irq_fn()) 190 * 191 * We only need one entry per interrupt in the table (not one per 192 * possible slot) seeing the interrupt-map-mask will allow the table 193 * to wrap to any number of devices. 194 */ 195 for (dev = 0; dev < PCI_NUM_PINS; dev++) { 196 int devfn = dev * 0x8; 197 198 for (pin = 0; pin < PCI_NUM_PINS; pin++) { 199 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 200 int i = 0; 201 202 /* Fill PCI address cells */ 203 irq_map[i] = cpu_to_be32(devfn << 8); 204 i += FDT_PCI_ADDR_CELLS; 205 206 /* Fill PCI Interrupt cells */ 207 irq_map[i] = cpu_to_be32(pin + 1); 208 i += FDT_PCI_INT_CELLS; 209 210 /* Fill interrupt controller phandle and cells */ 211 irq_map[i++] = cpu_to_be32(irqchip_phandle); 212 irq_map[i++] = cpu_to_be32(irq_nr); 213 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 214 irq_map[i++] = cpu_to_be32(0x4); 215 } 216 217 if (!irq_map_stride) { 218 irq_map_stride = i; 219 } 220 irq_map += irq_map_stride; 221 } 222 } 223 224 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 225 PCI_NUM_PINS * PCI_NUM_PINS * 226 irq_map_stride * sizeof(uint32_t)); 227 228 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 229 0x1800, 0, 0, 0x7); 230 } 231 232 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 233 char *clust_name, uint32_t *phandle, 234 uint32_t *intc_phandles) 235 { 236 int cpu; 237 uint32_t cpu_phandle; 238 MachineState *ms = MACHINE(s); 239 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 240 241 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 242 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 243 int8_t satp_mode_max = cpu_ptr->cfg.max_satp_mode; 244 g_autofree char *cpu_name = NULL; 245 g_autofree char *core_name = NULL; 246 g_autofree char *intc_name = NULL; 247 g_autofree char *sv_name = NULL; 248 249 cpu_phandle = (*phandle)++; 250 251 cpu_name = g_strdup_printf("/cpus/cpu@%d", 252 s->soc[socket].hartid_base + cpu); 253 qemu_fdt_add_subnode(ms->fdt, cpu_name); 254 255 if (satp_mode_max != -1) { 256 sv_name = g_strdup_printf("riscv,%s", 257 satp_mode_str(satp_mode_max, is_32_bit)); 258 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 259 } 260 261 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); 262 263 if (cpu_ptr->cfg.ext_zicbom) { 264 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 265 cpu_ptr->cfg.cbom_blocksize); 266 } 267 268 if (cpu_ptr->cfg.ext_zicboz) { 269 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 270 cpu_ptr->cfg.cboz_blocksize); 271 } 272 273 if (cpu_ptr->cfg.ext_zicbop) { 274 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 275 cpu_ptr->cfg.cbop_blocksize); 276 } 277 278 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 279 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 280 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 281 s->soc[socket].hartid_base + cpu); 282 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 283 riscv_socket_fdt_write_id(ms, cpu_name, socket); 284 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 285 286 intc_phandles[cpu] = (*phandle)++; 287 288 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 289 qemu_fdt_add_subnode(ms->fdt, intc_name); 290 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 291 intc_phandles[cpu]); 292 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 293 "riscv,cpu-intc"); 294 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 295 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 296 297 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 298 qemu_fdt_add_subnode(ms->fdt, core_name); 299 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 300 } 301 } 302 303 static void create_fdt_socket_memory(RISCVVirtState *s, int socket) 304 { 305 g_autofree char *mem_name = NULL; 306 hwaddr addr; 307 uint64_t size; 308 MachineState *ms = MACHINE(s); 309 310 addr = s->memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 311 size = riscv_socket_mem_size(ms, socket); 312 mem_name = g_strdup_printf("/memory@%"HWADDR_PRIx, addr); 313 qemu_fdt_add_subnode(ms->fdt, mem_name); 314 qemu_fdt_setprop_sized_cells(ms->fdt, mem_name, "reg", 2, addr, 2, size); 315 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 316 riscv_socket_fdt_write_id(ms, mem_name, socket); 317 } 318 319 static void create_fdt_socket_clint(RISCVVirtState *s, 320 int socket, 321 uint32_t *intc_phandles) 322 { 323 int cpu; 324 g_autofree char *clint_name = NULL; 325 g_autofree uint32_t *clint_cells = NULL; 326 hwaddr clint_addr; 327 MachineState *ms = MACHINE(s); 328 static const char * const clint_compat[2] = { 329 "sifive,clint0", "riscv,clint0" 330 }; 331 332 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 333 334 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 335 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 336 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 337 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 338 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 339 } 340 341 clint_addr = s->memmap[VIRT_CLINT].base + 342 s->memmap[VIRT_CLINT].size * socket; 343 clint_name = g_strdup_printf("/soc/clint@%"HWADDR_PRIx, clint_addr); 344 qemu_fdt_add_subnode(ms->fdt, clint_name); 345 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 346 (char **)&clint_compat, 347 ARRAY_SIZE(clint_compat)); 348 qemu_fdt_setprop_sized_cells(ms->fdt, clint_name, "reg", 349 2, clint_addr, 2, s->memmap[VIRT_CLINT].size); 350 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 351 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 352 riscv_socket_fdt_write_id(ms, clint_name, socket); 353 } 354 355 static void create_fdt_socket_aclint(RISCVVirtState *s, 356 int socket, 357 uint32_t *intc_phandles) 358 { 359 int cpu; 360 char *name; 361 unsigned long addr, size; 362 uint32_t aclint_cells_size; 363 g_autofree uint32_t *aclint_mswi_cells = NULL; 364 g_autofree uint32_t *aclint_sswi_cells = NULL; 365 g_autofree uint32_t *aclint_mtimer_cells = NULL; 366 MachineState *ms = MACHINE(s); 367 368 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 369 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 370 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 371 372 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 373 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 374 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 375 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 376 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 377 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 378 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 379 } 380 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 381 382 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 383 addr = s->memmap[VIRT_CLINT].base + 384 (s->memmap[VIRT_CLINT].size * socket); 385 name = g_strdup_printf("/soc/mswi@%lx", addr); 386 387 qemu_fdt_add_subnode(ms->fdt, name); 388 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 389 "riscv,aclint-mswi"); 390 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 391 2, addr, 2, RISCV_ACLINT_SWI_SIZE); 392 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 393 aclint_mswi_cells, aclint_cells_size); 394 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 395 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 396 riscv_socket_fdt_write_id(ms, name, socket); 397 g_free(name); 398 } 399 400 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 401 addr = s->memmap[VIRT_CLINT].base + 402 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 403 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 404 } else { 405 addr = s->memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 406 (s->memmap[VIRT_CLINT].size * socket); 407 size = s->memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 408 } 409 name = g_strdup_printf("/soc/mtimer@%lx", addr); 410 qemu_fdt_add_subnode(ms->fdt, name); 411 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 412 "riscv,aclint-mtimer"); 413 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 414 2, addr + RISCV_ACLINT_DEFAULT_MTIME, 415 2, size - RISCV_ACLINT_DEFAULT_MTIME, 416 2, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 417 2, RISCV_ACLINT_DEFAULT_MTIME); 418 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 419 aclint_mtimer_cells, aclint_cells_size); 420 riscv_socket_fdt_write_id(ms, name, socket); 421 g_free(name); 422 423 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 424 addr = s->memmap[VIRT_ACLINT_SSWI].base + 425 (s->memmap[VIRT_ACLINT_SSWI].size * socket); 426 427 name = g_strdup_printf("/soc/sswi@%lx", addr); 428 qemu_fdt_add_subnode(ms->fdt, name); 429 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 430 "riscv,aclint-sswi"); 431 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 432 2, addr, 2, s->memmap[VIRT_ACLINT_SSWI].size); 433 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 434 aclint_sswi_cells, aclint_cells_size); 435 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 436 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 437 riscv_socket_fdt_write_id(ms, name, socket); 438 g_free(name); 439 } 440 } 441 442 static void create_fdt_socket_plic(RISCVVirtState *s, 443 int socket, 444 uint32_t *phandle, uint32_t *intc_phandles, 445 uint32_t *plic_phandles) 446 { 447 int cpu; 448 g_autofree char *plic_name = NULL; 449 g_autofree uint32_t *plic_cells; 450 unsigned long plic_addr; 451 MachineState *ms = MACHINE(s); 452 static const char * const plic_compat[2] = { 453 "sifive,plic-1.0.0", "riscv,plic0" 454 }; 455 456 plic_phandles[socket] = (*phandle)++; 457 plic_addr = s->memmap[VIRT_PLIC].base + 458 (s->memmap[VIRT_PLIC].size * socket); 459 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 460 qemu_fdt_add_subnode(ms->fdt, plic_name); 461 qemu_fdt_setprop_cell(ms->fdt, plic_name, 462 "#interrupt-cells", FDT_PLIC_INT_CELLS); 463 qemu_fdt_setprop_cell(ms->fdt, plic_name, 464 "#address-cells", FDT_PLIC_ADDR_CELLS); 465 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 466 (char **)&plic_compat, 467 ARRAY_SIZE(plic_compat)); 468 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 469 470 if (kvm_enabled()) { 471 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 472 473 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 474 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 475 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 476 } 477 478 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 479 plic_cells, 480 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 481 } else { 482 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 483 484 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 485 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 486 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 487 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 488 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 489 } 490 491 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 492 plic_cells, 493 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 494 } 495 496 qemu_fdt_setprop_sized_cells(ms->fdt, plic_name, "reg", 497 2, plic_addr, 2, s->memmap[VIRT_PLIC].size); 498 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 499 VIRT_IRQCHIP_NUM_SOURCES - 1); 500 riscv_socket_fdt_write_id(ms, plic_name, socket); 501 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 502 plic_phandles[socket]); 503 504 if (!socket) { 505 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 506 s->memmap[VIRT_PLATFORM_BUS].base, 507 s->memmap[VIRT_PLATFORM_BUS].size, 508 VIRT_PLATFORM_BUS_IRQ); 509 } 510 } 511 512 uint32_t imsic_num_bits(uint32_t count) 513 { 514 uint32_t ret = 0; 515 516 while (BIT(ret) < count) { 517 ret++; 518 } 519 520 return ret; 521 } 522 523 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 524 uint32_t *intc_phandles, uint32_t msi_phandle, 525 bool m_mode, uint32_t imsic_guest_bits) 526 { 527 int cpu, socket; 528 g_autofree char *imsic_name = NULL; 529 MachineState *ms = MACHINE(s); 530 int socket_count = riscv_socket_count(ms); 531 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 532 g_autofree uint32_t *imsic_cells = NULL; 533 g_autofree uint32_t *imsic_regs = NULL; 534 static const char * const imsic_compat[2] = { 535 "qemu,imsics", "riscv,imsics" 536 }; 537 538 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 539 imsic_regs = g_new0(uint32_t, socket_count * 4); 540 541 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 542 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 543 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 544 } 545 546 imsic_max_hart_per_socket = 0; 547 for (socket = 0; socket < socket_count; socket++) { 548 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 549 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 550 s->soc[socket].num_harts; 551 imsic_regs[socket * 4 + 0] = 0; 552 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 553 imsic_regs[socket * 4 + 2] = 0; 554 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 555 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 556 imsic_max_hart_per_socket = s->soc[socket].num_harts; 557 } 558 } 559 560 imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx", 561 (unsigned long)base_addr); 562 qemu_fdt_add_subnode(ms->fdt, imsic_name); 563 qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", 564 (char **)&imsic_compat, 565 ARRAY_SIZE(imsic_compat)); 566 567 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 568 FDT_IMSIC_INT_CELLS); 569 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 570 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 571 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 572 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 573 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 574 socket_count * sizeof(uint32_t) * 4); 575 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 576 VIRT_IRQCHIP_NUM_MSIS); 577 578 if (imsic_guest_bits) { 579 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 580 imsic_guest_bits); 581 } 582 583 if (socket_count > 1) { 584 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 585 imsic_num_bits(imsic_max_hart_per_socket)); 586 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 587 imsic_num_bits(socket_count)); 588 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 589 IMSIC_MMIO_GROUP_MIN_SHIFT); 590 } 591 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 592 } 593 594 static void create_fdt_imsic(RISCVVirtState *s, 595 uint32_t *phandle, uint32_t *intc_phandles, 596 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 597 { 598 *msi_m_phandle = (*phandle)++; 599 *msi_s_phandle = (*phandle)++; 600 601 if (!kvm_enabled()) { 602 /* M-level IMSIC node */ 603 create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_M].base, intc_phandles, 604 *msi_m_phandle, true, 0); 605 } 606 607 /* S-level IMSIC node */ 608 create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_S].base, intc_phandles, 609 *msi_s_phandle, false, 610 imsic_num_bits(s->aia_guests + 1)); 611 612 } 613 614 /* Caller must free string after use */ 615 static char *fdt_get_aplic_nodename(unsigned long aplic_addr) 616 { 617 return g_strdup_printf("/soc/interrupt-controller@%lx", aplic_addr); 618 } 619 620 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 621 unsigned long aplic_addr, uint32_t aplic_size, 622 uint32_t msi_phandle, 623 uint32_t *intc_phandles, 624 uint32_t aplic_phandle, 625 uint32_t aplic_child_phandle, 626 bool m_mode, int num_harts) 627 { 628 int cpu; 629 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 630 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 631 MachineState *ms = MACHINE(s); 632 static const char * const aplic_compat[2] = { 633 "qemu,aplic", "riscv,aplic" 634 }; 635 636 for (cpu = 0; cpu < num_harts; cpu++) { 637 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 638 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 639 } 640 641 qemu_fdt_add_subnode(ms->fdt, aplic_name); 642 qemu_fdt_setprop_string_array(ms->fdt, aplic_name, "compatible", 643 (char **)&aplic_compat, 644 ARRAY_SIZE(aplic_compat)); 645 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells", 646 FDT_APLIC_ADDR_CELLS); 647 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 648 "#interrupt-cells", FDT_APLIC_INT_CELLS); 649 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 650 651 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 652 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 653 aplic_cells, num_harts * sizeof(uint32_t) * 2); 654 } else { 655 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 656 } 657 658 qemu_fdt_setprop_sized_cells(ms->fdt, aplic_name, "reg", 659 2, aplic_addr, 2, aplic_size); 660 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 661 VIRT_IRQCHIP_NUM_SOURCES); 662 663 if (aplic_child_phandle) { 664 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 665 aplic_child_phandle); 666 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation", 667 aplic_child_phandle, 0x1, 668 VIRT_IRQCHIP_NUM_SOURCES); 669 /* 670 * DEPRECATED_9.1: Compat property kept temporarily 671 * to allow old firmwares to work with AIA. Do *not* 672 * use 'riscv,delegate' in new code: use 673 * 'riscv,delegation' instead. 674 */ 675 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 676 aplic_child_phandle, 0x1, 677 VIRT_IRQCHIP_NUM_SOURCES); 678 } 679 680 riscv_socket_fdt_write_id(ms, aplic_name, socket); 681 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 682 } 683 684 static void create_fdt_socket_aplic(RISCVVirtState *s, 685 int socket, 686 uint32_t msi_m_phandle, 687 uint32_t msi_s_phandle, 688 uint32_t *phandle, 689 uint32_t *intc_phandles, 690 uint32_t *aplic_phandles, 691 int num_harts) 692 { 693 unsigned long aplic_addr; 694 MachineState *ms = MACHINE(s); 695 uint32_t aplic_m_phandle, aplic_s_phandle; 696 697 aplic_m_phandle = (*phandle)++; 698 aplic_s_phandle = (*phandle)++; 699 700 if (!kvm_enabled()) { 701 /* M-level APLIC node */ 702 aplic_addr = s->memmap[VIRT_APLIC_M].base + 703 (s->memmap[VIRT_APLIC_M].size * socket); 704 create_fdt_one_aplic(s, socket, aplic_addr, 705 s->memmap[VIRT_APLIC_M].size, 706 msi_m_phandle, intc_phandles, 707 aplic_m_phandle, aplic_s_phandle, 708 true, num_harts); 709 } 710 711 /* S-level APLIC node */ 712 aplic_addr = s->memmap[VIRT_APLIC_S].base + 713 (s->memmap[VIRT_APLIC_S].size * socket); 714 create_fdt_one_aplic(s, socket, aplic_addr, s->memmap[VIRT_APLIC_S].size, 715 msi_s_phandle, intc_phandles, 716 aplic_s_phandle, 0, 717 false, num_harts); 718 719 if (!socket) { 720 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 721 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 722 s->memmap[VIRT_PLATFORM_BUS].base, 723 s->memmap[VIRT_PLATFORM_BUS].size, 724 VIRT_PLATFORM_BUS_IRQ); 725 } 726 727 aplic_phandles[socket] = aplic_s_phandle; 728 } 729 730 static void create_fdt_pmu(RISCVVirtState *s) 731 { 732 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 733 MachineState *ms = MACHINE(s); 734 RISCVCPU hart = s->soc[0].harts[0]; 735 736 qemu_fdt_add_subnode(ms->fdt, pmu_name); 737 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 738 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 739 } 740 741 static void create_fdt_sockets(RISCVVirtState *s, 742 uint32_t *phandle, 743 uint32_t *irq_mmio_phandle, 744 uint32_t *irq_pcie_phandle, 745 uint32_t *irq_virtio_phandle, 746 uint32_t *msi_pcie_phandle) 747 { 748 int socket, phandle_pos; 749 MachineState *ms = MACHINE(s); 750 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 751 uint32_t xplic_phandles[MAX_NODES]; 752 g_autofree uint32_t *intc_phandles = NULL; 753 int socket_count = riscv_socket_count(ms); 754 755 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 756 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 757 kvm_enabled() ? 758 kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) : 759 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 760 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 761 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 762 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 763 764 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 765 766 phandle_pos = ms->smp.cpus; 767 for (socket = (socket_count - 1); socket >= 0; socket--) { 768 g_autofree char *clust_name = NULL; 769 phandle_pos -= s->soc[socket].num_harts; 770 771 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 772 qemu_fdt_add_subnode(ms->fdt, clust_name); 773 774 create_fdt_socket_cpus(s, socket, clust_name, phandle, 775 &intc_phandles[phandle_pos]); 776 777 create_fdt_socket_memory(s, socket); 778 779 if (virt_aclint_allowed() && s->have_aclint) { 780 create_fdt_socket_aclint(s, socket, 781 &intc_phandles[phandle_pos]); 782 } else if (tcg_enabled()) { 783 create_fdt_socket_clint(s, socket, 784 &intc_phandles[phandle_pos]); 785 } 786 } 787 788 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 789 create_fdt_imsic(s, phandle, intc_phandles, 790 &msi_m_phandle, &msi_s_phandle); 791 *msi_pcie_phandle = msi_s_phandle; 792 } 793 794 /* 795 * With KVM AIA aplic-imsic, using an irqchip without split 796 * mode, we'll use only one APLIC instance. 797 */ 798 if (!virt_use_emulated_aplic(s->aia_type)) { 799 create_fdt_socket_aplic(s, 0, 800 msi_m_phandle, msi_s_phandle, phandle, 801 &intc_phandles[0], xplic_phandles, 802 ms->smp.cpus); 803 804 *irq_mmio_phandle = xplic_phandles[0]; 805 *irq_virtio_phandle = xplic_phandles[0]; 806 *irq_pcie_phandle = xplic_phandles[0]; 807 } else { 808 phandle_pos = ms->smp.cpus; 809 for (socket = (socket_count - 1); socket >= 0; socket--) { 810 phandle_pos -= s->soc[socket].num_harts; 811 812 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 813 create_fdt_socket_plic(s, socket, phandle, 814 &intc_phandles[phandle_pos], 815 xplic_phandles); 816 } else { 817 create_fdt_socket_aplic(s, socket, 818 msi_m_phandle, msi_s_phandle, phandle, 819 &intc_phandles[phandle_pos], 820 xplic_phandles, 821 s->soc[socket].num_harts); 822 } 823 } 824 825 for (socket = 0; socket < socket_count; socket++) { 826 if (socket == 0) { 827 *irq_mmio_phandle = xplic_phandles[socket]; 828 *irq_virtio_phandle = xplic_phandles[socket]; 829 *irq_pcie_phandle = xplic_phandles[socket]; 830 } 831 if (socket == 1) { 832 *irq_virtio_phandle = xplic_phandles[socket]; 833 *irq_pcie_phandle = xplic_phandles[socket]; 834 } 835 if (socket == 2) { 836 *irq_pcie_phandle = xplic_phandles[socket]; 837 } 838 } 839 } 840 841 riscv_socket_fdt_write_distance_matrix(ms); 842 } 843 844 static void create_fdt_virtio(RISCVVirtState *s, uint32_t irq_virtio_phandle) 845 { 846 int i; 847 MachineState *ms = MACHINE(s); 848 hwaddr virtio_base = s->memmap[VIRT_VIRTIO].base; 849 850 for (i = 0; i < VIRTIO_COUNT; i++) { 851 g_autofree char *name = NULL; 852 uint64_t size = s->memmap[VIRT_VIRTIO].size; 853 hwaddr addr = virtio_base + i * size; 854 855 name = g_strdup_printf("/soc/virtio_mmio@%"HWADDR_PRIx, addr); 856 857 qemu_fdt_add_subnode(ms->fdt, name); 858 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 859 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, addr, 2, size); 860 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 861 irq_virtio_phandle); 862 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 863 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 864 VIRTIO_IRQ + i); 865 } else { 866 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 867 VIRTIO_IRQ + i, 0x4); 868 } 869 } 870 } 871 872 static void create_fdt_pcie(RISCVVirtState *s, 873 uint32_t irq_pcie_phandle, 874 uint32_t msi_pcie_phandle, 875 uint32_t iommu_sys_phandle) 876 { 877 g_autofree char *name = NULL; 878 MachineState *ms = MACHINE(s); 879 880 name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, 881 s->memmap[VIRT_PCIE_ECAM].base); 882 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 883 FDT_PCI_ADDR_CELLS); 884 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 885 FDT_PCI_INT_CELLS); 886 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 887 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 888 "pci-host-ecam-generic"); 889 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 890 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 891 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 892 s->memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 893 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 894 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 895 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 896 } 897 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 898 s->memmap[VIRT_PCIE_ECAM].base, 0, s->memmap[VIRT_PCIE_ECAM].size); 899 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 900 1, FDT_PCI_RANGE_IOPORT, 2, 0, 901 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size, 902 1, FDT_PCI_RANGE_MMIO, 903 2, s->memmap[VIRT_PCIE_MMIO].base, 904 2, s->memmap[VIRT_PCIE_MMIO].base, 2, s->memmap[VIRT_PCIE_MMIO].size, 905 1, FDT_PCI_RANGE_MMIO_64BIT, 906 2, virt_high_pcie_memmap.base, 907 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 908 909 if (virt_is_iommu_sys_enabled(s)) { 910 qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", 911 0, iommu_sys_phandle, 0, 0, 0, 912 iommu_sys_phandle, 0, 0xffff); 913 } 914 915 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 916 } 917 918 static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle) 919 { 920 char *name; 921 uint32_t test_phandle; 922 MachineState *ms = MACHINE(s); 923 924 test_phandle = (*phandle)++; 925 name = g_strdup_printf("/soc/test@%"HWADDR_PRIx, 926 s->memmap[VIRT_TEST].base); 927 qemu_fdt_add_subnode(ms->fdt, name); 928 { 929 static const char * const compat[3] = { 930 "sifive,test1", "sifive,test0", "syscon" 931 }; 932 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 933 (char **)&compat, ARRAY_SIZE(compat)); 934 } 935 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 936 0x0, s->memmap[VIRT_TEST].base, 0x0, s->memmap[VIRT_TEST].size); 937 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 938 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 939 g_free(name); 940 941 name = g_strdup_printf("/reboot"); 942 qemu_fdt_add_subnode(ms->fdt, name); 943 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 944 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 945 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 946 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 947 g_free(name); 948 949 name = g_strdup_printf("/poweroff"); 950 qemu_fdt_add_subnode(ms->fdt, name); 951 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 952 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 953 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 954 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 955 g_free(name); 956 } 957 958 static void create_fdt_uart(RISCVVirtState *s, 959 uint32_t irq_mmio_phandle) 960 { 961 g_autofree char *name = NULL; 962 MachineState *ms = MACHINE(s); 963 964 name = g_strdup_printf("/soc/serial@%"HWADDR_PRIx, 965 s->memmap[VIRT_UART0].base); 966 qemu_fdt_add_subnode(ms->fdt, name); 967 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 968 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 969 0x0, s->memmap[VIRT_UART0].base, 970 0x0, s->memmap[VIRT_UART0].size); 971 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 972 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 973 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 974 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 975 } else { 976 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 977 } 978 979 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 980 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); 981 } 982 983 static void create_fdt_rtc(RISCVVirtState *s, 984 uint32_t irq_mmio_phandle) 985 { 986 g_autofree char *name = NULL; 987 MachineState *ms = MACHINE(s); 988 989 name = g_strdup_printf("/soc/rtc@%"HWADDR_PRIx, 990 s->memmap[VIRT_RTC].base); 991 qemu_fdt_add_subnode(ms->fdt, name); 992 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 993 "google,goldfish-rtc"); 994 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 995 0x0, s->memmap[VIRT_RTC].base, 0x0, s->memmap[VIRT_RTC].size); 996 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 997 irq_mmio_phandle); 998 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 999 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 1000 } else { 1001 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 1002 } 1003 } 1004 1005 static void create_fdt_flash(RISCVVirtState *s) 1006 { 1007 MachineState *ms = MACHINE(s); 1008 hwaddr flashsize = s->memmap[VIRT_FLASH].size / 2; 1009 hwaddr flashbase = s->memmap[VIRT_FLASH].base; 1010 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 1011 1012 qemu_fdt_add_subnode(ms->fdt, name); 1013 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 1014 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 1015 2, flashbase, 2, flashsize, 1016 2, flashbase + flashsize, 2, flashsize); 1017 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 1018 } 1019 1020 static void create_fdt_fw_cfg(RISCVVirtState *s) 1021 { 1022 MachineState *ms = MACHINE(s); 1023 hwaddr base = s->memmap[VIRT_FW_CFG].base; 1024 hwaddr size = s->memmap[VIRT_FW_CFG].size; 1025 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1026 1027 qemu_fdt_add_subnode(ms->fdt, nodename); 1028 qemu_fdt_setprop_string(ms->fdt, nodename, 1029 "compatible", "qemu,fw-cfg-mmio"); 1030 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1031 2, base, 2, size); 1032 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1033 } 1034 1035 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) 1036 { 1037 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1038 void *fdt = MACHINE(s)->fdt; 1039 uint32_t iommu_phandle; 1040 g_autofree char *iommu_node = NULL; 1041 g_autofree char *pci_node = NULL; 1042 1043 pci_node = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, 1044 s->memmap[VIRT_PCIE_ECAM].base); 1045 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, 1046 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1047 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1048 1049 qemu_fdt_add_subnode(fdt, iommu_node); 1050 1051 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat)); 1052 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 1053 1, bdf << 8, 1, 0, 1, 0, 1054 1, 0, 1, 0); 1055 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1056 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1057 1058 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1059 0, iommu_phandle, 0, bdf, 1060 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1061 } 1062 1063 static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, 1064 uint32_t msi_phandle, 1065 uint32_t *iommu_sys_phandle) 1066 { 1067 const char comp[] = "riscv,iommu"; 1068 void *fdt = MACHINE(s)->fdt; 1069 uint32_t iommu_phandle; 1070 g_autofree char *iommu_node = NULL; 1071 hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base; 1072 hwaddr size = s->memmap[VIRT_IOMMU_SYS].size; 1073 uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = { 1074 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, 1075 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, 1076 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, 1077 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, 1078 }; 1079 1080 iommu_node = g_strdup_printf("/soc/iommu@%x", 1081 (unsigned int) s->memmap[VIRT_IOMMU_SYS].base); 1082 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1083 qemu_fdt_add_subnode(fdt, iommu_node); 1084 1085 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); 1086 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1087 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1088 1089 qemu_fdt_setprop_cells(fdt, iommu_node, "reg", 1090 addr >> 32, addr, size >> 32, size); 1091 qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); 1092 1093 qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", 1094 iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, 1095 iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, 1096 iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, 1097 iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); 1098 1099 qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); 1100 1101 *iommu_sys_phandle = iommu_phandle; 1102 } 1103 1104 static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) 1105 { 1106 const char comp[] = "riscv,pci-iommu"; 1107 void *fdt = MACHINE(s)->fdt; 1108 uint32_t iommu_phandle; 1109 g_autofree char *iommu_node = NULL; 1110 g_autofree char *pci_node = NULL; 1111 1112 pci_node = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, 1113 s->memmap[VIRT_PCIE_ECAM].base); 1114 iommu_node = g_strdup_printf("%s/iommu@%x", pci_node, bdf); 1115 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1116 qemu_fdt_add_subnode(fdt, iommu_node); 1117 1118 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); 1119 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1120 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1121 qemu_fdt_setprop_cells(fdt, iommu_node, "reg", 1122 bdf << 8, 0, 0, 0, 0); 1123 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1124 0, iommu_phandle, 0, bdf, 1125 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1126 s->pci_iommu_bdf = bdf; 1127 } 1128 1129 static void finalize_fdt(RISCVVirtState *s) 1130 { 1131 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1132 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1133 uint32_t iommu_sys_phandle = 1; 1134 1135 create_fdt_sockets(s, &phandle, &irq_mmio_phandle, 1136 &irq_pcie_phandle, &irq_virtio_phandle, 1137 &msi_pcie_phandle); 1138 1139 create_fdt_virtio(s, irq_virtio_phandle); 1140 1141 if (virt_is_iommu_sys_enabled(s)) { 1142 create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, 1143 &iommu_sys_phandle); 1144 } 1145 create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle, 1146 iommu_sys_phandle); 1147 1148 create_fdt_reset(s, &phandle); 1149 1150 create_fdt_uart(s, irq_mmio_phandle); 1151 1152 create_fdt_rtc(s, irq_mmio_phandle); 1153 } 1154 1155 static void create_fdt(RISCVVirtState *s) 1156 { 1157 MachineState *ms = MACHINE(s); 1158 uint8_t rng_seed[32]; 1159 g_autofree char *name = NULL; 1160 1161 ms->fdt = create_device_tree(&s->fdt_size); 1162 if (!ms->fdt) { 1163 error_report("create_device_tree() failed"); 1164 exit(1); 1165 } 1166 1167 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1168 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1169 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1170 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1171 1172 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1173 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1174 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1175 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1176 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1177 1178 /* 1179 * The "/soc/pci@..." node is needed for PCIE hotplugs 1180 * that might happen before finalize_fdt(). 1181 */ 1182 name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, 1183 s->memmap[VIRT_PCIE_ECAM].base); 1184 qemu_fdt_add_subnode(ms->fdt, name); 1185 1186 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1187 1188 /* Pass seed to RNG */ 1189 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1190 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1191 rng_seed, sizeof(rng_seed)); 1192 1193 qemu_fdt_add_subnode(ms->fdt, "/aliases"); 1194 1195 create_fdt_flash(s); 1196 create_fdt_fw_cfg(s); 1197 create_fdt_pmu(s); 1198 } 1199 1200 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1201 DeviceState *irqchip, 1202 RISCVVirtState *s) 1203 { 1204 DeviceState *dev; 1205 MemoryRegion *ecam_alias, *ecam_reg; 1206 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1207 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1208 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1209 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1210 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1211 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1212 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1213 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1214 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1215 qemu_irq irq; 1216 int i; 1217 1218 dev = qdev_new(TYPE_GPEX_HOST); 1219 1220 /* Set GPEX object properties for the virt machine */ 1221 object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE, 1222 ecam_base, NULL); 1223 object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE, 1224 ecam_size, NULL); 1225 object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE, 1226 mmio_base, NULL); 1227 object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE, 1228 mmio_size, NULL); 1229 object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE, 1230 high_mmio_base, NULL); 1231 object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1232 high_mmio_size, NULL); 1233 object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE, 1234 pio_base, NULL); 1235 object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, 1236 pio_size, NULL); 1237 1238 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1239 1240 ecam_alias = g_new0(MemoryRegion, 1); 1241 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1242 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1243 ecam_reg, 0, ecam_size); 1244 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1245 1246 mmio_alias = g_new0(MemoryRegion, 1); 1247 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1248 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1249 mmio_reg, mmio_base, mmio_size); 1250 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1251 1252 /* Map high MMIO space */ 1253 high_mmio_alias = g_new0(MemoryRegion, 1); 1254 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1255 mmio_reg, high_mmio_base, high_mmio_size); 1256 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1257 high_mmio_alias); 1258 1259 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1260 1261 for (i = 0; i < PCI_NUM_PINS; i++) { 1262 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1263 1264 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1265 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1266 } 1267 1268 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus; 1269 return dev; 1270 } 1271 1272 static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) 1273 { 1274 FWCfgState *fw_cfg; 1275 1276 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1277 &address_space_memory); 1278 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1279 1280 return fw_cfg; 1281 } 1282 1283 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1284 int base_hartid, int hart_count) 1285 { 1286 g_autofree char *plic_hart_config = NULL; 1287 1288 /* Per-socket PLIC hart topology configuration string */ 1289 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1290 1291 /* Per-socket PLIC */ 1292 return sifive_plic_create( 1293 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1294 plic_hart_config, hart_count, base_hartid, 1295 VIRT_IRQCHIP_NUM_SOURCES, 1296 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1297 VIRT_PLIC_PRIORITY_BASE, VIRT_PLIC_PENDING_BASE, 1298 VIRT_PLIC_ENABLE_BASE, VIRT_PLIC_ENABLE_STRIDE, 1299 VIRT_PLIC_CONTEXT_BASE, 1300 VIRT_PLIC_CONTEXT_STRIDE, 1301 memmap[VIRT_PLIC].size); 1302 } 1303 1304 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1305 const MemMapEntry *memmap, int socket, 1306 int base_hartid, int hart_count) 1307 { 1308 int i; 1309 hwaddr addr = 0; 1310 uint32_t guest_bits; 1311 DeviceState *aplic_s = NULL; 1312 DeviceState *aplic_m = NULL; 1313 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1314 1315 if (msimode) { 1316 if (!kvm_enabled()) { 1317 /* Per-socket M-level IMSICs */ 1318 addr = memmap[VIRT_IMSIC_M].base + 1319 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1320 for (i = 0; i < hart_count; i++) { 1321 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1322 base_hartid + i, true, 1, 1323 VIRT_IRQCHIP_NUM_MSIS); 1324 } 1325 } 1326 1327 /* Per-socket S-level IMSICs */ 1328 guest_bits = imsic_num_bits(aia_guests + 1); 1329 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1330 for (i = 0; i < hart_count; i++) { 1331 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1332 base_hartid + i, false, 1 + aia_guests, 1333 VIRT_IRQCHIP_NUM_MSIS); 1334 } 1335 } 1336 1337 if (!kvm_enabled()) { 1338 /* Per-socket M-level APLIC */ 1339 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1340 socket * memmap[VIRT_APLIC_M].size, 1341 memmap[VIRT_APLIC_M].size, 1342 (msimode) ? 0 : base_hartid, 1343 (msimode) ? 0 : hart_count, 1344 VIRT_IRQCHIP_NUM_SOURCES, 1345 VIRT_IRQCHIP_NUM_PRIO_BITS, 1346 msimode, true, NULL); 1347 } 1348 1349 /* Per-socket S-level APLIC */ 1350 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1351 socket * memmap[VIRT_APLIC_S].size, 1352 memmap[VIRT_APLIC_S].size, 1353 (msimode) ? 0 : base_hartid, 1354 (msimode) ? 0 : hart_count, 1355 VIRT_IRQCHIP_NUM_SOURCES, 1356 VIRT_IRQCHIP_NUM_PRIO_BITS, 1357 msimode, false, aplic_m); 1358 1359 if (kvm_enabled() && msimode) { 1360 riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr); 1361 } 1362 1363 return kvm_enabled() ? aplic_s : aplic_m; 1364 } 1365 1366 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1367 { 1368 DeviceState *dev; 1369 SysBusDevice *sysbus; 1370 int i; 1371 MemoryRegion *sysmem = get_system_memory(); 1372 1373 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1374 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1375 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1376 qdev_prop_set_uint32(dev, "mmio_size", s->memmap[VIRT_PLATFORM_BUS].size); 1377 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1378 s->platform_bus_dev = dev; 1379 1380 sysbus = SYS_BUS_DEVICE(dev); 1381 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1382 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1383 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1384 } 1385 1386 memory_region_add_subregion(sysmem, 1387 s->memmap[VIRT_PLATFORM_BUS].base, 1388 sysbus_mmio_get_region(sysbus, 0)); 1389 } 1390 1391 static void virt_build_smbios(RISCVVirtState *s) 1392 { 1393 MachineClass *mc = MACHINE_GET_CLASS(s); 1394 MachineState *ms = MACHINE(s); 1395 uint8_t *smbios_tables, *smbios_anchor; 1396 size_t smbios_tables_len, smbios_anchor_len; 1397 struct smbios_phys_mem_area mem_array; 1398 const char *product = "QEMU Virtual Machine"; 1399 1400 if (kvm_enabled()) { 1401 product = "KVM Virtual Machine"; 1402 } 1403 1404 smbios_set_defaults("QEMU", product, mc->name); 1405 1406 if (riscv_is_32bit(&s->soc[0])) { 1407 smbios_set_default_processor_family(0x200); 1408 } else { 1409 smbios_set_default_processor_family(0x201); 1410 } 1411 1412 /* build the array of physical mem area from base_memmap */ 1413 mem_array.address = s->memmap[VIRT_DRAM].base; 1414 mem_array.length = ms->ram_size; 1415 1416 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 1417 &mem_array, 1, 1418 &smbios_tables, &smbios_tables_len, 1419 &smbios_anchor, &smbios_anchor_len, 1420 &error_fatal); 1421 1422 if (smbios_anchor) { 1423 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables", 1424 smbios_tables, smbios_tables_len); 1425 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor", 1426 smbios_anchor, smbios_anchor_len); 1427 } 1428 } 1429 1430 static void virt_machine_done(Notifier *notifier, void *data) 1431 { 1432 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1433 machine_done); 1434 MachineState *machine = MACHINE(s); 1435 hwaddr start_addr = s->memmap[VIRT_DRAM].base; 1436 target_ulong firmware_end_addr, kernel_start_addr; 1437 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1438 uint64_t fdt_load_addr; 1439 uint64_t kernel_entry = 0; 1440 BlockBackend *pflash_blk0; 1441 RISCVBootInfo boot_info; 1442 1443 /* 1444 * An user provided dtb must include everything, including 1445 * dynamic sysbus devices. Our FDT needs to be finalized. 1446 */ 1447 if (machine->dtb == NULL) { 1448 finalize_fdt(s); 1449 } 1450 1451 /* 1452 * Only direct boot kernel is currently supported for KVM VM, 1453 * so the "-bios" parameter is not supported when KVM is enabled. 1454 */ 1455 if (kvm_enabled()) { 1456 if (machine->firmware) { 1457 if (strcmp(machine->firmware, "none")) { 1458 error_report("Machine mode firmware is not supported in " 1459 "combination with KVM."); 1460 exit(1); 1461 } 1462 } else { 1463 machine->firmware = g_strdup("none"); 1464 } 1465 } 1466 1467 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1468 &start_addr, NULL); 1469 1470 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1471 if (pflash_blk0) { 1472 if (machine->firmware && !strcmp(machine->firmware, "none") && 1473 !kvm_enabled()) { 1474 /* 1475 * Pflash was supplied but bios is none and not KVM guest, 1476 * let's overwrite the address we jump to after reset to 1477 * the base of the flash. 1478 */ 1479 start_addr = s->memmap[VIRT_FLASH].base; 1480 } else { 1481 /* 1482 * Pflash was supplied but either KVM guest or bios is not none. 1483 * In this case, base of the flash would contain S-mode payload. 1484 */ 1485 riscv_setup_firmware_boot(machine); 1486 kernel_entry = s->memmap[VIRT_FLASH].base; 1487 } 1488 } 1489 1490 riscv_boot_info_init(&boot_info, &s->soc[0]); 1491 1492 if (machine->kernel_filename && !kernel_entry) { 1493 kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info, 1494 firmware_end_addr); 1495 riscv_load_kernel(machine, &boot_info, kernel_start_addr, 1496 true, NULL); 1497 kernel_entry = boot_info.image_low_addr; 1498 } 1499 1500 fdt_load_addr = riscv_compute_fdt_addr(s->memmap[VIRT_DRAM].base, 1501 s->memmap[VIRT_DRAM].size, 1502 machine, &boot_info); 1503 riscv_load_fdt(fdt_load_addr, machine->fdt); 1504 1505 /* load the reset vector */ 1506 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1507 s->memmap[VIRT_MROM].base, 1508 s->memmap[VIRT_MROM].size, kernel_entry, 1509 fdt_load_addr); 1510 1511 /* 1512 * Only direct boot kernel is currently supported for KVM VM, 1513 * So here setup kernel start address and fdt address. 1514 * TODO:Support firmware loading and integrate to TCG start 1515 */ 1516 if (kvm_enabled()) { 1517 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1518 } 1519 1520 virt_build_smbios(s); 1521 1522 if (virt_is_acpi_enabled(s)) { 1523 virt_acpi_setup(s); 1524 } 1525 } 1526 1527 static void virt_machine_init(MachineState *machine) 1528 { 1529 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1530 MemoryRegion *system_memory = get_system_memory(); 1531 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1532 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1533 int i, base_hartid, hart_count; 1534 int socket_count = riscv_socket_count(machine); 1535 1536 s->memmap = virt_memmap; 1537 1538 /* Check socket count limit */ 1539 if (VIRT_SOCKETS_MAX < socket_count) { 1540 error_report("number of sockets/nodes should be less than %d", 1541 VIRT_SOCKETS_MAX); 1542 exit(1); 1543 } 1544 1545 if (!virt_aclint_allowed() && s->have_aclint) { 1546 error_report("'aclint' is only available with TCG acceleration"); 1547 exit(1); 1548 } 1549 1550 /* Initialize sockets */ 1551 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1552 for (i = 0; i < socket_count; i++) { 1553 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1554 1555 if (!riscv_socket_check_hartids(machine, i)) { 1556 error_report("discontinuous hartids in socket%d", i); 1557 exit(1); 1558 } 1559 1560 base_hartid = riscv_socket_first_hartid(machine, i); 1561 if (base_hartid < 0) { 1562 error_report("can't find hartid base for socket%d", i); 1563 exit(1); 1564 } 1565 1566 hart_count = riscv_socket_hart_count(machine, i); 1567 if (hart_count < 0) { 1568 error_report("can't find hart count for socket%d", i); 1569 exit(1); 1570 } 1571 1572 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1573 TYPE_RISCV_HART_ARRAY); 1574 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1575 machine->cpu_type, &error_abort); 1576 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1577 base_hartid, &error_abort); 1578 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1579 hart_count, &error_abort); 1580 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1581 1582 if (virt_aclint_allowed() && s->have_aclint) { 1583 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1584 /* Per-socket ACLINT MTIMER */ 1585 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + 1586 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1587 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1588 base_hartid, hart_count, 1589 RISCV_ACLINT_DEFAULT_MTIMECMP, 1590 RISCV_ACLINT_DEFAULT_MTIME, 1591 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1592 } else { 1593 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1594 riscv_aclint_swi_create(s->memmap[VIRT_CLINT].base + 1595 i * s->memmap[VIRT_CLINT].size, 1596 base_hartid, hart_count, false); 1597 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + 1598 i * s->memmap[VIRT_CLINT].size + 1599 RISCV_ACLINT_SWI_SIZE, 1600 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1601 base_hartid, hart_count, 1602 RISCV_ACLINT_DEFAULT_MTIMECMP, 1603 RISCV_ACLINT_DEFAULT_MTIME, 1604 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1605 riscv_aclint_swi_create(s->memmap[VIRT_ACLINT_SSWI].base + 1606 i * s->memmap[VIRT_ACLINT_SSWI].size, 1607 base_hartid, hart_count, true); 1608 } 1609 } else if (tcg_enabled()) { 1610 /* Per-socket SiFive CLINT */ 1611 riscv_aclint_swi_create( 1612 s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size, 1613 base_hartid, hart_count, false); 1614 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + 1615 i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1616 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1617 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1618 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1619 } 1620 1621 /* Per-socket interrupt controller */ 1622 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1623 s->irqchip[i] = virt_create_plic(s->memmap, i, 1624 base_hartid, hart_count); 1625 } else { 1626 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1627 s->memmap, i, base_hartid, 1628 hart_count); 1629 } 1630 1631 /* Try to use different IRQCHIP instance based device type */ 1632 if (i == 0) { 1633 mmio_irqchip = s->irqchip[i]; 1634 virtio_irqchip = s->irqchip[i]; 1635 pcie_irqchip = s->irqchip[i]; 1636 } 1637 if (i == 1) { 1638 virtio_irqchip = s->irqchip[i]; 1639 pcie_irqchip = s->irqchip[i]; 1640 } 1641 if (i == 2) { 1642 pcie_irqchip = s->irqchip[i]; 1643 } 1644 } 1645 1646 if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) { 1647 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1648 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1649 s->memmap[VIRT_APLIC_S].base, 1650 s->memmap[VIRT_IMSIC_S].base, 1651 s->aia_guests); 1652 } 1653 1654 if (riscv_is_32bit(&s->soc[0])) { 1655 #if HOST_LONG_BITS == 64 1656 /* limit RAM size in a 32-bit system */ 1657 if (machine->ram_size > 10 * GiB) { 1658 machine->ram_size = 10 * GiB; 1659 error_report("Limiting RAM size to 10 GiB"); 1660 } 1661 #endif 1662 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1663 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1664 } else { 1665 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1666 virt_high_pcie_memmap.base = s->memmap[VIRT_DRAM].base + 1667 machine->ram_size; 1668 virt_high_pcie_memmap.base = 1669 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1670 } 1671 1672 /* register system main memory (actual RAM) */ 1673 memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base, 1674 machine->ram); 1675 1676 /* boot rom */ 1677 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1678 s->memmap[VIRT_MROM].size, &error_fatal); 1679 memory_region_add_subregion(system_memory, s->memmap[VIRT_MROM].base, 1680 mask_rom); 1681 1682 /* 1683 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1684 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1685 */ 1686 s->fw_cfg = create_fw_cfg(machine, s->memmap[VIRT_FW_CFG].base); 1687 rom_set_fw(s->fw_cfg); 1688 1689 /* SiFive Test MMIO device */ 1690 sifive_test_create(s->memmap[VIRT_TEST].base); 1691 1692 /* VirtIO MMIO devices */ 1693 for (i = 0; i < VIRTIO_COUNT; i++) { 1694 sysbus_create_simple("virtio-mmio", 1695 s->memmap[VIRT_VIRTIO].base + i * s->memmap[VIRT_VIRTIO].size, 1696 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1697 } 1698 1699 gpex_pcie_init(system_memory, pcie_irqchip, s); 1700 1701 create_platform_bus(s, mmio_irqchip); 1702 1703 serial_mm_init(system_memory, s->memmap[VIRT_UART0].base, 1704 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1705 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1706 1707 sysbus_create_simple("goldfish_rtc", s->memmap[VIRT_RTC].base, 1708 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1709 1710 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1711 /* Map legacy -drive if=pflash to machine properties */ 1712 pflash_cfi01_legacy_drive(s->flash[i], 1713 drive_get(IF_PFLASH, 0, i)); 1714 } 1715 virt_flash_map(s, system_memory); 1716 1717 /* load/create device tree */ 1718 if (machine->dtb) { 1719 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1720 if (!machine->fdt) { 1721 error_report("load_device_tree() failed"); 1722 exit(1); 1723 } 1724 } else { 1725 create_fdt(s); 1726 } 1727 1728 if (virt_is_iommu_sys_enabled(s)) { 1729 DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS); 1730 1731 object_property_set_uint(OBJECT(iommu_sys), "addr", 1732 s->memmap[VIRT_IOMMU_SYS].base, 1733 &error_fatal); 1734 object_property_set_uint(OBJECT(iommu_sys), "base-irq", 1735 IOMMU_SYS_IRQ, 1736 &error_fatal); 1737 object_property_set_link(OBJECT(iommu_sys), "irqchip", 1738 OBJECT(mmio_irqchip), 1739 &error_fatal); 1740 1741 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal); 1742 } 1743 1744 s->machine_done.notify = virt_machine_done; 1745 qemu_add_machine_init_done_notifier(&s->machine_done); 1746 } 1747 1748 static void virt_machine_instance_init(Object *obj) 1749 { 1750 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1751 1752 virt_flash_create(s); 1753 1754 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1755 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1756 s->acpi = ON_OFF_AUTO_AUTO; 1757 s->iommu_sys = ON_OFF_AUTO_AUTO; 1758 } 1759 1760 static char *virt_get_aia_guests(Object *obj, Error **errp) 1761 { 1762 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1763 1764 return g_strdup_printf("%d", s->aia_guests); 1765 } 1766 1767 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1768 { 1769 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1770 1771 s->aia_guests = atoi(val); 1772 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1773 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1774 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1775 VIRT_IRQCHIP_MAX_GUESTS); 1776 } 1777 } 1778 1779 static char *virt_get_aia(Object *obj, Error **errp) 1780 { 1781 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1782 const char *val; 1783 1784 switch (s->aia_type) { 1785 case VIRT_AIA_TYPE_APLIC: 1786 val = "aplic"; 1787 break; 1788 case VIRT_AIA_TYPE_APLIC_IMSIC: 1789 val = "aplic-imsic"; 1790 break; 1791 default: 1792 val = "none"; 1793 break; 1794 }; 1795 1796 return g_strdup(val); 1797 } 1798 1799 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1800 { 1801 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1802 1803 if (!strcmp(val, "none")) { 1804 s->aia_type = VIRT_AIA_TYPE_NONE; 1805 } else if (!strcmp(val, "aplic")) { 1806 s->aia_type = VIRT_AIA_TYPE_APLIC; 1807 } else if (!strcmp(val, "aplic-imsic")) { 1808 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1809 } else { 1810 error_setg(errp, "Invalid AIA interrupt controller type"); 1811 error_append_hint(errp, "Valid values are none, aplic, and " 1812 "aplic-imsic.\n"); 1813 } 1814 } 1815 1816 static bool virt_get_aclint(Object *obj, Error **errp) 1817 { 1818 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1819 1820 return s->have_aclint; 1821 } 1822 1823 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1824 { 1825 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1826 1827 s->have_aclint = value; 1828 } 1829 1830 bool virt_is_iommu_sys_enabled(RISCVVirtState *s) 1831 { 1832 return s->iommu_sys == ON_OFF_AUTO_ON; 1833 } 1834 1835 static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name, 1836 void *opaque, Error **errp) 1837 { 1838 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1839 OnOffAuto iommu_sys = s->iommu_sys; 1840 1841 visit_type_OnOffAuto(v, name, &iommu_sys, errp); 1842 } 1843 1844 static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name, 1845 void *opaque, Error **errp) 1846 { 1847 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1848 1849 visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); 1850 } 1851 1852 bool virt_is_acpi_enabled(RISCVVirtState *s) 1853 { 1854 return s->acpi != ON_OFF_AUTO_OFF; 1855 } 1856 1857 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1858 void *opaque, Error **errp) 1859 { 1860 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1861 OnOffAuto acpi = s->acpi; 1862 1863 visit_type_OnOffAuto(v, name, &acpi, errp); 1864 } 1865 1866 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1867 void *opaque, Error **errp) 1868 { 1869 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1870 1871 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1872 } 1873 1874 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1875 DeviceState *dev) 1876 { 1877 MachineClass *mc = MACHINE_GET_CLASS(machine); 1878 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1879 1880 if (device_is_dynamic_sysbus(mc, dev) || 1881 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1882 object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { 1883 s->iommu_sys = ON_OFF_AUTO_OFF; 1884 return HOTPLUG_HANDLER(machine); 1885 } 1886 1887 return NULL; 1888 } 1889 1890 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1891 DeviceState *dev, Error **errp) 1892 { 1893 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1894 1895 if (s->platform_bus_dev) { 1896 MachineClass *mc = MACHINE_GET_CLASS(s); 1897 1898 if (device_is_dynamic_sysbus(mc, dev)) { 1899 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1900 SYS_BUS_DEVICE(dev)); 1901 } 1902 } 1903 1904 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1905 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1906 } 1907 1908 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { 1909 create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1910 s->iommu_sys = ON_OFF_AUTO_OFF; 1911 } 1912 } 1913 1914 static void virt_machine_class_init(ObjectClass *oc, const void *data) 1915 { 1916 MachineClass *mc = MACHINE_CLASS(oc); 1917 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1918 1919 mc->desc = "RISC-V VirtIO board"; 1920 mc->init = virt_machine_init; 1921 mc->max_cpus = VIRT_CPUS_MAX; 1922 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1923 mc->block_default_type = IF_VIRTIO; 1924 mc->no_cdrom = 1; 1925 mc->pci_allow_0_address = true; 1926 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1927 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1928 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1929 mc->numa_mem_supported = true; 1930 /* platform instead of architectural choice */ 1931 mc->cpu_cluster_has_numa_boundary = true; 1932 mc->default_ram_id = "riscv_virt_board.ram"; 1933 assert(!mc->get_hotplug_handler); 1934 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1935 1936 hc->plug = virt_machine_device_plug_cb; 1937 1938 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1939 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); 1940 #ifdef CONFIG_TPM 1941 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1942 #endif 1943 1944 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1945 virt_set_aclint); 1946 object_class_property_set_description(oc, "aclint", 1947 "(TCG only) Set on/off to " 1948 "enable/disable emulating " 1949 "ACLINT devices"); 1950 1951 object_class_property_add_str(oc, "aia", virt_get_aia, 1952 virt_set_aia); 1953 object_class_property_set_description(oc, "aia", 1954 "Set type of AIA interrupt " 1955 "controller. Valid values are " 1956 "none, aplic, and aplic-imsic."); 1957 1958 object_class_property_add_str(oc, "aia-guests", 1959 virt_get_aia_guests, 1960 virt_set_aia_guests); 1961 { 1962 g_autofree char *str = 1963 g_strdup_printf("Set number of guest MMIO pages for AIA IMSIC. " 1964 "Valid value should be between 0 and %d.", 1965 VIRT_IRQCHIP_MAX_GUESTS); 1966 object_class_property_set_description(oc, "aia-guests", str); 1967 } 1968 1969 object_class_property_add(oc, "acpi", "OnOffAuto", 1970 virt_get_acpi, virt_set_acpi, 1971 NULL, NULL); 1972 object_class_property_set_description(oc, "acpi", 1973 "Enable ACPI"); 1974 1975 object_class_property_add(oc, "iommu-sys", "OnOffAuto", 1976 virt_get_iommu_sys, virt_set_iommu_sys, 1977 NULL, NULL); 1978 object_class_property_set_description(oc, "iommu-sys", 1979 "Enable IOMMU platform device"); 1980 } 1981 1982 static const TypeInfo virt_machine_typeinfo = { 1983 .name = MACHINE_TYPE_NAME("virt"), 1984 .parent = TYPE_MACHINE, 1985 .class_init = virt_machine_class_init, 1986 .instance_init = virt_machine_instance_init, 1987 .instance_size = sizeof(RISCVVirtState), 1988 .interfaces = (const InterfaceInfo[]) { 1989 { TYPE_HOTPLUG_HANDLER }, 1990 { } 1991 }, 1992 }; 1993 1994 static void virt_machine_init_register_types(void) 1995 { 1996 type_register_static(&virt_machine_typeinfo); 1997 } 1998 1999 type_init(virt_machine_init_register_types) 2000