1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "hw/intc/riscv_aclint.h" 39 #include "hw/intc/riscv_aplic.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "hw/intc/sifive_plic.h" 42 #include "hw/misc/sifive_test.h" 43 #include "hw/platform-bus.h" 44 #include "chardev/char.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/tpm.h" 49 #include "hw/pci/pci.h" 50 #include "hw/pci-host/gpex.h" 51 #include "hw/display/ramfb.h" 52 53 /* 54 * The virt machine physical address space used by some of the devices 55 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 56 * number of CPUs, and number of IMSIC guest files. 57 * 58 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 59 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 60 * of virt machine physical address space. 61 */ 62 63 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 64 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 65 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 66 #error "Can't accomodate single IMSIC group in address space" 67 #endif 68 69 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 70 VIRT_IMSIC_GROUP_MAX_SIZE) 71 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 72 #error "Can't accomodate all IMSIC groups in address space" 73 #endif 74 75 static const MemMapEntry virt_memmap[] = { 76 [VIRT_DEBUG] = { 0x0, 0x100 }, 77 [VIRT_MROM] = { 0x1000, 0xf000 }, 78 [VIRT_TEST] = { 0x100000, 0x1000 }, 79 [VIRT_RTC] = { 0x101000, 0x1000 }, 80 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 81 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 82 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 83 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 84 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 85 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 86 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 87 [VIRT_UART0] = { 0x10000000, 0x100 }, 88 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 89 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 90 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 91 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 92 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 93 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 94 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 95 [VIRT_DRAM] = { 0x80000000, 0x0 }, 96 }; 97 98 /* PCIe high mmio is fixed for RV32 */ 99 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 100 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 101 102 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 103 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 104 105 static MemMapEntry virt_high_pcie_memmap; 106 107 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 108 109 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 110 const char *name, 111 const char *alias_prop_name) 112 { 113 /* 114 * Create a single flash device. We use the same parameters as 115 * the flash devices on the ARM virt board. 116 */ 117 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 118 119 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 120 qdev_prop_set_uint8(dev, "width", 4); 121 qdev_prop_set_uint8(dev, "device-width", 2); 122 qdev_prop_set_bit(dev, "big-endian", false); 123 qdev_prop_set_uint16(dev, "id0", 0x89); 124 qdev_prop_set_uint16(dev, "id1", 0x18); 125 qdev_prop_set_uint16(dev, "id2", 0x00); 126 qdev_prop_set_uint16(dev, "id3", 0x00); 127 qdev_prop_set_string(dev, "name", name); 128 129 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 130 object_property_add_alias(OBJECT(s), alias_prop_name, 131 OBJECT(dev), "drive"); 132 133 return PFLASH_CFI01(dev); 134 } 135 136 static void virt_flash_create(RISCVVirtState *s) 137 { 138 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 139 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 140 } 141 142 static void virt_flash_map1(PFlashCFI01 *flash, 143 hwaddr base, hwaddr size, 144 MemoryRegion *sysmem) 145 { 146 DeviceState *dev = DEVICE(flash); 147 148 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 149 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 150 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 151 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 152 153 memory_region_add_subregion(sysmem, base, 154 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 155 0)); 156 } 157 158 static void virt_flash_map(RISCVVirtState *s, 159 MemoryRegion *sysmem) 160 { 161 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 162 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 163 164 virt_flash_map1(s->flash[0], flashbase, flashsize, 165 sysmem); 166 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 167 sysmem); 168 } 169 170 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 171 uint32_t irqchip_phandle) 172 { 173 int pin, dev; 174 uint32_t irq_map_stride = 0; 175 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 176 FDT_MAX_INT_MAP_WIDTH] = {}; 177 uint32_t *irq_map = full_irq_map; 178 179 /* This code creates a standard swizzle of interrupts such that 180 * each device's first interrupt is based on it's PCI_SLOT number. 181 * (See pci_swizzle_map_irq_fn()) 182 * 183 * We only need one entry per interrupt in the table (not one per 184 * possible slot) seeing the interrupt-map-mask will allow the table 185 * to wrap to any number of devices. 186 */ 187 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 188 int devfn = dev * 0x8; 189 190 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 191 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 192 int i = 0; 193 194 /* Fill PCI address cells */ 195 irq_map[i] = cpu_to_be32(devfn << 8); 196 i += FDT_PCI_ADDR_CELLS; 197 198 /* Fill PCI Interrupt cells */ 199 irq_map[i] = cpu_to_be32(pin + 1); 200 i += FDT_PCI_INT_CELLS; 201 202 /* Fill interrupt controller phandle and cells */ 203 irq_map[i++] = cpu_to_be32(irqchip_phandle); 204 irq_map[i++] = cpu_to_be32(irq_nr); 205 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 206 irq_map[i++] = cpu_to_be32(0x4); 207 } 208 209 if (!irq_map_stride) { 210 irq_map_stride = i; 211 } 212 irq_map += irq_map_stride; 213 } 214 } 215 216 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 217 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 218 irq_map_stride * sizeof(uint32_t)); 219 220 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 221 0x1800, 0, 0, 0x7); 222 } 223 224 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 225 char *clust_name, uint32_t *phandle, 226 bool is_32_bit, uint32_t *intc_phandles) 227 { 228 int cpu; 229 uint32_t cpu_phandle; 230 MachineState *mc = MACHINE(s); 231 char *name, *cpu_name, *core_name, *intc_name; 232 233 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 234 cpu_phandle = (*phandle)++; 235 236 cpu_name = g_strdup_printf("/cpus/cpu@%d", 237 s->soc[socket].hartid_base + cpu); 238 qemu_fdt_add_subnode(mc->fdt, cpu_name); 239 if (riscv_feature(&s->soc[socket].harts[cpu].env, 240 RISCV_FEATURE_MMU)) { 241 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 242 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 243 } else { 244 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 245 "riscv,none"); 246 } 247 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 248 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); 249 g_free(name); 250 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); 251 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); 252 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", 253 s->soc[socket].hartid_base + cpu); 254 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); 255 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); 256 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); 257 258 intc_phandles[cpu] = (*phandle)++; 259 260 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 261 qemu_fdt_add_subnode(mc->fdt, intc_name); 262 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", 263 intc_phandles[cpu]); 264 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", 265 "riscv,cpu-intc"); 266 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); 267 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); 268 269 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 270 qemu_fdt_add_subnode(mc->fdt, core_name); 271 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); 272 273 g_free(core_name); 274 g_free(intc_name); 275 g_free(cpu_name); 276 } 277 } 278 279 static void create_fdt_socket_memory(RISCVVirtState *s, 280 const MemMapEntry *memmap, int socket) 281 { 282 char *mem_name; 283 uint64_t addr, size; 284 MachineState *mc = MACHINE(s); 285 286 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 287 size = riscv_socket_mem_size(mc, socket); 288 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 289 qemu_fdt_add_subnode(mc->fdt, mem_name); 290 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", 291 addr >> 32, addr, size >> 32, size); 292 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); 293 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); 294 g_free(mem_name); 295 } 296 297 static void create_fdt_socket_clint(RISCVVirtState *s, 298 const MemMapEntry *memmap, int socket, 299 uint32_t *intc_phandles) 300 { 301 int cpu; 302 char *clint_name; 303 uint32_t *clint_cells; 304 unsigned long clint_addr; 305 MachineState *mc = MACHINE(s); 306 static const char * const clint_compat[2] = { 307 "sifive,clint0", "riscv,clint0" 308 }; 309 310 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 311 312 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 313 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 314 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 315 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 316 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 317 } 318 319 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 320 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 321 qemu_fdt_add_subnode(mc->fdt, clint_name); 322 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", 323 (char **)&clint_compat, 324 ARRAY_SIZE(clint_compat)); 325 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", 326 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 327 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", 328 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 329 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); 330 g_free(clint_name); 331 332 g_free(clint_cells); 333 } 334 335 static void create_fdt_socket_aclint(RISCVVirtState *s, 336 const MemMapEntry *memmap, int socket, 337 uint32_t *intc_phandles) 338 { 339 int cpu; 340 char *name; 341 unsigned long addr, size; 342 uint32_t aclint_cells_size; 343 uint32_t *aclint_mswi_cells; 344 uint32_t *aclint_sswi_cells; 345 uint32_t *aclint_mtimer_cells; 346 MachineState *mc = MACHINE(s); 347 348 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 349 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 350 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 351 352 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 353 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 354 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 355 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 356 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 357 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 358 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 359 } 360 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 361 362 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 363 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 364 name = g_strdup_printf("/soc/mswi@%lx", addr); 365 qemu_fdt_add_subnode(mc->fdt, name); 366 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 367 "riscv,aclint-mswi"); 368 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 369 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 370 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 371 aclint_mswi_cells, aclint_cells_size); 372 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 373 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 374 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 375 g_free(name); 376 } 377 378 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 379 addr = memmap[VIRT_CLINT].base + 380 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 381 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 382 } else { 383 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 384 (memmap[VIRT_CLINT].size * socket); 385 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 386 } 387 name = g_strdup_printf("/soc/mtimer@%lx", addr); 388 qemu_fdt_add_subnode(mc->fdt, name); 389 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 390 "riscv,aclint-mtimer"); 391 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 392 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 393 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 394 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 395 0x0, RISCV_ACLINT_DEFAULT_MTIME); 396 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 397 aclint_mtimer_cells, aclint_cells_size); 398 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 399 g_free(name); 400 401 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 402 addr = memmap[VIRT_ACLINT_SSWI].base + 403 (memmap[VIRT_ACLINT_SSWI].size * socket); 404 name = g_strdup_printf("/soc/sswi@%lx", addr); 405 qemu_fdt_add_subnode(mc->fdt, name); 406 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 407 "riscv,aclint-sswi"); 408 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 409 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 410 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 411 aclint_sswi_cells, aclint_cells_size); 412 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 413 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 414 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 415 g_free(name); 416 } 417 418 g_free(aclint_mswi_cells); 419 g_free(aclint_mtimer_cells); 420 g_free(aclint_sswi_cells); 421 } 422 423 static void create_fdt_socket_plic(RISCVVirtState *s, 424 const MemMapEntry *memmap, int socket, 425 uint32_t *phandle, uint32_t *intc_phandles, 426 uint32_t *plic_phandles) 427 { 428 int cpu; 429 char *plic_name; 430 uint32_t *plic_cells; 431 unsigned long plic_addr; 432 MachineState *mc = MACHINE(s); 433 static const char * const plic_compat[2] = { 434 "sifive,plic-1.0.0", "riscv,plic0" 435 }; 436 437 if (kvm_enabled()) { 438 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 439 } else { 440 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 441 } 442 443 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 444 if (kvm_enabled()) { 445 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 446 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 447 } else { 448 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 449 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 450 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 451 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 452 } 453 } 454 455 plic_phandles[socket] = (*phandle)++; 456 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 457 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 458 qemu_fdt_add_subnode(mc->fdt, plic_name); 459 qemu_fdt_setprop_cell(mc->fdt, plic_name, 460 "#interrupt-cells", FDT_PLIC_INT_CELLS); 461 qemu_fdt_setprop_cell(mc->fdt, plic_name, 462 "#address-cells", FDT_PLIC_ADDR_CELLS); 463 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", 464 (char **)&plic_compat, 465 ARRAY_SIZE(plic_compat)); 466 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); 467 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", 468 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 469 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", 470 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 471 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 472 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); 473 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", 474 plic_phandles[socket]); 475 476 if (!socket) { 477 platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, 478 memmap[VIRT_PLATFORM_BUS].base, 479 memmap[VIRT_PLATFORM_BUS].size, 480 VIRT_PLATFORM_BUS_IRQ); 481 } 482 483 g_free(plic_name); 484 485 g_free(plic_cells); 486 } 487 488 static uint32_t imsic_num_bits(uint32_t count) 489 { 490 uint32_t ret = 0; 491 492 while (BIT(ret) < count) { 493 ret++; 494 } 495 496 return ret; 497 } 498 499 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 500 uint32_t *phandle, uint32_t *intc_phandles, 501 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 502 { 503 int cpu, socket; 504 char *imsic_name; 505 MachineState *mc = MACHINE(s); 506 uint32_t imsic_max_hart_per_socket, imsic_guest_bits; 507 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 508 509 *msi_m_phandle = (*phandle)++; 510 *msi_s_phandle = (*phandle)++; 511 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); 512 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); 513 514 /* M-level IMSIC node */ 515 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 516 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 517 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 518 } 519 imsic_max_hart_per_socket = 0; 520 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 521 imsic_addr = memmap[VIRT_IMSIC_M].base + 522 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 523 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; 524 imsic_regs[socket * 4 + 0] = 0; 525 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 526 imsic_regs[socket * 4 + 2] = 0; 527 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 528 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 529 imsic_max_hart_per_socket = s->soc[socket].num_harts; 530 } 531 } 532 imsic_name = g_strdup_printf("/soc/imsics@%lx", 533 (unsigned long)memmap[VIRT_IMSIC_M].base); 534 qemu_fdt_add_subnode(mc->fdt, imsic_name); 535 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 536 "riscv,imsics"); 537 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 538 FDT_IMSIC_INT_CELLS); 539 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 540 NULL, 0); 541 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 542 NULL, 0); 543 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 544 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 545 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 546 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 547 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 548 VIRT_IRQCHIP_NUM_MSIS); 549 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 550 VIRT_IRQCHIP_IPI_MSI); 551 if (riscv_socket_count(mc) > 1) { 552 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 553 imsic_num_bits(imsic_max_hart_per_socket)); 554 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 555 imsic_num_bits(riscv_socket_count(mc))); 556 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 557 IMSIC_MMIO_GROUP_MIN_SHIFT); 558 } 559 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); 560 561 g_free(imsic_name); 562 563 /* S-level IMSIC node */ 564 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 565 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 566 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 567 } 568 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); 569 imsic_max_hart_per_socket = 0; 570 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 571 imsic_addr = memmap[VIRT_IMSIC_S].base + 572 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 573 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 574 s->soc[socket].num_harts; 575 imsic_regs[socket * 4 + 0] = 0; 576 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 577 imsic_regs[socket * 4 + 2] = 0; 578 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 579 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 580 imsic_max_hart_per_socket = s->soc[socket].num_harts; 581 } 582 } 583 imsic_name = g_strdup_printf("/soc/imsics@%lx", 584 (unsigned long)memmap[VIRT_IMSIC_S].base); 585 qemu_fdt_add_subnode(mc->fdt, imsic_name); 586 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 587 "riscv,imsics"); 588 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 589 FDT_IMSIC_INT_CELLS); 590 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 591 NULL, 0); 592 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 593 NULL, 0); 594 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 595 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 596 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 597 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 598 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 599 VIRT_IRQCHIP_NUM_MSIS); 600 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 601 VIRT_IRQCHIP_IPI_MSI); 602 if (imsic_guest_bits) { 603 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", 604 imsic_guest_bits); 605 } 606 if (riscv_socket_count(mc) > 1) { 607 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 608 imsic_num_bits(imsic_max_hart_per_socket)); 609 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 610 imsic_num_bits(riscv_socket_count(mc))); 611 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 612 IMSIC_MMIO_GROUP_MIN_SHIFT); 613 } 614 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); 615 g_free(imsic_name); 616 617 g_free(imsic_regs); 618 g_free(imsic_cells); 619 } 620 621 static void create_fdt_socket_aplic(RISCVVirtState *s, 622 const MemMapEntry *memmap, int socket, 623 uint32_t msi_m_phandle, 624 uint32_t msi_s_phandle, 625 uint32_t *phandle, 626 uint32_t *intc_phandles, 627 uint32_t *aplic_phandles) 628 { 629 int cpu; 630 char *aplic_name; 631 uint32_t *aplic_cells; 632 unsigned long aplic_addr; 633 MachineState *mc = MACHINE(s); 634 uint32_t aplic_m_phandle, aplic_s_phandle; 635 636 aplic_m_phandle = (*phandle)++; 637 aplic_s_phandle = (*phandle)++; 638 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 639 640 /* M-level APLIC node */ 641 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 642 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 643 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 644 } 645 aplic_addr = memmap[VIRT_APLIC_M].base + 646 (memmap[VIRT_APLIC_M].size * socket); 647 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 648 qemu_fdt_add_subnode(mc->fdt, aplic_name); 649 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 650 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 651 "#interrupt-cells", FDT_APLIC_INT_CELLS); 652 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 653 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 654 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 655 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 656 } else { 657 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 658 msi_m_phandle); 659 } 660 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 661 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); 662 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 663 VIRT_IRQCHIP_NUM_SOURCES); 664 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", 665 aplic_s_phandle); 666 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", 667 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); 668 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 669 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); 670 g_free(aplic_name); 671 672 /* S-level APLIC node */ 673 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 674 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 675 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 676 } 677 aplic_addr = memmap[VIRT_APLIC_S].base + 678 (memmap[VIRT_APLIC_S].size * socket); 679 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 680 qemu_fdt_add_subnode(mc->fdt, aplic_name); 681 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 682 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 683 "#interrupt-cells", FDT_APLIC_INT_CELLS); 684 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 685 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 686 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 687 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 688 } else { 689 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 690 msi_s_phandle); 691 } 692 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 693 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); 694 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 695 VIRT_IRQCHIP_NUM_SOURCES); 696 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 697 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); 698 699 if (!socket) { 700 platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, 701 memmap[VIRT_PLATFORM_BUS].base, 702 memmap[VIRT_PLATFORM_BUS].size, 703 VIRT_PLATFORM_BUS_IRQ); 704 } 705 706 g_free(aplic_name); 707 708 g_free(aplic_cells); 709 aplic_phandles[socket] = aplic_s_phandle; 710 } 711 712 static void create_fdt_pmu(RISCVVirtState *s) 713 { 714 char *pmu_name; 715 MachineState *mc = MACHINE(s); 716 RISCVCPU hart = s->soc[0].harts[0]; 717 718 pmu_name = g_strdup_printf("/soc/pmu"); 719 qemu_fdt_add_subnode(mc->fdt, pmu_name); 720 qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); 721 riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); 722 723 g_free(pmu_name); 724 } 725 726 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 727 bool is_32_bit, uint32_t *phandle, 728 uint32_t *irq_mmio_phandle, 729 uint32_t *irq_pcie_phandle, 730 uint32_t *irq_virtio_phandle, 731 uint32_t *msi_pcie_phandle) 732 { 733 char *clust_name; 734 int socket, phandle_pos; 735 MachineState *mc = MACHINE(s); 736 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 737 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 738 739 qemu_fdt_add_subnode(mc->fdt, "/cpus"); 740 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", 741 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 742 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); 743 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); 744 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); 745 746 intc_phandles = g_new0(uint32_t, mc->smp.cpus); 747 748 phandle_pos = mc->smp.cpus; 749 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 750 phandle_pos -= s->soc[socket].num_harts; 751 752 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 753 qemu_fdt_add_subnode(mc->fdt, clust_name); 754 755 create_fdt_socket_cpus(s, socket, clust_name, phandle, 756 is_32_bit, &intc_phandles[phandle_pos]); 757 758 create_fdt_socket_memory(s, memmap, socket); 759 760 g_free(clust_name); 761 762 if (!kvm_enabled()) { 763 if (s->have_aclint) { 764 create_fdt_socket_aclint(s, memmap, socket, 765 &intc_phandles[phandle_pos]); 766 } else { 767 create_fdt_socket_clint(s, memmap, socket, 768 &intc_phandles[phandle_pos]); 769 } 770 } 771 } 772 773 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 774 create_fdt_imsic(s, memmap, phandle, intc_phandles, 775 &msi_m_phandle, &msi_s_phandle); 776 *msi_pcie_phandle = msi_s_phandle; 777 } 778 779 phandle_pos = mc->smp.cpus; 780 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 781 phandle_pos -= s->soc[socket].num_harts; 782 783 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 784 create_fdt_socket_plic(s, memmap, socket, phandle, 785 &intc_phandles[phandle_pos], xplic_phandles); 786 } else { 787 create_fdt_socket_aplic(s, memmap, socket, 788 msi_m_phandle, msi_s_phandle, phandle, 789 &intc_phandles[phandle_pos], xplic_phandles); 790 } 791 } 792 793 g_free(intc_phandles); 794 795 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 796 if (socket == 0) { 797 *irq_mmio_phandle = xplic_phandles[socket]; 798 *irq_virtio_phandle = xplic_phandles[socket]; 799 *irq_pcie_phandle = xplic_phandles[socket]; 800 } 801 if (socket == 1) { 802 *irq_virtio_phandle = xplic_phandles[socket]; 803 *irq_pcie_phandle = xplic_phandles[socket]; 804 } 805 if (socket == 2) { 806 *irq_pcie_phandle = xplic_phandles[socket]; 807 } 808 } 809 810 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); 811 } 812 813 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 814 uint32_t irq_virtio_phandle) 815 { 816 int i; 817 char *name; 818 MachineState *mc = MACHINE(s); 819 820 for (i = 0; i < VIRTIO_COUNT; i++) { 821 name = g_strdup_printf("/soc/virtio_mmio@%lx", 822 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 823 qemu_fdt_add_subnode(mc->fdt, name); 824 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); 825 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 826 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 827 0x0, memmap[VIRT_VIRTIO].size); 828 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 829 irq_virtio_phandle); 830 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 831 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", 832 VIRTIO_IRQ + i); 833 } else { 834 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", 835 VIRTIO_IRQ + i, 0x4); 836 } 837 g_free(name); 838 } 839 } 840 841 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 842 uint32_t irq_pcie_phandle, 843 uint32_t msi_pcie_phandle) 844 { 845 char *name; 846 MachineState *mc = MACHINE(s); 847 848 name = g_strdup_printf("/soc/pci@%lx", 849 (long) memmap[VIRT_PCIE_ECAM].base); 850 qemu_fdt_add_subnode(mc->fdt, name); 851 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", 852 FDT_PCI_ADDR_CELLS); 853 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 854 FDT_PCI_INT_CELLS); 855 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); 856 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 857 "pci-host-ecam-generic"); 858 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); 859 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); 860 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, 861 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 862 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); 863 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 864 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); 865 } 866 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, 867 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 868 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", 869 1, FDT_PCI_RANGE_IOPORT, 2, 0, 870 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 871 1, FDT_PCI_RANGE_MMIO, 872 2, memmap[VIRT_PCIE_MMIO].base, 873 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 874 1, FDT_PCI_RANGE_MMIO_64BIT, 875 2, virt_high_pcie_memmap.base, 876 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 877 878 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); 879 g_free(name); 880 } 881 882 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 883 uint32_t *phandle) 884 { 885 char *name; 886 uint32_t test_phandle; 887 MachineState *mc = MACHINE(s); 888 889 test_phandle = (*phandle)++; 890 name = g_strdup_printf("/soc/test@%lx", 891 (long)memmap[VIRT_TEST].base); 892 qemu_fdt_add_subnode(mc->fdt, name); 893 { 894 static const char * const compat[3] = { 895 "sifive,test1", "sifive,test0", "syscon" 896 }; 897 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", 898 (char **)&compat, ARRAY_SIZE(compat)); 899 } 900 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 901 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 902 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); 903 test_phandle = qemu_fdt_get_phandle(mc->fdt, name); 904 g_free(name); 905 906 name = g_strdup_printf("/reboot"); 907 qemu_fdt_add_subnode(mc->fdt, name); 908 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); 909 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 910 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 911 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); 912 g_free(name); 913 914 name = g_strdup_printf("/poweroff"); 915 qemu_fdt_add_subnode(mc->fdt, name); 916 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); 917 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 918 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 919 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); 920 g_free(name); 921 } 922 923 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 924 uint32_t irq_mmio_phandle) 925 { 926 char *name; 927 MachineState *mc = MACHINE(s); 928 929 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 930 qemu_fdt_add_subnode(mc->fdt, name); 931 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); 932 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 933 0x0, memmap[VIRT_UART0].base, 934 0x0, memmap[VIRT_UART0].size); 935 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); 936 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); 937 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 938 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); 939 } else { 940 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); 941 } 942 943 qemu_fdt_add_subnode(mc->fdt, "/chosen"); 944 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); 945 g_free(name); 946 } 947 948 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 949 uint32_t irq_mmio_phandle) 950 { 951 char *name; 952 MachineState *mc = MACHINE(s); 953 954 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 955 qemu_fdt_add_subnode(mc->fdt, name); 956 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 957 "google,goldfish-rtc"); 958 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 959 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 960 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 961 irq_mmio_phandle); 962 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 963 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); 964 } else { 965 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); 966 } 967 g_free(name); 968 } 969 970 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 971 { 972 char *name; 973 MachineState *mc = MACHINE(s); 974 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 975 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 976 977 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 978 qemu_fdt_add_subnode(mc->fdt, name); 979 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 980 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 981 2, flashbase, 2, flashsize, 982 2, flashbase + flashsize, 2, flashsize); 983 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 984 g_free(name); 985 } 986 987 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 988 { 989 char *nodename; 990 MachineState *mc = MACHINE(s); 991 hwaddr base = memmap[VIRT_FW_CFG].base; 992 hwaddr size = memmap[VIRT_FW_CFG].size; 993 994 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 995 qemu_fdt_add_subnode(mc->fdt, nodename); 996 qemu_fdt_setprop_string(mc->fdt, nodename, 997 "compatible", "qemu,fw-cfg-mmio"); 998 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 999 2, base, 2, size); 1000 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 1001 g_free(nodename); 1002 } 1003 1004 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 1005 uint64_t mem_size, const char *cmdline, bool is_32_bit) 1006 { 1007 MachineState *mc = MACHINE(s); 1008 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1009 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1010 uint8_t rng_seed[32]; 1011 1012 if (mc->dtb) { 1013 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 1014 if (!mc->fdt) { 1015 error_report("load_device_tree() failed"); 1016 exit(1); 1017 } 1018 goto update_bootargs; 1019 } else { 1020 mc->fdt = create_device_tree(&s->fdt_size); 1021 if (!mc->fdt) { 1022 error_report("create_device_tree() failed"); 1023 exit(1); 1024 } 1025 } 1026 1027 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); 1028 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); 1029 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); 1030 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); 1031 1032 qemu_fdt_add_subnode(mc->fdt, "/soc"); 1033 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); 1034 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); 1035 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); 1036 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); 1037 1038 create_fdt_sockets(s, memmap, is_32_bit, &phandle, 1039 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, 1040 &msi_pcie_phandle); 1041 1042 create_fdt_virtio(s, memmap, irq_virtio_phandle); 1043 1044 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); 1045 1046 create_fdt_reset(s, memmap, &phandle); 1047 1048 create_fdt_uart(s, memmap, irq_mmio_phandle); 1049 1050 create_fdt_rtc(s, memmap, irq_mmio_phandle); 1051 1052 create_fdt_flash(s, memmap); 1053 create_fdt_fw_cfg(s, memmap); 1054 create_fdt_pmu(s); 1055 1056 update_bootargs: 1057 if (cmdline && *cmdline) { 1058 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); 1059 } 1060 1061 /* Pass seed to RNG */ 1062 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1063 qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); 1064 } 1065 1066 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1067 hwaddr ecam_base, hwaddr ecam_size, 1068 hwaddr mmio_base, hwaddr mmio_size, 1069 hwaddr high_mmio_base, 1070 hwaddr high_mmio_size, 1071 hwaddr pio_base, 1072 DeviceState *irqchip) 1073 { 1074 DeviceState *dev; 1075 MemoryRegion *ecam_alias, *ecam_reg; 1076 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1077 qemu_irq irq; 1078 int i; 1079 1080 dev = qdev_new(TYPE_GPEX_HOST); 1081 1082 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1083 1084 ecam_alias = g_new0(MemoryRegion, 1); 1085 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1086 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1087 ecam_reg, 0, ecam_size); 1088 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1089 1090 mmio_alias = g_new0(MemoryRegion, 1); 1091 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1092 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1093 mmio_reg, mmio_base, mmio_size); 1094 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1095 1096 /* Map high MMIO space */ 1097 high_mmio_alias = g_new0(MemoryRegion, 1); 1098 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1099 mmio_reg, high_mmio_base, high_mmio_size); 1100 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1101 high_mmio_alias); 1102 1103 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1104 1105 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1106 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1107 1108 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1109 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1110 } 1111 1112 return dev; 1113 } 1114 1115 static FWCfgState *create_fw_cfg(const MachineState *mc) 1116 { 1117 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1118 FWCfgState *fw_cfg; 1119 1120 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1121 &address_space_memory); 1122 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 1123 1124 return fw_cfg; 1125 } 1126 1127 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1128 int base_hartid, int hart_count) 1129 { 1130 DeviceState *ret; 1131 char *plic_hart_config; 1132 1133 /* Per-socket PLIC hart topology configuration string */ 1134 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1135 1136 /* Per-socket PLIC */ 1137 ret = sifive_plic_create( 1138 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1139 plic_hart_config, hart_count, base_hartid, 1140 VIRT_IRQCHIP_NUM_SOURCES, 1141 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1142 VIRT_PLIC_PRIORITY_BASE, 1143 VIRT_PLIC_PENDING_BASE, 1144 VIRT_PLIC_ENABLE_BASE, 1145 VIRT_PLIC_ENABLE_STRIDE, 1146 VIRT_PLIC_CONTEXT_BASE, 1147 VIRT_PLIC_CONTEXT_STRIDE, 1148 memmap[VIRT_PLIC].size); 1149 1150 g_free(plic_hart_config); 1151 1152 return ret; 1153 } 1154 1155 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1156 const MemMapEntry *memmap, int socket, 1157 int base_hartid, int hart_count) 1158 { 1159 int i; 1160 hwaddr addr; 1161 uint32_t guest_bits; 1162 DeviceState *aplic_m; 1163 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; 1164 1165 if (msimode) { 1166 /* Per-socket M-level IMSICs */ 1167 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1168 for (i = 0; i < hart_count; i++) { 1169 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1170 base_hartid + i, true, 1, 1171 VIRT_IRQCHIP_NUM_MSIS); 1172 } 1173 1174 /* Per-socket S-level IMSICs */ 1175 guest_bits = imsic_num_bits(aia_guests + 1); 1176 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1177 for (i = 0; i < hart_count; i++) { 1178 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1179 base_hartid + i, false, 1 + aia_guests, 1180 VIRT_IRQCHIP_NUM_MSIS); 1181 } 1182 } 1183 1184 /* Per-socket M-level APLIC */ 1185 aplic_m = riscv_aplic_create( 1186 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, 1187 memmap[VIRT_APLIC_M].size, 1188 (msimode) ? 0 : base_hartid, 1189 (msimode) ? 0 : hart_count, 1190 VIRT_IRQCHIP_NUM_SOURCES, 1191 VIRT_IRQCHIP_NUM_PRIO_BITS, 1192 msimode, true, NULL); 1193 1194 if (aplic_m) { 1195 /* Per-socket S-level APLIC */ 1196 riscv_aplic_create( 1197 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, 1198 memmap[VIRT_APLIC_S].size, 1199 (msimode) ? 0 : base_hartid, 1200 (msimode) ? 0 : hart_count, 1201 VIRT_IRQCHIP_NUM_SOURCES, 1202 VIRT_IRQCHIP_NUM_PRIO_BITS, 1203 msimode, false, aplic_m); 1204 } 1205 1206 return aplic_m; 1207 } 1208 1209 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1210 { 1211 DeviceState *dev; 1212 SysBusDevice *sysbus; 1213 const MemMapEntry *memmap = virt_memmap; 1214 int i; 1215 MemoryRegion *sysmem = get_system_memory(); 1216 1217 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1218 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1219 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1220 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1221 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1222 s->platform_bus_dev = dev; 1223 1224 sysbus = SYS_BUS_DEVICE(dev); 1225 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1226 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1227 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1228 } 1229 1230 memory_region_add_subregion(sysmem, 1231 memmap[VIRT_PLATFORM_BUS].base, 1232 sysbus_mmio_get_region(sysbus, 0)); 1233 } 1234 1235 static void virt_machine_done(Notifier *notifier, void *data) 1236 { 1237 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1238 machine_done); 1239 const MemMapEntry *memmap = virt_memmap; 1240 MachineState *machine = MACHINE(s); 1241 target_ulong start_addr = memmap[VIRT_DRAM].base; 1242 target_ulong firmware_end_addr, kernel_start_addr; 1243 uint32_t fdt_load_addr; 1244 uint64_t kernel_entry; 1245 1246 /* 1247 * Only direct boot kernel is currently supported for KVM VM, 1248 * so the "-bios" parameter is not supported when KVM is enabled. 1249 */ 1250 if (kvm_enabled()) { 1251 if (machine->firmware) { 1252 if (strcmp(machine->firmware, "none")) { 1253 error_report("Machine mode firmware is not supported in " 1254 "combination with KVM."); 1255 exit(1); 1256 } 1257 } else { 1258 machine->firmware = g_strdup("none"); 1259 } 1260 } 1261 1262 if (riscv_is_32bit(&s->soc[0])) { 1263 firmware_end_addr = riscv_find_and_load_firmware(machine, 1264 RISCV32_BIOS_BIN, start_addr, NULL); 1265 } else { 1266 firmware_end_addr = riscv_find_and_load_firmware(machine, 1267 RISCV64_BIOS_BIN, start_addr, NULL); 1268 } 1269 1270 /* 1271 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 1272 * tree cannot be altered and we get FDT_ERR_NOSPACE. 1273 */ 1274 s->fw_cfg = create_fw_cfg(machine); 1275 rom_set_fw(s->fw_cfg); 1276 1277 if (drive_get(IF_PFLASH, 0, 1)) { 1278 /* 1279 * S-mode FW like EDK2 will be kept in second plash (unit 1). 1280 * When both kernel, initrd and pflash options are provided in the 1281 * command line, the kernel and initrd will be copied to the fw_cfg 1282 * table and opensbi will jump to the flash address which is the 1283 * entry point of S-mode FW. It is the job of the S-mode FW to load 1284 * the kernel and initrd using fw_cfg table. 1285 * 1286 * If only pflash is given but not -kernel, then it is the job of 1287 * of the S-mode firmware to locate and load the kernel. 1288 * In either case, the next_addr for opensbi will be the flash address. 1289 */ 1290 riscv_setup_firmware_boot(machine); 1291 kernel_entry = virt_memmap[VIRT_FLASH].base + 1292 virt_memmap[VIRT_FLASH].size / 2; 1293 } else if (machine->kernel_filename) { 1294 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1295 firmware_end_addr); 1296 1297 kernel_entry = riscv_load_kernel(machine->kernel_filename, 1298 kernel_start_addr, NULL); 1299 1300 if (machine->initrd_filename) { 1301 hwaddr start; 1302 hwaddr end = riscv_load_initrd(machine->initrd_filename, 1303 machine->ram_size, kernel_entry, 1304 &start); 1305 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 1306 "linux,initrd-start", start); 1307 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 1308 end); 1309 } 1310 } else { 1311 /* 1312 * If dynamic firmware is used, it doesn't know where is the next mode 1313 * if kernel argument is not set. 1314 */ 1315 kernel_entry = 0; 1316 } 1317 1318 if (drive_get(IF_PFLASH, 0, 0)) { 1319 /* 1320 * Pflash was supplied, let's overwrite the address we jump to after 1321 * reset to the base of the flash. 1322 */ 1323 start_addr = virt_memmap[VIRT_FLASH].base; 1324 } 1325 1326 /* Compute the fdt load address in dram */ 1327 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 1328 machine->ram_size, machine->fdt); 1329 /* load the reset vector */ 1330 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1331 virt_memmap[VIRT_MROM].base, 1332 virt_memmap[VIRT_MROM].size, kernel_entry, 1333 fdt_load_addr); 1334 1335 /* 1336 * Only direct boot kernel is currently supported for KVM VM, 1337 * So here setup kernel start address and fdt address. 1338 * TODO:Support firmware loading and integrate to TCG start 1339 */ 1340 if (kvm_enabled()) { 1341 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1342 } 1343 } 1344 1345 static void virt_machine_init(MachineState *machine) 1346 { 1347 const MemMapEntry *memmap = virt_memmap; 1348 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1349 MemoryRegion *system_memory = get_system_memory(); 1350 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1351 char *soc_name; 1352 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1353 int i, base_hartid, hart_count; 1354 1355 /* Check socket count limit */ 1356 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 1357 error_report("number of sockets/nodes should be less than %d", 1358 VIRT_SOCKETS_MAX); 1359 exit(1); 1360 } 1361 1362 /* Initialize sockets */ 1363 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1364 for (i = 0; i < riscv_socket_count(machine); i++) { 1365 if (!riscv_socket_check_hartids(machine, i)) { 1366 error_report("discontinuous hartids in socket%d", i); 1367 exit(1); 1368 } 1369 1370 base_hartid = riscv_socket_first_hartid(machine, i); 1371 if (base_hartid < 0) { 1372 error_report("can't find hartid base for socket%d", i); 1373 exit(1); 1374 } 1375 1376 hart_count = riscv_socket_hart_count(machine, i); 1377 if (hart_count < 0) { 1378 error_report("can't find hart count for socket%d", i); 1379 exit(1); 1380 } 1381 1382 soc_name = g_strdup_printf("soc%d", i); 1383 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1384 TYPE_RISCV_HART_ARRAY); 1385 g_free(soc_name); 1386 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1387 machine->cpu_type, &error_abort); 1388 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1389 base_hartid, &error_abort); 1390 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1391 hart_count, &error_abort); 1392 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1393 1394 if (!kvm_enabled()) { 1395 if (s->have_aclint) { 1396 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1397 /* Per-socket ACLINT MTIMER */ 1398 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1399 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1400 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1401 base_hartid, hart_count, 1402 RISCV_ACLINT_DEFAULT_MTIMECMP, 1403 RISCV_ACLINT_DEFAULT_MTIME, 1404 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1405 } else { 1406 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1407 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1408 i * memmap[VIRT_CLINT].size, 1409 base_hartid, hart_count, false); 1410 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1411 i * memmap[VIRT_CLINT].size + 1412 RISCV_ACLINT_SWI_SIZE, 1413 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1414 base_hartid, hart_count, 1415 RISCV_ACLINT_DEFAULT_MTIMECMP, 1416 RISCV_ACLINT_DEFAULT_MTIME, 1417 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1418 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1419 i * memmap[VIRT_ACLINT_SSWI].size, 1420 base_hartid, hart_count, true); 1421 } 1422 } else { 1423 /* Per-socket SiFive CLINT */ 1424 riscv_aclint_swi_create( 1425 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1426 base_hartid, hart_count, false); 1427 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1428 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1429 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1430 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1431 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1432 } 1433 } 1434 1435 /* Per-socket interrupt controller */ 1436 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1437 s->irqchip[i] = virt_create_plic(memmap, i, 1438 base_hartid, hart_count); 1439 } else { 1440 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1441 memmap, i, base_hartid, 1442 hart_count); 1443 } 1444 1445 /* Try to use different IRQCHIP instance based device type */ 1446 if (i == 0) { 1447 mmio_irqchip = s->irqchip[i]; 1448 virtio_irqchip = s->irqchip[i]; 1449 pcie_irqchip = s->irqchip[i]; 1450 } 1451 if (i == 1) { 1452 virtio_irqchip = s->irqchip[i]; 1453 pcie_irqchip = s->irqchip[i]; 1454 } 1455 if (i == 2) { 1456 pcie_irqchip = s->irqchip[i]; 1457 } 1458 } 1459 1460 if (riscv_is_32bit(&s->soc[0])) { 1461 #if HOST_LONG_BITS == 64 1462 /* limit RAM size in a 32-bit system */ 1463 if (machine->ram_size > 10 * GiB) { 1464 machine->ram_size = 10 * GiB; 1465 error_report("Limiting RAM size to 10 GiB"); 1466 } 1467 #endif 1468 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1469 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1470 } else { 1471 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1472 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1473 virt_high_pcie_memmap.base = 1474 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1475 } 1476 1477 /* register system main memory (actual RAM) */ 1478 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1479 machine->ram); 1480 1481 /* boot rom */ 1482 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1483 memmap[VIRT_MROM].size, &error_fatal); 1484 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1485 mask_rom); 1486 1487 /* SiFive Test MMIO device */ 1488 sifive_test_create(memmap[VIRT_TEST].base); 1489 1490 /* VirtIO MMIO devices */ 1491 for (i = 0; i < VIRTIO_COUNT; i++) { 1492 sysbus_create_simple("virtio-mmio", 1493 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1494 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); 1495 } 1496 1497 gpex_pcie_init(system_memory, 1498 memmap[VIRT_PCIE_ECAM].base, 1499 memmap[VIRT_PCIE_ECAM].size, 1500 memmap[VIRT_PCIE_MMIO].base, 1501 memmap[VIRT_PCIE_MMIO].size, 1502 virt_high_pcie_memmap.base, 1503 virt_high_pcie_memmap.size, 1504 memmap[VIRT_PCIE_PIO].base, 1505 DEVICE(pcie_irqchip)); 1506 1507 create_platform_bus(s, DEVICE(mmio_irqchip)); 1508 1509 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1510 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, 1511 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1512 1513 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1514 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); 1515 1516 virt_flash_create(s); 1517 1518 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1519 /* Map legacy -drive if=pflash to machine properties */ 1520 pflash_cfi01_legacy_drive(s->flash[i], 1521 drive_get(IF_PFLASH, 0, i)); 1522 } 1523 virt_flash_map(s, system_memory); 1524 1525 /* create device tree */ 1526 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 1527 riscv_is_32bit(&s->soc[0])); 1528 1529 s->machine_done.notify = virt_machine_done; 1530 qemu_add_machine_init_done_notifier(&s->machine_done); 1531 } 1532 1533 static void virt_machine_instance_init(Object *obj) 1534 { 1535 } 1536 1537 static char *virt_get_aia_guests(Object *obj, Error **errp) 1538 { 1539 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1540 char val[32]; 1541 1542 sprintf(val, "%d", s->aia_guests); 1543 return g_strdup(val); 1544 } 1545 1546 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1547 { 1548 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1549 1550 s->aia_guests = atoi(val); 1551 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1552 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1553 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1554 VIRT_IRQCHIP_MAX_GUESTS); 1555 } 1556 } 1557 1558 static char *virt_get_aia(Object *obj, Error **errp) 1559 { 1560 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1561 const char *val; 1562 1563 switch (s->aia_type) { 1564 case VIRT_AIA_TYPE_APLIC: 1565 val = "aplic"; 1566 break; 1567 case VIRT_AIA_TYPE_APLIC_IMSIC: 1568 val = "aplic-imsic"; 1569 break; 1570 default: 1571 val = "none"; 1572 break; 1573 }; 1574 1575 return g_strdup(val); 1576 } 1577 1578 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1579 { 1580 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1581 1582 if (!strcmp(val, "none")) { 1583 s->aia_type = VIRT_AIA_TYPE_NONE; 1584 } else if (!strcmp(val, "aplic")) { 1585 s->aia_type = VIRT_AIA_TYPE_APLIC; 1586 } else if (!strcmp(val, "aplic-imsic")) { 1587 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1588 } else { 1589 error_setg(errp, "Invalid AIA interrupt controller type"); 1590 error_append_hint(errp, "Valid values are none, aplic, and " 1591 "aplic-imsic.\n"); 1592 } 1593 } 1594 1595 static bool virt_get_aclint(Object *obj, Error **errp) 1596 { 1597 MachineState *ms = MACHINE(obj); 1598 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1599 1600 return s->have_aclint; 1601 } 1602 1603 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1604 { 1605 MachineState *ms = MACHINE(obj); 1606 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1607 1608 s->have_aclint = value; 1609 } 1610 1611 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1612 DeviceState *dev) 1613 { 1614 MachineClass *mc = MACHINE_GET_CLASS(machine); 1615 1616 if (device_is_dynamic_sysbus(mc, dev)) { 1617 return HOTPLUG_HANDLER(machine); 1618 } 1619 return NULL; 1620 } 1621 1622 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1623 DeviceState *dev, Error **errp) 1624 { 1625 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1626 1627 if (s->platform_bus_dev) { 1628 MachineClass *mc = MACHINE_GET_CLASS(s); 1629 1630 if (device_is_dynamic_sysbus(mc, dev)) { 1631 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1632 SYS_BUS_DEVICE(dev)); 1633 } 1634 } 1635 } 1636 1637 static void virt_machine_class_init(ObjectClass *oc, void *data) 1638 { 1639 char str[128]; 1640 MachineClass *mc = MACHINE_CLASS(oc); 1641 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1642 1643 mc->desc = "RISC-V VirtIO board"; 1644 mc->init = virt_machine_init; 1645 mc->max_cpus = VIRT_CPUS_MAX; 1646 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1647 mc->pci_allow_0_address = true; 1648 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1649 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1650 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1651 mc->numa_mem_supported = true; 1652 mc->default_ram_id = "riscv_virt_board.ram"; 1653 assert(!mc->get_hotplug_handler); 1654 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1655 1656 hc->plug = virt_machine_device_plug_cb; 1657 1658 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1659 #ifdef CONFIG_TPM 1660 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1661 #endif 1662 1663 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1664 virt_set_aclint); 1665 object_class_property_set_description(oc, "aclint", 1666 "Set on/off to enable/disable " 1667 "emulating ACLINT devices"); 1668 1669 object_class_property_add_str(oc, "aia", virt_get_aia, 1670 virt_set_aia); 1671 object_class_property_set_description(oc, "aia", 1672 "Set type of AIA interrupt " 1673 "conttoller. Valid values are " 1674 "none, aplic, and aplic-imsic."); 1675 1676 object_class_property_add_str(oc, "aia-guests", 1677 virt_get_aia_guests, 1678 virt_set_aia_guests); 1679 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1680 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1681 object_class_property_set_description(oc, "aia-guests", str); 1682 } 1683 1684 static const TypeInfo virt_machine_typeinfo = { 1685 .name = MACHINE_TYPE_NAME("virt"), 1686 .parent = TYPE_MACHINE, 1687 .class_init = virt_machine_class_init, 1688 .instance_init = virt_machine_instance_init, 1689 .instance_size = sizeof(RISCVVirtState), 1690 .interfaces = (InterfaceInfo[]) { 1691 { TYPE_HOTPLUG_HANDLER }, 1692 { } 1693 }, 1694 }; 1695 1696 static void virt_machine_init_register_types(void) 1697 { 1698 type_register_static(&virt_machine_typeinfo); 1699 } 1700 1701 type_init(virt_machine_init_register_types) 1702