1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/sysbus.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/char/serial.h" 30 #include "target/riscv/cpu.h" 31 #include "hw/riscv/riscv_hart.h" 32 #include "hw/riscv/virt.h" 33 #include "hw/riscv/boot.h" 34 #include "hw/riscv/numa.h" 35 #include "hw/intc/riscv_aclint.h" 36 #include "hw/intc/riscv_aplic.h" 37 #include "hw/intc/riscv_imsic.h" 38 #include "hw/intc/sifive_plic.h" 39 #include "hw/misc/sifive_test.h" 40 #include "chardev/char.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/kvm.h" 44 #include "hw/pci/pci.h" 45 #include "hw/pci-host/gpex.h" 46 #include "hw/display/ramfb.h" 47 48 /* 49 * The virt machine physical address space used by some of the devices 50 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 51 * number of CPUs, and number of IMSIC guest files. 52 * 53 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 54 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 55 * of virt machine physical address space. 56 */ 57 58 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 59 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 60 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 61 #error "Can't accomodate single IMSIC group in address space" 62 #endif 63 64 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 65 VIRT_IMSIC_GROUP_MAX_SIZE) 66 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 67 #error "Can't accomodate all IMSIC groups in address space" 68 #endif 69 70 static const MemMapEntry virt_memmap[] = { 71 [VIRT_DEBUG] = { 0x0, 0x100 }, 72 [VIRT_MROM] = { 0x1000, 0xf000 }, 73 [VIRT_TEST] = { 0x100000, 0x1000 }, 74 [VIRT_RTC] = { 0x101000, 0x1000 }, 75 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 76 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 77 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 78 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 79 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 80 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 81 [VIRT_UART0] = { 0x10000000, 0x100 }, 82 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 83 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 84 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 85 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 86 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 87 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 88 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 89 [VIRT_DRAM] = { 0x80000000, 0x0 }, 90 }; 91 92 /* PCIe high mmio is fixed for RV32 */ 93 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 94 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 95 96 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 97 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 98 99 static MemMapEntry virt_high_pcie_memmap; 100 101 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 102 103 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 104 const char *name, 105 const char *alias_prop_name) 106 { 107 /* 108 * Create a single flash device. We use the same parameters as 109 * the flash devices on the ARM virt board. 110 */ 111 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 112 113 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 114 qdev_prop_set_uint8(dev, "width", 4); 115 qdev_prop_set_uint8(dev, "device-width", 2); 116 qdev_prop_set_bit(dev, "big-endian", false); 117 qdev_prop_set_uint16(dev, "id0", 0x89); 118 qdev_prop_set_uint16(dev, "id1", 0x18); 119 qdev_prop_set_uint16(dev, "id2", 0x00); 120 qdev_prop_set_uint16(dev, "id3", 0x00); 121 qdev_prop_set_string(dev, "name", name); 122 123 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 124 object_property_add_alias(OBJECT(s), alias_prop_name, 125 OBJECT(dev), "drive"); 126 127 return PFLASH_CFI01(dev); 128 } 129 130 static void virt_flash_create(RISCVVirtState *s) 131 { 132 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 133 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 134 } 135 136 static void virt_flash_map1(PFlashCFI01 *flash, 137 hwaddr base, hwaddr size, 138 MemoryRegion *sysmem) 139 { 140 DeviceState *dev = DEVICE(flash); 141 142 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 143 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 144 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 145 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 146 147 memory_region_add_subregion(sysmem, base, 148 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 149 0)); 150 } 151 152 static void virt_flash_map(RISCVVirtState *s, 153 MemoryRegion *sysmem) 154 { 155 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 156 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 157 158 virt_flash_map1(s->flash[0], flashbase, flashsize, 159 sysmem); 160 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 161 sysmem); 162 } 163 164 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 165 uint32_t irqchip_phandle) 166 { 167 int pin, dev; 168 uint32_t irq_map_stride = 0; 169 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 170 FDT_MAX_INT_MAP_WIDTH] = {}; 171 uint32_t *irq_map = full_irq_map; 172 173 /* This code creates a standard swizzle of interrupts such that 174 * each device's first interrupt is based on it's PCI_SLOT number. 175 * (See pci_swizzle_map_irq_fn()) 176 * 177 * We only need one entry per interrupt in the table (not one per 178 * possible slot) seeing the interrupt-map-mask will allow the table 179 * to wrap to any number of devices. 180 */ 181 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 182 int devfn = dev * 0x8; 183 184 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 185 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 186 int i = 0; 187 188 /* Fill PCI address cells */ 189 irq_map[i] = cpu_to_be32(devfn << 8); 190 i += FDT_PCI_ADDR_CELLS; 191 192 /* Fill PCI Interrupt cells */ 193 irq_map[i] = cpu_to_be32(pin + 1); 194 i += FDT_PCI_INT_CELLS; 195 196 /* Fill interrupt controller phandle and cells */ 197 irq_map[i++] = cpu_to_be32(irqchip_phandle); 198 irq_map[i++] = cpu_to_be32(irq_nr); 199 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 200 irq_map[i++] = cpu_to_be32(0x4); 201 } 202 203 if (!irq_map_stride) { 204 irq_map_stride = i; 205 } 206 irq_map += irq_map_stride; 207 } 208 } 209 210 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 211 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 212 irq_map_stride * sizeof(uint32_t)); 213 214 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 215 0x1800, 0, 0, 0x7); 216 } 217 218 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 219 char *clust_name, uint32_t *phandle, 220 bool is_32_bit, uint32_t *intc_phandles) 221 { 222 int cpu; 223 uint32_t cpu_phandle; 224 MachineState *mc = MACHINE(s); 225 char *name, *cpu_name, *core_name, *intc_name; 226 227 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 228 cpu_phandle = (*phandle)++; 229 230 cpu_name = g_strdup_printf("/cpus/cpu@%d", 231 s->soc[socket].hartid_base + cpu); 232 qemu_fdt_add_subnode(mc->fdt, cpu_name); 233 if (riscv_feature(&s->soc[socket].harts[cpu].env, 234 RISCV_FEATURE_MMU)) { 235 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 236 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 237 } else { 238 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 239 "riscv,none"); 240 } 241 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 242 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); 243 g_free(name); 244 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); 245 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); 246 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", 247 s->soc[socket].hartid_base + cpu); 248 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); 249 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); 250 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); 251 252 intc_phandles[cpu] = (*phandle)++; 253 254 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 255 qemu_fdt_add_subnode(mc->fdt, intc_name); 256 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", 257 intc_phandles[cpu]); 258 if (riscv_feature(&s->soc[socket].harts[cpu].env, 259 RISCV_FEATURE_AIA)) { 260 static const char * const compat[2] = { 261 "riscv,cpu-intc-aia", "riscv,cpu-intc" 262 }; 263 qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible", 264 (char **)&compat, ARRAY_SIZE(compat)); 265 } else { 266 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", 267 "riscv,cpu-intc"); 268 } 269 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); 270 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); 271 272 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 273 qemu_fdt_add_subnode(mc->fdt, core_name); 274 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); 275 276 g_free(core_name); 277 g_free(intc_name); 278 g_free(cpu_name); 279 } 280 } 281 282 static void create_fdt_socket_memory(RISCVVirtState *s, 283 const MemMapEntry *memmap, int socket) 284 { 285 char *mem_name; 286 uint64_t addr, size; 287 MachineState *mc = MACHINE(s); 288 289 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 290 size = riscv_socket_mem_size(mc, socket); 291 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 292 qemu_fdt_add_subnode(mc->fdt, mem_name); 293 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", 294 addr >> 32, addr, size >> 32, size); 295 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); 296 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); 297 g_free(mem_name); 298 } 299 300 static void create_fdt_socket_clint(RISCVVirtState *s, 301 const MemMapEntry *memmap, int socket, 302 uint32_t *intc_phandles) 303 { 304 int cpu; 305 char *clint_name; 306 uint32_t *clint_cells; 307 unsigned long clint_addr; 308 MachineState *mc = MACHINE(s); 309 static const char * const clint_compat[2] = { 310 "sifive,clint0", "riscv,clint0" 311 }; 312 313 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 314 315 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 316 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 317 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 318 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 319 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 320 } 321 322 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 323 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 324 qemu_fdt_add_subnode(mc->fdt, clint_name); 325 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", 326 (char **)&clint_compat, 327 ARRAY_SIZE(clint_compat)); 328 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", 329 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 330 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", 331 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 332 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); 333 g_free(clint_name); 334 335 g_free(clint_cells); 336 } 337 338 static void create_fdt_socket_aclint(RISCVVirtState *s, 339 const MemMapEntry *memmap, int socket, 340 uint32_t *intc_phandles) 341 { 342 int cpu; 343 char *name; 344 unsigned long addr, size; 345 uint32_t aclint_cells_size; 346 uint32_t *aclint_mswi_cells; 347 uint32_t *aclint_sswi_cells; 348 uint32_t *aclint_mtimer_cells; 349 MachineState *mc = MACHINE(s); 350 351 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 352 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 353 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 354 355 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 356 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 357 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 358 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 359 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 360 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 361 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 362 } 363 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 364 365 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 366 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 367 name = g_strdup_printf("/soc/mswi@%lx", addr); 368 qemu_fdt_add_subnode(mc->fdt, name); 369 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 370 "riscv,aclint-mswi"); 371 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 372 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 373 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 374 aclint_mswi_cells, aclint_cells_size); 375 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 376 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 377 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 378 g_free(name); 379 } 380 381 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 382 addr = memmap[VIRT_CLINT].base + 383 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 384 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 385 } else { 386 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 387 (memmap[VIRT_CLINT].size * socket); 388 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 389 } 390 name = g_strdup_printf("/soc/mtimer@%lx", addr); 391 qemu_fdt_add_subnode(mc->fdt, name); 392 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 393 "riscv,aclint-mtimer"); 394 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 395 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 396 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 397 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 398 0x0, RISCV_ACLINT_DEFAULT_MTIME); 399 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 400 aclint_mtimer_cells, aclint_cells_size); 401 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 402 g_free(name); 403 404 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 405 addr = memmap[VIRT_ACLINT_SSWI].base + 406 (memmap[VIRT_ACLINT_SSWI].size * socket); 407 name = g_strdup_printf("/soc/sswi@%lx", addr); 408 qemu_fdt_add_subnode(mc->fdt, name); 409 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 410 "riscv,aclint-sswi"); 411 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 412 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 413 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 414 aclint_sswi_cells, aclint_cells_size); 415 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 416 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 417 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 418 g_free(name); 419 } 420 421 g_free(aclint_mswi_cells); 422 g_free(aclint_mtimer_cells); 423 g_free(aclint_sswi_cells); 424 } 425 426 static void create_fdt_socket_plic(RISCVVirtState *s, 427 const MemMapEntry *memmap, int socket, 428 uint32_t *phandle, uint32_t *intc_phandles, 429 uint32_t *plic_phandles) 430 { 431 int cpu; 432 char *plic_name; 433 uint32_t *plic_cells; 434 unsigned long plic_addr; 435 MachineState *mc = MACHINE(s); 436 static const char * const plic_compat[2] = { 437 "sifive,plic-1.0.0", "riscv,plic0" 438 }; 439 440 if (kvm_enabled()) { 441 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 442 } else { 443 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 444 } 445 446 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 447 if (kvm_enabled()) { 448 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 449 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 450 } else { 451 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 452 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 453 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 454 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 455 } 456 } 457 458 plic_phandles[socket] = (*phandle)++; 459 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 460 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 461 qemu_fdt_add_subnode(mc->fdt, plic_name); 462 qemu_fdt_setprop_cell(mc->fdt, plic_name, 463 "#interrupt-cells", FDT_PLIC_INT_CELLS); 464 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", 465 (char **)&plic_compat, 466 ARRAY_SIZE(plic_compat)); 467 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); 468 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", 469 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 470 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", 471 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 472 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 473 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); 474 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", 475 plic_phandles[socket]); 476 g_free(plic_name); 477 478 g_free(plic_cells); 479 } 480 481 static uint32_t imsic_num_bits(uint32_t count) 482 { 483 uint32_t ret = 0; 484 485 while (BIT(ret) < count) { 486 ret++; 487 } 488 489 return ret; 490 } 491 492 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 493 uint32_t *phandle, uint32_t *intc_phandles, 494 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 495 { 496 int cpu, socket; 497 char *imsic_name; 498 MachineState *mc = MACHINE(s); 499 uint32_t imsic_max_hart_per_socket, imsic_guest_bits; 500 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 501 502 *msi_m_phandle = (*phandle)++; 503 *msi_s_phandle = (*phandle)++; 504 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); 505 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); 506 507 /* M-level IMSIC node */ 508 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 509 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 510 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 511 } 512 imsic_max_hart_per_socket = 0; 513 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 514 imsic_addr = memmap[VIRT_IMSIC_M].base + 515 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 516 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; 517 imsic_regs[socket * 4 + 0] = 0; 518 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 519 imsic_regs[socket * 4 + 2] = 0; 520 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 521 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 522 imsic_max_hart_per_socket = s->soc[socket].num_harts; 523 } 524 } 525 imsic_name = g_strdup_printf("/soc/imsics@%lx", 526 (unsigned long)memmap[VIRT_IMSIC_M].base); 527 qemu_fdt_add_subnode(mc->fdt, imsic_name); 528 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 529 "riscv,imsics"); 530 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 531 FDT_IMSIC_INT_CELLS); 532 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 533 NULL, 0); 534 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 535 NULL, 0); 536 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 537 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 538 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 539 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 540 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 541 VIRT_IRQCHIP_NUM_MSIS); 542 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 543 VIRT_IRQCHIP_IPI_MSI); 544 if (riscv_socket_count(mc) > 1) { 545 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 546 imsic_num_bits(imsic_max_hart_per_socket)); 547 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 548 imsic_num_bits(riscv_socket_count(mc))); 549 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 550 IMSIC_MMIO_GROUP_MIN_SHIFT); 551 } 552 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); 553 g_free(imsic_name); 554 555 /* S-level IMSIC node */ 556 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 557 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 558 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 559 } 560 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); 561 imsic_max_hart_per_socket = 0; 562 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 563 imsic_addr = memmap[VIRT_IMSIC_S].base + 564 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 565 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 566 s->soc[socket].num_harts; 567 imsic_regs[socket * 4 + 0] = 0; 568 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 569 imsic_regs[socket * 4 + 2] = 0; 570 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 571 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 572 imsic_max_hart_per_socket = s->soc[socket].num_harts; 573 } 574 } 575 imsic_name = g_strdup_printf("/soc/imsics@%lx", 576 (unsigned long)memmap[VIRT_IMSIC_S].base); 577 qemu_fdt_add_subnode(mc->fdt, imsic_name); 578 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 579 "riscv,imsics"); 580 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 581 FDT_IMSIC_INT_CELLS); 582 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 583 NULL, 0); 584 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 585 NULL, 0); 586 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 587 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 588 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 589 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 590 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 591 VIRT_IRQCHIP_NUM_MSIS); 592 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 593 VIRT_IRQCHIP_IPI_MSI); 594 if (imsic_guest_bits) { 595 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", 596 imsic_guest_bits); 597 } 598 if (riscv_socket_count(mc) > 1) { 599 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 600 imsic_num_bits(imsic_max_hart_per_socket)); 601 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 602 imsic_num_bits(riscv_socket_count(mc))); 603 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 604 IMSIC_MMIO_GROUP_MIN_SHIFT); 605 } 606 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); 607 g_free(imsic_name); 608 609 g_free(imsic_regs); 610 g_free(imsic_cells); 611 } 612 613 static void create_fdt_socket_aplic(RISCVVirtState *s, 614 const MemMapEntry *memmap, int socket, 615 uint32_t msi_m_phandle, 616 uint32_t msi_s_phandle, 617 uint32_t *phandle, 618 uint32_t *intc_phandles, 619 uint32_t *aplic_phandles) 620 { 621 int cpu; 622 char *aplic_name; 623 uint32_t *aplic_cells; 624 unsigned long aplic_addr; 625 MachineState *mc = MACHINE(s); 626 uint32_t aplic_m_phandle, aplic_s_phandle; 627 628 aplic_m_phandle = (*phandle)++; 629 aplic_s_phandle = (*phandle)++; 630 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 631 632 /* M-level APLIC node */ 633 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 634 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 635 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 636 } 637 aplic_addr = memmap[VIRT_APLIC_M].base + 638 (memmap[VIRT_APLIC_M].size * socket); 639 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 640 qemu_fdt_add_subnode(mc->fdt, aplic_name); 641 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 642 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 643 "#interrupt-cells", FDT_APLIC_INT_CELLS); 644 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 645 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 646 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 647 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 648 } else { 649 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 650 msi_m_phandle); 651 } 652 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 653 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); 654 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 655 VIRT_IRQCHIP_NUM_SOURCES); 656 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", 657 aplic_s_phandle); 658 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", 659 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); 660 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 661 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); 662 g_free(aplic_name); 663 664 /* S-level APLIC node */ 665 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 666 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 667 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 668 } 669 aplic_addr = memmap[VIRT_APLIC_S].base + 670 (memmap[VIRT_APLIC_S].size * socket); 671 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 672 qemu_fdt_add_subnode(mc->fdt, aplic_name); 673 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 674 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 675 "#interrupt-cells", FDT_APLIC_INT_CELLS); 676 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 677 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 678 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 679 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 680 } else { 681 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 682 msi_s_phandle); 683 } 684 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 685 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); 686 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 687 VIRT_IRQCHIP_NUM_SOURCES); 688 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 689 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); 690 g_free(aplic_name); 691 692 g_free(aplic_cells); 693 aplic_phandles[socket] = aplic_s_phandle; 694 } 695 696 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 697 bool is_32_bit, uint32_t *phandle, 698 uint32_t *irq_mmio_phandle, 699 uint32_t *irq_pcie_phandle, 700 uint32_t *irq_virtio_phandle, 701 uint32_t *msi_pcie_phandle) 702 { 703 char *clust_name; 704 int socket, phandle_pos; 705 MachineState *mc = MACHINE(s); 706 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 707 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 708 709 qemu_fdt_add_subnode(mc->fdt, "/cpus"); 710 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", 711 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 712 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); 713 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); 714 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); 715 716 intc_phandles = g_new0(uint32_t, mc->smp.cpus); 717 718 phandle_pos = mc->smp.cpus; 719 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 720 phandle_pos -= s->soc[socket].num_harts; 721 722 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 723 qemu_fdt_add_subnode(mc->fdt, clust_name); 724 725 create_fdt_socket_cpus(s, socket, clust_name, phandle, 726 is_32_bit, &intc_phandles[phandle_pos]); 727 728 create_fdt_socket_memory(s, memmap, socket); 729 730 g_free(clust_name); 731 732 if (!kvm_enabled()) { 733 if (s->have_aclint) { 734 create_fdt_socket_aclint(s, memmap, socket, 735 &intc_phandles[phandle_pos]); 736 } else { 737 create_fdt_socket_clint(s, memmap, socket, 738 &intc_phandles[phandle_pos]); 739 } 740 } 741 } 742 743 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 744 create_fdt_imsic(s, memmap, phandle, intc_phandles, 745 &msi_m_phandle, &msi_s_phandle); 746 *msi_pcie_phandle = msi_s_phandle; 747 } 748 749 phandle_pos = mc->smp.cpus; 750 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 751 phandle_pos -= s->soc[socket].num_harts; 752 753 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 754 create_fdt_socket_plic(s, memmap, socket, phandle, 755 &intc_phandles[phandle_pos], xplic_phandles); 756 } else { 757 create_fdt_socket_aplic(s, memmap, socket, 758 msi_m_phandle, msi_s_phandle, phandle, 759 &intc_phandles[phandle_pos], xplic_phandles); 760 } 761 } 762 763 g_free(intc_phandles); 764 765 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 766 if (socket == 0) { 767 *irq_mmio_phandle = xplic_phandles[socket]; 768 *irq_virtio_phandle = xplic_phandles[socket]; 769 *irq_pcie_phandle = xplic_phandles[socket]; 770 } 771 if (socket == 1) { 772 *irq_virtio_phandle = xplic_phandles[socket]; 773 *irq_pcie_phandle = xplic_phandles[socket]; 774 } 775 if (socket == 2) { 776 *irq_pcie_phandle = xplic_phandles[socket]; 777 } 778 } 779 780 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); 781 } 782 783 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 784 uint32_t irq_virtio_phandle) 785 { 786 int i; 787 char *name; 788 MachineState *mc = MACHINE(s); 789 790 for (i = 0; i < VIRTIO_COUNT; i++) { 791 name = g_strdup_printf("/soc/virtio_mmio@%lx", 792 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 793 qemu_fdt_add_subnode(mc->fdt, name); 794 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); 795 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 796 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 797 0x0, memmap[VIRT_VIRTIO].size); 798 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 799 irq_virtio_phandle); 800 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 801 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", 802 VIRTIO_IRQ + i); 803 } else { 804 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", 805 VIRTIO_IRQ + i, 0x4); 806 } 807 g_free(name); 808 } 809 } 810 811 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 812 uint32_t irq_pcie_phandle, 813 uint32_t msi_pcie_phandle) 814 { 815 char *name; 816 MachineState *mc = MACHINE(s); 817 818 name = g_strdup_printf("/soc/pci@%lx", 819 (long) memmap[VIRT_PCIE_ECAM].base); 820 qemu_fdt_add_subnode(mc->fdt, name); 821 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", 822 FDT_PCI_ADDR_CELLS); 823 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 824 FDT_PCI_INT_CELLS); 825 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); 826 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 827 "pci-host-ecam-generic"); 828 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); 829 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); 830 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, 831 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 832 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); 833 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 834 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); 835 } 836 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, 837 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 838 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", 839 1, FDT_PCI_RANGE_IOPORT, 2, 0, 840 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 841 1, FDT_PCI_RANGE_MMIO, 842 2, memmap[VIRT_PCIE_MMIO].base, 843 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 844 1, FDT_PCI_RANGE_MMIO_64BIT, 845 2, virt_high_pcie_memmap.base, 846 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 847 848 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); 849 g_free(name); 850 } 851 852 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 853 uint32_t *phandle) 854 { 855 char *name; 856 uint32_t test_phandle; 857 MachineState *mc = MACHINE(s); 858 859 test_phandle = (*phandle)++; 860 name = g_strdup_printf("/soc/test@%lx", 861 (long)memmap[VIRT_TEST].base); 862 qemu_fdt_add_subnode(mc->fdt, name); 863 { 864 static const char * const compat[3] = { 865 "sifive,test1", "sifive,test0", "syscon" 866 }; 867 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", 868 (char **)&compat, ARRAY_SIZE(compat)); 869 } 870 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 871 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 872 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); 873 test_phandle = qemu_fdt_get_phandle(mc->fdt, name); 874 g_free(name); 875 876 name = g_strdup_printf("/soc/reboot"); 877 qemu_fdt_add_subnode(mc->fdt, name); 878 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); 879 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 880 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 881 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); 882 g_free(name); 883 884 name = g_strdup_printf("/soc/poweroff"); 885 qemu_fdt_add_subnode(mc->fdt, name); 886 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); 887 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 888 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 889 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); 890 g_free(name); 891 } 892 893 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 894 uint32_t irq_mmio_phandle) 895 { 896 char *name; 897 MachineState *mc = MACHINE(s); 898 899 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 900 qemu_fdt_add_subnode(mc->fdt, name); 901 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); 902 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 903 0x0, memmap[VIRT_UART0].base, 904 0x0, memmap[VIRT_UART0].size); 905 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); 906 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); 907 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 908 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); 909 } else { 910 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); 911 } 912 913 qemu_fdt_add_subnode(mc->fdt, "/chosen"); 914 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); 915 g_free(name); 916 } 917 918 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 919 uint32_t irq_mmio_phandle) 920 { 921 char *name; 922 MachineState *mc = MACHINE(s); 923 924 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 925 qemu_fdt_add_subnode(mc->fdt, name); 926 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 927 "google,goldfish-rtc"); 928 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 929 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 930 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 931 irq_mmio_phandle); 932 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 933 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); 934 } else { 935 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); 936 } 937 g_free(name); 938 } 939 940 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 941 { 942 char *name; 943 MachineState *mc = MACHINE(s); 944 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 945 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 946 947 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 948 qemu_fdt_add_subnode(mc->fdt, name); 949 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 950 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 951 2, flashbase, 2, flashsize, 952 2, flashbase + flashsize, 2, flashsize); 953 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 954 g_free(name); 955 } 956 957 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 958 uint64_t mem_size, const char *cmdline, bool is_32_bit) 959 { 960 MachineState *mc = MACHINE(s); 961 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 962 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 963 964 if (mc->dtb) { 965 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 966 if (!mc->fdt) { 967 error_report("load_device_tree() failed"); 968 exit(1); 969 } 970 goto update_bootargs; 971 } else { 972 mc->fdt = create_device_tree(&s->fdt_size); 973 if (!mc->fdt) { 974 error_report("create_device_tree() failed"); 975 exit(1); 976 } 977 } 978 979 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); 980 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); 981 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); 982 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); 983 984 qemu_fdt_add_subnode(mc->fdt, "/soc"); 985 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); 986 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); 987 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); 988 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); 989 990 create_fdt_sockets(s, memmap, is_32_bit, &phandle, 991 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, 992 &msi_pcie_phandle); 993 994 create_fdt_virtio(s, memmap, irq_virtio_phandle); 995 996 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); 997 998 create_fdt_reset(s, memmap, &phandle); 999 1000 create_fdt_uart(s, memmap, irq_mmio_phandle); 1001 1002 create_fdt_rtc(s, memmap, irq_mmio_phandle); 1003 1004 create_fdt_flash(s, memmap); 1005 1006 update_bootargs: 1007 if (cmdline && *cmdline) { 1008 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); 1009 } 1010 } 1011 1012 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1013 hwaddr ecam_base, hwaddr ecam_size, 1014 hwaddr mmio_base, hwaddr mmio_size, 1015 hwaddr high_mmio_base, 1016 hwaddr high_mmio_size, 1017 hwaddr pio_base, 1018 DeviceState *irqchip) 1019 { 1020 DeviceState *dev; 1021 MemoryRegion *ecam_alias, *ecam_reg; 1022 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1023 qemu_irq irq; 1024 int i; 1025 1026 dev = qdev_new(TYPE_GPEX_HOST); 1027 1028 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1029 1030 ecam_alias = g_new0(MemoryRegion, 1); 1031 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1032 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1033 ecam_reg, 0, ecam_size); 1034 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1035 1036 mmio_alias = g_new0(MemoryRegion, 1); 1037 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1038 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1039 mmio_reg, mmio_base, mmio_size); 1040 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1041 1042 /* Map high MMIO space */ 1043 high_mmio_alias = g_new0(MemoryRegion, 1); 1044 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1045 mmio_reg, high_mmio_base, high_mmio_size); 1046 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1047 high_mmio_alias); 1048 1049 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1050 1051 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1052 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1053 1054 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1055 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1056 } 1057 1058 return dev; 1059 } 1060 1061 static FWCfgState *create_fw_cfg(const MachineState *mc) 1062 { 1063 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1064 hwaddr size = virt_memmap[VIRT_FW_CFG].size; 1065 FWCfgState *fw_cfg; 1066 char *nodename; 1067 1068 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1069 &address_space_memory); 1070 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 1071 1072 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1073 qemu_fdt_add_subnode(mc->fdt, nodename); 1074 qemu_fdt_setprop_string(mc->fdt, nodename, 1075 "compatible", "qemu,fw-cfg-mmio"); 1076 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 1077 2, base, 2, size); 1078 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 1079 g_free(nodename); 1080 return fw_cfg; 1081 } 1082 1083 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1084 int base_hartid, int hart_count) 1085 { 1086 DeviceState *ret; 1087 char *plic_hart_config; 1088 1089 /* Per-socket PLIC hart topology configuration string */ 1090 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1091 1092 /* Per-socket PLIC */ 1093 ret = sifive_plic_create( 1094 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1095 plic_hart_config, hart_count, base_hartid, 1096 VIRT_IRQCHIP_NUM_SOURCES, 1097 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1098 VIRT_PLIC_PRIORITY_BASE, 1099 VIRT_PLIC_PENDING_BASE, 1100 VIRT_PLIC_ENABLE_BASE, 1101 VIRT_PLIC_ENABLE_STRIDE, 1102 VIRT_PLIC_CONTEXT_BASE, 1103 VIRT_PLIC_CONTEXT_STRIDE, 1104 memmap[VIRT_PLIC].size); 1105 1106 g_free(plic_hart_config); 1107 1108 return ret; 1109 } 1110 1111 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1112 const MemMapEntry *memmap, int socket, 1113 int base_hartid, int hart_count) 1114 { 1115 int i; 1116 hwaddr addr; 1117 uint32_t guest_bits; 1118 DeviceState *aplic_m; 1119 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; 1120 1121 if (msimode) { 1122 /* Per-socket M-level IMSICs */ 1123 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1124 for (i = 0; i < hart_count; i++) { 1125 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1126 base_hartid + i, true, 1, 1127 VIRT_IRQCHIP_NUM_MSIS); 1128 } 1129 1130 /* Per-socket S-level IMSICs */ 1131 guest_bits = imsic_num_bits(aia_guests + 1); 1132 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1133 for (i = 0; i < hart_count; i++) { 1134 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1135 base_hartid + i, false, 1 + aia_guests, 1136 VIRT_IRQCHIP_NUM_MSIS); 1137 } 1138 } 1139 1140 /* Per-socket M-level APLIC */ 1141 aplic_m = riscv_aplic_create( 1142 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, 1143 memmap[VIRT_APLIC_M].size, 1144 (msimode) ? 0 : base_hartid, 1145 (msimode) ? 0 : hart_count, 1146 VIRT_IRQCHIP_NUM_SOURCES, 1147 VIRT_IRQCHIP_NUM_PRIO_BITS, 1148 msimode, true, NULL); 1149 1150 if (aplic_m) { 1151 /* Per-socket S-level APLIC */ 1152 riscv_aplic_create( 1153 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, 1154 memmap[VIRT_APLIC_S].size, 1155 (msimode) ? 0 : base_hartid, 1156 (msimode) ? 0 : hart_count, 1157 VIRT_IRQCHIP_NUM_SOURCES, 1158 VIRT_IRQCHIP_NUM_PRIO_BITS, 1159 msimode, false, aplic_m); 1160 } 1161 1162 return aplic_m; 1163 } 1164 1165 static void virt_machine_init(MachineState *machine) 1166 { 1167 const MemMapEntry *memmap = virt_memmap; 1168 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1169 MemoryRegion *system_memory = get_system_memory(); 1170 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1171 char *soc_name; 1172 target_ulong start_addr = memmap[VIRT_DRAM].base; 1173 target_ulong firmware_end_addr, kernel_start_addr; 1174 uint32_t fdt_load_addr; 1175 uint64_t kernel_entry; 1176 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1177 int i, base_hartid, hart_count; 1178 1179 /* Check socket count limit */ 1180 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 1181 error_report("number of sockets/nodes should be less than %d", 1182 VIRT_SOCKETS_MAX); 1183 exit(1); 1184 } 1185 1186 /* Initialize sockets */ 1187 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1188 for (i = 0; i < riscv_socket_count(machine); i++) { 1189 if (!riscv_socket_check_hartids(machine, i)) { 1190 error_report("discontinuous hartids in socket%d", i); 1191 exit(1); 1192 } 1193 1194 base_hartid = riscv_socket_first_hartid(machine, i); 1195 if (base_hartid < 0) { 1196 error_report("can't find hartid base for socket%d", i); 1197 exit(1); 1198 } 1199 1200 hart_count = riscv_socket_hart_count(machine, i); 1201 if (hart_count < 0) { 1202 error_report("can't find hart count for socket%d", i); 1203 exit(1); 1204 } 1205 1206 soc_name = g_strdup_printf("soc%d", i); 1207 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1208 TYPE_RISCV_HART_ARRAY); 1209 g_free(soc_name); 1210 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1211 machine->cpu_type, &error_abort); 1212 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1213 base_hartid, &error_abort); 1214 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1215 hart_count, &error_abort); 1216 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 1217 1218 if (!kvm_enabled()) { 1219 if (s->have_aclint) { 1220 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1221 /* Per-socket ACLINT MTIMER */ 1222 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1223 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1224 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1225 base_hartid, hart_count, 1226 RISCV_ACLINT_DEFAULT_MTIMECMP, 1227 RISCV_ACLINT_DEFAULT_MTIME, 1228 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1229 } else { 1230 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1231 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1232 i * memmap[VIRT_CLINT].size, 1233 base_hartid, hart_count, false); 1234 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1235 i * memmap[VIRT_CLINT].size + 1236 RISCV_ACLINT_SWI_SIZE, 1237 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1238 base_hartid, hart_count, 1239 RISCV_ACLINT_DEFAULT_MTIMECMP, 1240 RISCV_ACLINT_DEFAULT_MTIME, 1241 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1242 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1243 i * memmap[VIRT_ACLINT_SSWI].size, 1244 base_hartid, hart_count, true); 1245 } 1246 } else { 1247 /* Per-socket SiFive CLINT */ 1248 riscv_aclint_swi_create( 1249 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1250 base_hartid, hart_count, false); 1251 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1252 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1253 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1254 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1255 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1256 } 1257 } 1258 1259 /* Per-socket interrupt controller */ 1260 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1261 s->irqchip[i] = virt_create_plic(memmap, i, 1262 base_hartid, hart_count); 1263 } else { 1264 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1265 memmap, i, base_hartid, 1266 hart_count); 1267 } 1268 1269 /* Try to use different IRQCHIP instance based device type */ 1270 if (i == 0) { 1271 mmio_irqchip = s->irqchip[i]; 1272 virtio_irqchip = s->irqchip[i]; 1273 pcie_irqchip = s->irqchip[i]; 1274 } 1275 if (i == 1) { 1276 virtio_irqchip = s->irqchip[i]; 1277 pcie_irqchip = s->irqchip[i]; 1278 } 1279 if (i == 2) { 1280 pcie_irqchip = s->irqchip[i]; 1281 } 1282 } 1283 1284 if (riscv_is_32bit(&s->soc[0])) { 1285 #if HOST_LONG_BITS == 64 1286 /* limit RAM size in a 32-bit system */ 1287 if (machine->ram_size > 10 * GiB) { 1288 machine->ram_size = 10 * GiB; 1289 error_report("Limiting RAM size to 10 GiB"); 1290 } 1291 #endif 1292 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1293 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1294 } else { 1295 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1296 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1297 virt_high_pcie_memmap.base = 1298 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1299 } 1300 1301 /* register system main memory (actual RAM) */ 1302 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1303 machine->ram); 1304 1305 /* create device tree */ 1306 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 1307 riscv_is_32bit(&s->soc[0])); 1308 1309 /* boot rom */ 1310 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1311 memmap[VIRT_MROM].size, &error_fatal); 1312 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1313 mask_rom); 1314 1315 /* 1316 * Only direct boot kernel is currently supported for KVM VM, 1317 * so the "-bios" parameter is not supported when KVM is enabled. 1318 */ 1319 if (kvm_enabled()) { 1320 if (machine->firmware) { 1321 if (strcmp(machine->firmware, "none")) { 1322 error_report("Machine mode firmware is not supported in " 1323 "combination with KVM."); 1324 exit(1); 1325 } 1326 } else { 1327 machine->firmware = g_strdup("none"); 1328 } 1329 } 1330 1331 if (riscv_is_32bit(&s->soc[0])) { 1332 firmware_end_addr = riscv_find_and_load_firmware(machine, 1333 RISCV32_BIOS_BIN, start_addr, NULL); 1334 } else { 1335 firmware_end_addr = riscv_find_and_load_firmware(machine, 1336 RISCV64_BIOS_BIN, start_addr, NULL); 1337 } 1338 1339 if (machine->kernel_filename) { 1340 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1341 firmware_end_addr); 1342 1343 kernel_entry = riscv_load_kernel(machine->kernel_filename, 1344 kernel_start_addr, NULL); 1345 1346 if (machine->initrd_filename) { 1347 hwaddr start; 1348 hwaddr end = riscv_load_initrd(machine->initrd_filename, 1349 machine->ram_size, kernel_entry, 1350 &start); 1351 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 1352 "linux,initrd-start", start); 1353 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 1354 end); 1355 } 1356 } else { 1357 /* 1358 * If dynamic firmware is used, it doesn't know where is the next mode 1359 * if kernel argument is not set. 1360 */ 1361 kernel_entry = 0; 1362 } 1363 1364 if (drive_get(IF_PFLASH, 0, 0)) { 1365 /* 1366 * Pflash was supplied, let's overwrite the address we jump to after 1367 * reset to the base of the flash. 1368 */ 1369 start_addr = virt_memmap[VIRT_FLASH].base; 1370 } 1371 1372 /* 1373 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 1374 * tree cannot be altered and we get FDT_ERR_NOSPACE. 1375 */ 1376 s->fw_cfg = create_fw_cfg(machine); 1377 rom_set_fw(s->fw_cfg); 1378 1379 /* Compute the fdt load address in dram */ 1380 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 1381 machine->ram_size, machine->fdt); 1382 /* load the reset vector */ 1383 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1384 virt_memmap[VIRT_MROM].base, 1385 virt_memmap[VIRT_MROM].size, kernel_entry, 1386 fdt_load_addr, machine->fdt); 1387 1388 /* 1389 * Only direct boot kernel is currently supported for KVM VM, 1390 * So here setup kernel start address and fdt address. 1391 * TODO:Support firmware loading and integrate to TCG start 1392 */ 1393 if (kvm_enabled()) { 1394 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1395 } 1396 1397 /* SiFive Test MMIO device */ 1398 sifive_test_create(memmap[VIRT_TEST].base); 1399 1400 /* VirtIO MMIO devices */ 1401 for (i = 0; i < VIRTIO_COUNT; i++) { 1402 sysbus_create_simple("virtio-mmio", 1403 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1404 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); 1405 } 1406 1407 gpex_pcie_init(system_memory, 1408 memmap[VIRT_PCIE_ECAM].base, 1409 memmap[VIRT_PCIE_ECAM].size, 1410 memmap[VIRT_PCIE_MMIO].base, 1411 memmap[VIRT_PCIE_MMIO].size, 1412 virt_high_pcie_memmap.base, 1413 virt_high_pcie_memmap.size, 1414 memmap[VIRT_PCIE_PIO].base, 1415 DEVICE(pcie_irqchip)); 1416 1417 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1418 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, 1419 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1420 1421 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1422 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); 1423 1424 virt_flash_create(s); 1425 1426 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1427 /* Map legacy -drive if=pflash to machine properties */ 1428 pflash_cfi01_legacy_drive(s->flash[i], 1429 drive_get(IF_PFLASH, 0, i)); 1430 } 1431 virt_flash_map(s, system_memory); 1432 } 1433 1434 static void virt_machine_instance_init(Object *obj) 1435 { 1436 } 1437 1438 static char *virt_get_aia_guests(Object *obj, Error **errp) 1439 { 1440 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1441 char val[32]; 1442 1443 sprintf(val, "%d", s->aia_guests); 1444 return g_strdup(val); 1445 } 1446 1447 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1448 { 1449 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1450 1451 s->aia_guests = atoi(val); 1452 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1453 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1454 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1455 VIRT_IRQCHIP_MAX_GUESTS); 1456 } 1457 } 1458 1459 static char *virt_get_aia(Object *obj, Error **errp) 1460 { 1461 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1462 const char *val; 1463 1464 switch (s->aia_type) { 1465 case VIRT_AIA_TYPE_APLIC: 1466 val = "aplic"; 1467 break; 1468 case VIRT_AIA_TYPE_APLIC_IMSIC: 1469 val = "aplic-imsic"; 1470 break; 1471 default: 1472 val = "none"; 1473 break; 1474 }; 1475 1476 return g_strdup(val); 1477 } 1478 1479 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1480 { 1481 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1482 1483 if (!strcmp(val, "none")) { 1484 s->aia_type = VIRT_AIA_TYPE_NONE; 1485 } else if (!strcmp(val, "aplic")) { 1486 s->aia_type = VIRT_AIA_TYPE_APLIC; 1487 } else if (!strcmp(val, "aplic-imsic")) { 1488 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1489 } else { 1490 error_setg(errp, "Invalid AIA interrupt controller type"); 1491 error_append_hint(errp, "Valid values are none, aplic, and " 1492 "aplic-imsic.\n"); 1493 } 1494 } 1495 1496 static bool virt_get_aclint(Object *obj, Error **errp) 1497 { 1498 MachineState *ms = MACHINE(obj); 1499 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1500 1501 return s->have_aclint; 1502 } 1503 1504 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1505 { 1506 MachineState *ms = MACHINE(obj); 1507 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1508 1509 s->have_aclint = value; 1510 } 1511 1512 static void virt_machine_class_init(ObjectClass *oc, void *data) 1513 { 1514 char str[128]; 1515 MachineClass *mc = MACHINE_CLASS(oc); 1516 1517 mc->desc = "RISC-V VirtIO board"; 1518 mc->init = virt_machine_init; 1519 mc->max_cpus = VIRT_CPUS_MAX; 1520 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1521 mc->pci_allow_0_address = true; 1522 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1523 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1524 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1525 mc->numa_mem_supported = true; 1526 mc->default_ram_id = "riscv_virt_board.ram"; 1527 1528 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1529 1530 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1531 virt_set_aclint); 1532 object_class_property_set_description(oc, "aclint", 1533 "Set on/off to enable/disable " 1534 "emulating ACLINT devices"); 1535 1536 object_class_property_add_str(oc, "aia", virt_get_aia, 1537 virt_set_aia); 1538 object_class_property_set_description(oc, "aia", 1539 "Set type of AIA interrupt " 1540 "conttoller. Valid values are " 1541 "none, aplic, and aplic-imsic."); 1542 1543 object_class_property_add_str(oc, "aia-guests", 1544 virt_get_aia_guests, 1545 virt_set_aia_guests); 1546 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1547 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1548 object_class_property_set_description(oc, "aia-guests", str); 1549 } 1550 1551 static const TypeInfo virt_machine_typeinfo = { 1552 .name = MACHINE_TYPE_NAME("virt"), 1553 .parent = TYPE_MACHINE, 1554 .class_init = virt_machine_class_init, 1555 .instance_init = virt_machine_instance_init, 1556 .instance_size = sizeof(RISCVVirtState), 1557 }; 1558 1559 static void virt_machine_init_register_types(void) 1560 { 1561 type_register_static(&virt_machine_typeinfo); 1562 } 1563 1564 type_init(virt_machine_init_register_types) 1565