1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/sysbus.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/char/serial.h" 30 #include "target/riscv/cpu.h" 31 #include "hw/riscv/riscv_hart.h" 32 #include "hw/riscv/virt.h" 33 #include "hw/riscv/boot.h" 34 #include "hw/riscv/numa.h" 35 #include "hw/intc/riscv_aclint.h" 36 #include "hw/intc/riscv_aplic.h" 37 #include "hw/intc/sifive_plic.h" 38 #include "hw/misc/sifive_test.h" 39 #include "chardev/char.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/sysemu.h" 42 #include "sysemu/kvm.h" 43 #include "hw/pci/pci.h" 44 #include "hw/pci-host/gpex.h" 45 #include "hw/display/ramfb.h" 46 47 static const MemMapEntry virt_memmap[] = { 48 [VIRT_DEBUG] = { 0x0, 0x100 }, 49 [VIRT_MROM] = { 0x1000, 0xf000 }, 50 [VIRT_TEST] = { 0x100000, 0x1000 }, 51 [VIRT_RTC] = { 0x101000, 0x1000 }, 52 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 53 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 54 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 55 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 56 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 57 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 58 [VIRT_UART0] = { 0x10000000, 0x100 }, 59 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 60 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 61 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 62 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 63 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 64 [VIRT_DRAM] = { 0x80000000, 0x0 }, 65 }; 66 67 /* PCIe high mmio is fixed for RV32 */ 68 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 69 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 70 71 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 72 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 73 74 static MemMapEntry virt_high_pcie_memmap; 75 76 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 77 78 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 79 const char *name, 80 const char *alias_prop_name) 81 { 82 /* 83 * Create a single flash device. We use the same parameters as 84 * the flash devices on the ARM virt board. 85 */ 86 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 87 88 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 89 qdev_prop_set_uint8(dev, "width", 4); 90 qdev_prop_set_uint8(dev, "device-width", 2); 91 qdev_prop_set_bit(dev, "big-endian", false); 92 qdev_prop_set_uint16(dev, "id0", 0x89); 93 qdev_prop_set_uint16(dev, "id1", 0x18); 94 qdev_prop_set_uint16(dev, "id2", 0x00); 95 qdev_prop_set_uint16(dev, "id3", 0x00); 96 qdev_prop_set_string(dev, "name", name); 97 98 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 99 object_property_add_alias(OBJECT(s), alias_prop_name, 100 OBJECT(dev), "drive"); 101 102 return PFLASH_CFI01(dev); 103 } 104 105 static void virt_flash_create(RISCVVirtState *s) 106 { 107 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 108 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 109 } 110 111 static void virt_flash_map1(PFlashCFI01 *flash, 112 hwaddr base, hwaddr size, 113 MemoryRegion *sysmem) 114 { 115 DeviceState *dev = DEVICE(flash); 116 117 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 118 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 119 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 120 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 121 122 memory_region_add_subregion(sysmem, base, 123 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 124 0)); 125 } 126 127 static void virt_flash_map(RISCVVirtState *s, 128 MemoryRegion *sysmem) 129 { 130 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 131 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 132 133 virt_flash_map1(s->flash[0], flashbase, flashsize, 134 sysmem); 135 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 136 sysmem); 137 } 138 139 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 140 uint32_t irqchip_phandle) 141 { 142 int pin, dev; 143 uint32_t irq_map_stride = 0; 144 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 145 FDT_MAX_INT_MAP_WIDTH] = {}; 146 uint32_t *irq_map = full_irq_map; 147 148 /* This code creates a standard swizzle of interrupts such that 149 * each device's first interrupt is based on it's PCI_SLOT number. 150 * (See pci_swizzle_map_irq_fn()) 151 * 152 * We only need one entry per interrupt in the table (not one per 153 * possible slot) seeing the interrupt-map-mask will allow the table 154 * to wrap to any number of devices. 155 */ 156 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 157 int devfn = dev * 0x8; 158 159 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 160 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 161 int i = 0; 162 163 /* Fill PCI address cells */ 164 irq_map[i] = cpu_to_be32(devfn << 8); 165 i += FDT_PCI_ADDR_CELLS; 166 167 /* Fill PCI Interrupt cells */ 168 irq_map[i] = cpu_to_be32(pin + 1); 169 i += FDT_PCI_INT_CELLS; 170 171 /* Fill interrupt controller phandle and cells */ 172 irq_map[i++] = cpu_to_be32(irqchip_phandle); 173 irq_map[i++] = cpu_to_be32(irq_nr); 174 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 175 irq_map[i++] = cpu_to_be32(0x4); 176 } 177 178 if (!irq_map_stride) { 179 irq_map_stride = i; 180 } 181 irq_map += irq_map_stride; 182 } 183 } 184 185 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 186 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 187 irq_map_stride * sizeof(uint32_t)); 188 189 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 190 0x1800, 0, 0, 0x7); 191 } 192 193 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 194 char *clust_name, uint32_t *phandle, 195 bool is_32_bit, uint32_t *intc_phandles) 196 { 197 int cpu; 198 uint32_t cpu_phandle; 199 MachineState *mc = MACHINE(s); 200 char *name, *cpu_name, *core_name, *intc_name; 201 202 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 203 cpu_phandle = (*phandle)++; 204 205 cpu_name = g_strdup_printf("/cpus/cpu@%d", 206 s->soc[socket].hartid_base + cpu); 207 qemu_fdt_add_subnode(mc->fdt, cpu_name); 208 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 209 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 210 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 211 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); 212 g_free(name); 213 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); 214 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); 215 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", 216 s->soc[socket].hartid_base + cpu); 217 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); 218 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); 219 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); 220 221 intc_phandles[cpu] = (*phandle)++; 222 223 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 224 qemu_fdt_add_subnode(mc->fdt, intc_name); 225 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", 226 intc_phandles[cpu]); 227 if (riscv_feature(&s->soc[socket].harts[cpu].env, 228 RISCV_FEATURE_AIA)) { 229 static const char * const compat[2] = { 230 "riscv,cpu-intc-aia", "riscv,cpu-intc" 231 }; 232 qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible", 233 (char **)&compat, ARRAY_SIZE(compat)); 234 } else { 235 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", 236 "riscv,cpu-intc"); 237 } 238 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); 239 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); 240 241 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 242 qemu_fdt_add_subnode(mc->fdt, core_name); 243 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); 244 245 g_free(core_name); 246 g_free(intc_name); 247 g_free(cpu_name); 248 } 249 } 250 251 static void create_fdt_socket_memory(RISCVVirtState *s, 252 const MemMapEntry *memmap, int socket) 253 { 254 char *mem_name; 255 uint64_t addr, size; 256 MachineState *mc = MACHINE(s); 257 258 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 259 size = riscv_socket_mem_size(mc, socket); 260 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 261 qemu_fdt_add_subnode(mc->fdt, mem_name); 262 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", 263 addr >> 32, addr, size >> 32, size); 264 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); 265 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); 266 g_free(mem_name); 267 } 268 269 static void create_fdt_socket_clint(RISCVVirtState *s, 270 const MemMapEntry *memmap, int socket, 271 uint32_t *intc_phandles) 272 { 273 int cpu; 274 char *clint_name; 275 uint32_t *clint_cells; 276 unsigned long clint_addr; 277 MachineState *mc = MACHINE(s); 278 static const char * const clint_compat[2] = { 279 "sifive,clint0", "riscv,clint0" 280 }; 281 282 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 283 284 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 285 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 286 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 287 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 288 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 289 } 290 291 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 292 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 293 qemu_fdt_add_subnode(mc->fdt, clint_name); 294 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", 295 (char **)&clint_compat, 296 ARRAY_SIZE(clint_compat)); 297 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", 298 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 299 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", 300 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 301 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); 302 g_free(clint_name); 303 304 g_free(clint_cells); 305 } 306 307 static void create_fdt_socket_aclint(RISCVVirtState *s, 308 const MemMapEntry *memmap, int socket, 309 uint32_t *intc_phandles) 310 { 311 int cpu; 312 char *name; 313 unsigned long addr; 314 uint32_t aclint_cells_size; 315 uint32_t *aclint_mswi_cells; 316 uint32_t *aclint_sswi_cells; 317 uint32_t *aclint_mtimer_cells; 318 MachineState *mc = MACHINE(s); 319 320 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 321 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 322 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 323 324 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 325 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 326 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 327 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 328 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 329 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 330 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 331 } 332 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 333 334 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 335 name = g_strdup_printf("/soc/mswi@%lx", addr); 336 qemu_fdt_add_subnode(mc->fdt, name); 337 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-mswi"); 338 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 339 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 340 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 341 aclint_mswi_cells, aclint_cells_size); 342 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 343 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 344 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 345 g_free(name); 346 347 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 348 (memmap[VIRT_CLINT].size * socket); 349 name = g_strdup_printf("/soc/mtimer@%lx", addr); 350 qemu_fdt_add_subnode(mc->fdt, name); 351 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 352 "riscv,aclint-mtimer"); 353 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 354 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 355 0x0, memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE - 356 RISCV_ACLINT_DEFAULT_MTIME, 357 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 358 0x0, RISCV_ACLINT_DEFAULT_MTIME); 359 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 360 aclint_mtimer_cells, aclint_cells_size); 361 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 362 g_free(name); 363 364 addr = memmap[VIRT_ACLINT_SSWI].base + 365 (memmap[VIRT_ACLINT_SSWI].size * socket); 366 name = g_strdup_printf("/soc/sswi@%lx", addr); 367 qemu_fdt_add_subnode(mc->fdt, name); 368 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-sswi"); 369 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 370 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 371 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 372 aclint_sswi_cells, aclint_cells_size); 373 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 374 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 375 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 376 g_free(name); 377 378 g_free(aclint_mswi_cells); 379 g_free(aclint_mtimer_cells); 380 g_free(aclint_sswi_cells); 381 } 382 383 static void create_fdt_socket_plic(RISCVVirtState *s, 384 const MemMapEntry *memmap, int socket, 385 uint32_t *phandle, uint32_t *intc_phandles, 386 uint32_t *plic_phandles) 387 { 388 int cpu; 389 char *plic_name; 390 uint32_t *plic_cells; 391 unsigned long plic_addr; 392 MachineState *mc = MACHINE(s); 393 static const char * const plic_compat[2] = { 394 "sifive,plic-1.0.0", "riscv,plic0" 395 }; 396 397 if (kvm_enabled()) { 398 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 399 } else { 400 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 401 } 402 403 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 404 if (kvm_enabled()) { 405 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 406 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 407 } else { 408 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 409 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 410 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 411 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 412 } 413 } 414 415 plic_phandles[socket] = (*phandle)++; 416 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 417 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 418 qemu_fdt_add_subnode(mc->fdt, plic_name); 419 qemu_fdt_setprop_cell(mc->fdt, plic_name, 420 "#interrupt-cells", FDT_PLIC_INT_CELLS); 421 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", 422 (char **)&plic_compat, 423 ARRAY_SIZE(plic_compat)); 424 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); 425 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", 426 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 427 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", 428 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 429 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 430 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); 431 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", 432 plic_phandles[socket]); 433 g_free(plic_name); 434 435 g_free(plic_cells); 436 } 437 438 static void create_fdt_socket_aia(RISCVVirtState *s, 439 const MemMapEntry *memmap, int socket, 440 uint32_t *phandle, uint32_t *intc_phandles, 441 uint32_t *aplic_phandles) 442 { 443 int cpu; 444 char *aplic_name; 445 uint32_t *aplic_cells; 446 unsigned long aplic_addr; 447 MachineState *mc = MACHINE(s); 448 uint32_t aplic_m_phandle, aplic_s_phandle; 449 450 aplic_m_phandle = (*phandle)++; 451 aplic_s_phandle = (*phandle)++; 452 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 453 454 /* M-level APLIC node */ 455 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 456 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 457 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 458 } 459 aplic_addr = memmap[VIRT_APLIC_M].base + 460 (memmap[VIRT_APLIC_M].size * socket); 461 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 462 qemu_fdt_add_subnode(mc->fdt, aplic_name); 463 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 464 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 465 "#interrupt-cells", FDT_APLIC_INT_CELLS); 466 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 467 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 468 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 469 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 470 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); 471 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 472 VIRT_IRQCHIP_NUM_SOURCES); 473 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", 474 aplic_s_phandle); 475 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", 476 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); 477 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 478 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); 479 g_free(aplic_name); 480 481 /* S-level APLIC node */ 482 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 483 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 484 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 485 } 486 aplic_addr = memmap[VIRT_APLIC_S].base + 487 (memmap[VIRT_APLIC_S].size * socket); 488 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 489 qemu_fdt_add_subnode(mc->fdt, aplic_name); 490 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 491 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 492 "#interrupt-cells", FDT_APLIC_INT_CELLS); 493 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 494 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 495 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 496 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 497 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); 498 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 499 VIRT_IRQCHIP_NUM_SOURCES); 500 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 501 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); 502 g_free(aplic_name); 503 504 g_free(aplic_cells); 505 aplic_phandles[socket] = aplic_s_phandle; 506 } 507 508 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 509 bool is_32_bit, uint32_t *phandle, 510 uint32_t *irq_mmio_phandle, 511 uint32_t *irq_pcie_phandle, 512 uint32_t *irq_virtio_phandle) 513 { 514 int socket; 515 char *clust_name; 516 uint32_t *intc_phandles; 517 MachineState *mc = MACHINE(s); 518 uint32_t xplic_phandles[MAX_NODES]; 519 520 qemu_fdt_add_subnode(mc->fdt, "/cpus"); 521 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", 522 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 523 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); 524 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); 525 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); 526 527 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 528 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 529 qemu_fdt_add_subnode(mc->fdt, clust_name); 530 531 intc_phandles = g_new0(uint32_t, s->soc[socket].num_harts); 532 533 create_fdt_socket_cpus(s, socket, clust_name, phandle, 534 is_32_bit, intc_phandles); 535 536 create_fdt_socket_memory(s, memmap, socket); 537 538 if (!kvm_enabled()) { 539 if (s->have_aclint) { 540 create_fdt_socket_aclint(s, memmap, socket, intc_phandles); 541 } else { 542 create_fdt_socket_clint(s, memmap, socket, intc_phandles); 543 } 544 } 545 546 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 547 create_fdt_socket_plic(s, memmap, socket, phandle, 548 intc_phandles, xplic_phandles); 549 } else { 550 create_fdt_socket_aia(s, memmap, socket, phandle, 551 intc_phandles, xplic_phandles); 552 } 553 554 g_free(intc_phandles); 555 g_free(clust_name); 556 } 557 558 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 559 if (socket == 0) { 560 *irq_mmio_phandle = xplic_phandles[socket]; 561 *irq_virtio_phandle = xplic_phandles[socket]; 562 *irq_pcie_phandle = xplic_phandles[socket]; 563 } 564 if (socket == 1) { 565 *irq_virtio_phandle = xplic_phandles[socket]; 566 *irq_pcie_phandle = xplic_phandles[socket]; 567 } 568 if (socket == 2) { 569 *irq_pcie_phandle = xplic_phandles[socket]; 570 } 571 } 572 573 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); 574 } 575 576 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 577 uint32_t irq_virtio_phandle) 578 { 579 int i; 580 char *name; 581 MachineState *mc = MACHINE(s); 582 583 for (i = 0; i < VIRTIO_COUNT; i++) { 584 name = g_strdup_printf("/soc/virtio_mmio@%lx", 585 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 586 qemu_fdt_add_subnode(mc->fdt, name); 587 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); 588 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 589 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 590 0x0, memmap[VIRT_VIRTIO].size); 591 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 592 irq_virtio_phandle); 593 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 594 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", 595 VIRTIO_IRQ + i); 596 } else { 597 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", 598 VIRTIO_IRQ + i, 0x4); 599 } 600 g_free(name); 601 } 602 } 603 604 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 605 uint32_t irq_pcie_phandle) 606 { 607 char *name; 608 MachineState *mc = MACHINE(s); 609 610 name = g_strdup_printf("/soc/pci@%lx", 611 (long) memmap[VIRT_PCIE_ECAM].base); 612 qemu_fdt_add_subnode(mc->fdt, name); 613 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", 614 FDT_PCI_ADDR_CELLS); 615 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 616 FDT_PCI_INT_CELLS); 617 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); 618 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 619 "pci-host-ecam-generic"); 620 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); 621 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); 622 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, 623 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 624 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); 625 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, 626 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 627 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", 628 1, FDT_PCI_RANGE_IOPORT, 2, 0, 629 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 630 1, FDT_PCI_RANGE_MMIO, 631 2, memmap[VIRT_PCIE_MMIO].base, 632 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 633 1, FDT_PCI_RANGE_MMIO_64BIT, 634 2, virt_high_pcie_memmap.base, 635 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 636 637 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); 638 g_free(name); 639 } 640 641 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 642 uint32_t *phandle) 643 { 644 char *name; 645 uint32_t test_phandle; 646 MachineState *mc = MACHINE(s); 647 648 test_phandle = (*phandle)++; 649 name = g_strdup_printf("/soc/test@%lx", 650 (long)memmap[VIRT_TEST].base); 651 qemu_fdt_add_subnode(mc->fdt, name); 652 { 653 static const char * const compat[3] = { 654 "sifive,test1", "sifive,test0", "syscon" 655 }; 656 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", 657 (char **)&compat, ARRAY_SIZE(compat)); 658 } 659 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 660 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 661 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); 662 test_phandle = qemu_fdt_get_phandle(mc->fdt, name); 663 g_free(name); 664 665 name = g_strdup_printf("/soc/reboot"); 666 qemu_fdt_add_subnode(mc->fdt, name); 667 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); 668 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 669 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 670 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); 671 g_free(name); 672 673 name = g_strdup_printf("/soc/poweroff"); 674 qemu_fdt_add_subnode(mc->fdt, name); 675 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); 676 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 677 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 678 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); 679 g_free(name); 680 } 681 682 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 683 uint32_t irq_mmio_phandle) 684 { 685 char *name; 686 MachineState *mc = MACHINE(s); 687 688 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 689 qemu_fdt_add_subnode(mc->fdt, name); 690 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); 691 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 692 0x0, memmap[VIRT_UART0].base, 693 0x0, memmap[VIRT_UART0].size); 694 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); 695 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); 696 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 697 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); 698 } else { 699 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); 700 } 701 702 qemu_fdt_add_subnode(mc->fdt, "/chosen"); 703 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); 704 g_free(name); 705 } 706 707 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 708 uint32_t irq_mmio_phandle) 709 { 710 char *name; 711 MachineState *mc = MACHINE(s); 712 713 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 714 qemu_fdt_add_subnode(mc->fdt, name); 715 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 716 "google,goldfish-rtc"); 717 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 718 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 719 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 720 irq_mmio_phandle); 721 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 722 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); 723 } else { 724 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); 725 } 726 g_free(name); 727 } 728 729 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 730 { 731 char *name; 732 MachineState *mc = MACHINE(s); 733 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 734 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 735 736 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 737 qemu_fdt_add_subnode(mc->fdt, name); 738 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 739 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 740 2, flashbase, 2, flashsize, 741 2, flashbase + flashsize, 2, flashsize); 742 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 743 g_free(name); 744 } 745 746 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 747 uint64_t mem_size, const char *cmdline, bool is_32_bit) 748 { 749 MachineState *mc = MACHINE(s); 750 uint32_t phandle = 1, irq_mmio_phandle = 1; 751 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 752 753 if (mc->dtb) { 754 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 755 if (!mc->fdt) { 756 error_report("load_device_tree() failed"); 757 exit(1); 758 } 759 goto update_bootargs; 760 } else { 761 mc->fdt = create_device_tree(&s->fdt_size); 762 if (!mc->fdt) { 763 error_report("create_device_tree() failed"); 764 exit(1); 765 } 766 } 767 768 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); 769 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); 770 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); 771 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); 772 773 qemu_fdt_add_subnode(mc->fdt, "/soc"); 774 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); 775 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); 776 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); 777 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); 778 779 create_fdt_sockets(s, memmap, is_32_bit, &phandle, 780 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle); 781 782 create_fdt_virtio(s, memmap, irq_virtio_phandle); 783 784 create_fdt_pcie(s, memmap, irq_pcie_phandle); 785 786 create_fdt_reset(s, memmap, &phandle); 787 788 create_fdt_uart(s, memmap, irq_mmio_phandle); 789 790 create_fdt_rtc(s, memmap, irq_mmio_phandle); 791 792 create_fdt_flash(s, memmap); 793 794 update_bootargs: 795 if (cmdline) { 796 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); 797 } 798 } 799 800 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 801 hwaddr ecam_base, hwaddr ecam_size, 802 hwaddr mmio_base, hwaddr mmio_size, 803 hwaddr high_mmio_base, 804 hwaddr high_mmio_size, 805 hwaddr pio_base, 806 DeviceState *irqchip) 807 { 808 DeviceState *dev; 809 MemoryRegion *ecam_alias, *ecam_reg; 810 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 811 qemu_irq irq; 812 int i; 813 814 dev = qdev_new(TYPE_GPEX_HOST); 815 816 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 817 818 ecam_alias = g_new0(MemoryRegion, 1); 819 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 820 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 821 ecam_reg, 0, ecam_size); 822 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 823 824 mmio_alias = g_new0(MemoryRegion, 1); 825 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 826 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 827 mmio_reg, mmio_base, mmio_size); 828 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 829 830 /* Map high MMIO space */ 831 high_mmio_alias = g_new0(MemoryRegion, 1); 832 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 833 mmio_reg, high_mmio_base, high_mmio_size); 834 memory_region_add_subregion(get_system_memory(), high_mmio_base, 835 high_mmio_alias); 836 837 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 838 839 for (i = 0; i < GPEX_NUM_IRQS; i++) { 840 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 841 842 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 843 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 844 } 845 846 return dev; 847 } 848 849 static FWCfgState *create_fw_cfg(const MachineState *mc) 850 { 851 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 852 hwaddr size = virt_memmap[VIRT_FW_CFG].size; 853 FWCfgState *fw_cfg; 854 char *nodename; 855 856 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 857 &address_space_memory); 858 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 859 860 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 861 qemu_fdt_add_subnode(mc->fdt, nodename); 862 qemu_fdt_setprop_string(mc->fdt, nodename, 863 "compatible", "qemu,fw-cfg-mmio"); 864 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 865 2, base, 2, size); 866 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 867 g_free(nodename); 868 return fw_cfg; 869 } 870 871 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 872 int base_hartid, int hart_count) 873 { 874 DeviceState *ret; 875 char *plic_hart_config; 876 877 /* Per-socket PLIC hart topology configuration string */ 878 plic_hart_config = riscv_plic_hart_config_string(hart_count); 879 880 /* Per-socket PLIC */ 881 ret = sifive_plic_create( 882 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 883 plic_hart_config, hart_count, base_hartid, 884 VIRT_IRQCHIP_NUM_SOURCES, 885 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 886 VIRT_PLIC_PRIORITY_BASE, 887 VIRT_PLIC_PENDING_BASE, 888 VIRT_PLIC_ENABLE_BASE, 889 VIRT_PLIC_ENABLE_STRIDE, 890 VIRT_PLIC_CONTEXT_BASE, 891 VIRT_PLIC_CONTEXT_STRIDE, 892 memmap[VIRT_PLIC].size); 893 894 g_free(plic_hart_config); 895 896 return ret; 897 } 898 899 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, 900 const MemMapEntry *memmap, int socket, 901 int base_hartid, int hart_count) 902 { 903 DeviceState *aplic_m; 904 905 /* Per-socket M-level APLIC */ 906 aplic_m = riscv_aplic_create( 907 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, 908 memmap[VIRT_APLIC_M].size, 909 base_hartid, hart_count, 910 VIRT_IRQCHIP_NUM_SOURCES, 911 VIRT_IRQCHIP_NUM_PRIO_BITS, 912 false, true, NULL); 913 914 if (aplic_m) { 915 /* Per-socket S-level APLIC */ 916 riscv_aplic_create( 917 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, 918 memmap[VIRT_APLIC_S].size, 919 base_hartid, hart_count, 920 VIRT_IRQCHIP_NUM_SOURCES, 921 VIRT_IRQCHIP_NUM_PRIO_BITS, 922 false, false, aplic_m); 923 } 924 925 return aplic_m; 926 } 927 928 static void virt_machine_init(MachineState *machine) 929 { 930 const MemMapEntry *memmap = virt_memmap; 931 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 932 MemoryRegion *system_memory = get_system_memory(); 933 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 934 char *soc_name; 935 target_ulong start_addr = memmap[VIRT_DRAM].base; 936 target_ulong firmware_end_addr, kernel_start_addr; 937 uint32_t fdt_load_addr; 938 uint64_t kernel_entry; 939 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 940 int i, base_hartid, hart_count; 941 942 /* Check socket count limit */ 943 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 944 error_report("number of sockets/nodes should be less than %d", 945 VIRT_SOCKETS_MAX); 946 exit(1); 947 } 948 949 /* Initialize sockets */ 950 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 951 for (i = 0; i < riscv_socket_count(machine); i++) { 952 if (!riscv_socket_check_hartids(machine, i)) { 953 error_report("discontinuous hartids in socket%d", i); 954 exit(1); 955 } 956 957 base_hartid = riscv_socket_first_hartid(machine, i); 958 if (base_hartid < 0) { 959 error_report("can't find hartid base for socket%d", i); 960 exit(1); 961 } 962 963 hart_count = riscv_socket_hart_count(machine, i); 964 if (hart_count < 0) { 965 error_report("can't find hart count for socket%d", i); 966 exit(1); 967 } 968 969 soc_name = g_strdup_printf("soc%d", i); 970 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 971 TYPE_RISCV_HART_ARRAY); 972 g_free(soc_name); 973 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 974 machine->cpu_type, &error_abort); 975 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 976 base_hartid, &error_abort); 977 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 978 hart_count, &error_abort); 979 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 980 981 if (!kvm_enabled()) { 982 /* Per-socket CLINT */ 983 riscv_aclint_swi_create( 984 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 985 base_hartid, hart_count, false); 986 riscv_aclint_mtimer_create( 987 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size + 988 RISCV_ACLINT_SWI_SIZE, 989 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 990 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 991 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 992 993 /* Per-socket ACLINT SSWI */ 994 if (s->have_aclint) { 995 riscv_aclint_swi_create( 996 memmap[VIRT_ACLINT_SSWI].base + 997 i * memmap[VIRT_ACLINT_SSWI].size, 998 base_hartid, hart_count, true); 999 } 1000 } 1001 1002 /* Per-socket interrupt controller */ 1003 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1004 s->irqchip[i] = virt_create_plic(memmap, i, 1005 base_hartid, hart_count); 1006 } else { 1007 s->irqchip[i] = virt_create_aia(s->aia_type, memmap, i, 1008 base_hartid, hart_count); 1009 } 1010 1011 /* Try to use different IRQCHIP instance based device type */ 1012 if (i == 0) { 1013 mmio_irqchip = s->irqchip[i]; 1014 virtio_irqchip = s->irqchip[i]; 1015 pcie_irqchip = s->irqchip[i]; 1016 } 1017 if (i == 1) { 1018 virtio_irqchip = s->irqchip[i]; 1019 pcie_irqchip = s->irqchip[i]; 1020 } 1021 if (i == 2) { 1022 pcie_irqchip = s->irqchip[i]; 1023 } 1024 } 1025 1026 if (riscv_is_32bit(&s->soc[0])) { 1027 #if HOST_LONG_BITS == 64 1028 /* limit RAM size in a 32-bit system */ 1029 if (machine->ram_size > 10 * GiB) { 1030 machine->ram_size = 10 * GiB; 1031 error_report("Limiting RAM size to 10 GiB"); 1032 } 1033 #endif 1034 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1035 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1036 } else { 1037 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1038 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1039 virt_high_pcie_memmap.base = 1040 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1041 } 1042 1043 /* register system main memory (actual RAM) */ 1044 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1045 machine->ram); 1046 1047 /* create device tree */ 1048 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 1049 riscv_is_32bit(&s->soc[0])); 1050 1051 /* boot rom */ 1052 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1053 memmap[VIRT_MROM].size, &error_fatal); 1054 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1055 mask_rom); 1056 1057 /* 1058 * Only direct boot kernel is currently supported for KVM VM, 1059 * so the "-bios" parameter is ignored and treated like "-bios none" 1060 * when KVM is enabled. 1061 */ 1062 if (kvm_enabled()) { 1063 g_free(machine->firmware); 1064 machine->firmware = g_strdup("none"); 1065 } 1066 1067 if (riscv_is_32bit(&s->soc[0])) { 1068 firmware_end_addr = riscv_find_and_load_firmware(machine, 1069 RISCV32_BIOS_BIN, start_addr, NULL); 1070 } else { 1071 firmware_end_addr = riscv_find_and_load_firmware(machine, 1072 RISCV64_BIOS_BIN, start_addr, NULL); 1073 } 1074 1075 if (machine->kernel_filename) { 1076 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1077 firmware_end_addr); 1078 1079 kernel_entry = riscv_load_kernel(machine->kernel_filename, 1080 kernel_start_addr, NULL); 1081 1082 if (machine->initrd_filename) { 1083 hwaddr start; 1084 hwaddr end = riscv_load_initrd(machine->initrd_filename, 1085 machine->ram_size, kernel_entry, 1086 &start); 1087 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 1088 "linux,initrd-start", start); 1089 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 1090 end); 1091 } 1092 } else { 1093 /* 1094 * If dynamic firmware is used, it doesn't know where is the next mode 1095 * if kernel argument is not set. 1096 */ 1097 kernel_entry = 0; 1098 } 1099 1100 if (drive_get(IF_PFLASH, 0, 0)) { 1101 /* 1102 * Pflash was supplied, let's overwrite the address we jump to after 1103 * reset to the base of the flash. 1104 */ 1105 start_addr = virt_memmap[VIRT_FLASH].base; 1106 } 1107 1108 /* 1109 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 1110 * tree cannot be altered and we get FDT_ERR_NOSPACE. 1111 */ 1112 s->fw_cfg = create_fw_cfg(machine); 1113 rom_set_fw(s->fw_cfg); 1114 1115 /* Compute the fdt load address in dram */ 1116 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 1117 machine->ram_size, machine->fdt); 1118 /* load the reset vector */ 1119 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1120 virt_memmap[VIRT_MROM].base, 1121 virt_memmap[VIRT_MROM].size, kernel_entry, 1122 fdt_load_addr, machine->fdt); 1123 1124 /* 1125 * Only direct boot kernel is currently supported for KVM VM, 1126 * So here setup kernel start address and fdt address. 1127 * TODO:Support firmware loading and integrate to TCG start 1128 */ 1129 if (kvm_enabled()) { 1130 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1131 } 1132 1133 /* SiFive Test MMIO device */ 1134 sifive_test_create(memmap[VIRT_TEST].base); 1135 1136 /* VirtIO MMIO devices */ 1137 for (i = 0; i < VIRTIO_COUNT; i++) { 1138 sysbus_create_simple("virtio-mmio", 1139 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1140 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); 1141 } 1142 1143 gpex_pcie_init(system_memory, 1144 memmap[VIRT_PCIE_ECAM].base, 1145 memmap[VIRT_PCIE_ECAM].size, 1146 memmap[VIRT_PCIE_MMIO].base, 1147 memmap[VIRT_PCIE_MMIO].size, 1148 virt_high_pcie_memmap.base, 1149 virt_high_pcie_memmap.size, 1150 memmap[VIRT_PCIE_PIO].base, 1151 DEVICE(pcie_irqchip)); 1152 1153 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1154 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, 1155 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1156 1157 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1158 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); 1159 1160 virt_flash_create(s); 1161 1162 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1163 /* Map legacy -drive if=pflash to machine properties */ 1164 pflash_cfi01_legacy_drive(s->flash[i], 1165 drive_get(IF_PFLASH, 0, i)); 1166 } 1167 virt_flash_map(s, system_memory); 1168 } 1169 1170 static void virt_machine_instance_init(Object *obj) 1171 { 1172 } 1173 1174 static char *virt_get_aia(Object *obj, Error **errp) 1175 { 1176 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1177 const char *val; 1178 1179 switch (s->aia_type) { 1180 case VIRT_AIA_TYPE_APLIC: 1181 val = "aplic"; 1182 break; 1183 default: 1184 val = "none"; 1185 break; 1186 }; 1187 1188 return g_strdup(val); 1189 } 1190 1191 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1192 { 1193 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1194 1195 if (!strcmp(val, "none")) { 1196 s->aia_type = VIRT_AIA_TYPE_NONE; 1197 } else if (!strcmp(val, "aplic")) { 1198 s->aia_type = VIRT_AIA_TYPE_APLIC; 1199 } else { 1200 error_setg(errp, "Invalid AIA interrupt controller type"); 1201 error_append_hint(errp, "Valid values are none, and aplic.\n"); 1202 } 1203 } 1204 1205 static bool virt_get_aclint(Object *obj, Error **errp) 1206 { 1207 MachineState *ms = MACHINE(obj); 1208 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1209 1210 return s->have_aclint; 1211 } 1212 1213 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1214 { 1215 MachineState *ms = MACHINE(obj); 1216 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1217 1218 s->have_aclint = value; 1219 } 1220 1221 static void virt_machine_class_init(ObjectClass *oc, void *data) 1222 { 1223 MachineClass *mc = MACHINE_CLASS(oc); 1224 1225 mc->desc = "RISC-V VirtIO board"; 1226 mc->init = virt_machine_init; 1227 mc->max_cpus = VIRT_CPUS_MAX; 1228 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1229 mc->pci_allow_0_address = true; 1230 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1231 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1232 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1233 mc->numa_mem_supported = true; 1234 mc->default_ram_id = "riscv_virt_board.ram"; 1235 1236 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1237 1238 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1239 virt_set_aclint); 1240 object_class_property_set_description(oc, "aclint", 1241 "Set on/off to enable/disable " 1242 "emulating ACLINT devices"); 1243 1244 object_class_property_add_str(oc, "aia", virt_get_aia, 1245 virt_set_aia); 1246 object_class_property_set_description(oc, "aia", 1247 "Set type of AIA interrupt " 1248 "conttoller. Valid values are " 1249 "none, and aplic."); 1250 } 1251 1252 static const TypeInfo virt_machine_typeinfo = { 1253 .name = MACHINE_TYPE_NAME("virt"), 1254 .parent = TYPE_MACHINE, 1255 .class_init = virt_machine_class_init, 1256 .instance_init = virt_machine_instance_init, 1257 .instance_size = sizeof(RISCVVirtState), 1258 }; 1259 1260 static void virt_machine_init_register_types(void) 1261 { 1262 type_register_static(&virt_machine_typeinfo); 1263 } 1264 1265 type_init(virt_machine_init_register_types) 1266