1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "hw/intc/riscv_aclint.h" 39 #include "hw/intc/riscv_aplic.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "hw/intc/sifive_plic.h" 42 #include "hw/misc/sifive_test.h" 43 #include "hw/platform-bus.h" 44 #include "chardev/char.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/tcg.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/tpm.h" 50 #include "hw/pci/pci.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/display/ramfb.h" 53 #include "hw/acpi/aml-build.h" 54 #include "qapi/qapi-visit-common.h" 55 56 /* 57 * The virt machine physical address space used by some of the devices 58 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 59 * number of CPUs, and number of IMSIC guest files. 60 * 61 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 62 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 63 * of virt machine physical address space. 64 */ 65 66 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 67 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 68 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 69 #error "Can't accommodate single IMSIC group in address space" 70 #endif 71 72 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 73 VIRT_IMSIC_GROUP_MAX_SIZE) 74 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 75 #error "Can't accommodate all IMSIC groups in address space" 76 #endif 77 78 static const MemMapEntry virt_memmap[] = { 79 [VIRT_DEBUG] = { 0x0, 0x100 }, 80 [VIRT_MROM] = { 0x1000, 0xf000 }, 81 [VIRT_TEST] = { 0x100000, 0x1000 }, 82 [VIRT_RTC] = { 0x101000, 0x1000 }, 83 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 84 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 85 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 86 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 87 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 88 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 89 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 90 [VIRT_UART0] = { 0x10000000, 0x100 }, 91 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 92 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 93 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 94 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 95 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 96 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 97 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 98 [VIRT_DRAM] = { 0x80000000, 0x0 }, 99 }; 100 101 /* PCIe high mmio is fixed for RV32 */ 102 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 103 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 104 105 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 106 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 107 108 static MemMapEntry virt_high_pcie_memmap; 109 110 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 111 112 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 113 const char *name, 114 const char *alias_prop_name) 115 { 116 /* 117 * Create a single flash device. We use the same parameters as 118 * the flash devices on the ARM virt board. 119 */ 120 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 121 122 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 123 qdev_prop_set_uint8(dev, "width", 4); 124 qdev_prop_set_uint8(dev, "device-width", 2); 125 qdev_prop_set_bit(dev, "big-endian", false); 126 qdev_prop_set_uint16(dev, "id0", 0x89); 127 qdev_prop_set_uint16(dev, "id1", 0x18); 128 qdev_prop_set_uint16(dev, "id2", 0x00); 129 qdev_prop_set_uint16(dev, "id3", 0x00); 130 qdev_prop_set_string(dev, "name", name); 131 132 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 133 object_property_add_alias(OBJECT(s), alias_prop_name, 134 OBJECT(dev), "drive"); 135 136 return PFLASH_CFI01(dev); 137 } 138 139 static void virt_flash_create(RISCVVirtState *s) 140 { 141 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 142 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 143 } 144 145 static void virt_flash_map1(PFlashCFI01 *flash, 146 hwaddr base, hwaddr size, 147 MemoryRegion *sysmem) 148 { 149 DeviceState *dev = DEVICE(flash); 150 151 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 152 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 153 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 154 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 155 156 memory_region_add_subregion(sysmem, base, 157 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 158 0)); 159 } 160 161 static void virt_flash_map(RISCVVirtState *s, 162 MemoryRegion *sysmem) 163 { 164 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 165 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 166 167 virt_flash_map1(s->flash[0], flashbase, flashsize, 168 sysmem); 169 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 170 sysmem); 171 } 172 173 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 174 uint32_t irqchip_phandle) 175 { 176 int pin, dev; 177 uint32_t irq_map_stride = 0; 178 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 179 FDT_MAX_INT_MAP_WIDTH] = {}; 180 uint32_t *irq_map = full_irq_map; 181 182 /* This code creates a standard swizzle of interrupts such that 183 * each device's first interrupt is based on it's PCI_SLOT number. 184 * (See pci_swizzle_map_irq_fn()) 185 * 186 * We only need one entry per interrupt in the table (not one per 187 * possible slot) seeing the interrupt-map-mask will allow the table 188 * to wrap to any number of devices. 189 */ 190 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 191 int devfn = dev * 0x8; 192 193 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 194 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 195 int i = 0; 196 197 /* Fill PCI address cells */ 198 irq_map[i] = cpu_to_be32(devfn << 8); 199 i += FDT_PCI_ADDR_CELLS; 200 201 /* Fill PCI Interrupt cells */ 202 irq_map[i] = cpu_to_be32(pin + 1); 203 i += FDT_PCI_INT_CELLS; 204 205 /* Fill interrupt controller phandle and cells */ 206 irq_map[i++] = cpu_to_be32(irqchip_phandle); 207 irq_map[i++] = cpu_to_be32(irq_nr); 208 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 209 irq_map[i++] = cpu_to_be32(0x4); 210 } 211 212 if (!irq_map_stride) { 213 irq_map_stride = i; 214 } 215 irq_map += irq_map_stride; 216 } 217 } 218 219 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 220 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 221 irq_map_stride * sizeof(uint32_t)); 222 223 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 224 0x1800, 0, 0, 0x7); 225 } 226 227 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 228 char *clust_name, uint32_t *phandle, 229 uint32_t *intc_phandles) 230 { 231 int cpu; 232 uint32_t cpu_phandle; 233 MachineState *ms = MACHINE(s); 234 char *name, *cpu_name, *core_name, *intc_name, *sv_name; 235 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 236 uint8_t satp_mode_max; 237 238 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 239 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 240 241 cpu_phandle = (*phandle)++; 242 243 cpu_name = g_strdup_printf("/cpus/cpu@%d", 244 s->soc[socket].hartid_base + cpu); 245 qemu_fdt_add_subnode(ms->fdt, cpu_name); 246 247 if (cpu_ptr->cfg.satp_mode.supported != 0) { 248 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 249 sv_name = g_strdup_printf("riscv,%s", 250 satp_mode_str(satp_mode_max, is_32_bit)); 251 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 252 g_free(sv_name); 253 } 254 255 name = riscv_isa_string(cpu_ptr); 256 qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); 257 g_free(name); 258 259 if (cpu_ptr->cfg.ext_icbom) { 260 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 261 cpu_ptr->cfg.cbom_blocksize); 262 } 263 264 if (cpu_ptr->cfg.ext_icboz) { 265 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 266 cpu_ptr->cfg.cboz_blocksize); 267 } 268 269 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 270 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 271 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 272 s->soc[socket].hartid_base + cpu); 273 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 274 riscv_socket_fdt_write_id(ms, cpu_name, socket); 275 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 276 277 intc_phandles[cpu] = (*phandle)++; 278 279 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 280 qemu_fdt_add_subnode(ms->fdt, intc_name); 281 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 282 intc_phandles[cpu]); 283 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 284 "riscv,cpu-intc"); 285 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 286 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 287 288 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 289 qemu_fdt_add_subnode(ms->fdt, core_name); 290 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 291 292 g_free(core_name); 293 g_free(intc_name); 294 g_free(cpu_name); 295 } 296 } 297 298 static void create_fdt_socket_memory(RISCVVirtState *s, 299 const MemMapEntry *memmap, int socket) 300 { 301 char *mem_name; 302 uint64_t addr, size; 303 MachineState *ms = MACHINE(s); 304 305 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 306 size = riscv_socket_mem_size(ms, socket); 307 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 308 qemu_fdt_add_subnode(ms->fdt, mem_name); 309 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 310 addr >> 32, addr, size >> 32, size); 311 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 312 riscv_socket_fdt_write_id(ms, mem_name, socket); 313 g_free(mem_name); 314 } 315 316 static void create_fdt_socket_clint(RISCVVirtState *s, 317 const MemMapEntry *memmap, int socket, 318 uint32_t *intc_phandles) 319 { 320 int cpu; 321 char *clint_name; 322 uint32_t *clint_cells; 323 unsigned long clint_addr; 324 MachineState *ms = MACHINE(s); 325 static const char * const clint_compat[2] = { 326 "sifive,clint0", "riscv,clint0" 327 }; 328 329 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 330 331 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 332 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 333 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 334 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 335 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 336 } 337 338 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 339 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 340 qemu_fdt_add_subnode(ms->fdt, clint_name); 341 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 342 (char **)&clint_compat, 343 ARRAY_SIZE(clint_compat)); 344 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 345 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 346 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 347 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 348 riscv_socket_fdt_write_id(ms, clint_name, socket); 349 g_free(clint_name); 350 351 g_free(clint_cells); 352 } 353 354 static void create_fdt_socket_aclint(RISCVVirtState *s, 355 const MemMapEntry *memmap, int socket, 356 uint32_t *intc_phandles) 357 { 358 int cpu; 359 char *name; 360 unsigned long addr, size; 361 uint32_t aclint_cells_size; 362 uint32_t *aclint_mswi_cells; 363 uint32_t *aclint_sswi_cells; 364 uint32_t *aclint_mtimer_cells; 365 MachineState *ms = MACHINE(s); 366 367 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 368 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 369 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 370 371 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 372 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 373 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 374 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 375 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 376 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 377 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 378 } 379 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 380 381 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 382 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 383 name = g_strdup_printf("/soc/mswi@%lx", addr); 384 qemu_fdt_add_subnode(ms->fdt, name); 385 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 386 "riscv,aclint-mswi"); 387 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 388 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 389 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 390 aclint_mswi_cells, aclint_cells_size); 391 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 392 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 393 riscv_socket_fdt_write_id(ms, name, socket); 394 g_free(name); 395 } 396 397 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 398 addr = memmap[VIRT_CLINT].base + 399 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 400 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 401 } else { 402 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 403 (memmap[VIRT_CLINT].size * socket); 404 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 405 } 406 name = g_strdup_printf("/soc/mtimer@%lx", addr); 407 qemu_fdt_add_subnode(ms->fdt, name); 408 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 409 "riscv,aclint-mtimer"); 410 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 411 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 412 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 413 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 414 0x0, RISCV_ACLINT_DEFAULT_MTIME); 415 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 416 aclint_mtimer_cells, aclint_cells_size); 417 riscv_socket_fdt_write_id(ms, name, socket); 418 g_free(name); 419 420 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 421 addr = memmap[VIRT_ACLINT_SSWI].base + 422 (memmap[VIRT_ACLINT_SSWI].size * socket); 423 name = g_strdup_printf("/soc/sswi@%lx", addr); 424 qemu_fdt_add_subnode(ms->fdt, name); 425 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 426 "riscv,aclint-sswi"); 427 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 428 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 429 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 430 aclint_sswi_cells, aclint_cells_size); 431 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 432 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 433 riscv_socket_fdt_write_id(ms, name, socket); 434 g_free(name); 435 } 436 437 g_free(aclint_mswi_cells); 438 g_free(aclint_mtimer_cells); 439 g_free(aclint_sswi_cells); 440 } 441 442 static void create_fdt_socket_plic(RISCVVirtState *s, 443 const MemMapEntry *memmap, int socket, 444 uint32_t *phandle, uint32_t *intc_phandles, 445 uint32_t *plic_phandles) 446 { 447 int cpu; 448 char *plic_name; 449 uint32_t *plic_cells; 450 unsigned long plic_addr; 451 MachineState *ms = MACHINE(s); 452 static const char * const plic_compat[2] = { 453 "sifive,plic-1.0.0", "riscv,plic0" 454 }; 455 456 if (kvm_enabled()) { 457 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 458 } else { 459 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 460 } 461 462 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 463 if (kvm_enabled()) { 464 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 465 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 466 } else { 467 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 468 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 469 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 470 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 471 } 472 } 473 474 plic_phandles[socket] = (*phandle)++; 475 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 476 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 477 qemu_fdt_add_subnode(ms->fdt, plic_name); 478 qemu_fdt_setprop_cell(ms->fdt, plic_name, 479 "#interrupt-cells", FDT_PLIC_INT_CELLS); 480 qemu_fdt_setprop_cell(ms->fdt, plic_name, 481 "#address-cells", FDT_PLIC_ADDR_CELLS); 482 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 483 (char **)&plic_compat, 484 ARRAY_SIZE(plic_compat)); 485 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 486 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 487 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 488 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 489 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 490 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 491 VIRT_IRQCHIP_NUM_SOURCES - 1); 492 riscv_socket_fdt_write_id(ms, plic_name, socket); 493 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 494 plic_phandles[socket]); 495 496 if (!socket) { 497 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 498 memmap[VIRT_PLATFORM_BUS].base, 499 memmap[VIRT_PLATFORM_BUS].size, 500 VIRT_PLATFORM_BUS_IRQ); 501 } 502 503 g_free(plic_name); 504 505 g_free(plic_cells); 506 } 507 508 static uint32_t imsic_num_bits(uint32_t count) 509 { 510 uint32_t ret = 0; 511 512 while (BIT(ret) < count) { 513 ret++; 514 } 515 516 return ret; 517 } 518 519 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 520 uint32_t *intc_phandles, uint32_t msi_phandle, 521 bool m_mode, uint32_t imsic_guest_bits) 522 { 523 int cpu, socket; 524 char *imsic_name; 525 MachineState *ms = MACHINE(s); 526 int socket_count = riscv_socket_count(ms); 527 uint32_t imsic_max_hart_per_socket; 528 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 529 530 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 531 imsic_regs = g_new0(uint32_t, socket_count * 4); 532 533 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 534 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 535 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 536 } 537 538 imsic_max_hart_per_socket = 0; 539 for (socket = 0; socket < socket_count; socket++) { 540 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 541 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 542 s->soc[socket].num_harts; 543 imsic_regs[socket * 4 + 0] = 0; 544 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 545 imsic_regs[socket * 4 + 2] = 0; 546 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 547 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 548 imsic_max_hart_per_socket = s->soc[socket].num_harts; 549 } 550 } 551 552 imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr); 553 qemu_fdt_add_subnode(ms->fdt, imsic_name); 554 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); 555 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 556 FDT_IMSIC_INT_CELLS); 557 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 558 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 559 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 560 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 561 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 562 socket_count * sizeof(uint32_t) * 4); 563 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 564 VIRT_IRQCHIP_NUM_MSIS); 565 566 if (imsic_guest_bits) { 567 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 568 imsic_guest_bits); 569 } 570 571 if (socket_count > 1) { 572 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 573 imsic_num_bits(imsic_max_hart_per_socket)); 574 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 575 imsic_num_bits(socket_count)); 576 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 577 IMSIC_MMIO_GROUP_MIN_SHIFT); 578 } 579 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 580 581 g_free(imsic_name); 582 g_free(imsic_regs); 583 g_free(imsic_cells); 584 } 585 586 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 587 uint32_t *phandle, uint32_t *intc_phandles, 588 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 589 { 590 *msi_m_phandle = (*phandle)++; 591 *msi_s_phandle = (*phandle)++; 592 593 if (!kvm_enabled()) { 594 /* M-level IMSIC node */ 595 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 596 *msi_m_phandle, true, 0); 597 } 598 599 /* S-level IMSIC node */ 600 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 601 *msi_s_phandle, false, 602 imsic_num_bits(s->aia_guests + 1)); 603 604 } 605 606 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 607 unsigned long aplic_addr, uint32_t aplic_size, 608 uint32_t msi_phandle, 609 uint32_t *intc_phandles, 610 uint32_t aplic_phandle, 611 uint32_t aplic_child_phandle, 612 bool m_mode) 613 { 614 int cpu; 615 char *aplic_name; 616 uint32_t *aplic_cells; 617 MachineState *ms = MACHINE(s); 618 619 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 620 621 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 622 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 623 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 624 } 625 626 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 627 qemu_fdt_add_subnode(ms->fdt, aplic_name); 628 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); 629 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 630 "#interrupt-cells", FDT_APLIC_INT_CELLS); 631 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 632 633 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 634 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 635 aplic_cells, 636 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 637 } else { 638 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 639 } 640 641 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 642 0x0, aplic_addr, 0x0, aplic_size); 643 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 644 VIRT_IRQCHIP_NUM_SOURCES); 645 646 if (aplic_child_phandle) { 647 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 648 aplic_child_phandle); 649 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 650 aplic_child_phandle, 0x1, 651 VIRT_IRQCHIP_NUM_SOURCES); 652 } 653 654 riscv_socket_fdt_write_id(ms, aplic_name, socket); 655 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 656 657 g_free(aplic_name); 658 g_free(aplic_cells); 659 } 660 661 static void create_fdt_socket_aplic(RISCVVirtState *s, 662 const MemMapEntry *memmap, int socket, 663 uint32_t msi_m_phandle, 664 uint32_t msi_s_phandle, 665 uint32_t *phandle, 666 uint32_t *intc_phandles, 667 uint32_t *aplic_phandles) 668 { 669 char *aplic_name; 670 unsigned long aplic_addr; 671 MachineState *ms = MACHINE(s); 672 uint32_t aplic_m_phandle, aplic_s_phandle; 673 674 aplic_m_phandle = (*phandle)++; 675 aplic_s_phandle = (*phandle)++; 676 677 if (!kvm_enabled()) { 678 /* M-level APLIC node */ 679 aplic_addr = memmap[VIRT_APLIC_M].base + 680 (memmap[VIRT_APLIC_M].size * socket); 681 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 682 msi_m_phandle, intc_phandles, 683 aplic_m_phandle, aplic_s_phandle, 684 true); 685 } 686 687 /* S-level APLIC node */ 688 aplic_addr = memmap[VIRT_APLIC_S].base + 689 (memmap[VIRT_APLIC_S].size * socket); 690 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 691 msi_s_phandle, intc_phandles, 692 aplic_s_phandle, 0, 693 false); 694 695 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 696 697 if (!socket) { 698 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 699 memmap[VIRT_PLATFORM_BUS].base, 700 memmap[VIRT_PLATFORM_BUS].size, 701 VIRT_PLATFORM_BUS_IRQ); 702 } 703 704 g_free(aplic_name); 705 706 aplic_phandles[socket] = aplic_s_phandle; 707 } 708 709 static void create_fdt_pmu(RISCVVirtState *s) 710 { 711 char *pmu_name; 712 MachineState *ms = MACHINE(s); 713 RISCVCPU hart = s->soc[0].harts[0]; 714 715 pmu_name = g_strdup_printf("/soc/pmu"); 716 qemu_fdt_add_subnode(ms->fdt, pmu_name); 717 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 718 riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); 719 720 g_free(pmu_name); 721 } 722 723 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 724 uint32_t *phandle, 725 uint32_t *irq_mmio_phandle, 726 uint32_t *irq_pcie_phandle, 727 uint32_t *irq_virtio_phandle, 728 uint32_t *msi_pcie_phandle) 729 { 730 char *clust_name; 731 int socket, phandle_pos; 732 MachineState *ms = MACHINE(s); 733 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 734 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 735 int socket_count = riscv_socket_count(ms); 736 737 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 738 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 739 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 740 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 741 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 742 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 743 744 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 745 746 phandle_pos = ms->smp.cpus; 747 for (socket = (socket_count - 1); socket >= 0; socket--) { 748 phandle_pos -= s->soc[socket].num_harts; 749 750 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 751 qemu_fdt_add_subnode(ms->fdt, clust_name); 752 753 create_fdt_socket_cpus(s, socket, clust_name, phandle, 754 &intc_phandles[phandle_pos]); 755 756 create_fdt_socket_memory(s, memmap, socket); 757 758 g_free(clust_name); 759 760 if (tcg_enabled()) { 761 if (s->have_aclint) { 762 create_fdt_socket_aclint(s, memmap, socket, 763 &intc_phandles[phandle_pos]); 764 } else { 765 create_fdt_socket_clint(s, memmap, socket, 766 &intc_phandles[phandle_pos]); 767 } 768 } 769 } 770 771 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 772 create_fdt_imsic(s, memmap, phandle, intc_phandles, 773 &msi_m_phandle, &msi_s_phandle); 774 *msi_pcie_phandle = msi_s_phandle; 775 } 776 777 phandle_pos = ms->smp.cpus; 778 for (socket = (socket_count - 1); socket >= 0; socket--) { 779 phandle_pos -= s->soc[socket].num_harts; 780 781 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 782 create_fdt_socket_plic(s, memmap, socket, phandle, 783 &intc_phandles[phandle_pos], xplic_phandles); 784 } else { 785 create_fdt_socket_aplic(s, memmap, socket, 786 msi_m_phandle, msi_s_phandle, phandle, 787 &intc_phandles[phandle_pos], xplic_phandles); 788 } 789 } 790 791 g_free(intc_phandles); 792 793 for (socket = 0; socket < socket_count; socket++) { 794 if (socket == 0) { 795 *irq_mmio_phandle = xplic_phandles[socket]; 796 *irq_virtio_phandle = xplic_phandles[socket]; 797 *irq_pcie_phandle = xplic_phandles[socket]; 798 } 799 if (socket == 1) { 800 *irq_virtio_phandle = xplic_phandles[socket]; 801 *irq_pcie_phandle = xplic_phandles[socket]; 802 } 803 if (socket == 2) { 804 *irq_pcie_phandle = xplic_phandles[socket]; 805 } 806 } 807 808 riscv_socket_fdt_write_distance_matrix(ms); 809 } 810 811 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 812 uint32_t irq_virtio_phandle) 813 { 814 int i; 815 char *name; 816 MachineState *ms = MACHINE(s); 817 818 for (i = 0; i < VIRTIO_COUNT; i++) { 819 name = g_strdup_printf("/soc/virtio_mmio@%lx", 820 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 821 qemu_fdt_add_subnode(ms->fdt, name); 822 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 823 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 824 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 825 0x0, memmap[VIRT_VIRTIO].size); 826 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 827 irq_virtio_phandle); 828 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 829 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 830 VIRTIO_IRQ + i); 831 } else { 832 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 833 VIRTIO_IRQ + i, 0x4); 834 } 835 g_free(name); 836 } 837 } 838 839 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 840 uint32_t irq_pcie_phandle, 841 uint32_t msi_pcie_phandle) 842 { 843 char *name; 844 MachineState *ms = MACHINE(s); 845 846 name = g_strdup_printf("/soc/pci@%lx", 847 (long) memmap[VIRT_PCIE_ECAM].base); 848 qemu_fdt_add_subnode(ms->fdt, name); 849 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 850 FDT_PCI_ADDR_CELLS); 851 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 852 FDT_PCI_INT_CELLS); 853 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 854 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 855 "pci-host-ecam-generic"); 856 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 857 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 858 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 859 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 860 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 861 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 862 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 863 } 864 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 865 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 866 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 867 1, FDT_PCI_RANGE_IOPORT, 2, 0, 868 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 869 1, FDT_PCI_RANGE_MMIO, 870 2, memmap[VIRT_PCIE_MMIO].base, 871 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 872 1, FDT_PCI_RANGE_MMIO_64BIT, 873 2, virt_high_pcie_memmap.base, 874 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 875 876 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 877 g_free(name); 878 } 879 880 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 881 uint32_t *phandle) 882 { 883 char *name; 884 uint32_t test_phandle; 885 MachineState *ms = MACHINE(s); 886 887 test_phandle = (*phandle)++; 888 name = g_strdup_printf("/soc/test@%lx", 889 (long)memmap[VIRT_TEST].base); 890 qemu_fdt_add_subnode(ms->fdt, name); 891 { 892 static const char * const compat[3] = { 893 "sifive,test1", "sifive,test0", "syscon" 894 }; 895 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 896 (char **)&compat, ARRAY_SIZE(compat)); 897 } 898 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 899 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 900 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 901 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 902 g_free(name); 903 904 name = g_strdup_printf("/reboot"); 905 qemu_fdt_add_subnode(ms->fdt, name); 906 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 907 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 908 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 909 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 910 g_free(name); 911 912 name = g_strdup_printf("/poweroff"); 913 qemu_fdt_add_subnode(ms->fdt, name); 914 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 915 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 916 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 917 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 918 g_free(name); 919 } 920 921 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 922 uint32_t irq_mmio_phandle) 923 { 924 char *name; 925 MachineState *ms = MACHINE(s); 926 927 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 928 qemu_fdt_add_subnode(ms->fdt, name); 929 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 930 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 931 0x0, memmap[VIRT_UART0].base, 932 0x0, memmap[VIRT_UART0].size); 933 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 934 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 935 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 936 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 937 } else { 938 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 939 } 940 941 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 942 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 943 g_free(name); 944 } 945 946 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 947 uint32_t irq_mmio_phandle) 948 { 949 char *name; 950 MachineState *ms = MACHINE(s); 951 952 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 953 qemu_fdt_add_subnode(ms->fdt, name); 954 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 955 "google,goldfish-rtc"); 956 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 957 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 958 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 959 irq_mmio_phandle); 960 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 961 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 962 } else { 963 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 964 } 965 g_free(name); 966 } 967 968 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 969 { 970 char *name; 971 MachineState *ms = MACHINE(s); 972 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 973 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 974 975 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 976 qemu_fdt_add_subnode(ms->fdt, name); 977 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 978 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 979 2, flashbase, 2, flashsize, 980 2, flashbase + flashsize, 2, flashsize); 981 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 982 g_free(name); 983 } 984 985 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 986 { 987 char *nodename; 988 MachineState *ms = MACHINE(s); 989 hwaddr base = memmap[VIRT_FW_CFG].base; 990 hwaddr size = memmap[VIRT_FW_CFG].size; 991 992 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 993 qemu_fdt_add_subnode(ms->fdt, nodename); 994 qemu_fdt_setprop_string(ms->fdt, nodename, 995 "compatible", "qemu,fw-cfg-mmio"); 996 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 997 2, base, 2, size); 998 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 999 g_free(nodename); 1000 } 1001 1002 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1003 { 1004 MachineState *ms = MACHINE(s); 1005 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1006 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1007 uint8_t rng_seed[32]; 1008 1009 ms->fdt = create_device_tree(&s->fdt_size); 1010 if (!ms->fdt) { 1011 error_report("create_device_tree() failed"); 1012 exit(1); 1013 } 1014 1015 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1016 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1017 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1018 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1019 1020 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1021 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1022 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1023 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1024 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1025 1026 create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, 1027 &irq_pcie_phandle, &irq_virtio_phandle, 1028 &msi_pcie_phandle); 1029 1030 create_fdt_virtio(s, memmap, irq_virtio_phandle); 1031 1032 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); 1033 1034 create_fdt_reset(s, memmap, &phandle); 1035 1036 create_fdt_uart(s, memmap, irq_mmio_phandle); 1037 1038 create_fdt_rtc(s, memmap, irq_mmio_phandle); 1039 1040 create_fdt_flash(s, memmap); 1041 create_fdt_fw_cfg(s, memmap); 1042 create_fdt_pmu(s); 1043 1044 /* Pass seed to RNG */ 1045 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1046 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1047 rng_seed, sizeof(rng_seed)); 1048 } 1049 1050 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1051 hwaddr ecam_base, hwaddr ecam_size, 1052 hwaddr mmio_base, hwaddr mmio_size, 1053 hwaddr high_mmio_base, 1054 hwaddr high_mmio_size, 1055 hwaddr pio_base, 1056 DeviceState *irqchip) 1057 { 1058 DeviceState *dev; 1059 MemoryRegion *ecam_alias, *ecam_reg; 1060 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1061 qemu_irq irq; 1062 int i; 1063 1064 dev = qdev_new(TYPE_GPEX_HOST); 1065 1066 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1067 1068 ecam_alias = g_new0(MemoryRegion, 1); 1069 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1070 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1071 ecam_reg, 0, ecam_size); 1072 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1073 1074 mmio_alias = g_new0(MemoryRegion, 1); 1075 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1076 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1077 mmio_reg, mmio_base, mmio_size); 1078 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1079 1080 /* Map high MMIO space */ 1081 high_mmio_alias = g_new0(MemoryRegion, 1); 1082 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1083 mmio_reg, high_mmio_base, high_mmio_size); 1084 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1085 high_mmio_alias); 1086 1087 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1088 1089 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1090 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1091 1092 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1093 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1094 } 1095 1096 return dev; 1097 } 1098 1099 static FWCfgState *create_fw_cfg(const MachineState *ms) 1100 { 1101 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1102 FWCfgState *fw_cfg; 1103 1104 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1105 &address_space_memory); 1106 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1107 1108 return fw_cfg; 1109 } 1110 1111 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1112 int base_hartid, int hart_count) 1113 { 1114 DeviceState *ret; 1115 char *plic_hart_config; 1116 1117 /* Per-socket PLIC hart topology configuration string */ 1118 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1119 1120 /* Per-socket PLIC */ 1121 ret = sifive_plic_create( 1122 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1123 plic_hart_config, hart_count, base_hartid, 1124 VIRT_IRQCHIP_NUM_SOURCES, 1125 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1126 VIRT_PLIC_PRIORITY_BASE, 1127 VIRT_PLIC_PENDING_BASE, 1128 VIRT_PLIC_ENABLE_BASE, 1129 VIRT_PLIC_ENABLE_STRIDE, 1130 VIRT_PLIC_CONTEXT_BASE, 1131 VIRT_PLIC_CONTEXT_STRIDE, 1132 memmap[VIRT_PLIC].size); 1133 1134 g_free(plic_hart_config); 1135 1136 return ret; 1137 } 1138 1139 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1140 const MemMapEntry *memmap, int socket, 1141 int base_hartid, int hart_count) 1142 { 1143 int i; 1144 hwaddr addr; 1145 uint32_t guest_bits; 1146 DeviceState *aplic_s = NULL; 1147 DeviceState *aplic_m = NULL; 1148 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1149 1150 if (msimode) { 1151 if (!kvm_enabled()) { 1152 /* Per-socket M-level IMSICs */ 1153 addr = memmap[VIRT_IMSIC_M].base + 1154 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1155 for (i = 0; i < hart_count; i++) { 1156 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1157 base_hartid + i, true, 1, 1158 VIRT_IRQCHIP_NUM_MSIS); 1159 } 1160 } 1161 1162 /* Per-socket S-level IMSICs */ 1163 guest_bits = imsic_num_bits(aia_guests + 1); 1164 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1165 for (i = 0; i < hart_count; i++) { 1166 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1167 base_hartid + i, false, 1 + aia_guests, 1168 VIRT_IRQCHIP_NUM_MSIS); 1169 } 1170 } 1171 1172 if (!kvm_enabled()) { 1173 /* Per-socket M-level APLIC */ 1174 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1175 socket * memmap[VIRT_APLIC_M].size, 1176 memmap[VIRT_APLIC_M].size, 1177 (msimode) ? 0 : base_hartid, 1178 (msimode) ? 0 : hart_count, 1179 VIRT_IRQCHIP_NUM_SOURCES, 1180 VIRT_IRQCHIP_NUM_PRIO_BITS, 1181 msimode, true, NULL); 1182 } 1183 1184 /* Per-socket S-level APLIC */ 1185 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1186 socket * memmap[VIRT_APLIC_S].size, 1187 memmap[VIRT_APLIC_S].size, 1188 (msimode) ? 0 : base_hartid, 1189 (msimode) ? 0 : hart_count, 1190 VIRT_IRQCHIP_NUM_SOURCES, 1191 VIRT_IRQCHIP_NUM_PRIO_BITS, 1192 msimode, false, aplic_m); 1193 1194 return kvm_enabled() ? aplic_s : aplic_m; 1195 } 1196 1197 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1198 { 1199 DeviceState *dev; 1200 SysBusDevice *sysbus; 1201 const MemMapEntry *memmap = virt_memmap; 1202 int i; 1203 MemoryRegion *sysmem = get_system_memory(); 1204 1205 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1206 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1207 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1208 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1209 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1210 s->platform_bus_dev = dev; 1211 1212 sysbus = SYS_BUS_DEVICE(dev); 1213 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1214 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1215 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1216 } 1217 1218 memory_region_add_subregion(sysmem, 1219 memmap[VIRT_PLATFORM_BUS].base, 1220 sysbus_mmio_get_region(sysbus, 0)); 1221 } 1222 1223 static void virt_machine_done(Notifier *notifier, void *data) 1224 { 1225 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1226 machine_done); 1227 const MemMapEntry *memmap = virt_memmap; 1228 MachineState *machine = MACHINE(s); 1229 target_ulong start_addr = memmap[VIRT_DRAM].base; 1230 target_ulong firmware_end_addr, kernel_start_addr; 1231 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1232 uint64_t fdt_load_addr; 1233 uint64_t kernel_entry = 0; 1234 BlockBackend *pflash_blk0; 1235 1236 /* load/create device tree */ 1237 if (machine->dtb) { 1238 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1239 if (!machine->fdt) { 1240 error_report("load_device_tree() failed"); 1241 exit(1); 1242 } 1243 } else { 1244 create_fdt(s, memmap); 1245 } 1246 1247 /* 1248 * Only direct boot kernel is currently supported for KVM VM, 1249 * so the "-bios" parameter is not supported when KVM is enabled. 1250 */ 1251 if (kvm_enabled()) { 1252 if (machine->firmware) { 1253 if (strcmp(machine->firmware, "none")) { 1254 error_report("Machine mode firmware is not supported in " 1255 "combination with KVM."); 1256 exit(1); 1257 } 1258 } else { 1259 machine->firmware = g_strdup("none"); 1260 } 1261 } 1262 1263 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1264 start_addr, NULL); 1265 1266 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1267 if (pflash_blk0) { 1268 if (machine->firmware && !strcmp(machine->firmware, "none") && 1269 !kvm_enabled()) { 1270 /* 1271 * Pflash was supplied but bios is none and not KVM guest, 1272 * let's overwrite the address we jump to after reset to 1273 * the base of the flash. 1274 */ 1275 start_addr = virt_memmap[VIRT_FLASH].base; 1276 } else { 1277 /* 1278 * Pflash was supplied but either KVM guest or bios is not none. 1279 * In this case, base of the flash would contain S-mode payload. 1280 */ 1281 riscv_setup_firmware_boot(machine); 1282 kernel_entry = virt_memmap[VIRT_FLASH].base; 1283 } 1284 } 1285 1286 if (machine->kernel_filename && !kernel_entry) { 1287 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1288 firmware_end_addr); 1289 1290 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1291 kernel_start_addr, true, NULL); 1292 } 1293 1294 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1295 memmap[VIRT_DRAM].size, 1296 machine); 1297 riscv_load_fdt(fdt_load_addr, machine->fdt); 1298 1299 /* load the reset vector */ 1300 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1301 virt_memmap[VIRT_MROM].base, 1302 virt_memmap[VIRT_MROM].size, kernel_entry, 1303 fdt_load_addr); 1304 1305 /* 1306 * Only direct boot kernel is currently supported for KVM VM, 1307 * So here setup kernel start address and fdt address. 1308 * TODO:Support firmware loading and integrate to TCG start 1309 */ 1310 if (kvm_enabled()) { 1311 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1312 } 1313 1314 if (virt_is_acpi_enabled(s)) { 1315 virt_acpi_setup(s); 1316 } 1317 } 1318 1319 static void virt_machine_init(MachineState *machine) 1320 { 1321 const MemMapEntry *memmap = virt_memmap; 1322 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1323 MemoryRegion *system_memory = get_system_memory(); 1324 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1325 char *soc_name; 1326 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1327 int i, base_hartid, hart_count; 1328 int socket_count = riscv_socket_count(machine); 1329 1330 /* Check socket count limit */ 1331 if (VIRT_SOCKETS_MAX < socket_count) { 1332 error_report("number of sockets/nodes should be less than %d", 1333 VIRT_SOCKETS_MAX); 1334 exit(1); 1335 } 1336 1337 if (!tcg_enabled() && s->have_aclint) { 1338 error_report("'aclint' is only available with TCG acceleration"); 1339 exit(1); 1340 } 1341 1342 /* Initialize sockets */ 1343 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1344 for (i = 0; i < socket_count; i++) { 1345 if (!riscv_socket_check_hartids(machine, i)) { 1346 error_report("discontinuous hartids in socket%d", i); 1347 exit(1); 1348 } 1349 1350 base_hartid = riscv_socket_first_hartid(machine, i); 1351 if (base_hartid < 0) { 1352 error_report("can't find hartid base for socket%d", i); 1353 exit(1); 1354 } 1355 1356 hart_count = riscv_socket_hart_count(machine, i); 1357 if (hart_count < 0) { 1358 error_report("can't find hart count for socket%d", i); 1359 exit(1); 1360 } 1361 1362 soc_name = g_strdup_printf("soc%d", i); 1363 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1364 TYPE_RISCV_HART_ARRAY); 1365 g_free(soc_name); 1366 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1367 machine->cpu_type, &error_abort); 1368 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1369 base_hartid, &error_abort); 1370 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1371 hart_count, &error_abort); 1372 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1373 1374 if (tcg_enabled()) { 1375 if (s->have_aclint) { 1376 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1377 /* Per-socket ACLINT MTIMER */ 1378 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1379 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1380 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1381 base_hartid, hart_count, 1382 RISCV_ACLINT_DEFAULT_MTIMECMP, 1383 RISCV_ACLINT_DEFAULT_MTIME, 1384 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1385 } else { 1386 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1387 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1388 i * memmap[VIRT_CLINT].size, 1389 base_hartid, hart_count, false); 1390 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1391 i * memmap[VIRT_CLINT].size + 1392 RISCV_ACLINT_SWI_SIZE, 1393 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1394 base_hartid, hart_count, 1395 RISCV_ACLINT_DEFAULT_MTIMECMP, 1396 RISCV_ACLINT_DEFAULT_MTIME, 1397 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1398 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1399 i * memmap[VIRT_ACLINT_SSWI].size, 1400 base_hartid, hart_count, true); 1401 } 1402 } else { 1403 /* Per-socket SiFive CLINT */ 1404 riscv_aclint_swi_create( 1405 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1406 base_hartid, hart_count, false); 1407 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1408 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1409 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1410 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1411 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1412 } 1413 } 1414 1415 /* Per-socket interrupt controller */ 1416 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1417 s->irqchip[i] = virt_create_plic(memmap, i, 1418 base_hartid, hart_count); 1419 } else { 1420 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1421 memmap, i, base_hartid, 1422 hart_count); 1423 } 1424 1425 /* Try to use different IRQCHIP instance based device type */ 1426 if (i == 0) { 1427 mmio_irqchip = s->irqchip[i]; 1428 virtio_irqchip = s->irqchip[i]; 1429 pcie_irqchip = s->irqchip[i]; 1430 } 1431 if (i == 1) { 1432 virtio_irqchip = s->irqchip[i]; 1433 pcie_irqchip = s->irqchip[i]; 1434 } 1435 if (i == 2) { 1436 pcie_irqchip = s->irqchip[i]; 1437 } 1438 } 1439 1440 if (riscv_is_32bit(&s->soc[0])) { 1441 #if HOST_LONG_BITS == 64 1442 /* limit RAM size in a 32-bit system */ 1443 if (machine->ram_size > 10 * GiB) { 1444 machine->ram_size = 10 * GiB; 1445 error_report("Limiting RAM size to 10 GiB"); 1446 } 1447 #endif 1448 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1449 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1450 } else { 1451 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1452 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1453 virt_high_pcie_memmap.base = 1454 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1455 } 1456 1457 s->memmap = virt_memmap; 1458 1459 /* register system main memory (actual RAM) */ 1460 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1461 machine->ram); 1462 1463 /* boot rom */ 1464 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1465 memmap[VIRT_MROM].size, &error_fatal); 1466 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1467 mask_rom); 1468 1469 /* 1470 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1471 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1472 */ 1473 s->fw_cfg = create_fw_cfg(machine); 1474 rom_set_fw(s->fw_cfg); 1475 1476 /* SiFive Test MMIO device */ 1477 sifive_test_create(memmap[VIRT_TEST].base); 1478 1479 /* VirtIO MMIO devices */ 1480 for (i = 0; i < VIRTIO_COUNT; i++) { 1481 sysbus_create_simple("virtio-mmio", 1482 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1483 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1484 } 1485 1486 gpex_pcie_init(system_memory, 1487 memmap[VIRT_PCIE_ECAM].base, 1488 memmap[VIRT_PCIE_ECAM].size, 1489 memmap[VIRT_PCIE_MMIO].base, 1490 memmap[VIRT_PCIE_MMIO].size, 1491 virt_high_pcie_memmap.base, 1492 virt_high_pcie_memmap.size, 1493 memmap[VIRT_PCIE_PIO].base, 1494 pcie_irqchip); 1495 1496 create_platform_bus(s, mmio_irqchip); 1497 1498 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1499 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1500 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1501 1502 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1503 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1504 1505 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1506 /* Map legacy -drive if=pflash to machine properties */ 1507 pflash_cfi01_legacy_drive(s->flash[i], 1508 drive_get(IF_PFLASH, 0, i)); 1509 } 1510 virt_flash_map(s, system_memory); 1511 1512 s->machine_done.notify = virt_machine_done; 1513 qemu_add_machine_init_done_notifier(&s->machine_done); 1514 } 1515 1516 static void virt_machine_instance_init(Object *obj) 1517 { 1518 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1519 1520 virt_flash_create(s); 1521 1522 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1523 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1524 s->acpi = ON_OFF_AUTO_AUTO; 1525 } 1526 1527 static char *virt_get_aia_guests(Object *obj, Error **errp) 1528 { 1529 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1530 char val[32]; 1531 1532 sprintf(val, "%d", s->aia_guests); 1533 return g_strdup(val); 1534 } 1535 1536 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1537 { 1538 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1539 1540 s->aia_guests = atoi(val); 1541 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1542 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1543 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1544 VIRT_IRQCHIP_MAX_GUESTS); 1545 } 1546 } 1547 1548 static char *virt_get_aia(Object *obj, Error **errp) 1549 { 1550 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1551 const char *val; 1552 1553 switch (s->aia_type) { 1554 case VIRT_AIA_TYPE_APLIC: 1555 val = "aplic"; 1556 break; 1557 case VIRT_AIA_TYPE_APLIC_IMSIC: 1558 val = "aplic-imsic"; 1559 break; 1560 default: 1561 val = "none"; 1562 break; 1563 }; 1564 1565 return g_strdup(val); 1566 } 1567 1568 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1569 { 1570 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1571 1572 if (!strcmp(val, "none")) { 1573 s->aia_type = VIRT_AIA_TYPE_NONE; 1574 } else if (!strcmp(val, "aplic")) { 1575 s->aia_type = VIRT_AIA_TYPE_APLIC; 1576 } else if (!strcmp(val, "aplic-imsic")) { 1577 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1578 } else { 1579 error_setg(errp, "Invalid AIA interrupt controller type"); 1580 error_append_hint(errp, "Valid values are none, aplic, and " 1581 "aplic-imsic.\n"); 1582 } 1583 } 1584 1585 static bool virt_get_aclint(Object *obj, Error **errp) 1586 { 1587 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1588 1589 return s->have_aclint; 1590 } 1591 1592 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1593 { 1594 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1595 1596 s->have_aclint = value; 1597 } 1598 1599 bool virt_is_acpi_enabled(RISCVVirtState *s) 1600 { 1601 return s->acpi != ON_OFF_AUTO_OFF; 1602 } 1603 1604 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1605 void *opaque, Error **errp) 1606 { 1607 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1608 OnOffAuto acpi = s->acpi; 1609 1610 visit_type_OnOffAuto(v, name, &acpi, errp); 1611 } 1612 1613 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1614 void *opaque, Error **errp) 1615 { 1616 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1617 1618 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1619 } 1620 1621 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1622 DeviceState *dev) 1623 { 1624 MachineClass *mc = MACHINE_GET_CLASS(machine); 1625 1626 if (device_is_dynamic_sysbus(mc, dev)) { 1627 return HOTPLUG_HANDLER(machine); 1628 } 1629 return NULL; 1630 } 1631 1632 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1633 DeviceState *dev, Error **errp) 1634 { 1635 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1636 1637 if (s->platform_bus_dev) { 1638 MachineClass *mc = MACHINE_GET_CLASS(s); 1639 1640 if (device_is_dynamic_sysbus(mc, dev)) { 1641 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1642 SYS_BUS_DEVICE(dev)); 1643 } 1644 } 1645 } 1646 1647 static void virt_machine_class_init(ObjectClass *oc, void *data) 1648 { 1649 char str[128]; 1650 MachineClass *mc = MACHINE_CLASS(oc); 1651 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1652 1653 mc->desc = "RISC-V VirtIO board"; 1654 mc->init = virt_machine_init; 1655 mc->max_cpus = VIRT_CPUS_MAX; 1656 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1657 mc->pci_allow_0_address = true; 1658 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1659 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1660 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1661 mc->numa_mem_supported = true; 1662 /* platform instead of architectural choice */ 1663 mc->cpu_cluster_has_numa_boundary = true; 1664 mc->default_ram_id = "riscv_virt_board.ram"; 1665 assert(!mc->get_hotplug_handler); 1666 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1667 1668 hc->plug = virt_machine_device_plug_cb; 1669 1670 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1671 #ifdef CONFIG_TPM 1672 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1673 #endif 1674 1675 1676 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1677 virt_set_aclint); 1678 object_class_property_set_description(oc, "aclint", 1679 "(TCG only) Set on/off to " 1680 "enable/disable emulating " 1681 "ACLINT devices"); 1682 1683 object_class_property_add_str(oc, "aia", virt_get_aia, 1684 virt_set_aia); 1685 object_class_property_set_description(oc, "aia", 1686 "Set type of AIA interrupt " 1687 "controller. Valid values are " 1688 "none, aplic, and aplic-imsic."); 1689 1690 object_class_property_add_str(oc, "aia-guests", 1691 virt_get_aia_guests, 1692 virt_set_aia_guests); 1693 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1694 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1695 object_class_property_set_description(oc, "aia-guests", str); 1696 object_class_property_add(oc, "acpi", "OnOffAuto", 1697 virt_get_acpi, virt_set_acpi, 1698 NULL, NULL); 1699 object_class_property_set_description(oc, "acpi", 1700 "Enable ACPI"); 1701 } 1702 1703 static const TypeInfo virt_machine_typeinfo = { 1704 .name = MACHINE_TYPE_NAME("virt"), 1705 .parent = TYPE_MACHINE, 1706 .class_init = virt_machine_class_init, 1707 .instance_init = virt_machine_instance_init, 1708 .instance_size = sizeof(RISCVVirtState), 1709 .interfaces = (InterfaceInfo[]) { 1710 { TYPE_HOTPLUG_HANDLER }, 1711 { } 1712 }, 1713 }; 1714 1715 static void virt_machine_init_register_types(void) 1716 { 1717 type_register_static(&virt_machine_typeinfo); 1718 } 1719 1720 type_init(virt_machine_init_register_types) 1721