1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/sysbus.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/char/serial.h" 30 #include "target/riscv/cpu.h" 31 #include "hw/riscv/riscv_hart.h" 32 #include "hw/riscv/virt.h" 33 #include "hw/riscv/boot.h" 34 #include "hw/riscv/numa.h" 35 #include "hw/intc/riscv_aclint.h" 36 #include "hw/intc/sifive_plic.h" 37 #include "hw/misc/sifive_test.h" 38 #include "chardev/char.h" 39 #include "sysemu/device_tree.h" 40 #include "sysemu/sysemu.h" 41 #include "sysemu/kvm.h" 42 #include "hw/pci/pci.h" 43 #include "hw/pci-host/gpex.h" 44 #include "hw/display/ramfb.h" 45 46 static const MemMapEntry virt_memmap[] = { 47 [VIRT_DEBUG] = { 0x0, 0x100 }, 48 [VIRT_MROM] = { 0x1000, 0xf000 }, 49 [VIRT_TEST] = { 0x100000, 0x1000 }, 50 [VIRT_RTC] = { 0x101000, 0x1000 }, 51 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 52 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 53 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 54 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 55 [VIRT_UART0] = { 0x10000000, 0x100 }, 56 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 57 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 58 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 59 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 60 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 61 [VIRT_DRAM] = { 0x80000000, 0x0 }, 62 }; 63 64 /* PCIe high mmio is fixed for RV32 */ 65 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 66 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 67 68 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 69 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 70 71 static MemMapEntry virt_high_pcie_memmap; 72 73 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 74 75 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 76 const char *name, 77 const char *alias_prop_name) 78 { 79 /* 80 * Create a single flash device. We use the same parameters as 81 * the flash devices on the ARM virt board. 82 */ 83 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 84 85 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 86 qdev_prop_set_uint8(dev, "width", 4); 87 qdev_prop_set_uint8(dev, "device-width", 2); 88 qdev_prop_set_bit(dev, "big-endian", false); 89 qdev_prop_set_uint16(dev, "id0", 0x89); 90 qdev_prop_set_uint16(dev, "id1", 0x18); 91 qdev_prop_set_uint16(dev, "id2", 0x00); 92 qdev_prop_set_uint16(dev, "id3", 0x00); 93 qdev_prop_set_string(dev, "name", name); 94 95 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 96 object_property_add_alias(OBJECT(s), alias_prop_name, 97 OBJECT(dev), "drive"); 98 99 return PFLASH_CFI01(dev); 100 } 101 102 static void virt_flash_create(RISCVVirtState *s) 103 { 104 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 105 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 106 } 107 108 static void virt_flash_map1(PFlashCFI01 *flash, 109 hwaddr base, hwaddr size, 110 MemoryRegion *sysmem) 111 { 112 DeviceState *dev = DEVICE(flash); 113 114 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 115 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 116 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 117 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 118 119 memory_region_add_subregion(sysmem, base, 120 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 121 0)); 122 } 123 124 static void virt_flash_map(RISCVVirtState *s, 125 MemoryRegion *sysmem) 126 { 127 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 128 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 129 130 virt_flash_map1(s->flash[0], flashbase, flashsize, 131 sysmem); 132 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 133 sysmem); 134 } 135 136 static void create_pcie_irq_map(void *fdt, char *nodename, 137 uint32_t plic_phandle) 138 { 139 int pin, dev; 140 uint32_t 141 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; 142 uint32_t *irq_map = full_irq_map; 143 144 /* This code creates a standard swizzle of interrupts such that 145 * each device's first interrupt is based on it's PCI_SLOT number. 146 * (See pci_swizzle_map_irq_fn()) 147 * 148 * We only need one entry per interrupt in the table (not one per 149 * possible slot) seeing the interrupt-map-mask will allow the table 150 * to wrap to any number of devices. 151 */ 152 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 153 int devfn = dev * 0x8; 154 155 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 156 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 157 int i = 0; 158 159 irq_map[i] = cpu_to_be32(devfn << 8); 160 161 i += FDT_PCI_ADDR_CELLS; 162 irq_map[i] = cpu_to_be32(pin + 1); 163 164 i += FDT_PCI_INT_CELLS; 165 irq_map[i++] = cpu_to_be32(plic_phandle); 166 167 i += FDT_PLIC_ADDR_CELLS; 168 irq_map[i] = cpu_to_be32(irq_nr); 169 170 irq_map += FDT_INT_MAP_WIDTH; 171 } 172 } 173 174 qemu_fdt_setprop(fdt, nodename, "interrupt-map", 175 full_irq_map, sizeof(full_irq_map)); 176 177 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 178 0x1800, 0, 0, 0x7); 179 } 180 181 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 182 char *clust_name, uint32_t *phandle, 183 bool is_32_bit, uint32_t *intc_phandles) 184 { 185 int cpu; 186 uint32_t cpu_phandle; 187 MachineState *mc = MACHINE(s); 188 char *name, *cpu_name, *core_name, *intc_name; 189 190 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 191 cpu_phandle = (*phandle)++; 192 193 cpu_name = g_strdup_printf("/cpus/cpu@%d", 194 s->soc[socket].hartid_base + cpu); 195 qemu_fdt_add_subnode(mc->fdt, cpu_name); 196 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 197 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 198 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 199 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); 200 g_free(name); 201 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); 202 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); 203 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", 204 s->soc[socket].hartid_base + cpu); 205 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); 206 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); 207 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); 208 209 intc_phandles[cpu] = (*phandle)++; 210 211 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 212 qemu_fdt_add_subnode(mc->fdt, intc_name); 213 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", 214 intc_phandles[cpu]); 215 if (riscv_feature(&s->soc[socket].harts[cpu].env, 216 RISCV_FEATURE_AIA)) { 217 static const char * const compat[2] = { 218 "riscv,cpu-intc-aia", "riscv,cpu-intc" 219 }; 220 qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible", 221 (char **)&compat, ARRAY_SIZE(compat)); 222 } else { 223 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", 224 "riscv,cpu-intc"); 225 } 226 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); 227 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); 228 229 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 230 qemu_fdt_add_subnode(mc->fdt, core_name); 231 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); 232 233 g_free(core_name); 234 g_free(intc_name); 235 g_free(cpu_name); 236 } 237 } 238 239 static void create_fdt_socket_memory(RISCVVirtState *s, 240 const MemMapEntry *memmap, int socket) 241 { 242 char *mem_name; 243 uint64_t addr, size; 244 MachineState *mc = MACHINE(s); 245 246 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 247 size = riscv_socket_mem_size(mc, socket); 248 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 249 qemu_fdt_add_subnode(mc->fdt, mem_name); 250 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", 251 addr >> 32, addr, size >> 32, size); 252 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); 253 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); 254 g_free(mem_name); 255 } 256 257 static void create_fdt_socket_clint(RISCVVirtState *s, 258 const MemMapEntry *memmap, int socket, 259 uint32_t *intc_phandles) 260 { 261 int cpu; 262 char *clint_name; 263 uint32_t *clint_cells; 264 unsigned long clint_addr; 265 MachineState *mc = MACHINE(s); 266 static const char * const clint_compat[2] = { 267 "sifive,clint0", "riscv,clint0" 268 }; 269 270 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 271 272 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 273 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 274 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 275 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 276 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 277 } 278 279 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 280 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 281 qemu_fdt_add_subnode(mc->fdt, clint_name); 282 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", 283 (char **)&clint_compat, 284 ARRAY_SIZE(clint_compat)); 285 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", 286 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 287 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", 288 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 289 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); 290 g_free(clint_name); 291 292 g_free(clint_cells); 293 } 294 295 static void create_fdt_socket_aclint(RISCVVirtState *s, 296 const MemMapEntry *memmap, int socket, 297 uint32_t *intc_phandles) 298 { 299 int cpu; 300 char *name; 301 unsigned long addr; 302 uint32_t aclint_cells_size; 303 uint32_t *aclint_mswi_cells; 304 uint32_t *aclint_sswi_cells; 305 uint32_t *aclint_mtimer_cells; 306 MachineState *mc = MACHINE(s); 307 308 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 309 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 310 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 311 312 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 313 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 314 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 315 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 316 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 317 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 318 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 319 } 320 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 321 322 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 323 name = g_strdup_printf("/soc/mswi@%lx", addr); 324 qemu_fdt_add_subnode(mc->fdt, name); 325 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-mswi"); 326 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 327 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 328 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 329 aclint_mswi_cells, aclint_cells_size); 330 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 331 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 332 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 333 g_free(name); 334 335 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 336 (memmap[VIRT_CLINT].size * socket); 337 name = g_strdup_printf("/soc/mtimer@%lx", addr); 338 qemu_fdt_add_subnode(mc->fdt, name); 339 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 340 "riscv,aclint-mtimer"); 341 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 342 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 343 0x0, memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE - 344 RISCV_ACLINT_DEFAULT_MTIME, 345 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 346 0x0, RISCV_ACLINT_DEFAULT_MTIME); 347 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 348 aclint_mtimer_cells, aclint_cells_size); 349 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 350 g_free(name); 351 352 addr = memmap[VIRT_ACLINT_SSWI].base + 353 (memmap[VIRT_ACLINT_SSWI].size * socket); 354 name = g_strdup_printf("/soc/sswi@%lx", addr); 355 qemu_fdt_add_subnode(mc->fdt, name); 356 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-sswi"); 357 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 358 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 359 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 360 aclint_sswi_cells, aclint_cells_size); 361 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 362 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 363 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 364 g_free(name); 365 366 g_free(aclint_mswi_cells); 367 g_free(aclint_mtimer_cells); 368 g_free(aclint_sswi_cells); 369 } 370 371 static void create_fdt_socket_plic(RISCVVirtState *s, 372 const MemMapEntry *memmap, int socket, 373 uint32_t *phandle, uint32_t *intc_phandles, 374 uint32_t *plic_phandles) 375 { 376 int cpu; 377 char *plic_name; 378 uint32_t *plic_cells; 379 unsigned long plic_addr; 380 MachineState *mc = MACHINE(s); 381 static const char * const plic_compat[2] = { 382 "sifive,plic-1.0.0", "riscv,plic0" 383 }; 384 385 if (kvm_enabled()) { 386 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 387 } else { 388 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 389 } 390 391 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 392 if (kvm_enabled()) { 393 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 394 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 395 } else { 396 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 397 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 398 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 399 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 400 } 401 } 402 403 plic_phandles[socket] = (*phandle)++; 404 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 405 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 406 qemu_fdt_add_subnode(mc->fdt, plic_name); 407 qemu_fdt_setprop_cell(mc->fdt, plic_name, 408 "#address-cells", FDT_PLIC_ADDR_CELLS); 409 qemu_fdt_setprop_cell(mc->fdt, plic_name, 410 "#interrupt-cells", FDT_PLIC_INT_CELLS); 411 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", 412 (char **)&plic_compat, 413 ARRAY_SIZE(plic_compat)); 414 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); 415 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", 416 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 417 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", 418 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 419 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 420 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); 421 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", 422 plic_phandles[socket]); 423 g_free(plic_name); 424 425 g_free(plic_cells); 426 } 427 428 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 429 bool is_32_bit, uint32_t *phandle, 430 uint32_t *irq_mmio_phandle, 431 uint32_t *irq_pcie_phandle, 432 uint32_t *irq_virtio_phandle) 433 { 434 int socket; 435 char *clust_name; 436 uint32_t *intc_phandles; 437 MachineState *mc = MACHINE(s); 438 uint32_t xplic_phandles[MAX_NODES]; 439 440 qemu_fdt_add_subnode(mc->fdt, "/cpus"); 441 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", 442 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 443 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); 444 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); 445 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); 446 447 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 448 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 449 qemu_fdt_add_subnode(mc->fdt, clust_name); 450 451 intc_phandles = g_new0(uint32_t, s->soc[socket].num_harts); 452 453 create_fdt_socket_cpus(s, socket, clust_name, phandle, 454 is_32_bit, intc_phandles); 455 456 create_fdt_socket_memory(s, memmap, socket); 457 458 if (!kvm_enabled()) { 459 if (s->have_aclint) { 460 create_fdt_socket_aclint(s, memmap, socket, intc_phandles); 461 } else { 462 create_fdt_socket_clint(s, memmap, socket, intc_phandles); 463 } 464 } 465 466 create_fdt_socket_plic(s, memmap, socket, phandle, 467 intc_phandles, xplic_phandles); 468 469 g_free(intc_phandles); 470 g_free(clust_name); 471 } 472 473 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 474 if (socket == 0) { 475 *irq_mmio_phandle = xplic_phandles[socket]; 476 *irq_virtio_phandle = xplic_phandles[socket]; 477 *irq_pcie_phandle = xplic_phandles[socket]; 478 } 479 if (socket == 1) { 480 *irq_virtio_phandle = xplic_phandles[socket]; 481 *irq_pcie_phandle = xplic_phandles[socket]; 482 } 483 if (socket == 2) { 484 *irq_pcie_phandle = xplic_phandles[socket]; 485 } 486 } 487 488 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); 489 } 490 491 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 492 uint32_t irq_virtio_phandle) 493 { 494 int i; 495 char *name; 496 MachineState *mc = MACHINE(s); 497 498 for (i = 0; i < VIRTIO_COUNT; i++) { 499 name = g_strdup_printf("/soc/virtio_mmio@%lx", 500 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 501 qemu_fdt_add_subnode(mc->fdt, name); 502 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); 503 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 504 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 505 0x0, memmap[VIRT_VIRTIO].size); 506 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 507 irq_virtio_phandle); 508 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", VIRTIO_IRQ + i); 509 g_free(name); 510 } 511 } 512 513 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 514 uint32_t irq_pcie_phandle) 515 { 516 char *name; 517 MachineState *mc = MACHINE(s); 518 519 name = g_strdup_printf("/soc/pci@%lx", 520 (long) memmap[VIRT_PCIE_ECAM].base); 521 qemu_fdt_add_subnode(mc->fdt, name); 522 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", 523 FDT_PCI_ADDR_CELLS); 524 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 525 FDT_PCI_INT_CELLS); 526 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); 527 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 528 "pci-host-ecam-generic"); 529 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); 530 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); 531 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, 532 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 533 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); 534 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, 535 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 536 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", 537 1, FDT_PCI_RANGE_IOPORT, 2, 0, 538 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 539 1, FDT_PCI_RANGE_MMIO, 540 2, memmap[VIRT_PCIE_MMIO].base, 541 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 542 1, FDT_PCI_RANGE_MMIO_64BIT, 543 2, virt_high_pcie_memmap.base, 544 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 545 546 create_pcie_irq_map(mc->fdt, name, irq_pcie_phandle); 547 g_free(name); 548 } 549 550 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 551 uint32_t *phandle) 552 { 553 char *name; 554 uint32_t test_phandle; 555 MachineState *mc = MACHINE(s); 556 557 test_phandle = (*phandle)++; 558 name = g_strdup_printf("/soc/test@%lx", 559 (long)memmap[VIRT_TEST].base); 560 qemu_fdt_add_subnode(mc->fdt, name); 561 { 562 static const char * const compat[3] = { 563 "sifive,test1", "sifive,test0", "syscon" 564 }; 565 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", 566 (char **)&compat, ARRAY_SIZE(compat)); 567 } 568 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 569 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 570 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); 571 test_phandle = qemu_fdt_get_phandle(mc->fdt, name); 572 g_free(name); 573 574 name = g_strdup_printf("/soc/reboot"); 575 qemu_fdt_add_subnode(mc->fdt, name); 576 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); 577 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 578 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 579 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); 580 g_free(name); 581 582 name = g_strdup_printf("/soc/poweroff"); 583 qemu_fdt_add_subnode(mc->fdt, name); 584 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); 585 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 586 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 587 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); 588 g_free(name); 589 } 590 591 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 592 uint32_t irq_mmio_phandle) 593 { 594 char *name; 595 MachineState *mc = MACHINE(s); 596 597 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 598 qemu_fdt_add_subnode(mc->fdt, name); 599 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); 600 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 601 0x0, memmap[VIRT_UART0].base, 602 0x0, memmap[VIRT_UART0].size); 603 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); 604 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); 605 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); 606 607 qemu_fdt_add_subnode(mc->fdt, "/chosen"); 608 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); 609 g_free(name); 610 } 611 612 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 613 uint32_t irq_mmio_phandle) 614 { 615 char *name; 616 MachineState *mc = MACHINE(s); 617 618 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 619 qemu_fdt_add_subnode(mc->fdt, name); 620 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 621 "google,goldfish-rtc"); 622 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 623 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 624 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 625 irq_mmio_phandle); 626 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); 627 g_free(name); 628 } 629 630 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 631 { 632 char *name; 633 MachineState *mc = MACHINE(s); 634 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 635 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 636 637 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 638 qemu_fdt_add_subnode(mc->fdt, name); 639 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 640 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 641 2, flashbase, 2, flashsize, 642 2, flashbase + flashsize, 2, flashsize); 643 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 644 g_free(name); 645 } 646 647 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 648 uint64_t mem_size, const char *cmdline, bool is_32_bit) 649 { 650 MachineState *mc = MACHINE(s); 651 uint32_t phandle = 1, irq_mmio_phandle = 1; 652 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 653 654 if (mc->dtb) { 655 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 656 if (!mc->fdt) { 657 error_report("load_device_tree() failed"); 658 exit(1); 659 } 660 goto update_bootargs; 661 } else { 662 mc->fdt = create_device_tree(&s->fdt_size); 663 if (!mc->fdt) { 664 error_report("create_device_tree() failed"); 665 exit(1); 666 } 667 } 668 669 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); 670 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); 671 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); 672 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); 673 674 qemu_fdt_add_subnode(mc->fdt, "/soc"); 675 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); 676 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); 677 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); 678 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); 679 680 create_fdt_sockets(s, memmap, is_32_bit, &phandle, 681 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle); 682 683 create_fdt_virtio(s, memmap, irq_virtio_phandle); 684 685 create_fdt_pcie(s, memmap, irq_pcie_phandle); 686 687 create_fdt_reset(s, memmap, &phandle); 688 689 create_fdt_uart(s, memmap, irq_mmio_phandle); 690 691 create_fdt_rtc(s, memmap, irq_mmio_phandle); 692 693 create_fdt_flash(s, memmap); 694 695 update_bootargs: 696 if (cmdline) { 697 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); 698 } 699 } 700 701 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 702 hwaddr ecam_base, hwaddr ecam_size, 703 hwaddr mmio_base, hwaddr mmio_size, 704 hwaddr high_mmio_base, 705 hwaddr high_mmio_size, 706 hwaddr pio_base, 707 DeviceState *plic) 708 { 709 DeviceState *dev; 710 MemoryRegion *ecam_alias, *ecam_reg; 711 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 712 qemu_irq irq; 713 int i; 714 715 dev = qdev_new(TYPE_GPEX_HOST); 716 717 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 718 719 ecam_alias = g_new0(MemoryRegion, 1); 720 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 721 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 722 ecam_reg, 0, ecam_size); 723 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 724 725 mmio_alias = g_new0(MemoryRegion, 1); 726 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 727 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 728 mmio_reg, mmio_base, mmio_size); 729 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 730 731 /* Map high MMIO space */ 732 high_mmio_alias = g_new0(MemoryRegion, 1); 733 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 734 mmio_reg, high_mmio_base, high_mmio_size); 735 memory_region_add_subregion(get_system_memory(), high_mmio_base, 736 high_mmio_alias); 737 738 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 739 740 for (i = 0; i < GPEX_NUM_IRQS; i++) { 741 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); 742 743 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 744 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 745 } 746 747 return dev; 748 } 749 750 static FWCfgState *create_fw_cfg(const MachineState *mc) 751 { 752 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 753 hwaddr size = virt_memmap[VIRT_FW_CFG].size; 754 FWCfgState *fw_cfg; 755 char *nodename; 756 757 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 758 &address_space_memory); 759 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 760 761 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 762 qemu_fdt_add_subnode(mc->fdt, nodename); 763 qemu_fdt_setprop_string(mc->fdt, nodename, 764 "compatible", "qemu,fw-cfg-mmio"); 765 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 766 2, base, 2, size); 767 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 768 g_free(nodename); 769 return fw_cfg; 770 } 771 772 static void virt_machine_init(MachineState *machine) 773 { 774 const MemMapEntry *memmap = virt_memmap; 775 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 776 MemoryRegion *system_memory = get_system_memory(); 777 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 778 char *plic_hart_config, *soc_name; 779 target_ulong start_addr = memmap[VIRT_DRAM].base; 780 target_ulong firmware_end_addr, kernel_start_addr; 781 uint32_t fdt_load_addr; 782 uint64_t kernel_entry; 783 DeviceState *mmio_plic, *virtio_plic, *pcie_plic; 784 int i, base_hartid, hart_count; 785 786 /* Check socket count limit */ 787 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 788 error_report("number of sockets/nodes should be less than %d", 789 VIRT_SOCKETS_MAX); 790 exit(1); 791 } 792 793 /* Initialize sockets */ 794 mmio_plic = virtio_plic = pcie_plic = NULL; 795 for (i = 0; i < riscv_socket_count(machine); i++) { 796 if (!riscv_socket_check_hartids(machine, i)) { 797 error_report("discontinuous hartids in socket%d", i); 798 exit(1); 799 } 800 801 base_hartid = riscv_socket_first_hartid(machine, i); 802 if (base_hartid < 0) { 803 error_report("can't find hartid base for socket%d", i); 804 exit(1); 805 } 806 807 hart_count = riscv_socket_hart_count(machine, i); 808 if (hart_count < 0) { 809 error_report("can't find hart count for socket%d", i); 810 exit(1); 811 } 812 813 soc_name = g_strdup_printf("soc%d", i); 814 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 815 TYPE_RISCV_HART_ARRAY); 816 g_free(soc_name); 817 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 818 machine->cpu_type, &error_abort); 819 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 820 base_hartid, &error_abort); 821 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 822 hart_count, &error_abort); 823 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 824 825 if (!kvm_enabled()) { 826 /* Per-socket CLINT */ 827 riscv_aclint_swi_create( 828 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 829 base_hartid, hart_count, false); 830 riscv_aclint_mtimer_create( 831 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size + 832 RISCV_ACLINT_SWI_SIZE, 833 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 834 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 835 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 836 837 /* Per-socket ACLINT SSWI */ 838 if (s->have_aclint) { 839 riscv_aclint_swi_create( 840 memmap[VIRT_ACLINT_SSWI].base + 841 i * memmap[VIRT_ACLINT_SSWI].size, 842 base_hartid, hart_count, true); 843 } 844 } 845 846 /* Per-socket PLIC hart topology configuration string */ 847 plic_hart_config = riscv_plic_hart_config_string(hart_count); 848 849 /* Per-socket PLIC */ 850 s->plic[i] = sifive_plic_create( 851 memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, 852 plic_hart_config, hart_count, base_hartid, 853 VIRT_PLIC_NUM_SOURCES, 854 VIRT_PLIC_NUM_PRIORITIES, 855 VIRT_PLIC_PRIORITY_BASE, 856 VIRT_PLIC_PENDING_BASE, 857 VIRT_PLIC_ENABLE_BASE, 858 VIRT_PLIC_ENABLE_STRIDE, 859 VIRT_PLIC_CONTEXT_BASE, 860 VIRT_PLIC_CONTEXT_STRIDE, 861 memmap[VIRT_PLIC].size); 862 g_free(plic_hart_config); 863 864 /* Try to use different PLIC instance based device type */ 865 if (i == 0) { 866 mmio_plic = s->plic[i]; 867 virtio_plic = s->plic[i]; 868 pcie_plic = s->plic[i]; 869 } 870 if (i == 1) { 871 virtio_plic = s->plic[i]; 872 pcie_plic = s->plic[i]; 873 } 874 if (i == 2) { 875 pcie_plic = s->plic[i]; 876 } 877 } 878 879 if (riscv_is_32bit(&s->soc[0])) { 880 #if HOST_LONG_BITS == 64 881 /* limit RAM size in a 32-bit system */ 882 if (machine->ram_size > 10 * GiB) { 883 machine->ram_size = 10 * GiB; 884 error_report("Limiting RAM size to 10 GiB"); 885 } 886 #endif 887 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 888 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 889 } else { 890 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 891 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 892 virt_high_pcie_memmap.base = 893 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 894 } 895 896 /* register system main memory (actual RAM) */ 897 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 898 machine->ram); 899 900 /* create device tree */ 901 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 902 riscv_is_32bit(&s->soc[0])); 903 904 /* boot rom */ 905 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 906 memmap[VIRT_MROM].size, &error_fatal); 907 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 908 mask_rom); 909 910 /* 911 * Only direct boot kernel is currently supported for KVM VM, 912 * so the "-bios" parameter is ignored and treated like "-bios none" 913 * when KVM is enabled. 914 */ 915 if (kvm_enabled()) { 916 g_free(machine->firmware); 917 machine->firmware = g_strdup("none"); 918 } 919 920 if (riscv_is_32bit(&s->soc[0])) { 921 firmware_end_addr = riscv_find_and_load_firmware(machine, 922 RISCV32_BIOS_BIN, start_addr, NULL); 923 } else { 924 firmware_end_addr = riscv_find_and_load_firmware(machine, 925 RISCV64_BIOS_BIN, start_addr, NULL); 926 } 927 928 if (machine->kernel_filename) { 929 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 930 firmware_end_addr); 931 932 kernel_entry = riscv_load_kernel(machine->kernel_filename, 933 kernel_start_addr, NULL); 934 935 if (machine->initrd_filename) { 936 hwaddr start; 937 hwaddr end = riscv_load_initrd(machine->initrd_filename, 938 machine->ram_size, kernel_entry, 939 &start); 940 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 941 "linux,initrd-start", start); 942 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 943 end); 944 } 945 } else { 946 /* 947 * If dynamic firmware is used, it doesn't know where is the next mode 948 * if kernel argument is not set. 949 */ 950 kernel_entry = 0; 951 } 952 953 if (drive_get(IF_PFLASH, 0, 0)) { 954 /* 955 * Pflash was supplied, let's overwrite the address we jump to after 956 * reset to the base of the flash. 957 */ 958 start_addr = virt_memmap[VIRT_FLASH].base; 959 } 960 961 /* 962 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 963 * tree cannot be altered and we get FDT_ERR_NOSPACE. 964 */ 965 s->fw_cfg = create_fw_cfg(machine); 966 rom_set_fw(s->fw_cfg); 967 968 /* Compute the fdt load address in dram */ 969 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 970 machine->ram_size, machine->fdt); 971 /* load the reset vector */ 972 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 973 virt_memmap[VIRT_MROM].base, 974 virt_memmap[VIRT_MROM].size, kernel_entry, 975 fdt_load_addr, machine->fdt); 976 977 /* 978 * Only direct boot kernel is currently supported for KVM VM, 979 * So here setup kernel start address and fdt address. 980 * TODO:Support firmware loading and integrate to TCG start 981 */ 982 if (kvm_enabled()) { 983 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 984 } 985 986 /* SiFive Test MMIO device */ 987 sifive_test_create(memmap[VIRT_TEST].base); 988 989 /* VirtIO MMIO devices */ 990 for (i = 0; i < VIRTIO_COUNT; i++) { 991 sysbus_create_simple("virtio-mmio", 992 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 993 qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); 994 } 995 996 gpex_pcie_init(system_memory, 997 memmap[VIRT_PCIE_ECAM].base, 998 memmap[VIRT_PCIE_ECAM].size, 999 memmap[VIRT_PCIE_MMIO].base, 1000 memmap[VIRT_PCIE_MMIO].size, 1001 virt_high_pcie_memmap.base, 1002 virt_high_pcie_memmap.size, 1003 memmap[VIRT_PCIE_PIO].base, 1004 DEVICE(pcie_plic)); 1005 1006 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1007 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, 1008 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1009 1010 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1011 qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); 1012 1013 virt_flash_create(s); 1014 1015 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1016 /* Map legacy -drive if=pflash to machine properties */ 1017 pflash_cfi01_legacy_drive(s->flash[i], 1018 drive_get(IF_PFLASH, 0, i)); 1019 } 1020 virt_flash_map(s, system_memory); 1021 } 1022 1023 static void virt_machine_instance_init(Object *obj) 1024 { 1025 } 1026 1027 static bool virt_get_aclint(Object *obj, Error **errp) 1028 { 1029 MachineState *ms = MACHINE(obj); 1030 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1031 1032 return s->have_aclint; 1033 } 1034 1035 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1036 { 1037 MachineState *ms = MACHINE(obj); 1038 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1039 1040 s->have_aclint = value; 1041 } 1042 1043 static void virt_machine_class_init(ObjectClass *oc, void *data) 1044 { 1045 MachineClass *mc = MACHINE_CLASS(oc); 1046 1047 mc->desc = "RISC-V VirtIO board"; 1048 mc->init = virt_machine_init; 1049 mc->max_cpus = VIRT_CPUS_MAX; 1050 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1051 mc->pci_allow_0_address = true; 1052 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1053 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1054 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1055 mc->numa_mem_supported = true; 1056 mc->default_ram_id = "riscv_virt_board.ram"; 1057 1058 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1059 1060 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1061 virt_set_aclint); 1062 object_class_property_set_description(oc, "aclint", 1063 "Set on/off to enable/disable " 1064 "emulating ACLINT devices"); 1065 } 1066 1067 static const TypeInfo virt_machine_typeinfo = { 1068 .name = MACHINE_TYPE_NAME("virt"), 1069 .parent = TYPE_MACHINE, 1070 .class_init = virt_machine_class_init, 1071 .instance_init = virt_machine_instance_init, 1072 .instance_size = sizeof(RISCVVirtState), 1073 }; 1074 1075 static void virt_machine_init_register_types(void) 1076 { 1077 type_register_static(&virt_machine_typeinfo); 1078 } 1079 1080 type_init(virt_machine_init_register_types) 1081