1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "kvm/kvm_riscv.h" 39 #include "hw/intc/riscv_aclint.h" 40 #include "hw/intc/riscv_aplic.h" 41 #include "hw/intc/sifive_plic.h" 42 #include "hw/misc/sifive_test.h" 43 #include "hw/platform-bus.h" 44 #include "chardev/char.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/tcg.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/tpm.h" 50 #include "hw/pci/pci.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/display/ramfb.h" 53 #include "hw/acpi/aml-build.h" 54 #include "qapi/qapi-visit-common.h" 55 56 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 57 static bool virt_use_kvm_aia(RISCVVirtState *s) 58 { 59 return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 60 } 61 62 static const MemMapEntry virt_memmap[] = { 63 [VIRT_DEBUG] = { 0x0, 0x100 }, 64 [VIRT_MROM] = { 0x1000, 0xf000 }, 65 [VIRT_TEST] = { 0x100000, 0x1000 }, 66 [VIRT_RTC] = { 0x101000, 0x1000 }, 67 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 68 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 69 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 70 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 71 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 72 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 73 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 74 [VIRT_UART0] = { 0x10000000, 0x100 }, 75 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 76 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 77 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 78 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 79 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 80 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 81 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 82 [VIRT_DRAM] = { 0x80000000, 0x0 }, 83 }; 84 85 /* PCIe high mmio is fixed for RV32 */ 86 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 87 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 88 89 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 90 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 91 92 static MemMapEntry virt_high_pcie_memmap; 93 94 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 95 96 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 97 const char *name, 98 const char *alias_prop_name) 99 { 100 /* 101 * Create a single flash device. We use the same parameters as 102 * the flash devices on the ARM virt board. 103 */ 104 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 105 106 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 107 qdev_prop_set_uint8(dev, "width", 4); 108 qdev_prop_set_uint8(dev, "device-width", 2); 109 qdev_prop_set_bit(dev, "big-endian", false); 110 qdev_prop_set_uint16(dev, "id0", 0x89); 111 qdev_prop_set_uint16(dev, "id1", 0x18); 112 qdev_prop_set_uint16(dev, "id2", 0x00); 113 qdev_prop_set_uint16(dev, "id3", 0x00); 114 qdev_prop_set_string(dev, "name", name); 115 116 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 117 object_property_add_alias(OBJECT(s), alias_prop_name, 118 OBJECT(dev), "drive"); 119 120 return PFLASH_CFI01(dev); 121 } 122 123 static void virt_flash_create(RISCVVirtState *s) 124 { 125 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 126 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 127 } 128 129 static void virt_flash_map1(PFlashCFI01 *flash, 130 hwaddr base, hwaddr size, 131 MemoryRegion *sysmem) 132 { 133 DeviceState *dev = DEVICE(flash); 134 135 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 136 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 137 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 138 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 139 140 memory_region_add_subregion(sysmem, base, 141 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 142 0)); 143 } 144 145 static void virt_flash_map(RISCVVirtState *s, 146 MemoryRegion *sysmem) 147 { 148 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 149 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 150 151 virt_flash_map1(s->flash[0], flashbase, flashsize, 152 sysmem); 153 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 154 sysmem); 155 } 156 157 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 158 uint32_t irqchip_phandle) 159 { 160 int pin, dev; 161 uint32_t irq_map_stride = 0; 162 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 163 FDT_MAX_INT_MAP_WIDTH] = {}; 164 uint32_t *irq_map = full_irq_map; 165 166 /* This code creates a standard swizzle of interrupts such that 167 * each device's first interrupt is based on it's PCI_SLOT number. 168 * (See pci_swizzle_map_irq_fn()) 169 * 170 * We only need one entry per interrupt in the table (not one per 171 * possible slot) seeing the interrupt-map-mask will allow the table 172 * to wrap to any number of devices. 173 */ 174 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 175 int devfn = dev * 0x8; 176 177 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 178 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 179 int i = 0; 180 181 /* Fill PCI address cells */ 182 irq_map[i] = cpu_to_be32(devfn << 8); 183 i += FDT_PCI_ADDR_CELLS; 184 185 /* Fill PCI Interrupt cells */ 186 irq_map[i] = cpu_to_be32(pin + 1); 187 i += FDT_PCI_INT_CELLS; 188 189 /* Fill interrupt controller phandle and cells */ 190 irq_map[i++] = cpu_to_be32(irqchip_phandle); 191 irq_map[i++] = cpu_to_be32(irq_nr); 192 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 193 irq_map[i++] = cpu_to_be32(0x4); 194 } 195 196 if (!irq_map_stride) { 197 irq_map_stride = i; 198 } 199 irq_map += irq_map_stride; 200 } 201 } 202 203 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 204 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 205 irq_map_stride * sizeof(uint32_t)); 206 207 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 208 0x1800, 0, 0, 0x7); 209 } 210 211 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 212 char *clust_name, uint32_t *phandle, 213 uint32_t *intc_phandles) 214 { 215 int cpu; 216 uint32_t cpu_phandle; 217 MachineState *ms = MACHINE(s); 218 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 219 uint8_t satp_mode_max; 220 221 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 222 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 223 g_autofree char *name = NULL; 224 g_autofree char *cpu_name = NULL; 225 g_autofree char *core_name = NULL; 226 g_autofree char *intc_name = NULL; 227 g_autofree char *sv_name = NULL; 228 229 cpu_phandle = (*phandle)++; 230 231 cpu_name = g_strdup_printf("/cpus/cpu@%d", 232 s->soc[socket].hartid_base + cpu); 233 qemu_fdt_add_subnode(ms->fdt, cpu_name); 234 235 if (cpu_ptr->cfg.satp_mode.supported != 0) { 236 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 237 sv_name = g_strdup_printf("riscv,%s", 238 satp_mode_str(satp_mode_max, is_32_bit)); 239 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 240 } 241 242 name = riscv_isa_string(cpu_ptr); 243 qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); 244 245 if (cpu_ptr->cfg.ext_zicbom) { 246 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 247 cpu_ptr->cfg.cbom_blocksize); 248 } 249 250 if (cpu_ptr->cfg.ext_zicboz) { 251 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 252 cpu_ptr->cfg.cboz_blocksize); 253 } 254 255 if (cpu_ptr->cfg.ext_zicbop) { 256 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 257 cpu_ptr->cfg.cbop_blocksize); 258 } 259 260 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 261 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 262 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 263 s->soc[socket].hartid_base + cpu); 264 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 265 riscv_socket_fdt_write_id(ms, cpu_name, socket); 266 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 267 268 intc_phandles[cpu] = (*phandle)++; 269 270 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 271 qemu_fdt_add_subnode(ms->fdt, intc_name); 272 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 273 intc_phandles[cpu]); 274 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 275 "riscv,cpu-intc"); 276 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 277 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 278 279 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 280 qemu_fdt_add_subnode(ms->fdt, core_name); 281 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 282 } 283 } 284 285 static void create_fdt_socket_memory(RISCVVirtState *s, 286 const MemMapEntry *memmap, int socket) 287 { 288 g_autofree char *mem_name = NULL; 289 uint64_t addr, size; 290 MachineState *ms = MACHINE(s); 291 292 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 293 size = riscv_socket_mem_size(ms, socket); 294 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 295 qemu_fdt_add_subnode(ms->fdt, mem_name); 296 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 297 addr >> 32, addr, size >> 32, size); 298 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 299 riscv_socket_fdt_write_id(ms, mem_name, socket); 300 } 301 302 static void create_fdt_socket_clint(RISCVVirtState *s, 303 const MemMapEntry *memmap, int socket, 304 uint32_t *intc_phandles) 305 { 306 int cpu; 307 g_autofree char *clint_name = NULL; 308 g_autofree uint32_t *clint_cells = NULL; 309 unsigned long clint_addr; 310 MachineState *ms = MACHINE(s); 311 static const char * const clint_compat[2] = { 312 "sifive,clint0", "riscv,clint0" 313 }; 314 315 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 316 317 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 318 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 319 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 320 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 321 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 322 } 323 324 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 325 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 326 qemu_fdt_add_subnode(ms->fdt, clint_name); 327 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 328 (char **)&clint_compat, 329 ARRAY_SIZE(clint_compat)); 330 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 331 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 332 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 333 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 334 riscv_socket_fdt_write_id(ms, clint_name, socket); 335 } 336 337 static void create_fdt_socket_aclint(RISCVVirtState *s, 338 const MemMapEntry *memmap, int socket, 339 uint32_t *intc_phandles) 340 { 341 int cpu; 342 char *name; 343 unsigned long addr, size; 344 uint32_t aclint_cells_size; 345 g_autofree uint32_t *aclint_mswi_cells = NULL; 346 g_autofree uint32_t *aclint_sswi_cells = NULL; 347 g_autofree uint32_t *aclint_mtimer_cells = NULL; 348 MachineState *ms = MACHINE(s); 349 350 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 351 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 352 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 353 354 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 355 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 356 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 357 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 358 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 359 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 360 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 361 } 362 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 363 364 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 365 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 366 name = g_strdup_printf("/soc/mswi@%lx", addr); 367 qemu_fdt_add_subnode(ms->fdt, name); 368 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 369 "riscv,aclint-mswi"); 370 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 371 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 372 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 373 aclint_mswi_cells, aclint_cells_size); 374 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 375 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 376 riscv_socket_fdt_write_id(ms, name, socket); 377 g_free(name); 378 } 379 380 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 381 addr = memmap[VIRT_CLINT].base + 382 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 383 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 384 } else { 385 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 386 (memmap[VIRT_CLINT].size * socket); 387 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 388 } 389 name = g_strdup_printf("/soc/mtimer@%lx", addr); 390 qemu_fdt_add_subnode(ms->fdt, name); 391 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 392 "riscv,aclint-mtimer"); 393 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 394 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 395 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 396 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 397 0x0, RISCV_ACLINT_DEFAULT_MTIME); 398 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 399 aclint_mtimer_cells, aclint_cells_size); 400 riscv_socket_fdt_write_id(ms, name, socket); 401 g_free(name); 402 403 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 404 addr = memmap[VIRT_ACLINT_SSWI].base + 405 (memmap[VIRT_ACLINT_SSWI].size * socket); 406 name = g_strdup_printf("/soc/sswi@%lx", addr); 407 qemu_fdt_add_subnode(ms->fdt, name); 408 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 409 "riscv,aclint-sswi"); 410 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 411 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 412 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 413 aclint_sswi_cells, aclint_cells_size); 414 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 415 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 416 riscv_socket_fdt_write_id(ms, name, socket); 417 g_free(name); 418 } 419 } 420 421 static void create_fdt_socket_plic(RISCVVirtState *s, 422 const MemMapEntry *memmap, int socket, 423 uint32_t *phandle, uint32_t *intc_phandles, 424 uint32_t *plic_phandles) 425 { 426 int cpu; 427 g_autofree char *plic_name = NULL; 428 g_autofree uint32_t *plic_cells; 429 unsigned long plic_addr; 430 MachineState *ms = MACHINE(s); 431 static const char * const plic_compat[2] = { 432 "sifive,plic-1.0.0", "riscv,plic0" 433 }; 434 435 plic_phandles[socket] = (*phandle)++; 436 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 437 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 438 qemu_fdt_add_subnode(ms->fdt, plic_name); 439 qemu_fdt_setprop_cell(ms->fdt, plic_name, 440 "#interrupt-cells", FDT_PLIC_INT_CELLS); 441 qemu_fdt_setprop_cell(ms->fdt, plic_name, 442 "#address-cells", FDT_PLIC_ADDR_CELLS); 443 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 444 (char **)&plic_compat, 445 ARRAY_SIZE(plic_compat)); 446 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 447 448 if (kvm_enabled()) { 449 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 450 451 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 452 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 453 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 454 } 455 456 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 457 plic_cells, 458 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 459 } else { 460 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 461 462 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 463 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 464 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 465 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 466 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 467 } 468 469 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 470 plic_cells, 471 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 472 } 473 474 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 475 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 476 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 477 VIRT_IRQCHIP_NUM_SOURCES - 1); 478 riscv_socket_fdt_write_id(ms, plic_name, socket); 479 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 480 plic_phandles[socket]); 481 482 if (!socket) { 483 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 484 memmap[VIRT_PLATFORM_BUS].base, 485 memmap[VIRT_PLATFORM_BUS].size, 486 VIRT_PLATFORM_BUS_IRQ); 487 } 488 } 489 490 uint32_t imsic_num_bits(uint32_t count) 491 { 492 uint32_t ret = 0; 493 494 while (BIT(ret) < count) { 495 ret++; 496 } 497 498 return ret; 499 } 500 501 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 502 uint32_t *intc_phandles, uint32_t msi_phandle, 503 bool m_mode, uint32_t imsic_guest_bits) 504 { 505 int cpu, socket; 506 g_autofree char *imsic_name = NULL; 507 MachineState *ms = MACHINE(s); 508 int socket_count = riscv_socket_count(ms); 509 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 510 g_autofree uint32_t *imsic_cells = NULL; 511 g_autofree uint32_t *imsic_regs = NULL; 512 513 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 514 imsic_regs = g_new0(uint32_t, socket_count * 4); 515 516 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 517 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 518 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 519 } 520 521 imsic_max_hart_per_socket = 0; 522 for (socket = 0; socket < socket_count; socket++) { 523 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 524 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 525 s->soc[socket].num_harts; 526 imsic_regs[socket * 4 + 0] = 0; 527 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 528 imsic_regs[socket * 4 + 2] = 0; 529 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 530 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 531 imsic_max_hart_per_socket = s->soc[socket].num_harts; 532 } 533 } 534 535 imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr); 536 qemu_fdt_add_subnode(ms->fdt, imsic_name); 537 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); 538 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 539 FDT_IMSIC_INT_CELLS); 540 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 541 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 542 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 543 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 544 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 545 socket_count * sizeof(uint32_t) * 4); 546 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 547 VIRT_IRQCHIP_NUM_MSIS); 548 549 if (imsic_guest_bits) { 550 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 551 imsic_guest_bits); 552 } 553 554 if (socket_count > 1) { 555 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 556 imsic_num_bits(imsic_max_hart_per_socket)); 557 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 558 imsic_num_bits(socket_count)); 559 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 560 IMSIC_MMIO_GROUP_MIN_SHIFT); 561 } 562 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 563 } 564 565 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 566 uint32_t *phandle, uint32_t *intc_phandles, 567 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 568 { 569 *msi_m_phandle = (*phandle)++; 570 *msi_s_phandle = (*phandle)++; 571 572 if (!kvm_enabled()) { 573 /* M-level IMSIC node */ 574 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 575 *msi_m_phandle, true, 0); 576 } 577 578 /* S-level IMSIC node */ 579 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 580 *msi_s_phandle, false, 581 imsic_num_bits(s->aia_guests + 1)); 582 583 } 584 585 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 586 unsigned long aplic_addr, uint32_t aplic_size, 587 uint32_t msi_phandle, 588 uint32_t *intc_phandles, 589 uint32_t aplic_phandle, 590 uint32_t aplic_child_phandle, 591 bool m_mode, int num_harts) 592 { 593 int cpu; 594 g_autofree char *aplic_name = NULL; 595 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 596 MachineState *ms = MACHINE(s); 597 598 for (cpu = 0; cpu < num_harts; cpu++) { 599 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 600 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 601 } 602 603 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 604 qemu_fdt_add_subnode(ms->fdt, aplic_name); 605 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); 606 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 607 "#interrupt-cells", FDT_APLIC_INT_CELLS); 608 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 609 610 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 611 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 612 aplic_cells, num_harts * sizeof(uint32_t) * 2); 613 } else { 614 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 615 } 616 617 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 618 0x0, aplic_addr, 0x0, aplic_size); 619 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 620 VIRT_IRQCHIP_NUM_SOURCES); 621 622 if (aplic_child_phandle) { 623 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 624 aplic_child_phandle); 625 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 626 aplic_child_phandle, 0x1, 627 VIRT_IRQCHIP_NUM_SOURCES); 628 } 629 630 riscv_socket_fdt_write_id(ms, aplic_name, socket); 631 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 632 } 633 634 static void create_fdt_socket_aplic(RISCVVirtState *s, 635 const MemMapEntry *memmap, int socket, 636 uint32_t msi_m_phandle, 637 uint32_t msi_s_phandle, 638 uint32_t *phandle, 639 uint32_t *intc_phandles, 640 uint32_t *aplic_phandles, 641 int num_harts) 642 { 643 g_autofree char *aplic_name = NULL; 644 unsigned long aplic_addr; 645 MachineState *ms = MACHINE(s); 646 uint32_t aplic_m_phandle, aplic_s_phandle; 647 648 aplic_m_phandle = (*phandle)++; 649 aplic_s_phandle = (*phandle)++; 650 651 if (!kvm_enabled()) { 652 /* M-level APLIC node */ 653 aplic_addr = memmap[VIRT_APLIC_M].base + 654 (memmap[VIRT_APLIC_M].size * socket); 655 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 656 msi_m_phandle, intc_phandles, 657 aplic_m_phandle, aplic_s_phandle, 658 true, num_harts); 659 } 660 661 /* S-level APLIC node */ 662 aplic_addr = memmap[VIRT_APLIC_S].base + 663 (memmap[VIRT_APLIC_S].size * socket); 664 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 665 msi_s_phandle, intc_phandles, 666 aplic_s_phandle, 0, 667 false, num_harts); 668 669 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 670 671 if (!socket) { 672 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 673 memmap[VIRT_PLATFORM_BUS].base, 674 memmap[VIRT_PLATFORM_BUS].size, 675 VIRT_PLATFORM_BUS_IRQ); 676 } 677 678 aplic_phandles[socket] = aplic_s_phandle; 679 } 680 681 static void create_fdt_pmu(RISCVVirtState *s) 682 { 683 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 684 MachineState *ms = MACHINE(s); 685 RISCVCPU hart = s->soc[0].harts[0]; 686 687 qemu_fdt_add_subnode(ms->fdt, pmu_name); 688 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 689 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 690 } 691 692 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 693 uint32_t *phandle, 694 uint32_t *irq_mmio_phandle, 695 uint32_t *irq_pcie_phandle, 696 uint32_t *irq_virtio_phandle, 697 uint32_t *msi_pcie_phandle) 698 { 699 int socket, phandle_pos; 700 MachineState *ms = MACHINE(s); 701 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 702 uint32_t xplic_phandles[MAX_NODES]; 703 g_autofree uint32_t *intc_phandles = NULL; 704 int socket_count = riscv_socket_count(ms); 705 706 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 707 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 708 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 709 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 710 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 711 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 712 713 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 714 715 phandle_pos = ms->smp.cpus; 716 for (socket = (socket_count - 1); socket >= 0; socket--) { 717 g_autofree char *clust_name = NULL; 718 phandle_pos -= s->soc[socket].num_harts; 719 720 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 721 qemu_fdt_add_subnode(ms->fdt, clust_name); 722 723 create_fdt_socket_cpus(s, socket, clust_name, phandle, 724 &intc_phandles[phandle_pos]); 725 726 create_fdt_socket_memory(s, memmap, socket); 727 728 if (tcg_enabled()) { 729 if (s->have_aclint) { 730 create_fdt_socket_aclint(s, memmap, socket, 731 &intc_phandles[phandle_pos]); 732 } else { 733 create_fdt_socket_clint(s, memmap, socket, 734 &intc_phandles[phandle_pos]); 735 } 736 } 737 } 738 739 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 740 create_fdt_imsic(s, memmap, phandle, intc_phandles, 741 &msi_m_phandle, &msi_s_phandle); 742 *msi_pcie_phandle = msi_s_phandle; 743 } 744 745 /* KVM AIA only has one APLIC instance */ 746 if (kvm_enabled() && virt_use_kvm_aia(s)) { 747 create_fdt_socket_aplic(s, memmap, 0, 748 msi_m_phandle, msi_s_phandle, phandle, 749 &intc_phandles[0], xplic_phandles, 750 ms->smp.cpus); 751 } else { 752 phandle_pos = ms->smp.cpus; 753 for (socket = (socket_count - 1); socket >= 0; socket--) { 754 phandle_pos -= s->soc[socket].num_harts; 755 756 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 757 create_fdt_socket_plic(s, memmap, socket, phandle, 758 &intc_phandles[phandle_pos], 759 xplic_phandles); 760 } else { 761 create_fdt_socket_aplic(s, memmap, socket, 762 msi_m_phandle, msi_s_phandle, phandle, 763 &intc_phandles[phandle_pos], 764 xplic_phandles, 765 s->soc[socket].num_harts); 766 } 767 } 768 } 769 770 if (kvm_enabled() && virt_use_kvm_aia(s)) { 771 *irq_mmio_phandle = xplic_phandles[0]; 772 *irq_virtio_phandle = xplic_phandles[0]; 773 *irq_pcie_phandle = xplic_phandles[0]; 774 } else { 775 for (socket = 0; socket < socket_count; socket++) { 776 if (socket == 0) { 777 *irq_mmio_phandle = xplic_phandles[socket]; 778 *irq_virtio_phandle = xplic_phandles[socket]; 779 *irq_pcie_phandle = xplic_phandles[socket]; 780 } 781 if (socket == 1) { 782 *irq_virtio_phandle = xplic_phandles[socket]; 783 *irq_pcie_phandle = xplic_phandles[socket]; 784 } 785 if (socket == 2) { 786 *irq_pcie_phandle = xplic_phandles[socket]; 787 } 788 } 789 } 790 791 riscv_socket_fdt_write_distance_matrix(ms); 792 } 793 794 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 795 uint32_t irq_virtio_phandle) 796 { 797 int i; 798 MachineState *ms = MACHINE(s); 799 800 for (i = 0; i < VIRTIO_COUNT; i++) { 801 g_autofree char *name = g_strdup_printf("/soc/virtio_mmio@%lx", 802 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 803 804 qemu_fdt_add_subnode(ms->fdt, name); 805 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 806 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 807 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 808 0x0, memmap[VIRT_VIRTIO].size); 809 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 810 irq_virtio_phandle); 811 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 812 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 813 VIRTIO_IRQ + i); 814 } else { 815 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 816 VIRTIO_IRQ + i, 0x4); 817 } 818 } 819 } 820 821 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 822 uint32_t irq_pcie_phandle, 823 uint32_t msi_pcie_phandle) 824 { 825 g_autofree char *name = NULL; 826 MachineState *ms = MACHINE(s); 827 828 name = g_strdup_printf("/soc/pci@%lx", 829 (long) memmap[VIRT_PCIE_ECAM].base); 830 qemu_fdt_add_subnode(ms->fdt, name); 831 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 832 FDT_PCI_ADDR_CELLS); 833 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 834 FDT_PCI_INT_CELLS); 835 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 836 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 837 "pci-host-ecam-generic"); 838 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 839 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 840 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 841 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 842 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 843 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 844 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 845 } 846 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 847 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 848 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 849 1, FDT_PCI_RANGE_IOPORT, 2, 0, 850 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 851 1, FDT_PCI_RANGE_MMIO, 852 2, memmap[VIRT_PCIE_MMIO].base, 853 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 854 1, FDT_PCI_RANGE_MMIO_64BIT, 855 2, virt_high_pcie_memmap.base, 856 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 857 858 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 859 } 860 861 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 862 uint32_t *phandle) 863 { 864 char *name; 865 uint32_t test_phandle; 866 MachineState *ms = MACHINE(s); 867 868 test_phandle = (*phandle)++; 869 name = g_strdup_printf("/soc/test@%lx", 870 (long)memmap[VIRT_TEST].base); 871 qemu_fdt_add_subnode(ms->fdt, name); 872 { 873 static const char * const compat[3] = { 874 "sifive,test1", "sifive,test0", "syscon" 875 }; 876 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 877 (char **)&compat, ARRAY_SIZE(compat)); 878 } 879 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 880 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 881 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 882 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 883 g_free(name); 884 885 name = g_strdup_printf("/reboot"); 886 qemu_fdt_add_subnode(ms->fdt, name); 887 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 888 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 889 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 890 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 891 g_free(name); 892 893 name = g_strdup_printf("/poweroff"); 894 qemu_fdt_add_subnode(ms->fdt, name); 895 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 896 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 897 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 898 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 899 g_free(name); 900 } 901 902 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 903 uint32_t irq_mmio_phandle) 904 { 905 g_autofree char *name = NULL; 906 MachineState *ms = MACHINE(s); 907 908 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 909 qemu_fdt_add_subnode(ms->fdt, name); 910 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 911 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 912 0x0, memmap[VIRT_UART0].base, 913 0x0, memmap[VIRT_UART0].size); 914 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 915 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 916 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 917 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 918 } else { 919 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 920 } 921 922 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 923 } 924 925 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 926 uint32_t irq_mmio_phandle) 927 { 928 g_autofree char *name = NULL; 929 MachineState *ms = MACHINE(s); 930 931 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 932 qemu_fdt_add_subnode(ms->fdt, name); 933 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 934 "google,goldfish-rtc"); 935 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 936 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 937 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 938 irq_mmio_phandle); 939 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 940 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 941 } else { 942 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 943 } 944 } 945 946 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 947 { 948 MachineState *ms = MACHINE(s); 949 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 950 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 951 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 952 953 qemu_fdt_add_subnode(ms->fdt, name); 954 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 955 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 956 2, flashbase, 2, flashsize, 957 2, flashbase + flashsize, 2, flashsize); 958 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 959 } 960 961 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 962 { 963 MachineState *ms = MACHINE(s); 964 hwaddr base = memmap[VIRT_FW_CFG].base; 965 hwaddr size = memmap[VIRT_FW_CFG].size; 966 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 967 968 qemu_fdt_add_subnode(ms->fdt, nodename); 969 qemu_fdt_setprop_string(ms->fdt, nodename, 970 "compatible", "qemu,fw-cfg-mmio"); 971 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 972 2, base, 2, size); 973 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 974 } 975 976 static void finalize_fdt(RISCVVirtState *s) 977 { 978 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 979 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 980 981 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 982 &irq_pcie_phandle, &irq_virtio_phandle, 983 &msi_pcie_phandle); 984 985 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 986 987 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); 988 989 create_fdt_reset(s, virt_memmap, &phandle); 990 991 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 992 993 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 994 } 995 996 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 997 { 998 MachineState *ms = MACHINE(s); 999 uint8_t rng_seed[32]; 1000 1001 ms->fdt = create_device_tree(&s->fdt_size); 1002 if (!ms->fdt) { 1003 error_report("create_device_tree() failed"); 1004 exit(1); 1005 } 1006 1007 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1008 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1009 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1010 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1011 1012 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1013 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1014 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1015 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1016 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1017 1018 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1019 1020 /* Pass seed to RNG */ 1021 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1022 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1023 rng_seed, sizeof(rng_seed)); 1024 1025 create_fdt_flash(s, memmap); 1026 create_fdt_fw_cfg(s, memmap); 1027 create_fdt_pmu(s); 1028 } 1029 1030 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1031 DeviceState *irqchip, 1032 RISCVVirtState *s) 1033 { 1034 DeviceState *dev; 1035 MemoryRegion *ecam_alias, *ecam_reg; 1036 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1037 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1038 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1039 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1040 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1041 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1042 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1043 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1044 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1045 qemu_irq irq; 1046 int i; 1047 1048 dev = qdev_new(TYPE_GPEX_HOST); 1049 1050 /* Set GPEX object properties for the virt machine */ 1051 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, 1052 ecam_base, NULL); 1053 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, 1054 ecam_size, NULL); 1055 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1056 PCI_HOST_BELOW_4G_MMIO_BASE, 1057 mmio_base, NULL); 1058 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, 1059 mmio_size, NULL); 1060 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1061 PCI_HOST_ABOVE_4G_MMIO_BASE, 1062 high_mmio_base, NULL); 1063 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1064 high_mmio_size, NULL); 1065 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, 1066 pio_base, NULL); 1067 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, 1068 pio_size, NULL); 1069 1070 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1071 1072 ecam_alias = g_new0(MemoryRegion, 1); 1073 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1074 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1075 ecam_reg, 0, ecam_size); 1076 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1077 1078 mmio_alias = g_new0(MemoryRegion, 1); 1079 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1080 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1081 mmio_reg, mmio_base, mmio_size); 1082 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1083 1084 /* Map high MMIO space */ 1085 high_mmio_alias = g_new0(MemoryRegion, 1); 1086 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1087 mmio_reg, high_mmio_base, high_mmio_size); 1088 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1089 high_mmio_alias); 1090 1091 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1092 1093 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1094 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1095 1096 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1097 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1098 } 1099 1100 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; 1101 return dev; 1102 } 1103 1104 static FWCfgState *create_fw_cfg(const MachineState *ms) 1105 { 1106 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1107 FWCfgState *fw_cfg; 1108 1109 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1110 &address_space_memory); 1111 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1112 1113 return fw_cfg; 1114 } 1115 1116 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1117 int base_hartid, int hart_count) 1118 { 1119 DeviceState *ret; 1120 g_autofree char *plic_hart_config = NULL; 1121 1122 /* Per-socket PLIC hart topology configuration string */ 1123 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1124 1125 /* Per-socket PLIC */ 1126 ret = sifive_plic_create( 1127 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1128 plic_hart_config, hart_count, base_hartid, 1129 VIRT_IRQCHIP_NUM_SOURCES, 1130 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1131 VIRT_PLIC_PRIORITY_BASE, 1132 VIRT_PLIC_PENDING_BASE, 1133 VIRT_PLIC_ENABLE_BASE, 1134 VIRT_PLIC_ENABLE_STRIDE, 1135 VIRT_PLIC_CONTEXT_BASE, 1136 VIRT_PLIC_CONTEXT_STRIDE, 1137 memmap[VIRT_PLIC].size); 1138 1139 return ret; 1140 } 1141 1142 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1143 const MemMapEntry *memmap, int socket, 1144 int base_hartid, int hart_count) 1145 { 1146 int i; 1147 hwaddr addr; 1148 uint32_t guest_bits; 1149 DeviceState *aplic_s = NULL; 1150 DeviceState *aplic_m = NULL; 1151 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1152 1153 if (msimode) { 1154 if (!kvm_enabled()) { 1155 /* Per-socket M-level IMSICs */ 1156 addr = memmap[VIRT_IMSIC_M].base + 1157 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1158 for (i = 0; i < hart_count; i++) { 1159 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1160 base_hartid + i, true, 1, 1161 VIRT_IRQCHIP_NUM_MSIS); 1162 } 1163 } 1164 1165 /* Per-socket S-level IMSICs */ 1166 guest_bits = imsic_num_bits(aia_guests + 1); 1167 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1168 for (i = 0; i < hart_count; i++) { 1169 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1170 base_hartid + i, false, 1 + aia_guests, 1171 VIRT_IRQCHIP_NUM_MSIS); 1172 } 1173 } 1174 1175 if (!kvm_enabled()) { 1176 /* Per-socket M-level APLIC */ 1177 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1178 socket * memmap[VIRT_APLIC_M].size, 1179 memmap[VIRT_APLIC_M].size, 1180 (msimode) ? 0 : base_hartid, 1181 (msimode) ? 0 : hart_count, 1182 VIRT_IRQCHIP_NUM_SOURCES, 1183 VIRT_IRQCHIP_NUM_PRIO_BITS, 1184 msimode, true, NULL); 1185 } 1186 1187 /* Per-socket S-level APLIC */ 1188 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1189 socket * memmap[VIRT_APLIC_S].size, 1190 memmap[VIRT_APLIC_S].size, 1191 (msimode) ? 0 : base_hartid, 1192 (msimode) ? 0 : hart_count, 1193 VIRT_IRQCHIP_NUM_SOURCES, 1194 VIRT_IRQCHIP_NUM_PRIO_BITS, 1195 msimode, false, aplic_m); 1196 1197 return kvm_enabled() ? aplic_s : aplic_m; 1198 } 1199 1200 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1201 { 1202 DeviceState *dev; 1203 SysBusDevice *sysbus; 1204 const MemMapEntry *memmap = virt_memmap; 1205 int i; 1206 MemoryRegion *sysmem = get_system_memory(); 1207 1208 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1209 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1210 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1211 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1212 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1213 s->platform_bus_dev = dev; 1214 1215 sysbus = SYS_BUS_DEVICE(dev); 1216 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1217 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1218 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1219 } 1220 1221 memory_region_add_subregion(sysmem, 1222 memmap[VIRT_PLATFORM_BUS].base, 1223 sysbus_mmio_get_region(sysbus, 0)); 1224 } 1225 1226 static void virt_machine_done(Notifier *notifier, void *data) 1227 { 1228 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1229 machine_done); 1230 const MemMapEntry *memmap = virt_memmap; 1231 MachineState *machine = MACHINE(s); 1232 target_ulong start_addr = memmap[VIRT_DRAM].base; 1233 target_ulong firmware_end_addr, kernel_start_addr; 1234 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1235 uint64_t fdt_load_addr; 1236 uint64_t kernel_entry = 0; 1237 BlockBackend *pflash_blk0; 1238 1239 /* 1240 * An user provided dtb must include everything, including 1241 * dynamic sysbus devices. Our FDT needs to be finalized. 1242 */ 1243 if (machine->dtb == NULL) { 1244 finalize_fdt(s); 1245 } 1246 1247 /* 1248 * Only direct boot kernel is currently supported for KVM VM, 1249 * so the "-bios" parameter is not supported when KVM is enabled. 1250 */ 1251 if (kvm_enabled()) { 1252 if (machine->firmware) { 1253 if (strcmp(machine->firmware, "none")) { 1254 error_report("Machine mode firmware is not supported in " 1255 "combination with KVM."); 1256 exit(1); 1257 } 1258 } else { 1259 machine->firmware = g_strdup("none"); 1260 } 1261 } 1262 1263 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1264 start_addr, NULL); 1265 1266 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1267 if (pflash_blk0) { 1268 if (machine->firmware && !strcmp(machine->firmware, "none") && 1269 !kvm_enabled()) { 1270 /* 1271 * Pflash was supplied but bios is none and not KVM guest, 1272 * let's overwrite the address we jump to after reset to 1273 * the base of the flash. 1274 */ 1275 start_addr = virt_memmap[VIRT_FLASH].base; 1276 } else { 1277 /* 1278 * Pflash was supplied but either KVM guest or bios is not none. 1279 * In this case, base of the flash would contain S-mode payload. 1280 */ 1281 riscv_setup_firmware_boot(machine); 1282 kernel_entry = virt_memmap[VIRT_FLASH].base; 1283 } 1284 } 1285 1286 if (machine->kernel_filename && !kernel_entry) { 1287 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1288 firmware_end_addr); 1289 1290 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1291 kernel_start_addr, true, NULL); 1292 } 1293 1294 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1295 memmap[VIRT_DRAM].size, 1296 machine); 1297 riscv_load_fdt(fdt_load_addr, machine->fdt); 1298 1299 /* load the reset vector */ 1300 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1301 virt_memmap[VIRT_MROM].base, 1302 virt_memmap[VIRT_MROM].size, kernel_entry, 1303 fdt_load_addr); 1304 1305 /* 1306 * Only direct boot kernel is currently supported for KVM VM, 1307 * So here setup kernel start address and fdt address. 1308 * TODO:Support firmware loading and integrate to TCG start 1309 */ 1310 if (kvm_enabled()) { 1311 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1312 } 1313 1314 if (virt_is_acpi_enabled(s)) { 1315 virt_acpi_setup(s); 1316 } 1317 } 1318 1319 static void virt_machine_init(MachineState *machine) 1320 { 1321 const MemMapEntry *memmap = virt_memmap; 1322 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1323 MemoryRegion *system_memory = get_system_memory(); 1324 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1325 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1326 int i, base_hartid, hart_count; 1327 int socket_count = riscv_socket_count(machine); 1328 1329 /* Check socket count limit */ 1330 if (VIRT_SOCKETS_MAX < socket_count) { 1331 error_report("number of sockets/nodes should be less than %d", 1332 VIRT_SOCKETS_MAX); 1333 exit(1); 1334 } 1335 1336 if (!tcg_enabled() && s->have_aclint) { 1337 error_report("'aclint' is only available with TCG acceleration"); 1338 exit(1); 1339 } 1340 1341 /* Initialize sockets */ 1342 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1343 for (i = 0; i < socket_count; i++) { 1344 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1345 1346 if (!riscv_socket_check_hartids(machine, i)) { 1347 error_report("discontinuous hartids in socket%d", i); 1348 exit(1); 1349 } 1350 1351 base_hartid = riscv_socket_first_hartid(machine, i); 1352 if (base_hartid < 0) { 1353 error_report("can't find hartid base for socket%d", i); 1354 exit(1); 1355 } 1356 1357 hart_count = riscv_socket_hart_count(machine, i); 1358 if (hart_count < 0) { 1359 error_report("can't find hart count for socket%d", i); 1360 exit(1); 1361 } 1362 1363 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1364 TYPE_RISCV_HART_ARRAY); 1365 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1366 machine->cpu_type, &error_abort); 1367 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1368 base_hartid, &error_abort); 1369 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1370 hart_count, &error_abort); 1371 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1372 1373 if (tcg_enabled()) { 1374 if (s->have_aclint) { 1375 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1376 /* Per-socket ACLINT MTIMER */ 1377 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1378 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1379 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1380 base_hartid, hart_count, 1381 RISCV_ACLINT_DEFAULT_MTIMECMP, 1382 RISCV_ACLINT_DEFAULT_MTIME, 1383 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1384 } else { 1385 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1386 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1387 i * memmap[VIRT_CLINT].size, 1388 base_hartid, hart_count, false); 1389 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1390 i * memmap[VIRT_CLINT].size + 1391 RISCV_ACLINT_SWI_SIZE, 1392 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1393 base_hartid, hart_count, 1394 RISCV_ACLINT_DEFAULT_MTIMECMP, 1395 RISCV_ACLINT_DEFAULT_MTIME, 1396 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1397 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1398 i * memmap[VIRT_ACLINT_SSWI].size, 1399 base_hartid, hart_count, true); 1400 } 1401 } else { 1402 /* Per-socket SiFive CLINT */ 1403 riscv_aclint_swi_create( 1404 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1405 base_hartid, hart_count, false); 1406 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1407 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1408 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1409 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1410 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1411 } 1412 } 1413 1414 /* Per-socket interrupt controller */ 1415 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1416 s->irqchip[i] = virt_create_plic(memmap, i, 1417 base_hartid, hart_count); 1418 } else { 1419 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1420 memmap, i, base_hartid, 1421 hart_count); 1422 } 1423 1424 /* Try to use different IRQCHIP instance based device type */ 1425 if (i == 0) { 1426 mmio_irqchip = s->irqchip[i]; 1427 virtio_irqchip = s->irqchip[i]; 1428 pcie_irqchip = s->irqchip[i]; 1429 } 1430 if (i == 1) { 1431 virtio_irqchip = s->irqchip[i]; 1432 pcie_irqchip = s->irqchip[i]; 1433 } 1434 if (i == 2) { 1435 pcie_irqchip = s->irqchip[i]; 1436 } 1437 } 1438 1439 if (kvm_enabled() && virt_use_kvm_aia(s)) { 1440 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1441 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1442 memmap[VIRT_APLIC_S].base, 1443 memmap[VIRT_IMSIC_S].base, 1444 s->aia_guests); 1445 } 1446 1447 if (riscv_is_32bit(&s->soc[0])) { 1448 #if HOST_LONG_BITS == 64 1449 /* limit RAM size in a 32-bit system */ 1450 if (machine->ram_size > 10 * GiB) { 1451 machine->ram_size = 10 * GiB; 1452 error_report("Limiting RAM size to 10 GiB"); 1453 } 1454 #endif 1455 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1456 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1457 } else { 1458 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1459 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1460 virt_high_pcie_memmap.base = 1461 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1462 } 1463 1464 s->memmap = virt_memmap; 1465 1466 /* register system main memory (actual RAM) */ 1467 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1468 machine->ram); 1469 1470 /* boot rom */ 1471 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1472 memmap[VIRT_MROM].size, &error_fatal); 1473 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1474 mask_rom); 1475 1476 /* 1477 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1478 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1479 */ 1480 s->fw_cfg = create_fw_cfg(machine); 1481 rom_set_fw(s->fw_cfg); 1482 1483 /* SiFive Test MMIO device */ 1484 sifive_test_create(memmap[VIRT_TEST].base); 1485 1486 /* VirtIO MMIO devices */ 1487 for (i = 0; i < VIRTIO_COUNT; i++) { 1488 sysbus_create_simple("virtio-mmio", 1489 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1490 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1491 } 1492 1493 gpex_pcie_init(system_memory, pcie_irqchip, s); 1494 1495 create_platform_bus(s, mmio_irqchip); 1496 1497 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1498 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1499 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1500 1501 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1502 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1503 1504 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1505 /* Map legacy -drive if=pflash to machine properties */ 1506 pflash_cfi01_legacy_drive(s->flash[i], 1507 drive_get(IF_PFLASH, 0, i)); 1508 } 1509 virt_flash_map(s, system_memory); 1510 1511 /* load/create device tree */ 1512 if (machine->dtb) { 1513 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1514 if (!machine->fdt) { 1515 error_report("load_device_tree() failed"); 1516 exit(1); 1517 } 1518 } else { 1519 create_fdt(s, memmap); 1520 } 1521 1522 s->machine_done.notify = virt_machine_done; 1523 qemu_add_machine_init_done_notifier(&s->machine_done); 1524 } 1525 1526 static void virt_machine_instance_init(Object *obj) 1527 { 1528 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1529 1530 virt_flash_create(s); 1531 1532 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1533 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1534 s->acpi = ON_OFF_AUTO_AUTO; 1535 } 1536 1537 static char *virt_get_aia_guests(Object *obj, Error **errp) 1538 { 1539 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1540 char val[32]; 1541 1542 sprintf(val, "%d", s->aia_guests); 1543 return g_strdup(val); 1544 } 1545 1546 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1547 { 1548 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1549 1550 s->aia_guests = atoi(val); 1551 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1552 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1553 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1554 VIRT_IRQCHIP_MAX_GUESTS); 1555 } 1556 } 1557 1558 static char *virt_get_aia(Object *obj, Error **errp) 1559 { 1560 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1561 const char *val; 1562 1563 switch (s->aia_type) { 1564 case VIRT_AIA_TYPE_APLIC: 1565 val = "aplic"; 1566 break; 1567 case VIRT_AIA_TYPE_APLIC_IMSIC: 1568 val = "aplic-imsic"; 1569 break; 1570 default: 1571 val = "none"; 1572 break; 1573 }; 1574 1575 return g_strdup(val); 1576 } 1577 1578 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1579 { 1580 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1581 1582 if (!strcmp(val, "none")) { 1583 s->aia_type = VIRT_AIA_TYPE_NONE; 1584 } else if (!strcmp(val, "aplic")) { 1585 s->aia_type = VIRT_AIA_TYPE_APLIC; 1586 } else if (!strcmp(val, "aplic-imsic")) { 1587 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1588 } else { 1589 error_setg(errp, "Invalid AIA interrupt controller type"); 1590 error_append_hint(errp, "Valid values are none, aplic, and " 1591 "aplic-imsic.\n"); 1592 } 1593 } 1594 1595 static bool virt_get_aclint(Object *obj, Error **errp) 1596 { 1597 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1598 1599 return s->have_aclint; 1600 } 1601 1602 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1603 { 1604 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1605 1606 s->have_aclint = value; 1607 } 1608 1609 bool virt_is_acpi_enabled(RISCVVirtState *s) 1610 { 1611 return s->acpi != ON_OFF_AUTO_OFF; 1612 } 1613 1614 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1615 void *opaque, Error **errp) 1616 { 1617 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1618 OnOffAuto acpi = s->acpi; 1619 1620 visit_type_OnOffAuto(v, name, &acpi, errp); 1621 } 1622 1623 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1624 void *opaque, Error **errp) 1625 { 1626 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1627 1628 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1629 } 1630 1631 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1632 DeviceState *dev) 1633 { 1634 MachineClass *mc = MACHINE_GET_CLASS(machine); 1635 1636 if (device_is_dynamic_sysbus(mc, dev)) { 1637 return HOTPLUG_HANDLER(machine); 1638 } 1639 return NULL; 1640 } 1641 1642 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1643 DeviceState *dev, Error **errp) 1644 { 1645 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1646 1647 if (s->platform_bus_dev) { 1648 MachineClass *mc = MACHINE_GET_CLASS(s); 1649 1650 if (device_is_dynamic_sysbus(mc, dev)) { 1651 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1652 SYS_BUS_DEVICE(dev)); 1653 } 1654 } 1655 } 1656 1657 static void virt_machine_class_init(ObjectClass *oc, void *data) 1658 { 1659 char str[128]; 1660 MachineClass *mc = MACHINE_CLASS(oc); 1661 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1662 1663 mc->desc = "RISC-V VirtIO board"; 1664 mc->init = virt_machine_init; 1665 mc->max_cpus = VIRT_CPUS_MAX; 1666 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1667 mc->pci_allow_0_address = true; 1668 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1669 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1670 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1671 mc->numa_mem_supported = true; 1672 /* platform instead of architectural choice */ 1673 mc->cpu_cluster_has_numa_boundary = true; 1674 mc->default_ram_id = "riscv_virt_board.ram"; 1675 assert(!mc->get_hotplug_handler); 1676 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1677 1678 hc->plug = virt_machine_device_plug_cb; 1679 1680 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1681 #ifdef CONFIG_TPM 1682 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1683 #endif 1684 1685 1686 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1687 virt_set_aclint); 1688 object_class_property_set_description(oc, "aclint", 1689 "(TCG only) Set on/off to " 1690 "enable/disable emulating " 1691 "ACLINT devices"); 1692 1693 object_class_property_add_str(oc, "aia", virt_get_aia, 1694 virt_set_aia); 1695 object_class_property_set_description(oc, "aia", 1696 "Set type of AIA interrupt " 1697 "controller. Valid values are " 1698 "none, aplic, and aplic-imsic."); 1699 1700 object_class_property_add_str(oc, "aia-guests", 1701 virt_get_aia_guests, 1702 virt_set_aia_guests); 1703 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1704 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1705 object_class_property_set_description(oc, "aia-guests", str); 1706 object_class_property_add(oc, "acpi", "OnOffAuto", 1707 virt_get_acpi, virt_set_acpi, 1708 NULL, NULL); 1709 object_class_property_set_description(oc, "acpi", 1710 "Enable ACPI"); 1711 } 1712 1713 static const TypeInfo virt_machine_typeinfo = { 1714 .name = MACHINE_TYPE_NAME("virt"), 1715 .parent = TYPE_MACHINE, 1716 .class_init = virt_machine_class_init, 1717 .instance_init = virt_machine_instance_init, 1718 .instance_size = sizeof(RISCVVirtState), 1719 .interfaces = (InterfaceInfo[]) { 1720 { TYPE_HOTPLUG_HANDLER }, 1721 { } 1722 }, 1723 }; 1724 1725 static void virt_machine_init_register_types(void) 1726 { 1727 type_register_static(&virt_machine_typeinfo); 1728 } 1729 1730 type_init(virt_machine_init_register_types) 1731