1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/log.h" 24 #include "qemu/error-report.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/riscv/riscv_hart.h" 33 #include "hw/riscv/virt.h" 34 #include "hw/riscv/boot.h" 35 #include "hw/riscv/numa.h" 36 #include "hw/intc/sifive_clint.h" 37 #include "hw/intc/sifive_plic.h" 38 #include "hw/misc/sifive_test.h" 39 #include "chardev/char.h" 40 #include "sysemu/arch_init.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/sysemu.h" 43 #include "hw/pci/pci.h" 44 #include "hw/pci-host/gpex.h" 45 #include "hw/display/ramfb.h" 46 47 static const MemMapEntry virt_memmap[] = { 48 [VIRT_DEBUG] = { 0x0, 0x100 }, 49 [VIRT_MROM] = { 0x1000, 0xf000 }, 50 [VIRT_TEST] = { 0x100000, 0x1000 }, 51 [VIRT_RTC] = { 0x101000, 0x1000 }, 52 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 53 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 54 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 55 [VIRT_UART0] = { 0x10000000, 0x100 }, 56 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 57 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 58 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 59 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 60 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 61 [VIRT_DRAM] = { 0x80000000, 0x0 }, 62 }; 63 64 /* PCIe high mmio is fixed for RV32 */ 65 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 66 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 67 68 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 69 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 70 71 static MemMapEntry virt_high_pcie_memmap; 72 73 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 74 75 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 76 const char *name, 77 const char *alias_prop_name) 78 { 79 /* 80 * Create a single flash device. We use the same parameters as 81 * the flash devices on the ARM virt board. 82 */ 83 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 84 85 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 86 qdev_prop_set_uint8(dev, "width", 4); 87 qdev_prop_set_uint8(dev, "device-width", 2); 88 qdev_prop_set_bit(dev, "big-endian", false); 89 qdev_prop_set_uint16(dev, "id0", 0x89); 90 qdev_prop_set_uint16(dev, "id1", 0x18); 91 qdev_prop_set_uint16(dev, "id2", 0x00); 92 qdev_prop_set_uint16(dev, "id3", 0x00); 93 qdev_prop_set_string(dev, "name", name); 94 95 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 96 object_property_add_alias(OBJECT(s), alias_prop_name, 97 OBJECT(dev), "drive"); 98 99 return PFLASH_CFI01(dev); 100 } 101 102 static void virt_flash_create(RISCVVirtState *s) 103 { 104 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 105 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 106 } 107 108 static void virt_flash_map1(PFlashCFI01 *flash, 109 hwaddr base, hwaddr size, 110 MemoryRegion *sysmem) 111 { 112 DeviceState *dev = DEVICE(flash); 113 114 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 115 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 116 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 117 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 118 119 memory_region_add_subregion(sysmem, base, 120 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 121 0)); 122 } 123 124 static void virt_flash_map(RISCVVirtState *s, 125 MemoryRegion *sysmem) 126 { 127 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 128 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 129 130 virt_flash_map1(s->flash[0], flashbase, flashsize, 131 sysmem); 132 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 133 sysmem); 134 } 135 136 static void create_pcie_irq_map(void *fdt, char *nodename, 137 uint32_t plic_phandle) 138 { 139 int pin, dev; 140 uint32_t 141 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; 142 uint32_t *irq_map = full_irq_map; 143 144 /* This code creates a standard swizzle of interrupts such that 145 * each device's first interrupt is based on it's PCI_SLOT number. 146 * (See pci_swizzle_map_irq_fn()) 147 * 148 * We only need one entry per interrupt in the table (not one per 149 * possible slot) seeing the interrupt-map-mask will allow the table 150 * to wrap to any number of devices. 151 */ 152 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 153 int devfn = dev * 0x8; 154 155 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 156 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 157 int i = 0; 158 159 irq_map[i] = cpu_to_be32(devfn << 8); 160 161 i += FDT_PCI_ADDR_CELLS; 162 irq_map[i] = cpu_to_be32(pin + 1); 163 164 i += FDT_PCI_INT_CELLS; 165 irq_map[i++] = cpu_to_be32(plic_phandle); 166 167 i += FDT_PLIC_ADDR_CELLS; 168 irq_map[i] = cpu_to_be32(irq_nr); 169 170 irq_map += FDT_INT_MAP_WIDTH; 171 } 172 } 173 174 qemu_fdt_setprop(fdt, nodename, "interrupt-map", 175 full_irq_map, sizeof(full_irq_map)); 176 177 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 178 0x1800, 0, 0, 0x7); 179 } 180 181 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 182 uint64_t mem_size, const char *cmdline, bool is_32_bit) 183 { 184 void *fdt; 185 int i, cpu, socket; 186 MachineState *mc = MACHINE(s); 187 uint64_t addr, size; 188 uint32_t *clint_cells, *plic_cells; 189 unsigned long clint_addr, plic_addr; 190 uint32_t plic_phandle[MAX_NODES]; 191 uint32_t cpu_phandle, intc_phandle, test_phandle; 192 uint32_t phandle = 1, plic_mmio_phandle = 1; 193 uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; 194 char *mem_name, *cpu_name, *core_name, *intc_name; 195 char *name, *clint_name, *plic_name, *clust_name; 196 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 197 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 198 199 if (mc->dtb) { 200 fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 201 if (!fdt) { 202 error_report("load_device_tree() failed"); 203 exit(1); 204 } 205 goto update_bootargs; 206 } else { 207 fdt = mc->fdt = create_device_tree(&s->fdt_size); 208 if (!fdt) { 209 error_report("create_device_tree() failed"); 210 exit(1); 211 } 212 } 213 214 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); 215 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); 216 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 217 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 218 219 qemu_fdt_add_subnode(fdt, "/soc"); 220 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 221 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 222 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 223 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 224 225 qemu_fdt_add_subnode(fdt, "/cpus"); 226 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 227 SIFIVE_CLINT_TIMEBASE_FREQ); 228 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 229 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 230 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 231 232 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 233 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 234 qemu_fdt_add_subnode(fdt, clust_name); 235 236 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 237 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 238 239 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 240 cpu_phandle = phandle++; 241 242 cpu_name = g_strdup_printf("/cpus/cpu@%d", 243 s->soc[socket].hartid_base + cpu); 244 qemu_fdt_add_subnode(fdt, cpu_name); 245 if (is_32_bit) { 246 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 247 } else { 248 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 249 } 250 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 251 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 252 g_free(name); 253 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 254 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 255 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 256 s->soc[socket].hartid_base + cpu); 257 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 258 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 259 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 260 261 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 262 qemu_fdt_add_subnode(fdt, intc_name); 263 intc_phandle = phandle++; 264 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 265 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 266 "riscv,cpu-intc"); 267 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 268 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 269 270 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 271 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 272 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 273 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 274 275 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 276 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 277 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 278 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 279 280 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 281 qemu_fdt_add_subnode(fdt, core_name); 282 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 283 284 g_free(core_name); 285 g_free(intc_name); 286 g_free(cpu_name); 287 } 288 289 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 290 size = riscv_socket_mem_size(mc, socket); 291 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 292 qemu_fdt_add_subnode(fdt, mem_name); 293 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 294 addr >> 32, addr, size >> 32, size); 295 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 296 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 297 g_free(mem_name); 298 299 clint_addr = memmap[VIRT_CLINT].base + 300 (memmap[VIRT_CLINT].size * socket); 301 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 302 qemu_fdt_add_subnode(fdt, clint_name); 303 qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); 304 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 305 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 306 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 307 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 308 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 309 g_free(clint_name); 310 311 plic_phandle[socket] = phandle++; 312 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 313 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 314 qemu_fdt_add_subnode(fdt, plic_name); 315 qemu_fdt_setprop_cell(fdt, plic_name, 316 "#address-cells", FDT_PLIC_ADDR_CELLS); 317 qemu_fdt_setprop_cell(fdt, plic_name, 318 "#interrupt-cells", FDT_PLIC_INT_CELLS); 319 qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); 320 qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); 321 qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", 322 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 323 qemu_fdt_setprop_cells(fdt, plic_name, "reg", 324 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 325 qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 326 riscv_socket_fdt_write_id(mc, fdt, plic_name, socket); 327 qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]); 328 g_free(plic_name); 329 330 g_free(clint_cells); 331 g_free(plic_cells); 332 g_free(clust_name); 333 } 334 335 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 336 if (socket == 0) { 337 plic_mmio_phandle = plic_phandle[socket]; 338 plic_virtio_phandle = plic_phandle[socket]; 339 plic_pcie_phandle = plic_phandle[socket]; 340 } 341 if (socket == 1) { 342 plic_virtio_phandle = plic_phandle[socket]; 343 plic_pcie_phandle = plic_phandle[socket]; 344 } 345 if (socket == 2) { 346 plic_pcie_phandle = plic_phandle[socket]; 347 } 348 } 349 350 riscv_socket_fdt_write_distance_matrix(mc, fdt); 351 352 for (i = 0; i < VIRTIO_COUNT; i++) { 353 name = g_strdup_printf("/soc/virtio_mmio@%lx", 354 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 355 qemu_fdt_add_subnode(fdt, name); 356 qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); 357 qemu_fdt_setprop_cells(fdt, name, "reg", 358 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 359 0x0, memmap[VIRT_VIRTIO].size); 360 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", 361 plic_virtio_phandle); 362 qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); 363 g_free(name); 364 } 365 366 name = g_strdup_printf("/soc/pci@%lx", 367 (long) memmap[VIRT_PCIE_ECAM].base); 368 qemu_fdt_add_subnode(fdt, name); 369 qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); 370 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); 371 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); 372 qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); 373 qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); 374 qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); 375 qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, 376 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 377 qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); 378 qemu_fdt_setprop_cells(fdt, name, "reg", 0, 379 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 380 qemu_fdt_setprop_sized_cells(fdt, name, "ranges", 381 1, FDT_PCI_RANGE_IOPORT, 2, 0, 382 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 383 1, FDT_PCI_RANGE_MMIO, 384 2, memmap[VIRT_PCIE_MMIO].base, 385 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 386 1, FDT_PCI_RANGE_MMIO_64BIT, 387 2, virt_high_pcie_memmap.base, 388 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 389 390 create_pcie_irq_map(fdt, name, plic_pcie_phandle); 391 g_free(name); 392 393 test_phandle = phandle++; 394 name = g_strdup_printf("/soc/test@%lx", 395 (long)memmap[VIRT_TEST].base); 396 qemu_fdt_add_subnode(fdt, name); 397 { 398 const char compat[] = "sifive,test1\0sifive,test0\0syscon"; 399 qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat)); 400 } 401 qemu_fdt_setprop_cells(fdt, name, "reg", 402 0x0, memmap[VIRT_TEST].base, 403 0x0, memmap[VIRT_TEST].size); 404 qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); 405 test_phandle = qemu_fdt_get_phandle(fdt, name); 406 g_free(name); 407 408 name = g_strdup_printf("/soc/reboot"); 409 qemu_fdt_add_subnode(fdt, name); 410 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); 411 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 412 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 413 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); 414 g_free(name); 415 416 name = g_strdup_printf("/soc/poweroff"); 417 qemu_fdt_add_subnode(fdt, name); 418 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); 419 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 420 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 421 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); 422 g_free(name); 423 424 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 425 qemu_fdt_add_subnode(fdt, name); 426 qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); 427 qemu_fdt_setprop_cells(fdt, name, "reg", 428 0x0, memmap[VIRT_UART0].base, 429 0x0, memmap[VIRT_UART0].size); 430 qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); 431 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 432 qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); 433 434 qemu_fdt_add_subnode(fdt, "/chosen"); 435 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); 436 g_free(name); 437 438 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 439 qemu_fdt_add_subnode(fdt, name); 440 qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); 441 qemu_fdt_setprop_cells(fdt, name, "reg", 442 0x0, memmap[VIRT_RTC].base, 443 0x0, memmap[VIRT_RTC].size); 444 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 445 qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); 446 g_free(name); 447 448 name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); 449 qemu_fdt_add_subnode(mc->fdt, name); 450 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 451 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 452 2, flashbase, 2, flashsize, 453 2, flashbase + flashsize, 2, flashsize); 454 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 455 g_free(name); 456 457 update_bootargs: 458 if (cmdline) { 459 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 460 } 461 } 462 463 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 464 hwaddr ecam_base, hwaddr ecam_size, 465 hwaddr mmio_base, hwaddr mmio_size, 466 hwaddr high_mmio_base, 467 hwaddr high_mmio_size, 468 hwaddr pio_base, 469 DeviceState *plic) 470 { 471 DeviceState *dev; 472 MemoryRegion *ecam_alias, *ecam_reg; 473 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 474 qemu_irq irq; 475 int i; 476 477 dev = qdev_new(TYPE_GPEX_HOST); 478 479 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 480 481 ecam_alias = g_new0(MemoryRegion, 1); 482 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 483 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 484 ecam_reg, 0, ecam_size); 485 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 486 487 mmio_alias = g_new0(MemoryRegion, 1); 488 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 489 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 490 mmio_reg, mmio_base, mmio_size); 491 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 492 493 /* Map high MMIO space */ 494 high_mmio_alias = g_new0(MemoryRegion, 1); 495 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 496 mmio_reg, high_mmio_base, high_mmio_size); 497 memory_region_add_subregion(get_system_memory(), high_mmio_base, 498 high_mmio_alias); 499 500 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 501 502 for (i = 0; i < GPEX_NUM_IRQS; i++) { 503 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); 504 505 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 506 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 507 } 508 509 return dev; 510 } 511 512 static FWCfgState *create_fw_cfg(const MachineState *mc) 513 { 514 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 515 hwaddr size = virt_memmap[VIRT_FW_CFG].size; 516 FWCfgState *fw_cfg; 517 char *nodename; 518 519 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 520 &address_space_memory); 521 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 522 523 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 524 qemu_fdt_add_subnode(mc->fdt, nodename); 525 qemu_fdt_setprop_string(mc->fdt, nodename, 526 "compatible", "qemu,fw-cfg-mmio"); 527 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 528 2, base, 2, size); 529 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 530 g_free(nodename); 531 return fw_cfg; 532 } 533 534 static void virt_machine_init(MachineState *machine) 535 { 536 const MemMapEntry *memmap = virt_memmap; 537 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 538 MemoryRegion *system_memory = get_system_memory(); 539 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 540 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 541 char *plic_hart_config, *soc_name; 542 size_t plic_hart_config_len; 543 target_ulong start_addr = memmap[VIRT_DRAM].base; 544 target_ulong firmware_end_addr, kernel_start_addr; 545 uint32_t fdt_load_addr; 546 uint64_t kernel_entry; 547 DeviceState *mmio_plic, *virtio_plic, *pcie_plic; 548 int i, j, base_hartid, hart_count; 549 550 /* Check socket count limit */ 551 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 552 error_report("number of sockets/nodes should be less than %d", 553 VIRT_SOCKETS_MAX); 554 exit(1); 555 } 556 557 /* Initialize sockets */ 558 mmio_plic = virtio_plic = pcie_plic = NULL; 559 for (i = 0; i < riscv_socket_count(machine); i++) { 560 if (!riscv_socket_check_hartids(machine, i)) { 561 error_report("discontinuous hartids in socket%d", i); 562 exit(1); 563 } 564 565 base_hartid = riscv_socket_first_hartid(machine, i); 566 if (base_hartid < 0) { 567 error_report("can't find hartid base for socket%d", i); 568 exit(1); 569 } 570 571 hart_count = riscv_socket_hart_count(machine, i); 572 if (hart_count < 0) { 573 error_report("can't find hart count for socket%d", i); 574 exit(1); 575 } 576 577 soc_name = g_strdup_printf("soc%d", i); 578 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 579 TYPE_RISCV_HART_ARRAY); 580 g_free(soc_name); 581 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 582 machine->cpu_type, &error_abort); 583 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 584 base_hartid, &error_abort); 585 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 586 hart_count, &error_abort); 587 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 588 589 /* Per-socket CLINT */ 590 sifive_clint_create( 591 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 592 memmap[VIRT_CLINT].size, base_hartid, hart_count, 593 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 594 SIFIVE_CLINT_TIMEBASE_FREQ, true); 595 596 /* Per-socket PLIC hart topology configuration string */ 597 plic_hart_config_len = 598 (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count; 599 plic_hart_config = g_malloc0(plic_hart_config_len); 600 for (j = 0; j < hart_count; j++) { 601 if (j != 0) { 602 strncat(plic_hart_config, ",", plic_hart_config_len); 603 } 604 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, 605 plic_hart_config_len); 606 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); 607 } 608 609 /* Per-socket PLIC */ 610 s->plic[i] = sifive_plic_create( 611 memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, 612 plic_hart_config, base_hartid, 613 VIRT_PLIC_NUM_SOURCES, 614 VIRT_PLIC_NUM_PRIORITIES, 615 VIRT_PLIC_PRIORITY_BASE, 616 VIRT_PLIC_PENDING_BASE, 617 VIRT_PLIC_ENABLE_BASE, 618 VIRT_PLIC_ENABLE_STRIDE, 619 VIRT_PLIC_CONTEXT_BASE, 620 VIRT_PLIC_CONTEXT_STRIDE, 621 memmap[VIRT_PLIC].size); 622 g_free(plic_hart_config); 623 624 /* Try to use different PLIC instance based device type */ 625 if (i == 0) { 626 mmio_plic = s->plic[i]; 627 virtio_plic = s->plic[i]; 628 pcie_plic = s->plic[i]; 629 } 630 if (i == 1) { 631 virtio_plic = s->plic[i]; 632 pcie_plic = s->plic[i]; 633 } 634 if (i == 2) { 635 pcie_plic = s->plic[i]; 636 } 637 } 638 639 if (riscv_is_32bit(&s->soc[0])) { 640 #if HOST_LONG_BITS == 64 641 /* limit RAM size in a 32-bit system */ 642 if (machine->ram_size > 10 * GiB) { 643 machine->ram_size = 10 * GiB; 644 error_report("Limiting RAM size to 10 GiB"); 645 } 646 #endif 647 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 648 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 649 } else { 650 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 651 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 652 virt_high_pcie_memmap.base = 653 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 654 } 655 656 /* register system main memory (actual RAM) */ 657 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", 658 machine->ram_size, &error_fatal); 659 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 660 main_mem); 661 662 /* create device tree */ 663 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 664 riscv_is_32bit(&s->soc[0])); 665 666 /* boot rom */ 667 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 668 memmap[VIRT_MROM].size, &error_fatal); 669 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 670 mask_rom); 671 672 if (riscv_is_32bit(&s->soc[0])) { 673 firmware_end_addr = riscv_find_and_load_firmware(machine, 674 "opensbi-riscv32-generic-fw_dynamic.bin", 675 start_addr, NULL); 676 } else { 677 firmware_end_addr = riscv_find_and_load_firmware(machine, 678 "opensbi-riscv64-generic-fw_dynamic.bin", 679 start_addr, NULL); 680 } 681 682 if (machine->kernel_filename) { 683 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 684 firmware_end_addr); 685 686 kernel_entry = riscv_load_kernel(machine->kernel_filename, 687 kernel_start_addr, NULL); 688 689 if (machine->initrd_filename) { 690 hwaddr start; 691 hwaddr end = riscv_load_initrd(machine->initrd_filename, 692 machine->ram_size, kernel_entry, 693 &start); 694 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 695 "linux,initrd-start", start); 696 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 697 end); 698 } 699 } else { 700 /* 701 * If dynamic firmware is used, it doesn't know where is the next mode 702 * if kernel argument is not set. 703 */ 704 kernel_entry = 0; 705 } 706 707 if (drive_get(IF_PFLASH, 0, 0)) { 708 /* 709 * Pflash was supplied, let's overwrite the address we jump to after 710 * reset to the base of the flash. 711 */ 712 start_addr = virt_memmap[VIRT_FLASH].base; 713 } 714 715 /* 716 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 717 * tree cannot be altered and we get FDT_ERR_NOSPACE. 718 */ 719 s->fw_cfg = create_fw_cfg(machine); 720 rom_set_fw(s->fw_cfg); 721 722 /* Compute the fdt load address in dram */ 723 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 724 machine->ram_size, machine->fdt); 725 /* load the reset vector */ 726 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 727 virt_memmap[VIRT_MROM].base, 728 virt_memmap[VIRT_MROM].size, kernel_entry, 729 fdt_load_addr, machine->fdt); 730 731 /* SiFive Test MMIO device */ 732 sifive_test_create(memmap[VIRT_TEST].base); 733 734 /* VirtIO MMIO devices */ 735 for (i = 0; i < VIRTIO_COUNT; i++) { 736 sysbus_create_simple("virtio-mmio", 737 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 738 qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); 739 } 740 741 gpex_pcie_init(system_memory, 742 memmap[VIRT_PCIE_ECAM].base, 743 memmap[VIRT_PCIE_ECAM].size, 744 memmap[VIRT_PCIE_MMIO].base, 745 memmap[VIRT_PCIE_MMIO].size, 746 virt_high_pcie_memmap.base, 747 virt_high_pcie_memmap.size, 748 memmap[VIRT_PCIE_PIO].base, 749 DEVICE(pcie_plic)); 750 751 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 752 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, 753 serial_hd(0), DEVICE_LITTLE_ENDIAN); 754 755 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 756 qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); 757 758 virt_flash_create(s); 759 760 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 761 /* Map legacy -drive if=pflash to machine properties */ 762 pflash_cfi01_legacy_drive(s->flash[i], 763 drive_get(IF_PFLASH, 0, i)); 764 } 765 virt_flash_map(s, system_memory); 766 } 767 768 static void virt_machine_instance_init(Object *obj) 769 { 770 } 771 772 static void virt_machine_class_init(ObjectClass *oc, void *data) 773 { 774 MachineClass *mc = MACHINE_CLASS(oc); 775 776 mc->desc = "RISC-V VirtIO board"; 777 mc->init = virt_machine_init; 778 mc->max_cpus = VIRT_CPUS_MAX; 779 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 780 mc->pci_allow_0_address = true; 781 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 782 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 783 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 784 mc->numa_mem_supported = true; 785 786 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 787 } 788 789 static const TypeInfo virt_machine_typeinfo = { 790 .name = MACHINE_TYPE_NAME("virt"), 791 .parent = TYPE_MACHINE, 792 .class_init = virt_machine_class_init, 793 .instance_init = virt_machine_instance_init, 794 .instance_size = sizeof(RISCVVirtState), 795 }; 796 797 static void virt_machine_init_register_types(void) 798 { 799 type_register_static(&virt_machine_typeinfo); 800 } 801 802 type_init(virt_machine_init_register_types) 803