1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/log.h" 24 #include "qemu/error-report.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/riscv/riscv_hart.h" 33 #include "hw/riscv/virt.h" 34 #include "hw/riscv/boot.h" 35 #include "hw/riscv/numa.h" 36 #include "hw/intc/sifive_clint.h" 37 #include "hw/intc/sifive_plic.h" 38 #include "hw/misc/sifive_test.h" 39 #include "chardev/char.h" 40 #include "sysemu/arch_init.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/sysemu.h" 43 #include "hw/pci/pci.h" 44 #include "hw/pci-host/gpex.h" 45 46 static const MemMapEntry virt_memmap[] = { 47 [VIRT_DEBUG] = { 0x0, 0x100 }, 48 [VIRT_MROM] = { 0x1000, 0xf000 }, 49 [VIRT_TEST] = { 0x100000, 0x1000 }, 50 [VIRT_RTC] = { 0x101000, 0x1000 }, 51 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 52 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 53 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 54 [VIRT_UART0] = { 0x10000000, 0x100 }, 55 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 56 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 57 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 58 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 59 [VIRT_DRAM] = { 0x80000000, 0x0 }, 60 }; 61 62 /* PCIe high mmio is fixed for RV32 */ 63 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 64 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 65 66 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 67 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 68 69 static MemMapEntry virt_high_pcie_memmap; 70 71 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 72 73 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 74 const char *name, 75 const char *alias_prop_name) 76 { 77 /* 78 * Create a single flash device. We use the same parameters as 79 * the flash devices on the ARM virt board. 80 */ 81 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 82 83 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 84 qdev_prop_set_uint8(dev, "width", 4); 85 qdev_prop_set_uint8(dev, "device-width", 2); 86 qdev_prop_set_bit(dev, "big-endian", false); 87 qdev_prop_set_uint16(dev, "id0", 0x89); 88 qdev_prop_set_uint16(dev, "id1", 0x18); 89 qdev_prop_set_uint16(dev, "id2", 0x00); 90 qdev_prop_set_uint16(dev, "id3", 0x00); 91 qdev_prop_set_string(dev, "name", name); 92 93 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 94 object_property_add_alias(OBJECT(s), alias_prop_name, 95 OBJECT(dev), "drive"); 96 97 return PFLASH_CFI01(dev); 98 } 99 100 static void virt_flash_create(RISCVVirtState *s) 101 { 102 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 103 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 104 } 105 106 static void virt_flash_map1(PFlashCFI01 *flash, 107 hwaddr base, hwaddr size, 108 MemoryRegion *sysmem) 109 { 110 DeviceState *dev = DEVICE(flash); 111 112 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 113 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 114 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 115 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 116 117 memory_region_add_subregion(sysmem, base, 118 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 119 0)); 120 } 121 122 static void virt_flash_map(RISCVVirtState *s, 123 MemoryRegion *sysmem) 124 { 125 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 126 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 127 128 virt_flash_map1(s->flash[0], flashbase, flashsize, 129 sysmem); 130 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 131 sysmem); 132 } 133 134 static void create_pcie_irq_map(void *fdt, char *nodename, 135 uint32_t plic_phandle) 136 { 137 int pin, dev; 138 uint32_t 139 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; 140 uint32_t *irq_map = full_irq_map; 141 142 /* This code creates a standard swizzle of interrupts such that 143 * each device's first interrupt is based on it's PCI_SLOT number. 144 * (See pci_swizzle_map_irq_fn()) 145 * 146 * We only need one entry per interrupt in the table (not one per 147 * possible slot) seeing the interrupt-map-mask will allow the table 148 * to wrap to any number of devices. 149 */ 150 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 151 int devfn = dev * 0x8; 152 153 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 154 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 155 int i = 0; 156 157 irq_map[i] = cpu_to_be32(devfn << 8); 158 159 i += FDT_PCI_ADDR_CELLS; 160 irq_map[i] = cpu_to_be32(pin + 1); 161 162 i += FDT_PCI_INT_CELLS; 163 irq_map[i++] = cpu_to_be32(plic_phandle); 164 165 i += FDT_PLIC_ADDR_CELLS; 166 irq_map[i] = cpu_to_be32(irq_nr); 167 168 irq_map += FDT_INT_MAP_WIDTH; 169 } 170 } 171 172 qemu_fdt_setprop(fdt, nodename, "interrupt-map", 173 full_irq_map, sizeof(full_irq_map)); 174 175 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 176 0x1800, 0, 0, 0x7); 177 } 178 179 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 180 uint64_t mem_size, const char *cmdline, bool is_32_bit) 181 { 182 void *fdt; 183 int i, cpu, socket; 184 MachineState *mc = MACHINE(s); 185 uint64_t addr, size; 186 uint32_t *clint_cells, *plic_cells; 187 unsigned long clint_addr, plic_addr; 188 uint32_t plic_phandle[MAX_NODES]; 189 uint32_t cpu_phandle, intc_phandle, test_phandle; 190 uint32_t phandle = 1, plic_mmio_phandle = 1; 191 uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; 192 char *mem_name, *cpu_name, *core_name, *intc_name; 193 char *name, *clint_name, *plic_name, *clust_name; 194 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 195 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 196 197 if (mc->dtb) { 198 fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 199 if (!fdt) { 200 error_report("load_device_tree() failed"); 201 exit(1); 202 } 203 goto update_bootargs; 204 } else { 205 fdt = mc->fdt = create_device_tree(&s->fdt_size); 206 if (!fdt) { 207 error_report("create_device_tree() failed"); 208 exit(1); 209 } 210 } 211 212 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); 213 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); 214 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 215 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 216 217 qemu_fdt_add_subnode(fdt, "/soc"); 218 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 219 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 220 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 221 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 222 223 qemu_fdt_add_subnode(fdt, "/cpus"); 224 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 225 SIFIVE_CLINT_TIMEBASE_FREQ); 226 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 227 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 228 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 229 230 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 231 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 232 qemu_fdt_add_subnode(fdt, clust_name); 233 234 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 235 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 236 237 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 238 cpu_phandle = phandle++; 239 240 cpu_name = g_strdup_printf("/cpus/cpu@%d", 241 s->soc[socket].hartid_base + cpu); 242 qemu_fdt_add_subnode(fdt, cpu_name); 243 if (is_32_bit) { 244 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 245 } else { 246 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 247 } 248 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 249 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 250 g_free(name); 251 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 252 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 253 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 254 s->soc[socket].hartid_base + cpu); 255 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 256 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 257 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 258 259 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 260 qemu_fdt_add_subnode(fdt, intc_name); 261 intc_phandle = phandle++; 262 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 263 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 264 "riscv,cpu-intc"); 265 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 266 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 267 268 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 269 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 270 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 271 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 272 273 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 274 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 275 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 276 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 277 278 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 279 qemu_fdt_add_subnode(fdt, core_name); 280 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 281 282 g_free(core_name); 283 g_free(intc_name); 284 g_free(cpu_name); 285 } 286 287 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 288 size = riscv_socket_mem_size(mc, socket); 289 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 290 qemu_fdt_add_subnode(fdt, mem_name); 291 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 292 addr >> 32, addr, size >> 32, size); 293 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 294 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 295 g_free(mem_name); 296 297 clint_addr = memmap[VIRT_CLINT].base + 298 (memmap[VIRT_CLINT].size * socket); 299 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 300 qemu_fdt_add_subnode(fdt, clint_name); 301 qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); 302 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 303 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 304 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 305 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 306 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 307 g_free(clint_name); 308 309 plic_phandle[socket] = phandle++; 310 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 311 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 312 qemu_fdt_add_subnode(fdt, plic_name); 313 qemu_fdt_setprop_cell(fdt, plic_name, 314 "#address-cells", FDT_PLIC_ADDR_CELLS); 315 qemu_fdt_setprop_cell(fdt, plic_name, 316 "#interrupt-cells", FDT_PLIC_INT_CELLS); 317 qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); 318 qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); 319 qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", 320 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 321 qemu_fdt_setprop_cells(fdt, plic_name, "reg", 322 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 323 qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 324 riscv_socket_fdt_write_id(mc, fdt, plic_name, socket); 325 qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]); 326 g_free(plic_name); 327 328 g_free(clint_cells); 329 g_free(plic_cells); 330 g_free(clust_name); 331 } 332 333 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 334 if (socket == 0) { 335 plic_mmio_phandle = plic_phandle[socket]; 336 plic_virtio_phandle = plic_phandle[socket]; 337 plic_pcie_phandle = plic_phandle[socket]; 338 } 339 if (socket == 1) { 340 plic_virtio_phandle = plic_phandle[socket]; 341 plic_pcie_phandle = plic_phandle[socket]; 342 } 343 if (socket == 2) { 344 plic_pcie_phandle = plic_phandle[socket]; 345 } 346 } 347 348 riscv_socket_fdt_write_distance_matrix(mc, fdt); 349 350 for (i = 0; i < VIRTIO_COUNT; i++) { 351 name = g_strdup_printf("/soc/virtio_mmio@%lx", 352 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 353 qemu_fdt_add_subnode(fdt, name); 354 qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); 355 qemu_fdt_setprop_cells(fdt, name, "reg", 356 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 357 0x0, memmap[VIRT_VIRTIO].size); 358 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", 359 plic_virtio_phandle); 360 qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); 361 g_free(name); 362 } 363 364 name = g_strdup_printf("/soc/pci@%lx", 365 (long) memmap[VIRT_PCIE_ECAM].base); 366 qemu_fdt_add_subnode(fdt, name); 367 qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); 368 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); 369 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); 370 qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); 371 qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); 372 qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); 373 qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, 374 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 375 qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); 376 qemu_fdt_setprop_cells(fdt, name, "reg", 0, 377 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 378 qemu_fdt_setprop_sized_cells(fdt, name, "ranges", 379 1, FDT_PCI_RANGE_IOPORT, 2, 0, 380 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 381 1, FDT_PCI_RANGE_MMIO, 382 2, memmap[VIRT_PCIE_MMIO].base, 383 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 384 1, FDT_PCI_RANGE_MMIO_64BIT, 385 2, virt_high_pcie_memmap.base, 386 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 387 388 create_pcie_irq_map(fdt, name, plic_pcie_phandle); 389 g_free(name); 390 391 test_phandle = phandle++; 392 name = g_strdup_printf("/soc/test@%lx", 393 (long)memmap[VIRT_TEST].base); 394 qemu_fdt_add_subnode(fdt, name); 395 { 396 const char compat[] = "sifive,test1\0sifive,test0\0syscon"; 397 qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat)); 398 } 399 qemu_fdt_setprop_cells(fdt, name, "reg", 400 0x0, memmap[VIRT_TEST].base, 401 0x0, memmap[VIRT_TEST].size); 402 qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); 403 test_phandle = qemu_fdt_get_phandle(fdt, name); 404 g_free(name); 405 406 name = g_strdup_printf("/soc/reboot"); 407 qemu_fdt_add_subnode(fdt, name); 408 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); 409 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 410 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 411 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); 412 g_free(name); 413 414 name = g_strdup_printf("/soc/poweroff"); 415 qemu_fdt_add_subnode(fdt, name); 416 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); 417 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 418 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 419 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); 420 g_free(name); 421 422 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 423 qemu_fdt_add_subnode(fdt, name); 424 qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); 425 qemu_fdt_setprop_cells(fdt, name, "reg", 426 0x0, memmap[VIRT_UART0].base, 427 0x0, memmap[VIRT_UART0].size); 428 qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); 429 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 430 qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); 431 432 qemu_fdt_add_subnode(fdt, "/chosen"); 433 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); 434 g_free(name); 435 436 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 437 qemu_fdt_add_subnode(fdt, name); 438 qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); 439 qemu_fdt_setprop_cells(fdt, name, "reg", 440 0x0, memmap[VIRT_RTC].base, 441 0x0, memmap[VIRT_RTC].size); 442 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 443 qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); 444 g_free(name); 445 446 name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); 447 qemu_fdt_add_subnode(mc->fdt, name); 448 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 449 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 450 2, flashbase, 2, flashsize, 451 2, flashbase + flashsize, 2, flashsize); 452 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 453 g_free(name); 454 455 update_bootargs: 456 if (cmdline) { 457 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 458 } 459 } 460 461 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 462 hwaddr ecam_base, hwaddr ecam_size, 463 hwaddr mmio_base, hwaddr mmio_size, 464 hwaddr high_mmio_base, 465 hwaddr high_mmio_size, 466 hwaddr pio_base, 467 DeviceState *plic) 468 { 469 DeviceState *dev; 470 MemoryRegion *ecam_alias, *ecam_reg; 471 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 472 qemu_irq irq; 473 int i; 474 475 dev = qdev_new(TYPE_GPEX_HOST); 476 477 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 478 479 ecam_alias = g_new0(MemoryRegion, 1); 480 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 481 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 482 ecam_reg, 0, ecam_size); 483 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 484 485 mmio_alias = g_new0(MemoryRegion, 1); 486 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 487 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 488 mmio_reg, mmio_base, mmio_size); 489 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 490 491 /* Map high MMIO space */ 492 high_mmio_alias = g_new0(MemoryRegion, 1); 493 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 494 mmio_reg, high_mmio_base, high_mmio_size); 495 memory_region_add_subregion(get_system_memory(), high_mmio_base, 496 high_mmio_alias); 497 498 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 499 500 for (i = 0; i < GPEX_NUM_IRQS; i++) { 501 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); 502 503 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 504 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 505 } 506 507 return dev; 508 } 509 510 static void virt_machine_init(MachineState *machine) 511 { 512 const MemMapEntry *memmap = virt_memmap; 513 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 514 MemoryRegion *system_memory = get_system_memory(); 515 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 516 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 517 char *plic_hart_config, *soc_name; 518 size_t plic_hart_config_len; 519 target_ulong start_addr = memmap[VIRT_DRAM].base; 520 target_ulong firmware_end_addr, kernel_start_addr; 521 uint32_t fdt_load_addr; 522 uint64_t kernel_entry; 523 DeviceState *mmio_plic, *virtio_plic, *pcie_plic; 524 int i, j, base_hartid, hart_count; 525 526 /* Check socket count limit */ 527 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 528 error_report("number of sockets/nodes should be less than %d", 529 VIRT_SOCKETS_MAX); 530 exit(1); 531 } 532 533 /* Initialize sockets */ 534 mmio_plic = virtio_plic = pcie_plic = NULL; 535 for (i = 0; i < riscv_socket_count(machine); i++) { 536 if (!riscv_socket_check_hartids(machine, i)) { 537 error_report("discontinuous hartids in socket%d", i); 538 exit(1); 539 } 540 541 base_hartid = riscv_socket_first_hartid(machine, i); 542 if (base_hartid < 0) { 543 error_report("can't find hartid base for socket%d", i); 544 exit(1); 545 } 546 547 hart_count = riscv_socket_hart_count(machine, i); 548 if (hart_count < 0) { 549 error_report("can't find hart count for socket%d", i); 550 exit(1); 551 } 552 553 soc_name = g_strdup_printf("soc%d", i); 554 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 555 TYPE_RISCV_HART_ARRAY); 556 g_free(soc_name); 557 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 558 machine->cpu_type, &error_abort); 559 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 560 base_hartid, &error_abort); 561 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 562 hart_count, &error_abort); 563 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 564 565 /* Per-socket CLINT */ 566 sifive_clint_create( 567 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 568 memmap[VIRT_CLINT].size, base_hartid, hart_count, 569 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 570 SIFIVE_CLINT_TIMEBASE_FREQ, true); 571 572 /* Per-socket PLIC hart topology configuration string */ 573 plic_hart_config_len = 574 (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count; 575 plic_hart_config = g_malloc0(plic_hart_config_len); 576 for (j = 0; j < hart_count; j++) { 577 if (j != 0) { 578 strncat(plic_hart_config, ",", plic_hart_config_len); 579 } 580 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, 581 plic_hart_config_len); 582 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); 583 } 584 585 /* Per-socket PLIC */ 586 s->plic[i] = sifive_plic_create( 587 memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, 588 plic_hart_config, base_hartid, 589 VIRT_PLIC_NUM_SOURCES, 590 VIRT_PLIC_NUM_PRIORITIES, 591 VIRT_PLIC_PRIORITY_BASE, 592 VIRT_PLIC_PENDING_BASE, 593 VIRT_PLIC_ENABLE_BASE, 594 VIRT_PLIC_ENABLE_STRIDE, 595 VIRT_PLIC_CONTEXT_BASE, 596 VIRT_PLIC_CONTEXT_STRIDE, 597 memmap[VIRT_PLIC].size); 598 g_free(plic_hart_config); 599 600 /* Try to use different PLIC instance based device type */ 601 if (i == 0) { 602 mmio_plic = s->plic[i]; 603 virtio_plic = s->plic[i]; 604 pcie_plic = s->plic[i]; 605 } 606 if (i == 1) { 607 virtio_plic = s->plic[i]; 608 pcie_plic = s->plic[i]; 609 } 610 if (i == 2) { 611 pcie_plic = s->plic[i]; 612 } 613 } 614 615 if (riscv_is_32bit(&s->soc[0])) { 616 #if HOST_LONG_BITS == 64 617 /* limit RAM size in a 32-bit system */ 618 if (machine->ram_size > 10 * GiB) { 619 machine->ram_size = 10 * GiB; 620 error_report("Limiting RAM size to 10 GiB"); 621 } 622 #endif 623 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 624 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 625 } else { 626 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 627 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 628 virt_high_pcie_memmap.base = 629 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 630 } 631 632 /* register system main memory (actual RAM) */ 633 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", 634 machine->ram_size, &error_fatal); 635 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 636 main_mem); 637 638 /* create device tree */ 639 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 640 riscv_is_32bit(&s->soc[0])); 641 642 /* boot rom */ 643 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 644 memmap[VIRT_MROM].size, &error_fatal); 645 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 646 mask_rom); 647 648 if (riscv_is_32bit(&s->soc[0])) { 649 firmware_end_addr = riscv_find_and_load_firmware(machine, 650 "opensbi-riscv32-generic-fw_dynamic.bin", 651 start_addr, NULL); 652 } else { 653 firmware_end_addr = riscv_find_and_load_firmware(machine, 654 "opensbi-riscv64-generic-fw_dynamic.bin", 655 start_addr, NULL); 656 } 657 658 if (machine->kernel_filename) { 659 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 660 firmware_end_addr); 661 662 kernel_entry = riscv_load_kernel(machine->kernel_filename, 663 kernel_start_addr, NULL); 664 665 if (machine->initrd_filename) { 666 hwaddr start; 667 hwaddr end = riscv_load_initrd(machine->initrd_filename, 668 machine->ram_size, kernel_entry, 669 &start); 670 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 671 "linux,initrd-start", start); 672 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 673 end); 674 } 675 } else { 676 /* 677 * If dynamic firmware is used, it doesn't know where is the next mode 678 * if kernel argument is not set. 679 */ 680 kernel_entry = 0; 681 } 682 683 if (drive_get(IF_PFLASH, 0, 0)) { 684 /* 685 * Pflash was supplied, let's overwrite the address we jump to after 686 * reset to the base of the flash. 687 */ 688 start_addr = virt_memmap[VIRT_FLASH].base; 689 } 690 691 /* Compute the fdt load address in dram */ 692 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 693 machine->ram_size, machine->fdt); 694 /* load the reset vector */ 695 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 696 virt_memmap[VIRT_MROM].base, 697 virt_memmap[VIRT_MROM].size, kernel_entry, 698 fdt_load_addr, machine->fdt); 699 700 /* SiFive Test MMIO device */ 701 sifive_test_create(memmap[VIRT_TEST].base); 702 703 /* VirtIO MMIO devices */ 704 for (i = 0; i < VIRTIO_COUNT; i++) { 705 sysbus_create_simple("virtio-mmio", 706 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 707 qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); 708 } 709 710 gpex_pcie_init(system_memory, 711 memmap[VIRT_PCIE_ECAM].base, 712 memmap[VIRT_PCIE_ECAM].size, 713 memmap[VIRT_PCIE_MMIO].base, 714 memmap[VIRT_PCIE_MMIO].size, 715 virt_high_pcie_memmap.base, 716 virt_high_pcie_memmap.size, 717 memmap[VIRT_PCIE_PIO].base, 718 DEVICE(pcie_plic)); 719 720 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 721 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, 722 serial_hd(0), DEVICE_LITTLE_ENDIAN); 723 724 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 725 qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); 726 727 virt_flash_create(s); 728 729 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 730 /* Map legacy -drive if=pflash to machine properties */ 731 pflash_cfi01_legacy_drive(s->flash[i], 732 drive_get(IF_PFLASH, 0, i)); 733 } 734 virt_flash_map(s, system_memory); 735 } 736 737 static void virt_machine_instance_init(Object *obj) 738 { 739 } 740 741 static void virt_machine_class_init(ObjectClass *oc, void *data) 742 { 743 MachineClass *mc = MACHINE_CLASS(oc); 744 745 mc->desc = "RISC-V VirtIO board"; 746 mc->init = virt_machine_init; 747 mc->max_cpus = VIRT_CPUS_MAX; 748 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 749 mc->pci_allow_0_address = true; 750 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 751 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 752 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 753 mc->numa_mem_supported = true; 754 } 755 756 static const TypeInfo virt_machine_typeinfo = { 757 .name = MACHINE_TYPE_NAME("virt"), 758 .parent = TYPE_MACHINE, 759 .class_init = virt_machine_class_init, 760 .instance_init = virt_machine_instance_init, 761 .instance_size = sizeof(RISCVVirtState), 762 }; 763 764 static void virt_machine_init_register_types(void) 765 { 766 type_register_static(&virt_machine_typeinfo); 767 } 768 769 type_init(virt_machine_init_register_types) 770