1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "hw/intc/riscv_aclint.h" 39 #include "hw/intc/riscv_aplic.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "hw/intc/sifive_plic.h" 42 #include "hw/misc/sifive_test.h" 43 #include "hw/platform-bus.h" 44 #include "chardev/char.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/tpm.h" 49 #include "hw/pci/pci.h" 50 #include "hw/pci-host/gpex.h" 51 #include "hw/display/ramfb.h" 52 53 /* 54 * The virt machine physical address space used by some of the devices 55 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 56 * number of CPUs, and number of IMSIC guest files. 57 * 58 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 59 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 60 * of virt machine physical address space. 61 */ 62 63 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 64 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 65 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 66 #error "Can't accomodate single IMSIC group in address space" 67 #endif 68 69 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 70 VIRT_IMSIC_GROUP_MAX_SIZE) 71 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 72 #error "Can't accomodate all IMSIC groups in address space" 73 #endif 74 75 static const MemMapEntry virt_memmap[] = { 76 [VIRT_DEBUG] = { 0x0, 0x100 }, 77 [VIRT_MROM] = { 0x1000, 0xf000 }, 78 [VIRT_TEST] = { 0x100000, 0x1000 }, 79 [VIRT_RTC] = { 0x101000, 0x1000 }, 80 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 81 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 82 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 83 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 84 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 85 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 86 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 87 [VIRT_UART0] = { 0x10000000, 0x100 }, 88 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 89 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 90 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 91 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 92 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 93 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 94 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 95 [VIRT_DRAM] = { 0x80000000, 0x0 }, 96 }; 97 98 /* PCIe high mmio is fixed for RV32 */ 99 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 100 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 101 102 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 103 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 104 105 static MemMapEntry virt_high_pcie_memmap; 106 107 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 108 109 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 110 const char *name, 111 const char *alias_prop_name) 112 { 113 /* 114 * Create a single flash device. We use the same parameters as 115 * the flash devices on the ARM virt board. 116 */ 117 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 118 119 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 120 qdev_prop_set_uint8(dev, "width", 4); 121 qdev_prop_set_uint8(dev, "device-width", 2); 122 qdev_prop_set_bit(dev, "big-endian", false); 123 qdev_prop_set_uint16(dev, "id0", 0x89); 124 qdev_prop_set_uint16(dev, "id1", 0x18); 125 qdev_prop_set_uint16(dev, "id2", 0x00); 126 qdev_prop_set_uint16(dev, "id3", 0x00); 127 qdev_prop_set_string(dev, "name", name); 128 129 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 130 object_property_add_alias(OBJECT(s), alias_prop_name, 131 OBJECT(dev), "drive"); 132 133 return PFLASH_CFI01(dev); 134 } 135 136 static void virt_flash_create(RISCVVirtState *s) 137 { 138 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 139 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 140 } 141 142 static void virt_flash_map1(PFlashCFI01 *flash, 143 hwaddr base, hwaddr size, 144 MemoryRegion *sysmem) 145 { 146 DeviceState *dev = DEVICE(flash); 147 148 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 149 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 150 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 151 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 152 153 memory_region_add_subregion(sysmem, base, 154 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 155 0)); 156 } 157 158 static void virt_flash_map(RISCVVirtState *s, 159 MemoryRegion *sysmem) 160 { 161 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 162 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 163 164 virt_flash_map1(s->flash[0], flashbase, flashsize, 165 sysmem); 166 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 167 sysmem); 168 } 169 170 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 171 uint32_t irqchip_phandle) 172 { 173 int pin, dev; 174 uint32_t irq_map_stride = 0; 175 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 176 FDT_MAX_INT_MAP_WIDTH] = {}; 177 uint32_t *irq_map = full_irq_map; 178 179 /* This code creates a standard swizzle of interrupts such that 180 * each device's first interrupt is based on it's PCI_SLOT number. 181 * (See pci_swizzle_map_irq_fn()) 182 * 183 * We only need one entry per interrupt in the table (not one per 184 * possible slot) seeing the interrupt-map-mask will allow the table 185 * to wrap to any number of devices. 186 */ 187 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 188 int devfn = dev * 0x8; 189 190 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 191 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 192 int i = 0; 193 194 /* Fill PCI address cells */ 195 irq_map[i] = cpu_to_be32(devfn << 8); 196 i += FDT_PCI_ADDR_CELLS; 197 198 /* Fill PCI Interrupt cells */ 199 irq_map[i] = cpu_to_be32(pin + 1); 200 i += FDT_PCI_INT_CELLS; 201 202 /* Fill interrupt controller phandle and cells */ 203 irq_map[i++] = cpu_to_be32(irqchip_phandle); 204 irq_map[i++] = cpu_to_be32(irq_nr); 205 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 206 irq_map[i++] = cpu_to_be32(0x4); 207 } 208 209 if (!irq_map_stride) { 210 irq_map_stride = i; 211 } 212 irq_map += irq_map_stride; 213 } 214 } 215 216 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 217 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 218 irq_map_stride * sizeof(uint32_t)); 219 220 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 221 0x1800, 0, 0, 0x7); 222 } 223 224 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 225 char *clust_name, uint32_t *phandle, 226 uint32_t *intc_phandles) 227 { 228 int cpu; 229 uint32_t cpu_phandle; 230 MachineState *ms = MACHINE(s); 231 char *name, *cpu_name, *core_name, *intc_name; 232 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 233 234 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 235 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 236 237 cpu_phandle = (*phandle)++; 238 239 cpu_name = g_strdup_printf("/cpus/cpu@%d", 240 s->soc[socket].hartid_base + cpu); 241 qemu_fdt_add_subnode(ms->fdt, cpu_name); 242 if (cpu_ptr->cfg.mmu) { 243 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", 244 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 245 } else { 246 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", 247 "riscv,none"); 248 } 249 name = riscv_isa_string(cpu_ptr); 250 qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); 251 g_free(name); 252 253 if (cpu_ptr->cfg.ext_icbom) { 254 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 255 cpu_ptr->cfg.cbom_blocksize); 256 } 257 258 if (cpu_ptr->cfg.ext_icboz) { 259 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 260 cpu_ptr->cfg.cboz_blocksize); 261 } 262 263 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 264 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 265 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 266 s->soc[socket].hartid_base + cpu); 267 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 268 riscv_socket_fdt_write_id(ms, cpu_name, socket); 269 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 270 271 intc_phandles[cpu] = (*phandle)++; 272 273 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 274 qemu_fdt_add_subnode(ms->fdt, intc_name); 275 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 276 intc_phandles[cpu]); 277 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 278 "riscv,cpu-intc"); 279 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 280 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 281 282 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 283 qemu_fdt_add_subnode(ms->fdt, core_name); 284 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 285 286 g_free(core_name); 287 g_free(intc_name); 288 g_free(cpu_name); 289 } 290 } 291 292 static void create_fdt_socket_memory(RISCVVirtState *s, 293 const MemMapEntry *memmap, int socket) 294 { 295 char *mem_name; 296 uint64_t addr, size; 297 MachineState *ms = MACHINE(s); 298 299 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 300 size = riscv_socket_mem_size(ms, socket); 301 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 302 qemu_fdt_add_subnode(ms->fdt, mem_name); 303 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 304 addr >> 32, addr, size >> 32, size); 305 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 306 riscv_socket_fdt_write_id(ms, mem_name, socket); 307 g_free(mem_name); 308 } 309 310 static void create_fdt_socket_clint(RISCVVirtState *s, 311 const MemMapEntry *memmap, int socket, 312 uint32_t *intc_phandles) 313 { 314 int cpu; 315 char *clint_name; 316 uint32_t *clint_cells; 317 unsigned long clint_addr; 318 MachineState *ms = MACHINE(s); 319 static const char * const clint_compat[2] = { 320 "sifive,clint0", "riscv,clint0" 321 }; 322 323 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 324 325 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 326 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 327 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 328 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 329 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 330 } 331 332 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 333 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 334 qemu_fdt_add_subnode(ms->fdt, clint_name); 335 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 336 (char **)&clint_compat, 337 ARRAY_SIZE(clint_compat)); 338 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 339 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 340 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 341 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 342 riscv_socket_fdt_write_id(ms, clint_name, socket); 343 g_free(clint_name); 344 345 g_free(clint_cells); 346 } 347 348 static void create_fdt_socket_aclint(RISCVVirtState *s, 349 const MemMapEntry *memmap, int socket, 350 uint32_t *intc_phandles) 351 { 352 int cpu; 353 char *name; 354 unsigned long addr, size; 355 uint32_t aclint_cells_size; 356 uint32_t *aclint_mswi_cells; 357 uint32_t *aclint_sswi_cells; 358 uint32_t *aclint_mtimer_cells; 359 MachineState *ms = MACHINE(s); 360 361 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 362 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 363 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 364 365 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 366 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 367 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 368 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 369 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 370 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 371 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 372 } 373 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 374 375 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 376 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 377 name = g_strdup_printf("/soc/mswi@%lx", addr); 378 qemu_fdt_add_subnode(ms->fdt, name); 379 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 380 "riscv,aclint-mswi"); 381 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 382 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 383 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 384 aclint_mswi_cells, aclint_cells_size); 385 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 386 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 387 riscv_socket_fdt_write_id(ms, name, socket); 388 g_free(name); 389 } 390 391 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 392 addr = memmap[VIRT_CLINT].base + 393 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 394 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 395 } else { 396 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 397 (memmap[VIRT_CLINT].size * socket); 398 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 399 } 400 name = g_strdup_printf("/soc/mtimer@%lx", addr); 401 qemu_fdt_add_subnode(ms->fdt, name); 402 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 403 "riscv,aclint-mtimer"); 404 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 405 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 406 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 407 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 408 0x0, RISCV_ACLINT_DEFAULT_MTIME); 409 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 410 aclint_mtimer_cells, aclint_cells_size); 411 riscv_socket_fdt_write_id(ms, name, socket); 412 g_free(name); 413 414 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 415 addr = memmap[VIRT_ACLINT_SSWI].base + 416 (memmap[VIRT_ACLINT_SSWI].size * socket); 417 name = g_strdup_printf("/soc/sswi@%lx", addr); 418 qemu_fdt_add_subnode(ms->fdt, name); 419 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 420 "riscv,aclint-sswi"); 421 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 422 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 423 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 424 aclint_sswi_cells, aclint_cells_size); 425 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 426 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 427 riscv_socket_fdt_write_id(ms, name, socket); 428 g_free(name); 429 } 430 431 g_free(aclint_mswi_cells); 432 g_free(aclint_mtimer_cells); 433 g_free(aclint_sswi_cells); 434 } 435 436 static void create_fdt_socket_plic(RISCVVirtState *s, 437 const MemMapEntry *memmap, int socket, 438 uint32_t *phandle, uint32_t *intc_phandles, 439 uint32_t *plic_phandles) 440 { 441 int cpu; 442 char *plic_name; 443 uint32_t *plic_cells; 444 unsigned long plic_addr; 445 MachineState *ms = MACHINE(s); 446 static const char * const plic_compat[2] = { 447 "sifive,plic-1.0.0", "riscv,plic0" 448 }; 449 450 if (kvm_enabled()) { 451 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 452 } else { 453 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 454 } 455 456 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 457 if (kvm_enabled()) { 458 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 459 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 460 } else { 461 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 462 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 463 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 464 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 465 } 466 } 467 468 plic_phandles[socket] = (*phandle)++; 469 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 470 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 471 qemu_fdt_add_subnode(ms->fdt, plic_name); 472 qemu_fdt_setprop_cell(ms->fdt, plic_name, 473 "#interrupt-cells", FDT_PLIC_INT_CELLS); 474 qemu_fdt_setprop_cell(ms->fdt, plic_name, 475 "#address-cells", FDT_PLIC_ADDR_CELLS); 476 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 477 (char **)&plic_compat, 478 ARRAY_SIZE(plic_compat)); 479 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 480 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 481 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 482 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 483 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 484 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 485 VIRT_IRQCHIP_NUM_SOURCES - 1); 486 riscv_socket_fdt_write_id(ms, plic_name, socket); 487 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 488 plic_phandles[socket]); 489 490 if (!socket) { 491 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 492 memmap[VIRT_PLATFORM_BUS].base, 493 memmap[VIRT_PLATFORM_BUS].size, 494 VIRT_PLATFORM_BUS_IRQ); 495 } 496 497 g_free(plic_name); 498 499 g_free(plic_cells); 500 } 501 502 static uint32_t imsic_num_bits(uint32_t count) 503 { 504 uint32_t ret = 0; 505 506 while (BIT(ret) < count) { 507 ret++; 508 } 509 510 return ret; 511 } 512 513 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 514 uint32_t *phandle, uint32_t *intc_phandles, 515 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 516 { 517 int cpu, socket; 518 char *imsic_name; 519 MachineState *ms = MACHINE(s); 520 int socket_count = riscv_socket_count(ms); 521 uint32_t imsic_max_hart_per_socket, imsic_guest_bits; 522 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 523 524 *msi_m_phandle = (*phandle)++; 525 *msi_s_phandle = (*phandle)++; 526 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 527 imsic_regs = g_new0(uint32_t, socket_count * 4); 528 529 /* M-level IMSIC node */ 530 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 531 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 532 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 533 } 534 imsic_max_hart_per_socket = 0; 535 for (socket = 0; socket < socket_count; socket++) { 536 imsic_addr = memmap[VIRT_IMSIC_M].base + 537 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 538 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; 539 imsic_regs[socket * 4 + 0] = 0; 540 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 541 imsic_regs[socket * 4 + 2] = 0; 542 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 543 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 544 imsic_max_hart_per_socket = s->soc[socket].num_harts; 545 } 546 } 547 imsic_name = g_strdup_printf("/soc/imsics@%lx", 548 (unsigned long)memmap[VIRT_IMSIC_M].base); 549 qemu_fdt_add_subnode(ms->fdt, imsic_name); 550 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", 551 "riscv,imsics"); 552 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 553 FDT_IMSIC_INT_CELLS); 554 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", 555 NULL, 0); 556 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", 557 NULL, 0); 558 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 559 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 560 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 561 socket_count * sizeof(uint32_t) * 4); 562 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 563 VIRT_IRQCHIP_NUM_MSIS); 564 if (socket_count > 1) { 565 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 566 imsic_num_bits(imsic_max_hart_per_socket)); 567 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 568 imsic_num_bits(socket_count)); 569 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 570 IMSIC_MMIO_GROUP_MIN_SHIFT); 571 } 572 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle); 573 574 g_free(imsic_name); 575 576 /* S-level IMSIC node */ 577 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 578 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 579 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 580 } 581 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); 582 imsic_max_hart_per_socket = 0; 583 for (socket = 0; socket < socket_count; socket++) { 584 imsic_addr = memmap[VIRT_IMSIC_S].base + 585 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 586 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 587 s->soc[socket].num_harts; 588 imsic_regs[socket * 4 + 0] = 0; 589 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 590 imsic_regs[socket * 4 + 2] = 0; 591 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 592 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 593 imsic_max_hart_per_socket = s->soc[socket].num_harts; 594 } 595 } 596 imsic_name = g_strdup_printf("/soc/imsics@%lx", 597 (unsigned long)memmap[VIRT_IMSIC_S].base); 598 qemu_fdt_add_subnode(ms->fdt, imsic_name); 599 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", 600 "riscv,imsics"); 601 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 602 FDT_IMSIC_INT_CELLS); 603 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", 604 NULL, 0); 605 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", 606 NULL, 0); 607 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 608 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 609 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 610 socket_count * sizeof(uint32_t) * 4); 611 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 612 VIRT_IRQCHIP_NUM_MSIS); 613 if (imsic_guest_bits) { 614 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 615 imsic_guest_bits); 616 } 617 if (socket_count > 1) { 618 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 619 imsic_num_bits(imsic_max_hart_per_socket)); 620 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 621 imsic_num_bits(socket_count)); 622 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 623 IMSIC_MMIO_GROUP_MIN_SHIFT); 624 } 625 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle); 626 g_free(imsic_name); 627 628 g_free(imsic_regs); 629 g_free(imsic_cells); 630 } 631 632 static void create_fdt_socket_aplic(RISCVVirtState *s, 633 const MemMapEntry *memmap, int socket, 634 uint32_t msi_m_phandle, 635 uint32_t msi_s_phandle, 636 uint32_t *phandle, 637 uint32_t *intc_phandles, 638 uint32_t *aplic_phandles) 639 { 640 int cpu; 641 char *aplic_name; 642 uint32_t *aplic_cells; 643 unsigned long aplic_addr; 644 MachineState *ms = MACHINE(s); 645 uint32_t aplic_m_phandle, aplic_s_phandle; 646 647 aplic_m_phandle = (*phandle)++; 648 aplic_s_phandle = (*phandle)++; 649 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 650 651 /* M-level APLIC node */ 652 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 653 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 654 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 655 } 656 aplic_addr = memmap[VIRT_APLIC_M].base + 657 (memmap[VIRT_APLIC_M].size * socket); 658 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 659 qemu_fdt_add_subnode(ms->fdt, aplic_name); 660 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); 661 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 662 "#interrupt-cells", FDT_APLIC_INT_CELLS); 663 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 664 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 665 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 666 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 667 } else { 668 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", 669 msi_m_phandle); 670 } 671 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 672 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); 673 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 674 VIRT_IRQCHIP_NUM_SOURCES); 675 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 676 aplic_s_phandle); 677 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 678 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); 679 riscv_socket_fdt_write_id(ms, aplic_name, socket); 680 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle); 681 g_free(aplic_name); 682 683 /* S-level APLIC node */ 684 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 685 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 686 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 687 } 688 aplic_addr = memmap[VIRT_APLIC_S].base + 689 (memmap[VIRT_APLIC_S].size * socket); 690 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 691 qemu_fdt_add_subnode(ms->fdt, aplic_name); 692 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); 693 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 694 "#interrupt-cells", FDT_APLIC_INT_CELLS); 695 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 696 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 697 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 698 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 699 } else { 700 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", 701 msi_s_phandle); 702 } 703 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 704 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); 705 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 706 VIRT_IRQCHIP_NUM_SOURCES); 707 riscv_socket_fdt_write_id(ms, aplic_name, socket); 708 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle); 709 710 if (!socket) { 711 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 712 memmap[VIRT_PLATFORM_BUS].base, 713 memmap[VIRT_PLATFORM_BUS].size, 714 VIRT_PLATFORM_BUS_IRQ); 715 } 716 717 g_free(aplic_name); 718 719 g_free(aplic_cells); 720 aplic_phandles[socket] = aplic_s_phandle; 721 } 722 723 static void create_fdt_pmu(RISCVVirtState *s) 724 { 725 char *pmu_name; 726 MachineState *ms = MACHINE(s); 727 RISCVCPU hart = s->soc[0].harts[0]; 728 729 pmu_name = g_strdup_printf("/soc/pmu"); 730 qemu_fdt_add_subnode(ms->fdt, pmu_name); 731 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 732 riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); 733 734 g_free(pmu_name); 735 } 736 737 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 738 uint32_t *phandle, 739 uint32_t *irq_mmio_phandle, 740 uint32_t *irq_pcie_phandle, 741 uint32_t *irq_virtio_phandle, 742 uint32_t *msi_pcie_phandle) 743 { 744 char *clust_name; 745 int socket, phandle_pos; 746 MachineState *ms = MACHINE(s); 747 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 748 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 749 int socket_count = riscv_socket_count(ms); 750 751 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 752 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 753 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 754 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 755 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 756 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 757 758 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 759 760 phandle_pos = ms->smp.cpus; 761 for (socket = (socket_count - 1); socket >= 0; socket--) { 762 phandle_pos -= s->soc[socket].num_harts; 763 764 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 765 qemu_fdt_add_subnode(ms->fdt, clust_name); 766 767 create_fdt_socket_cpus(s, socket, clust_name, phandle, 768 &intc_phandles[phandle_pos]); 769 770 create_fdt_socket_memory(s, memmap, socket); 771 772 g_free(clust_name); 773 774 if (!kvm_enabled()) { 775 if (s->have_aclint) { 776 create_fdt_socket_aclint(s, memmap, socket, 777 &intc_phandles[phandle_pos]); 778 } else { 779 create_fdt_socket_clint(s, memmap, socket, 780 &intc_phandles[phandle_pos]); 781 } 782 } 783 } 784 785 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 786 create_fdt_imsic(s, memmap, phandle, intc_phandles, 787 &msi_m_phandle, &msi_s_phandle); 788 *msi_pcie_phandle = msi_s_phandle; 789 } 790 791 phandle_pos = ms->smp.cpus; 792 for (socket = (socket_count - 1); socket >= 0; socket--) { 793 phandle_pos -= s->soc[socket].num_harts; 794 795 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 796 create_fdt_socket_plic(s, memmap, socket, phandle, 797 &intc_phandles[phandle_pos], xplic_phandles); 798 } else { 799 create_fdt_socket_aplic(s, memmap, socket, 800 msi_m_phandle, msi_s_phandle, phandle, 801 &intc_phandles[phandle_pos], xplic_phandles); 802 } 803 } 804 805 g_free(intc_phandles); 806 807 for (socket = 0; socket < socket_count; socket++) { 808 if (socket == 0) { 809 *irq_mmio_phandle = xplic_phandles[socket]; 810 *irq_virtio_phandle = xplic_phandles[socket]; 811 *irq_pcie_phandle = xplic_phandles[socket]; 812 } 813 if (socket == 1) { 814 *irq_virtio_phandle = xplic_phandles[socket]; 815 *irq_pcie_phandle = xplic_phandles[socket]; 816 } 817 if (socket == 2) { 818 *irq_pcie_phandle = xplic_phandles[socket]; 819 } 820 } 821 822 riscv_socket_fdt_write_distance_matrix(ms); 823 } 824 825 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 826 uint32_t irq_virtio_phandle) 827 { 828 int i; 829 char *name; 830 MachineState *ms = MACHINE(s); 831 832 for (i = 0; i < VIRTIO_COUNT; i++) { 833 name = g_strdup_printf("/soc/virtio_mmio@%lx", 834 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 835 qemu_fdt_add_subnode(ms->fdt, name); 836 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 837 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 838 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 839 0x0, memmap[VIRT_VIRTIO].size); 840 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 841 irq_virtio_phandle); 842 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 843 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 844 VIRTIO_IRQ + i); 845 } else { 846 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 847 VIRTIO_IRQ + i, 0x4); 848 } 849 g_free(name); 850 } 851 } 852 853 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 854 uint32_t irq_pcie_phandle, 855 uint32_t msi_pcie_phandle) 856 { 857 char *name; 858 MachineState *ms = MACHINE(s); 859 860 name = g_strdup_printf("/soc/pci@%lx", 861 (long) memmap[VIRT_PCIE_ECAM].base); 862 qemu_fdt_add_subnode(ms->fdt, name); 863 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 864 FDT_PCI_ADDR_CELLS); 865 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 866 FDT_PCI_INT_CELLS); 867 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 868 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 869 "pci-host-ecam-generic"); 870 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 871 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 872 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 873 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 874 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 875 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 876 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 877 } 878 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 879 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 880 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 881 1, FDT_PCI_RANGE_IOPORT, 2, 0, 882 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 883 1, FDT_PCI_RANGE_MMIO, 884 2, memmap[VIRT_PCIE_MMIO].base, 885 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 886 1, FDT_PCI_RANGE_MMIO_64BIT, 887 2, virt_high_pcie_memmap.base, 888 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 889 890 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 891 g_free(name); 892 } 893 894 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 895 uint32_t *phandle) 896 { 897 char *name; 898 uint32_t test_phandle; 899 MachineState *ms = MACHINE(s); 900 901 test_phandle = (*phandle)++; 902 name = g_strdup_printf("/soc/test@%lx", 903 (long)memmap[VIRT_TEST].base); 904 qemu_fdt_add_subnode(ms->fdt, name); 905 { 906 static const char * const compat[3] = { 907 "sifive,test1", "sifive,test0", "syscon" 908 }; 909 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 910 (char **)&compat, ARRAY_SIZE(compat)); 911 } 912 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 913 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 914 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 915 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 916 g_free(name); 917 918 name = g_strdup_printf("/reboot"); 919 qemu_fdt_add_subnode(ms->fdt, name); 920 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 921 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 922 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 923 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 924 g_free(name); 925 926 name = g_strdup_printf("/poweroff"); 927 qemu_fdt_add_subnode(ms->fdt, name); 928 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 929 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 930 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 931 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 932 g_free(name); 933 } 934 935 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 936 uint32_t irq_mmio_phandle) 937 { 938 char *name; 939 MachineState *ms = MACHINE(s); 940 941 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 942 qemu_fdt_add_subnode(ms->fdt, name); 943 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 944 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 945 0x0, memmap[VIRT_UART0].base, 946 0x0, memmap[VIRT_UART0].size); 947 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 948 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 949 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 950 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 951 } else { 952 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 953 } 954 955 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 956 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 957 g_free(name); 958 } 959 960 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 961 uint32_t irq_mmio_phandle) 962 { 963 char *name; 964 MachineState *ms = MACHINE(s); 965 966 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 967 qemu_fdt_add_subnode(ms->fdt, name); 968 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 969 "google,goldfish-rtc"); 970 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 971 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 972 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 973 irq_mmio_phandle); 974 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 975 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 976 } else { 977 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 978 } 979 g_free(name); 980 } 981 982 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 983 { 984 char *name; 985 MachineState *ms = MACHINE(s); 986 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 987 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 988 989 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 990 qemu_fdt_add_subnode(ms->fdt, name); 991 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 992 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 993 2, flashbase, 2, flashsize, 994 2, flashbase + flashsize, 2, flashsize); 995 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 996 g_free(name); 997 } 998 999 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 1000 { 1001 char *nodename; 1002 MachineState *ms = MACHINE(s); 1003 hwaddr base = memmap[VIRT_FW_CFG].base; 1004 hwaddr size = memmap[VIRT_FW_CFG].size; 1005 1006 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1007 qemu_fdt_add_subnode(ms->fdt, nodename); 1008 qemu_fdt_setprop_string(ms->fdt, nodename, 1009 "compatible", "qemu,fw-cfg-mmio"); 1010 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1011 2, base, 2, size); 1012 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1013 g_free(nodename); 1014 } 1015 1016 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1017 { 1018 MachineState *ms = MACHINE(s); 1019 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1020 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1021 uint8_t rng_seed[32]; 1022 1023 ms->fdt = create_device_tree(&s->fdt_size); 1024 if (!ms->fdt) { 1025 error_report("create_device_tree() failed"); 1026 exit(1); 1027 } 1028 1029 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1030 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1031 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1032 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1033 1034 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1035 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1036 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1037 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1038 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1039 1040 create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, 1041 &irq_pcie_phandle, &irq_virtio_phandle, 1042 &msi_pcie_phandle); 1043 1044 create_fdt_virtio(s, memmap, irq_virtio_phandle); 1045 1046 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); 1047 1048 create_fdt_reset(s, memmap, &phandle); 1049 1050 create_fdt_uart(s, memmap, irq_mmio_phandle); 1051 1052 create_fdt_rtc(s, memmap, irq_mmio_phandle); 1053 1054 create_fdt_flash(s, memmap); 1055 create_fdt_fw_cfg(s, memmap); 1056 create_fdt_pmu(s); 1057 1058 /* Pass seed to RNG */ 1059 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1060 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1061 rng_seed, sizeof(rng_seed)); 1062 } 1063 1064 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1065 hwaddr ecam_base, hwaddr ecam_size, 1066 hwaddr mmio_base, hwaddr mmio_size, 1067 hwaddr high_mmio_base, 1068 hwaddr high_mmio_size, 1069 hwaddr pio_base, 1070 DeviceState *irqchip) 1071 { 1072 DeviceState *dev; 1073 MemoryRegion *ecam_alias, *ecam_reg; 1074 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1075 qemu_irq irq; 1076 int i; 1077 1078 dev = qdev_new(TYPE_GPEX_HOST); 1079 1080 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1081 1082 ecam_alias = g_new0(MemoryRegion, 1); 1083 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1084 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1085 ecam_reg, 0, ecam_size); 1086 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1087 1088 mmio_alias = g_new0(MemoryRegion, 1); 1089 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1090 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1091 mmio_reg, mmio_base, mmio_size); 1092 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1093 1094 /* Map high MMIO space */ 1095 high_mmio_alias = g_new0(MemoryRegion, 1); 1096 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1097 mmio_reg, high_mmio_base, high_mmio_size); 1098 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1099 high_mmio_alias); 1100 1101 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1102 1103 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1104 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1105 1106 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1107 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1108 } 1109 1110 return dev; 1111 } 1112 1113 static FWCfgState *create_fw_cfg(const MachineState *ms) 1114 { 1115 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1116 FWCfgState *fw_cfg; 1117 1118 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1119 &address_space_memory); 1120 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1121 1122 return fw_cfg; 1123 } 1124 1125 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1126 int base_hartid, int hart_count) 1127 { 1128 DeviceState *ret; 1129 char *plic_hart_config; 1130 1131 /* Per-socket PLIC hart topology configuration string */ 1132 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1133 1134 /* Per-socket PLIC */ 1135 ret = sifive_plic_create( 1136 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1137 plic_hart_config, hart_count, base_hartid, 1138 VIRT_IRQCHIP_NUM_SOURCES, 1139 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1140 VIRT_PLIC_PRIORITY_BASE, 1141 VIRT_PLIC_PENDING_BASE, 1142 VIRT_PLIC_ENABLE_BASE, 1143 VIRT_PLIC_ENABLE_STRIDE, 1144 VIRT_PLIC_CONTEXT_BASE, 1145 VIRT_PLIC_CONTEXT_STRIDE, 1146 memmap[VIRT_PLIC].size); 1147 1148 g_free(plic_hart_config); 1149 1150 return ret; 1151 } 1152 1153 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1154 const MemMapEntry *memmap, int socket, 1155 int base_hartid, int hart_count) 1156 { 1157 int i; 1158 hwaddr addr; 1159 uint32_t guest_bits; 1160 DeviceState *aplic_m; 1161 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; 1162 1163 if (msimode) { 1164 /* Per-socket M-level IMSICs */ 1165 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1166 for (i = 0; i < hart_count; i++) { 1167 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1168 base_hartid + i, true, 1, 1169 VIRT_IRQCHIP_NUM_MSIS); 1170 } 1171 1172 /* Per-socket S-level IMSICs */ 1173 guest_bits = imsic_num_bits(aia_guests + 1); 1174 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1175 for (i = 0; i < hart_count; i++) { 1176 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1177 base_hartid + i, false, 1 + aia_guests, 1178 VIRT_IRQCHIP_NUM_MSIS); 1179 } 1180 } 1181 1182 /* Per-socket M-level APLIC */ 1183 aplic_m = riscv_aplic_create( 1184 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, 1185 memmap[VIRT_APLIC_M].size, 1186 (msimode) ? 0 : base_hartid, 1187 (msimode) ? 0 : hart_count, 1188 VIRT_IRQCHIP_NUM_SOURCES, 1189 VIRT_IRQCHIP_NUM_PRIO_BITS, 1190 msimode, true, NULL); 1191 1192 if (aplic_m) { 1193 /* Per-socket S-level APLIC */ 1194 riscv_aplic_create( 1195 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, 1196 memmap[VIRT_APLIC_S].size, 1197 (msimode) ? 0 : base_hartid, 1198 (msimode) ? 0 : hart_count, 1199 VIRT_IRQCHIP_NUM_SOURCES, 1200 VIRT_IRQCHIP_NUM_PRIO_BITS, 1201 msimode, false, aplic_m); 1202 } 1203 1204 return aplic_m; 1205 } 1206 1207 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1208 { 1209 DeviceState *dev; 1210 SysBusDevice *sysbus; 1211 const MemMapEntry *memmap = virt_memmap; 1212 int i; 1213 MemoryRegion *sysmem = get_system_memory(); 1214 1215 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1216 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1217 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1218 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1219 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1220 s->platform_bus_dev = dev; 1221 1222 sysbus = SYS_BUS_DEVICE(dev); 1223 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1224 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1225 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1226 } 1227 1228 memory_region_add_subregion(sysmem, 1229 memmap[VIRT_PLATFORM_BUS].base, 1230 sysbus_mmio_get_region(sysbus, 0)); 1231 } 1232 1233 static void virt_machine_done(Notifier *notifier, void *data) 1234 { 1235 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1236 machine_done); 1237 const MemMapEntry *memmap = virt_memmap; 1238 MachineState *machine = MACHINE(s); 1239 target_ulong start_addr = memmap[VIRT_DRAM].base; 1240 target_ulong firmware_end_addr, kernel_start_addr; 1241 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1242 uint32_t fdt_load_addr; 1243 uint64_t kernel_entry; 1244 1245 /* 1246 * Only direct boot kernel is currently supported for KVM VM, 1247 * so the "-bios" parameter is not supported when KVM is enabled. 1248 */ 1249 if (kvm_enabled()) { 1250 if (machine->firmware) { 1251 if (strcmp(machine->firmware, "none")) { 1252 error_report("Machine mode firmware is not supported in " 1253 "combination with KVM."); 1254 exit(1); 1255 } 1256 } else { 1257 machine->firmware = g_strdup("none"); 1258 } 1259 } 1260 1261 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1262 start_addr, NULL); 1263 1264 if (drive_get(IF_PFLASH, 0, 1)) { 1265 /* 1266 * S-mode FW like EDK2 will be kept in second plash (unit 1). 1267 * When both kernel, initrd and pflash options are provided in the 1268 * command line, the kernel and initrd will be copied to the fw_cfg 1269 * table and opensbi will jump to the flash address which is the 1270 * entry point of S-mode FW. It is the job of the S-mode FW to load 1271 * the kernel and initrd using fw_cfg table. 1272 * 1273 * If only pflash is given but not -kernel, then it is the job of 1274 * of the S-mode firmware to locate and load the kernel. 1275 * In either case, the next_addr for opensbi will be the flash address. 1276 */ 1277 riscv_setup_firmware_boot(machine); 1278 kernel_entry = virt_memmap[VIRT_FLASH].base + 1279 virt_memmap[VIRT_FLASH].size / 2; 1280 } else if (machine->kernel_filename) { 1281 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1282 firmware_end_addr); 1283 1284 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1285 kernel_start_addr, true, NULL); 1286 } else { 1287 /* 1288 * If dynamic firmware is used, it doesn't know where is the next mode 1289 * if kernel argument is not set. 1290 */ 1291 kernel_entry = 0; 1292 } 1293 1294 if (drive_get(IF_PFLASH, 0, 0)) { 1295 /* 1296 * Pflash was supplied, let's overwrite the address we jump to after 1297 * reset to the base of the flash. 1298 */ 1299 start_addr = virt_memmap[VIRT_FLASH].base; 1300 } 1301 1302 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1303 memmap[VIRT_DRAM].size, 1304 machine); 1305 riscv_load_fdt(fdt_load_addr, machine->fdt); 1306 1307 /* load the reset vector */ 1308 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1309 virt_memmap[VIRT_MROM].base, 1310 virt_memmap[VIRT_MROM].size, kernel_entry, 1311 fdt_load_addr); 1312 1313 /* 1314 * Only direct boot kernel is currently supported for KVM VM, 1315 * So here setup kernel start address and fdt address. 1316 * TODO:Support firmware loading and integrate to TCG start 1317 */ 1318 if (kvm_enabled()) { 1319 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1320 } 1321 } 1322 1323 static void virt_machine_init(MachineState *machine) 1324 { 1325 const MemMapEntry *memmap = virt_memmap; 1326 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1327 MemoryRegion *system_memory = get_system_memory(); 1328 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1329 char *soc_name; 1330 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1331 int i, base_hartid, hart_count; 1332 int socket_count = riscv_socket_count(machine); 1333 1334 /* Check socket count limit */ 1335 if (VIRT_SOCKETS_MAX < socket_count) { 1336 error_report("number of sockets/nodes should be less than %d", 1337 VIRT_SOCKETS_MAX); 1338 exit(1); 1339 } 1340 1341 /* Initialize sockets */ 1342 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1343 for (i = 0; i < socket_count; i++) { 1344 if (!riscv_socket_check_hartids(machine, i)) { 1345 error_report("discontinuous hartids in socket%d", i); 1346 exit(1); 1347 } 1348 1349 base_hartid = riscv_socket_first_hartid(machine, i); 1350 if (base_hartid < 0) { 1351 error_report("can't find hartid base for socket%d", i); 1352 exit(1); 1353 } 1354 1355 hart_count = riscv_socket_hart_count(machine, i); 1356 if (hart_count < 0) { 1357 error_report("can't find hart count for socket%d", i); 1358 exit(1); 1359 } 1360 1361 soc_name = g_strdup_printf("soc%d", i); 1362 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1363 TYPE_RISCV_HART_ARRAY); 1364 g_free(soc_name); 1365 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1366 machine->cpu_type, &error_abort); 1367 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1368 base_hartid, &error_abort); 1369 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1370 hart_count, &error_abort); 1371 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1372 1373 if (!kvm_enabled()) { 1374 if (s->have_aclint) { 1375 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1376 /* Per-socket ACLINT MTIMER */ 1377 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1378 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1379 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1380 base_hartid, hart_count, 1381 RISCV_ACLINT_DEFAULT_MTIMECMP, 1382 RISCV_ACLINT_DEFAULT_MTIME, 1383 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1384 } else { 1385 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1386 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1387 i * memmap[VIRT_CLINT].size, 1388 base_hartid, hart_count, false); 1389 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1390 i * memmap[VIRT_CLINT].size + 1391 RISCV_ACLINT_SWI_SIZE, 1392 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1393 base_hartid, hart_count, 1394 RISCV_ACLINT_DEFAULT_MTIMECMP, 1395 RISCV_ACLINT_DEFAULT_MTIME, 1396 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1397 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1398 i * memmap[VIRT_ACLINT_SSWI].size, 1399 base_hartid, hart_count, true); 1400 } 1401 } else { 1402 /* Per-socket SiFive CLINT */ 1403 riscv_aclint_swi_create( 1404 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1405 base_hartid, hart_count, false); 1406 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1407 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1408 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1409 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1410 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1411 } 1412 } 1413 1414 /* Per-socket interrupt controller */ 1415 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1416 s->irqchip[i] = virt_create_plic(memmap, i, 1417 base_hartid, hart_count); 1418 } else { 1419 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1420 memmap, i, base_hartid, 1421 hart_count); 1422 } 1423 1424 /* Try to use different IRQCHIP instance based device type */ 1425 if (i == 0) { 1426 mmio_irqchip = s->irqchip[i]; 1427 virtio_irqchip = s->irqchip[i]; 1428 pcie_irqchip = s->irqchip[i]; 1429 } 1430 if (i == 1) { 1431 virtio_irqchip = s->irqchip[i]; 1432 pcie_irqchip = s->irqchip[i]; 1433 } 1434 if (i == 2) { 1435 pcie_irqchip = s->irqchip[i]; 1436 } 1437 } 1438 1439 if (riscv_is_32bit(&s->soc[0])) { 1440 #if HOST_LONG_BITS == 64 1441 /* limit RAM size in a 32-bit system */ 1442 if (machine->ram_size > 10 * GiB) { 1443 machine->ram_size = 10 * GiB; 1444 error_report("Limiting RAM size to 10 GiB"); 1445 } 1446 #endif 1447 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1448 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1449 } else { 1450 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1451 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1452 virt_high_pcie_memmap.base = 1453 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1454 } 1455 1456 /* register system main memory (actual RAM) */ 1457 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1458 machine->ram); 1459 1460 /* boot rom */ 1461 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1462 memmap[VIRT_MROM].size, &error_fatal); 1463 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1464 mask_rom); 1465 1466 /* 1467 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1468 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1469 */ 1470 s->fw_cfg = create_fw_cfg(machine); 1471 rom_set_fw(s->fw_cfg); 1472 1473 /* SiFive Test MMIO device */ 1474 sifive_test_create(memmap[VIRT_TEST].base); 1475 1476 /* VirtIO MMIO devices */ 1477 for (i = 0; i < VIRTIO_COUNT; i++) { 1478 sysbus_create_simple("virtio-mmio", 1479 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1480 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); 1481 } 1482 1483 gpex_pcie_init(system_memory, 1484 memmap[VIRT_PCIE_ECAM].base, 1485 memmap[VIRT_PCIE_ECAM].size, 1486 memmap[VIRT_PCIE_MMIO].base, 1487 memmap[VIRT_PCIE_MMIO].size, 1488 virt_high_pcie_memmap.base, 1489 virt_high_pcie_memmap.size, 1490 memmap[VIRT_PCIE_PIO].base, 1491 DEVICE(pcie_irqchip)); 1492 1493 create_platform_bus(s, DEVICE(mmio_irqchip)); 1494 1495 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1496 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, 1497 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1498 1499 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1500 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); 1501 1502 virt_flash_create(s); 1503 1504 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1505 /* Map legacy -drive if=pflash to machine properties */ 1506 pflash_cfi01_legacy_drive(s->flash[i], 1507 drive_get(IF_PFLASH, 0, i)); 1508 } 1509 virt_flash_map(s, system_memory); 1510 1511 /* load/create device tree */ 1512 if (machine->dtb) { 1513 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1514 if (!machine->fdt) { 1515 error_report("load_device_tree() failed"); 1516 exit(1); 1517 } 1518 } else { 1519 create_fdt(s, memmap); 1520 } 1521 1522 s->machine_done.notify = virt_machine_done; 1523 qemu_add_machine_init_done_notifier(&s->machine_done); 1524 } 1525 1526 static void virt_machine_instance_init(Object *obj) 1527 { 1528 } 1529 1530 static char *virt_get_aia_guests(Object *obj, Error **errp) 1531 { 1532 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1533 char val[32]; 1534 1535 sprintf(val, "%d", s->aia_guests); 1536 return g_strdup(val); 1537 } 1538 1539 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1540 { 1541 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1542 1543 s->aia_guests = atoi(val); 1544 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1545 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1546 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1547 VIRT_IRQCHIP_MAX_GUESTS); 1548 } 1549 } 1550 1551 static char *virt_get_aia(Object *obj, Error **errp) 1552 { 1553 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1554 const char *val; 1555 1556 switch (s->aia_type) { 1557 case VIRT_AIA_TYPE_APLIC: 1558 val = "aplic"; 1559 break; 1560 case VIRT_AIA_TYPE_APLIC_IMSIC: 1561 val = "aplic-imsic"; 1562 break; 1563 default: 1564 val = "none"; 1565 break; 1566 }; 1567 1568 return g_strdup(val); 1569 } 1570 1571 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1572 { 1573 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1574 1575 if (!strcmp(val, "none")) { 1576 s->aia_type = VIRT_AIA_TYPE_NONE; 1577 } else if (!strcmp(val, "aplic")) { 1578 s->aia_type = VIRT_AIA_TYPE_APLIC; 1579 } else if (!strcmp(val, "aplic-imsic")) { 1580 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1581 } else { 1582 error_setg(errp, "Invalid AIA interrupt controller type"); 1583 error_append_hint(errp, "Valid values are none, aplic, and " 1584 "aplic-imsic.\n"); 1585 } 1586 } 1587 1588 static bool virt_get_aclint(Object *obj, Error **errp) 1589 { 1590 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1591 1592 return s->have_aclint; 1593 } 1594 1595 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1596 { 1597 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1598 1599 s->have_aclint = value; 1600 } 1601 1602 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1603 DeviceState *dev) 1604 { 1605 MachineClass *mc = MACHINE_GET_CLASS(machine); 1606 1607 if (device_is_dynamic_sysbus(mc, dev)) { 1608 return HOTPLUG_HANDLER(machine); 1609 } 1610 return NULL; 1611 } 1612 1613 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1614 DeviceState *dev, Error **errp) 1615 { 1616 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1617 1618 if (s->platform_bus_dev) { 1619 MachineClass *mc = MACHINE_GET_CLASS(s); 1620 1621 if (device_is_dynamic_sysbus(mc, dev)) { 1622 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1623 SYS_BUS_DEVICE(dev)); 1624 } 1625 } 1626 } 1627 1628 static void virt_machine_class_init(ObjectClass *oc, void *data) 1629 { 1630 char str[128]; 1631 MachineClass *mc = MACHINE_CLASS(oc); 1632 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1633 1634 mc->desc = "RISC-V VirtIO board"; 1635 mc->init = virt_machine_init; 1636 mc->max_cpus = VIRT_CPUS_MAX; 1637 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1638 mc->pci_allow_0_address = true; 1639 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1640 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1641 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1642 mc->numa_mem_supported = true; 1643 mc->default_ram_id = "riscv_virt_board.ram"; 1644 assert(!mc->get_hotplug_handler); 1645 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1646 1647 hc->plug = virt_machine_device_plug_cb; 1648 1649 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1650 #ifdef CONFIG_TPM 1651 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1652 #endif 1653 1654 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1655 virt_set_aclint); 1656 object_class_property_set_description(oc, "aclint", 1657 "Set on/off to enable/disable " 1658 "emulating ACLINT devices"); 1659 1660 object_class_property_add_str(oc, "aia", virt_get_aia, 1661 virt_set_aia); 1662 object_class_property_set_description(oc, "aia", 1663 "Set type of AIA interrupt " 1664 "conttoller. Valid values are " 1665 "none, aplic, and aplic-imsic."); 1666 1667 object_class_property_add_str(oc, "aia-guests", 1668 virt_get_aia_guests, 1669 virt_set_aia_guests); 1670 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1671 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1672 object_class_property_set_description(oc, "aia-guests", str); 1673 } 1674 1675 static const TypeInfo virt_machine_typeinfo = { 1676 .name = MACHINE_TYPE_NAME("virt"), 1677 .parent = TYPE_MACHINE, 1678 .class_init = virt_machine_class_init, 1679 .instance_init = virt_machine_instance_init, 1680 .instance_size = sizeof(RISCVVirtState), 1681 .interfaces = (InterfaceInfo[]) { 1682 { TYPE_HOTPLUG_HANDLER }, 1683 { } 1684 }, 1685 }; 1686 1687 static void virt_machine_init_register_types(void) 1688 { 1689 type_register_static(&virt_machine_typeinfo); 1690 } 1691 1692 type_init(virt_machine_init_register_types) 1693