1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "kvm/kvm_riscv.h" 39 #include "hw/intc/riscv_aclint.h" 40 #include "hw/intc/riscv_aplic.h" 41 #include "hw/intc/sifive_plic.h" 42 #include "hw/misc/sifive_test.h" 43 #include "hw/platform-bus.h" 44 #include "chardev/char.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/tcg.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/tpm.h" 50 #include "hw/pci/pci.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/display/ramfb.h" 53 #include "hw/acpi/aml-build.h" 54 #include "qapi/qapi-visit-common.h" 55 56 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 57 static bool virt_use_kvm_aia(RISCVVirtState *s) 58 { 59 return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 60 } 61 62 static const MemMapEntry virt_memmap[] = { 63 [VIRT_DEBUG] = { 0x0, 0x100 }, 64 [VIRT_MROM] = { 0x1000, 0xf000 }, 65 [VIRT_TEST] = { 0x100000, 0x1000 }, 66 [VIRT_RTC] = { 0x101000, 0x1000 }, 67 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 68 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 69 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 70 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 71 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 72 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 73 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 74 [VIRT_UART0] = { 0x10000000, 0x100 }, 75 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 76 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 77 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 78 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 79 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 80 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 81 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 82 [VIRT_DRAM] = { 0x80000000, 0x0 }, 83 }; 84 85 /* PCIe high mmio is fixed for RV32 */ 86 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 87 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 88 89 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 90 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 91 92 static MemMapEntry virt_high_pcie_memmap; 93 94 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 95 96 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 97 const char *name, 98 const char *alias_prop_name) 99 { 100 /* 101 * Create a single flash device. We use the same parameters as 102 * the flash devices on the ARM virt board. 103 */ 104 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 105 106 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 107 qdev_prop_set_uint8(dev, "width", 4); 108 qdev_prop_set_uint8(dev, "device-width", 2); 109 qdev_prop_set_bit(dev, "big-endian", false); 110 qdev_prop_set_uint16(dev, "id0", 0x89); 111 qdev_prop_set_uint16(dev, "id1", 0x18); 112 qdev_prop_set_uint16(dev, "id2", 0x00); 113 qdev_prop_set_uint16(dev, "id3", 0x00); 114 qdev_prop_set_string(dev, "name", name); 115 116 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 117 object_property_add_alias(OBJECT(s), alias_prop_name, 118 OBJECT(dev), "drive"); 119 120 return PFLASH_CFI01(dev); 121 } 122 123 static void virt_flash_create(RISCVVirtState *s) 124 { 125 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 126 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 127 } 128 129 static void virt_flash_map1(PFlashCFI01 *flash, 130 hwaddr base, hwaddr size, 131 MemoryRegion *sysmem) 132 { 133 DeviceState *dev = DEVICE(flash); 134 135 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 136 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 137 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 138 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 139 140 memory_region_add_subregion(sysmem, base, 141 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 142 0)); 143 } 144 145 static void virt_flash_map(RISCVVirtState *s, 146 MemoryRegion *sysmem) 147 { 148 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 149 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 150 151 virt_flash_map1(s->flash[0], flashbase, flashsize, 152 sysmem); 153 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 154 sysmem); 155 } 156 157 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 158 uint32_t irqchip_phandle) 159 { 160 int pin, dev; 161 uint32_t irq_map_stride = 0; 162 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 163 FDT_MAX_INT_MAP_WIDTH] = {}; 164 uint32_t *irq_map = full_irq_map; 165 166 /* This code creates a standard swizzle of interrupts such that 167 * each device's first interrupt is based on it's PCI_SLOT number. 168 * (See pci_swizzle_map_irq_fn()) 169 * 170 * We only need one entry per interrupt in the table (not one per 171 * possible slot) seeing the interrupt-map-mask will allow the table 172 * to wrap to any number of devices. 173 */ 174 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 175 int devfn = dev * 0x8; 176 177 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 178 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 179 int i = 0; 180 181 /* Fill PCI address cells */ 182 irq_map[i] = cpu_to_be32(devfn << 8); 183 i += FDT_PCI_ADDR_CELLS; 184 185 /* Fill PCI Interrupt cells */ 186 irq_map[i] = cpu_to_be32(pin + 1); 187 i += FDT_PCI_INT_CELLS; 188 189 /* Fill interrupt controller phandle and cells */ 190 irq_map[i++] = cpu_to_be32(irqchip_phandle); 191 irq_map[i++] = cpu_to_be32(irq_nr); 192 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 193 irq_map[i++] = cpu_to_be32(0x4); 194 } 195 196 if (!irq_map_stride) { 197 irq_map_stride = i; 198 } 199 irq_map += irq_map_stride; 200 } 201 } 202 203 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 204 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 205 irq_map_stride * sizeof(uint32_t)); 206 207 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 208 0x1800, 0, 0, 0x7); 209 } 210 211 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 212 char *clust_name, uint32_t *phandle, 213 uint32_t *intc_phandles) 214 { 215 int cpu; 216 uint32_t cpu_phandle; 217 MachineState *ms = MACHINE(s); 218 char *name, *cpu_name, *core_name, *intc_name, *sv_name; 219 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 220 uint8_t satp_mode_max; 221 222 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 223 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 224 225 cpu_phandle = (*phandle)++; 226 227 cpu_name = g_strdup_printf("/cpus/cpu@%d", 228 s->soc[socket].hartid_base + cpu); 229 qemu_fdt_add_subnode(ms->fdt, cpu_name); 230 231 if (cpu_ptr->cfg.satp_mode.supported != 0) { 232 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 233 sv_name = g_strdup_printf("riscv,%s", 234 satp_mode_str(satp_mode_max, is_32_bit)); 235 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 236 g_free(sv_name); 237 } 238 239 name = riscv_isa_string(cpu_ptr); 240 qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); 241 g_free(name); 242 243 if (cpu_ptr->cfg.ext_zicbom) { 244 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 245 cpu_ptr->cfg.cbom_blocksize); 246 } 247 248 if (cpu_ptr->cfg.ext_zicboz) { 249 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 250 cpu_ptr->cfg.cboz_blocksize); 251 } 252 253 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 254 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 255 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 256 s->soc[socket].hartid_base + cpu); 257 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 258 riscv_socket_fdt_write_id(ms, cpu_name, socket); 259 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 260 261 intc_phandles[cpu] = (*phandle)++; 262 263 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 264 qemu_fdt_add_subnode(ms->fdt, intc_name); 265 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 266 intc_phandles[cpu]); 267 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 268 "riscv,cpu-intc"); 269 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 270 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 271 272 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 273 qemu_fdt_add_subnode(ms->fdt, core_name); 274 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 275 276 g_free(core_name); 277 g_free(intc_name); 278 g_free(cpu_name); 279 } 280 } 281 282 static void create_fdt_socket_memory(RISCVVirtState *s, 283 const MemMapEntry *memmap, int socket) 284 { 285 char *mem_name; 286 uint64_t addr, size; 287 MachineState *ms = MACHINE(s); 288 289 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 290 size = riscv_socket_mem_size(ms, socket); 291 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 292 qemu_fdt_add_subnode(ms->fdt, mem_name); 293 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 294 addr >> 32, addr, size >> 32, size); 295 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 296 riscv_socket_fdt_write_id(ms, mem_name, socket); 297 g_free(mem_name); 298 } 299 300 static void create_fdt_socket_clint(RISCVVirtState *s, 301 const MemMapEntry *memmap, int socket, 302 uint32_t *intc_phandles) 303 { 304 int cpu; 305 char *clint_name; 306 uint32_t *clint_cells; 307 unsigned long clint_addr; 308 MachineState *ms = MACHINE(s); 309 static const char * const clint_compat[2] = { 310 "sifive,clint0", "riscv,clint0" 311 }; 312 313 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 314 315 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 316 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 317 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 318 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 319 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 320 } 321 322 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 323 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 324 qemu_fdt_add_subnode(ms->fdt, clint_name); 325 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 326 (char **)&clint_compat, 327 ARRAY_SIZE(clint_compat)); 328 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 329 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 330 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 331 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 332 riscv_socket_fdt_write_id(ms, clint_name, socket); 333 g_free(clint_name); 334 335 g_free(clint_cells); 336 } 337 338 static void create_fdt_socket_aclint(RISCVVirtState *s, 339 const MemMapEntry *memmap, int socket, 340 uint32_t *intc_phandles) 341 { 342 int cpu; 343 char *name; 344 unsigned long addr, size; 345 uint32_t aclint_cells_size; 346 uint32_t *aclint_mswi_cells; 347 uint32_t *aclint_sswi_cells; 348 uint32_t *aclint_mtimer_cells; 349 MachineState *ms = MACHINE(s); 350 351 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 352 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 353 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 354 355 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 356 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 357 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 358 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 359 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 360 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 361 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 362 } 363 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 364 365 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 366 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 367 name = g_strdup_printf("/soc/mswi@%lx", addr); 368 qemu_fdt_add_subnode(ms->fdt, name); 369 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 370 "riscv,aclint-mswi"); 371 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 372 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 373 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 374 aclint_mswi_cells, aclint_cells_size); 375 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 376 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 377 riscv_socket_fdt_write_id(ms, name, socket); 378 g_free(name); 379 } 380 381 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 382 addr = memmap[VIRT_CLINT].base + 383 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 384 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 385 } else { 386 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 387 (memmap[VIRT_CLINT].size * socket); 388 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 389 } 390 name = g_strdup_printf("/soc/mtimer@%lx", addr); 391 qemu_fdt_add_subnode(ms->fdt, name); 392 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 393 "riscv,aclint-mtimer"); 394 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 395 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 396 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 397 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 398 0x0, RISCV_ACLINT_DEFAULT_MTIME); 399 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 400 aclint_mtimer_cells, aclint_cells_size); 401 riscv_socket_fdt_write_id(ms, name, socket); 402 g_free(name); 403 404 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 405 addr = memmap[VIRT_ACLINT_SSWI].base + 406 (memmap[VIRT_ACLINT_SSWI].size * socket); 407 name = g_strdup_printf("/soc/sswi@%lx", addr); 408 qemu_fdt_add_subnode(ms->fdt, name); 409 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 410 "riscv,aclint-sswi"); 411 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 412 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 413 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 414 aclint_sswi_cells, aclint_cells_size); 415 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 416 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 417 riscv_socket_fdt_write_id(ms, name, socket); 418 g_free(name); 419 } 420 421 g_free(aclint_mswi_cells); 422 g_free(aclint_mtimer_cells); 423 g_free(aclint_sswi_cells); 424 } 425 426 static void create_fdt_socket_plic(RISCVVirtState *s, 427 const MemMapEntry *memmap, int socket, 428 uint32_t *phandle, uint32_t *intc_phandles, 429 uint32_t *plic_phandles) 430 { 431 int cpu; 432 char *plic_name; 433 uint32_t *plic_cells; 434 unsigned long plic_addr; 435 MachineState *ms = MACHINE(s); 436 static const char * const plic_compat[2] = { 437 "sifive,plic-1.0.0", "riscv,plic0" 438 }; 439 440 plic_phandles[socket] = (*phandle)++; 441 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 442 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 443 qemu_fdt_add_subnode(ms->fdt, plic_name); 444 qemu_fdt_setprop_cell(ms->fdt, plic_name, 445 "#interrupt-cells", FDT_PLIC_INT_CELLS); 446 qemu_fdt_setprop_cell(ms->fdt, plic_name, 447 "#address-cells", FDT_PLIC_ADDR_CELLS); 448 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 449 (char **)&plic_compat, 450 ARRAY_SIZE(plic_compat)); 451 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 452 453 if (kvm_enabled()) { 454 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 455 456 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 457 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 458 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 459 } 460 461 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 462 plic_cells, 463 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 464 } else { 465 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 466 467 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 468 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 469 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 470 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 471 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 472 } 473 474 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 475 plic_cells, 476 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 477 } 478 479 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 480 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 481 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 482 VIRT_IRQCHIP_NUM_SOURCES - 1); 483 riscv_socket_fdt_write_id(ms, plic_name, socket); 484 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 485 plic_phandles[socket]); 486 487 if (!socket) { 488 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 489 memmap[VIRT_PLATFORM_BUS].base, 490 memmap[VIRT_PLATFORM_BUS].size, 491 VIRT_PLATFORM_BUS_IRQ); 492 } 493 494 g_free(plic_name); 495 496 g_free(plic_cells); 497 } 498 499 uint32_t imsic_num_bits(uint32_t count) 500 { 501 uint32_t ret = 0; 502 503 while (BIT(ret) < count) { 504 ret++; 505 } 506 507 return ret; 508 } 509 510 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 511 uint32_t *intc_phandles, uint32_t msi_phandle, 512 bool m_mode, uint32_t imsic_guest_bits) 513 { 514 int cpu, socket; 515 char *imsic_name; 516 MachineState *ms = MACHINE(s); 517 int socket_count = riscv_socket_count(ms); 518 uint32_t imsic_max_hart_per_socket; 519 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 520 521 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 522 imsic_regs = g_new0(uint32_t, socket_count * 4); 523 524 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 525 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 526 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 527 } 528 529 imsic_max_hart_per_socket = 0; 530 for (socket = 0; socket < socket_count; socket++) { 531 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 532 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 533 s->soc[socket].num_harts; 534 imsic_regs[socket * 4 + 0] = 0; 535 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 536 imsic_regs[socket * 4 + 2] = 0; 537 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 538 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 539 imsic_max_hart_per_socket = s->soc[socket].num_harts; 540 } 541 } 542 543 imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr); 544 qemu_fdt_add_subnode(ms->fdt, imsic_name); 545 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); 546 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 547 FDT_IMSIC_INT_CELLS); 548 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 549 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 550 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 551 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 552 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 553 socket_count * sizeof(uint32_t) * 4); 554 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 555 VIRT_IRQCHIP_NUM_MSIS); 556 557 if (imsic_guest_bits) { 558 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 559 imsic_guest_bits); 560 } 561 562 if (socket_count > 1) { 563 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 564 imsic_num_bits(imsic_max_hart_per_socket)); 565 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 566 imsic_num_bits(socket_count)); 567 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 568 IMSIC_MMIO_GROUP_MIN_SHIFT); 569 } 570 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 571 572 g_free(imsic_name); 573 g_free(imsic_regs); 574 g_free(imsic_cells); 575 } 576 577 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 578 uint32_t *phandle, uint32_t *intc_phandles, 579 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 580 { 581 *msi_m_phandle = (*phandle)++; 582 *msi_s_phandle = (*phandle)++; 583 584 if (!kvm_enabled()) { 585 /* M-level IMSIC node */ 586 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 587 *msi_m_phandle, true, 0); 588 } 589 590 /* S-level IMSIC node */ 591 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 592 *msi_s_phandle, false, 593 imsic_num_bits(s->aia_guests + 1)); 594 595 } 596 597 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 598 unsigned long aplic_addr, uint32_t aplic_size, 599 uint32_t msi_phandle, 600 uint32_t *intc_phandles, 601 uint32_t aplic_phandle, 602 uint32_t aplic_child_phandle, 603 bool m_mode, int num_harts) 604 { 605 int cpu; 606 char *aplic_name; 607 uint32_t *aplic_cells; 608 MachineState *ms = MACHINE(s); 609 610 aplic_cells = g_new0(uint32_t, num_harts * 2); 611 612 for (cpu = 0; cpu < num_harts; cpu++) { 613 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 614 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 615 } 616 617 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 618 qemu_fdt_add_subnode(ms->fdt, aplic_name); 619 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); 620 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 621 "#interrupt-cells", FDT_APLIC_INT_CELLS); 622 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 623 624 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 625 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 626 aplic_cells, num_harts * sizeof(uint32_t) * 2); 627 } else { 628 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 629 } 630 631 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 632 0x0, aplic_addr, 0x0, aplic_size); 633 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 634 VIRT_IRQCHIP_NUM_SOURCES); 635 636 if (aplic_child_phandle) { 637 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 638 aplic_child_phandle); 639 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 640 aplic_child_phandle, 0x1, 641 VIRT_IRQCHIP_NUM_SOURCES); 642 } 643 644 riscv_socket_fdt_write_id(ms, aplic_name, socket); 645 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 646 647 g_free(aplic_name); 648 g_free(aplic_cells); 649 } 650 651 static void create_fdt_socket_aplic(RISCVVirtState *s, 652 const MemMapEntry *memmap, int socket, 653 uint32_t msi_m_phandle, 654 uint32_t msi_s_phandle, 655 uint32_t *phandle, 656 uint32_t *intc_phandles, 657 uint32_t *aplic_phandles, 658 int num_harts) 659 { 660 char *aplic_name; 661 unsigned long aplic_addr; 662 MachineState *ms = MACHINE(s); 663 uint32_t aplic_m_phandle, aplic_s_phandle; 664 665 aplic_m_phandle = (*phandle)++; 666 aplic_s_phandle = (*phandle)++; 667 668 if (!kvm_enabled()) { 669 /* M-level APLIC node */ 670 aplic_addr = memmap[VIRT_APLIC_M].base + 671 (memmap[VIRT_APLIC_M].size * socket); 672 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 673 msi_m_phandle, intc_phandles, 674 aplic_m_phandle, aplic_s_phandle, 675 true, num_harts); 676 } 677 678 /* S-level APLIC node */ 679 aplic_addr = memmap[VIRT_APLIC_S].base + 680 (memmap[VIRT_APLIC_S].size * socket); 681 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 682 msi_s_phandle, intc_phandles, 683 aplic_s_phandle, 0, 684 false, num_harts); 685 686 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 687 688 if (!socket) { 689 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 690 memmap[VIRT_PLATFORM_BUS].base, 691 memmap[VIRT_PLATFORM_BUS].size, 692 VIRT_PLATFORM_BUS_IRQ); 693 } 694 695 g_free(aplic_name); 696 697 aplic_phandles[socket] = aplic_s_phandle; 698 } 699 700 static void create_fdt_pmu(RISCVVirtState *s) 701 { 702 char *pmu_name; 703 MachineState *ms = MACHINE(s); 704 RISCVCPU hart = s->soc[0].harts[0]; 705 706 pmu_name = g_strdup_printf("/pmu"); 707 qemu_fdt_add_subnode(ms->fdt, pmu_name); 708 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 709 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 710 711 g_free(pmu_name); 712 } 713 714 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 715 uint32_t *phandle, 716 uint32_t *irq_mmio_phandle, 717 uint32_t *irq_pcie_phandle, 718 uint32_t *irq_virtio_phandle, 719 uint32_t *msi_pcie_phandle) 720 { 721 char *clust_name; 722 int socket, phandle_pos; 723 MachineState *ms = MACHINE(s); 724 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 725 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 726 int socket_count = riscv_socket_count(ms); 727 728 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 729 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 730 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 731 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 732 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 733 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 734 735 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 736 737 phandle_pos = ms->smp.cpus; 738 for (socket = (socket_count - 1); socket >= 0; socket--) { 739 phandle_pos -= s->soc[socket].num_harts; 740 741 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 742 qemu_fdt_add_subnode(ms->fdt, clust_name); 743 744 create_fdt_socket_cpus(s, socket, clust_name, phandle, 745 &intc_phandles[phandle_pos]); 746 747 create_fdt_socket_memory(s, memmap, socket); 748 749 g_free(clust_name); 750 751 if (tcg_enabled()) { 752 if (s->have_aclint) { 753 create_fdt_socket_aclint(s, memmap, socket, 754 &intc_phandles[phandle_pos]); 755 } else { 756 create_fdt_socket_clint(s, memmap, socket, 757 &intc_phandles[phandle_pos]); 758 } 759 } 760 } 761 762 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 763 create_fdt_imsic(s, memmap, phandle, intc_phandles, 764 &msi_m_phandle, &msi_s_phandle); 765 *msi_pcie_phandle = msi_s_phandle; 766 } 767 768 /* KVM AIA only has one APLIC instance */ 769 if (kvm_enabled() && virt_use_kvm_aia(s)) { 770 create_fdt_socket_aplic(s, memmap, 0, 771 msi_m_phandle, msi_s_phandle, phandle, 772 &intc_phandles[0], xplic_phandles, 773 ms->smp.cpus); 774 } else { 775 phandle_pos = ms->smp.cpus; 776 for (socket = (socket_count - 1); socket >= 0; socket--) { 777 phandle_pos -= s->soc[socket].num_harts; 778 779 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 780 create_fdt_socket_plic(s, memmap, socket, phandle, 781 &intc_phandles[phandle_pos], 782 xplic_phandles); 783 } else { 784 create_fdt_socket_aplic(s, memmap, socket, 785 msi_m_phandle, msi_s_phandle, phandle, 786 &intc_phandles[phandle_pos], 787 xplic_phandles, 788 s->soc[socket].num_harts); 789 } 790 } 791 } 792 793 g_free(intc_phandles); 794 795 if (kvm_enabled() && virt_use_kvm_aia(s)) { 796 *irq_mmio_phandle = xplic_phandles[0]; 797 *irq_virtio_phandle = xplic_phandles[0]; 798 *irq_pcie_phandle = xplic_phandles[0]; 799 } else { 800 for (socket = 0; socket < socket_count; socket++) { 801 if (socket == 0) { 802 *irq_mmio_phandle = xplic_phandles[socket]; 803 *irq_virtio_phandle = xplic_phandles[socket]; 804 *irq_pcie_phandle = xplic_phandles[socket]; 805 } 806 if (socket == 1) { 807 *irq_virtio_phandle = xplic_phandles[socket]; 808 *irq_pcie_phandle = xplic_phandles[socket]; 809 } 810 if (socket == 2) { 811 *irq_pcie_phandle = xplic_phandles[socket]; 812 } 813 } 814 } 815 816 riscv_socket_fdt_write_distance_matrix(ms); 817 } 818 819 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 820 uint32_t irq_virtio_phandle) 821 { 822 int i; 823 char *name; 824 MachineState *ms = MACHINE(s); 825 826 for (i = 0; i < VIRTIO_COUNT; i++) { 827 name = g_strdup_printf("/soc/virtio_mmio@%lx", 828 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 829 qemu_fdt_add_subnode(ms->fdt, name); 830 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 831 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 832 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 833 0x0, memmap[VIRT_VIRTIO].size); 834 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 835 irq_virtio_phandle); 836 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 837 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 838 VIRTIO_IRQ + i); 839 } else { 840 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 841 VIRTIO_IRQ + i, 0x4); 842 } 843 g_free(name); 844 } 845 } 846 847 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 848 uint32_t irq_pcie_phandle, 849 uint32_t msi_pcie_phandle) 850 { 851 char *name; 852 MachineState *ms = MACHINE(s); 853 854 name = g_strdup_printf("/soc/pci@%lx", 855 (long) memmap[VIRT_PCIE_ECAM].base); 856 qemu_fdt_add_subnode(ms->fdt, name); 857 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 858 FDT_PCI_ADDR_CELLS); 859 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 860 FDT_PCI_INT_CELLS); 861 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 862 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 863 "pci-host-ecam-generic"); 864 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 865 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 866 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 867 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 868 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 869 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 870 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 871 } 872 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 873 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 874 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 875 1, FDT_PCI_RANGE_IOPORT, 2, 0, 876 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 877 1, FDT_PCI_RANGE_MMIO, 878 2, memmap[VIRT_PCIE_MMIO].base, 879 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 880 1, FDT_PCI_RANGE_MMIO_64BIT, 881 2, virt_high_pcie_memmap.base, 882 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 883 884 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 885 g_free(name); 886 } 887 888 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 889 uint32_t *phandle) 890 { 891 char *name; 892 uint32_t test_phandle; 893 MachineState *ms = MACHINE(s); 894 895 test_phandle = (*phandle)++; 896 name = g_strdup_printf("/soc/test@%lx", 897 (long)memmap[VIRT_TEST].base); 898 qemu_fdt_add_subnode(ms->fdt, name); 899 { 900 static const char * const compat[3] = { 901 "sifive,test1", "sifive,test0", "syscon" 902 }; 903 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 904 (char **)&compat, ARRAY_SIZE(compat)); 905 } 906 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 907 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 908 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 909 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 910 g_free(name); 911 912 name = g_strdup_printf("/reboot"); 913 qemu_fdt_add_subnode(ms->fdt, name); 914 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 915 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 916 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 917 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 918 g_free(name); 919 920 name = g_strdup_printf("/poweroff"); 921 qemu_fdt_add_subnode(ms->fdt, name); 922 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 923 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 924 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 925 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 926 g_free(name); 927 } 928 929 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 930 uint32_t irq_mmio_phandle) 931 { 932 char *name; 933 MachineState *ms = MACHINE(s); 934 935 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 936 qemu_fdt_add_subnode(ms->fdt, name); 937 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 938 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 939 0x0, memmap[VIRT_UART0].base, 940 0x0, memmap[VIRT_UART0].size); 941 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 942 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 943 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 944 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 945 } else { 946 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 947 } 948 949 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 950 g_free(name); 951 } 952 953 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 954 uint32_t irq_mmio_phandle) 955 { 956 char *name; 957 MachineState *ms = MACHINE(s); 958 959 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 960 qemu_fdt_add_subnode(ms->fdt, name); 961 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 962 "google,goldfish-rtc"); 963 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 964 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 965 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 966 irq_mmio_phandle); 967 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 968 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 969 } else { 970 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 971 } 972 g_free(name); 973 } 974 975 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 976 { 977 char *name; 978 MachineState *ms = MACHINE(s); 979 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 980 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 981 982 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 983 qemu_fdt_add_subnode(ms->fdt, name); 984 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 985 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 986 2, flashbase, 2, flashsize, 987 2, flashbase + flashsize, 2, flashsize); 988 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 989 g_free(name); 990 } 991 992 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 993 { 994 char *nodename; 995 MachineState *ms = MACHINE(s); 996 hwaddr base = memmap[VIRT_FW_CFG].base; 997 hwaddr size = memmap[VIRT_FW_CFG].size; 998 999 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1000 qemu_fdt_add_subnode(ms->fdt, nodename); 1001 qemu_fdt_setprop_string(ms->fdt, nodename, 1002 "compatible", "qemu,fw-cfg-mmio"); 1003 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1004 2, base, 2, size); 1005 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1006 g_free(nodename); 1007 } 1008 1009 static void finalize_fdt(RISCVVirtState *s) 1010 { 1011 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1012 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1013 1014 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 1015 &irq_pcie_phandle, &irq_virtio_phandle, 1016 &msi_pcie_phandle); 1017 1018 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 1019 1020 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); 1021 1022 create_fdt_reset(s, virt_memmap, &phandle); 1023 1024 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 1025 1026 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 1027 } 1028 1029 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1030 { 1031 MachineState *ms = MACHINE(s); 1032 uint8_t rng_seed[32]; 1033 1034 ms->fdt = create_device_tree(&s->fdt_size); 1035 if (!ms->fdt) { 1036 error_report("create_device_tree() failed"); 1037 exit(1); 1038 } 1039 1040 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1041 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1042 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1043 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1044 1045 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1046 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1047 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1048 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1049 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1050 1051 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1052 1053 /* Pass seed to RNG */ 1054 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1055 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1056 rng_seed, sizeof(rng_seed)); 1057 1058 create_fdt_flash(s, memmap); 1059 create_fdt_fw_cfg(s, memmap); 1060 create_fdt_pmu(s); 1061 } 1062 1063 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1064 DeviceState *irqchip, 1065 RISCVVirtState *s) 1066 { 1067 DeviceState *dev; 1068 MemoryRegion *ecam_alias, *ecam_reg; 1069 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1070 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1071 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1072 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1073 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1074 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1075 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1076 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1077 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1078 qemu_irq irq; 1079 int i; 1080 1081 dev = qdev_new(TYPE_GPEX_HOST); 1082 1083 /* Set GPEX object properties for the virt machine */ 1084 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, 1085 ecam_base, NULL); 1086 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, 1087 ecam_size, NULL); 1088 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1089 PCI_HOST_BELOW_4G_MMIO_BASE, 1090 mmio_base, NULL); 1091 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, 1092 mmio_size, NULL); 1093 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1094 PCI_HOST_ABOVE_4G_MMIO_BASE, 1095 high_mmio_base, NULL); 1096 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1097 high_mmio_size, NULL); 1098 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, 1099 pio_base, NULL); 1100 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, 1101 pio_size, NULL); 1102 1103 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1104 1105 ecam_alias = g_new0(MemoryRegion, 1); 1106 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1107 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1108 ecam_reg, 0, ecam_size); 1109 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1110 1111 mmio_alias = g_new0(MemoryRegion, 1); 1112 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1113 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1114 mmio_reg, mmio_base, mmio_size); 1115 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1116 1117 /* Map high MMIO space */ 1118 high_mmio_alias = g_new0(MemoryRegion, 1); 1119 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1120 mmio_reg, high_mmio_base, high_mmio_size); 1121 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1122 high_mmio_alias); 1123 1124 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1125 1126 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1127 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1128 1129 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1130 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1131 } 1132 1133 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; 1134 return dev; 1135 } 1136 1137 static FWCfgState *create_fw_cfg(const MachineState *ms) 1138 { 1139 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1140 FWCfgState *fw_cfg; 1141 1142 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1143 &address_space_memory); 1144 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1145 1146 return fw_cfg; 1147 } 1148 1149 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1150 int base_hartid, int hart_count) 1151 { 1152 DeviceState *ret; 1153 char *plic_hart_config; 1154 1155 /* Per-socket PLIC hart topology configuration string */ 1156 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1157 1158 /* Per-socket PLIC */ 1159 ret = sifive_plic_create( 1160 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1161 plic_hart_config, hart_count, base_hartid, 1162 VIRT_IRQCHIP_NUM_SOURCES, 1163 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1164 VIRT_PLIC_PRIORITY_BASE, 1165 VIRT_PLIC_PENDING_BASE, 1166 VIRT_PLIC_ENABLE_BASE, 1167 VIRT_PLIC_ENABLE_STRIDE, 1168 VIRT_PLIC_CONTEXT_BASE, 1169 VIRT_PLIC_CONTEXT_STRIDE, 1170 memmap[VIRT_PLIC].size); 1171 1172 g_free(plic_hart_config); 1173 1174 return ret; 1175 } 1176 1177 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1178 const MemMapEntry *memmap, int socket, 1179 int base_hartid, int hart_count) 1180 { 1181 int i; 1182 hwaddr addr; 1183 uint32_t guest_bits; 1184 DeviceState *aplic_s = NULL; 1185 DeviceState *aplic_m = NULL; 1186 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1187 1188 if (msimode) { 1189 if (!kvm_enabled()) { 1190 /* Per-socket M-level IMSICs */ 1191 addr = memmap[VIRT_IMSIC_M].base + 1192 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1193 for (i = 0; i < hart_count; i++) { 1194 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1195 base_hartid + i, true, 1, 1196 VIRT_IRQCHIP_NUM_MSIS); 1197 } 1198 } 1199 1200 /* Per-socket S-level IMSICs */ 1201 guest_bits = imsic_num_bits(aia_guests + 1); 1202 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1203 for (i = 0; i < hart_count; i++) { 1204 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1205 base_hartid + i, false, 1 + aia_guests, 1206 VIRT_IRQCHIP_NUM_MSIS); 1207 } 1208 } 1209 1210 if (!kvm_enabled()) { 1211 /* Per-socket M-level APLIC */ 1212 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1213 socket * memmap[VIRT_APLIC_M].size, 1214 memmap[VIRT_APLIC_M].size, 1215 (msimode) ? 0 : base_hartid, 1216 (msimode) ? 0 : hart_count, 1217 VIRT_IRQCHIP_NUM_SOURCES, 1218 VIRT_IRQCHIP_NUM_PRIO_BITS, 1219 msimode, true, NULL); 1220 } 1221 1222 /* Per-socket S-level APLIC */ 1223 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1224 socket * memmap[VIRT_APLIC_S].size, 1225 memmap[VIRT_APLIC_S].size, 1226 (msimode) ? 0 : base_hartid, 1227 (msimode) ? 0 : hart_count, 1228 VIRT_IRQCHIP_NUM_SOURCES, 1229 VIRT_IRQCHIP_NUM_PRIO_BITS, 1230 msimode, false, aplic_m); 1231 1232 return kvm_enabled() ? aplic_s : aplic_m; 1233 } 1234 1235 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1236 { 1237 DeviceState *dev; 1238 SysBusDevice *sysbus; 1239 const MemMapEntry *memmap = virt_memmap; 1240 int i; 1241 MemoryRegion *sysmem = get_system_memory(); 1242 1243 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1244 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1245 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1246 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1247 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1248 s->platform_bus_dev = dev; 1249 1250 sysbus = SYS_BUS_DEVICE(dev); 1251 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1252 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1253 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1254 } 1255 1256 memory_region_add_subregion(sysmem, 1257 memmap[VIRT_PLATFORM_BUS].base, 1258 sysbus_mmio_get_region(sysbus, 0)); 1259 } 1260 1261 static void virt_machine_done(Notifier *notifier, void *data) 1262 { 1263 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1264 machine_done); 1265 const MemMapEntry *memmap = virt_memmap; 1266 MachineState *machine = MACHINE(s); 1267 target_ulong start_addr = memmap[VIRT_DRAM].base; 1268 target_ulong firmware_end_addr, kernel_start_addr; 1269 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1270 uint64_t fdt_load_addr; 1271 uint64_t kernel_entry = 0; 1272 BlockBackend *pflash_blk0; 1273 1274 /* 1275 * An user provided dtb must include everything, including 1276 * dynamic sysbus devices. Our FDT needs to be finalized. 1277 */ 1278 if (machine->dtb == NULL) { 1279 finalize_fdt(s); 1280 } 1281 1282 /* 1283 * Only direct boot kernel is currently supported for KVM VM, 1284 * so the "-bios" parameter is not supported when KVM is enabled. 1285 */ 1286 if (kvm_enabled()) { 1287 if (machine->firmware) { 1288 if (strcmp(machine->firmware, "none")) { 1289 error_report("Machine mode firmware is not supported in " 1290 "combination with KVM."); 1291 exit(1); 1292 } 1293 } else { 1294 machine->firmware = g_strdup("none"); 1295 } 1296 } 1297 1298 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1299 start_addr, NULL); 1300 1301 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1302 if (pflash_blk0) { 1303 if (machine->firmware && !strcmp(machine->firmware, "none") && 1304 !kvm_enabled()) { 1305 /* 1306 * Pflash was supplied but bios is none and not KVM guest, 1307 * let's overwrite the address we jump to after reset to 1308 * the base of the flash. 1309 */ 1310 start_addr = virt_memmap[VIRT_FLASH].base; 1311 } else { 1312 /* 1313 * Pflash was supplied but either KVM guest or bios is not none. 1314 * In this case, base of the flash would contain S-mode payload. 1315 */ 1316 riscv_setup_firmware_boot(machine); 1317 kernel_entry = virt_memmap[VIRT_FLASH].base; 1318 } 1319 } 1320 1321 if (machine->kernel_filename && !kernel_entry) { 1322 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1323 firmware_end_addr); 1324 1325 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1326 kernel_start_addr, true, NULL); 1327 } 1328 1329 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1330 memmap[VIRT_DRAM].size, 1331 machine); 1332 riscv_load_fdt(fdt_load_addr, machine->fdt); 1333 1334 /* load the reset vector */ 1335 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1336 virt_memmap[VIRT_MROM].base, 1337 virt_memmap[VIRT_MROM].size, kernel_entry, 1338 fdt_load_addr); 1339 1340 /* 1341 * Only direct boot kernel is currently supported for KVM VM, 1342 * So here setup kernel start address and fdt address. 1343 * TODO:Support firmware loading and integrate to TCG start 1344 */ 1345 if (kvm_enabled()) { 1346 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1347 } 1348 1349 if (virt_is_acpi_enabled(s)) { 1350 virt_acpi_setup(s); 1351 } 1352 } 1353 1354 static void virt_machine_init(MachineState *machine) 1355 { 1356 const MemMapEntry *memmap = virt_memmap; 1357 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1358 MemoryRegion *system_memory = get_system_memory(); 1359 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1360 char *soc_name; 1361 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1362 int i, base_hartid, hart_count; 1363 int socket_count = riscv_socket_count(machine); 1364 1365 /* Check socket count limit */ 1366 if (VIRT_SOCKETS_MAX < socket_count) { 1367 error_report("number of sockets/nodes should be less than %d", 1368 VIRT_SOCKETS_MAX); 1369 exit(1); 1370 } 1371 1372 if (!tcg_enabled() && s->have_aclint) { 1373 error_report("'aclint' is only available with TCG acceleration"); 1374 exit(1); 1375 } 1376 1377 /* Initialize sockets */ 1378 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1379 for (i = 0; i < socket_count; i++) { 1380 if (!riscv_socket_check_hartids(machine, i)) { 1381 error_report("discontinuous hartids in socket%d", i); 1382 exit(1); 1383 } 1384 1385 base_hartid = riscv_socket_first_hartid(machine, i); 1386 if (base_hartid < 0) { 1387 error_report("can't find hartid base for socket%d", i); 1388 exit(1); 1389 } 1390 1391 hart_count = riscv_socket_hart_count(machine, i); 1392 if (hart_count < 0) { 1393 error_report("can't find hart count for socket%d", i); 1394 exit(1); 1395 } 1396 1397 soc_name = g_strdup_printf("soc%d", i); 1398 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1399 TYPE_RISCV_HART_ARRAY); 1400 g_free(soc_name); 1401 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1402 machine->cpu_type, &error_abort); 1403 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1404 base_hartid, &error_abort); 1405 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1406 hart_count, &error_abort); 1407 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1408 1409 if (tcg_enabled()) { 1410 if (s->have_aclint) { 1411 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1412 /* Per-socket ACLINT MTIMER */ 1413 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1414 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1415 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1416 base_hartid, hart_count, 1417 RISCV_ACLINT_DEFAULT_MTIMECMP, 1418 RISCV_ACLINT_DEFAULT_MTIME, 1419 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1420 } else { 1421 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1422 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1423 i * memmap[VIRT_CLINT].size, 1424 base_hartid, hart_count, false); 1425 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1426 i * memmap[VIRT_CLINT].size + 1427 RISCV_ACLINT_SWI_SIZE, 1428 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1429 base_hartid, hart_count, 1430 RISCV_ACLINT_DEFAULT_MTIMECMP, 1431 RISCV_ACLINT_DEFAULT_MTIME, 1432 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1433 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1434 i * memmap[VIRT_ACLINT_SSWI].size, 1435 base_hartid, hart_count, true); 1436 } 1437 } else { 1438 /* Per-socket SiFive CLINT */ 1439 riscv_aclint_swi_create( 1440 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1441 base_hartid, hart_count, false); 1442 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1443 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1444 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1445 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1446 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1447 } 1448 } 1449 1450 /* Per-socket interrupt controller */ 1451 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1452 s->irqchip[i] = virt_create_plic(memmap, i, 1453 base_hartid, hart_count); 1454 } else { 1455 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1456 memmap, i, base_hartid, 1457 hart_count); 1458 } 1459 1460 /* Try to use different IRQCHIP instance based device type */ 1461 if (i == 0) { 1462 mmio_irqchip = s->irqchip[i]; 1463 virtio_irqchip = s->irqchip[i]; 1464 pcie_irqchip = s->irqchip[i]; 1465 } 1466 if (i == 1) { 1467 virtio_irqchip = s->irqchip[i]; 1468 pcie_irqchip = s->irqchip[i]; 1469 } 1470 if (i == 2) { 1471 pcie_irqchip = s->irqchip[i]; 1472 } 1473 } 1474 1475 if (kvm_enabled() && virt_use_kvm_aia(s)) { 1476 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1477 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1478 memmap[VIRT_APLIC_S].base, 1479 memmap[VIRT_IMSIC_S].base, 1480 s->aia_guests); 1481 } 1482 1483 if (riscv_is_32bit(&s->soc[0])) { 1484 #if HOST_LONG_BITS == 64 1485 /* limit RAM size in a 32-bit system */ 1486 if (machine->ram_size > 10 * GiB) { 1487 machine->ram_size = 10 * GiB; 1488 error_report("Limiting RAM size to 10 GiB"); 1489 } 1490 #endif 1491 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1492 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1493 } else { 1494 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1495 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1496 virt_high_pcie_memmap.base = 1497 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1498 } 1499 1500 s->memmap = virt_memmap; 1501 1502 /* register system main memory (actual RAM) */ 1503 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1504 machine->ram); 1505 1506 /* boot rom */ 1507 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1508 memmap[VIRT_MROM].size, &error_fatal); 1509 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1510 mask_rom); 1511 1512 /* 1513 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1514 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1515 */ 1516 s->fw_cfg = create_fw_cfg(machine); 1517 rom_set_fw(s->fw_cfg); 1518 1519 /* SiFive Test MMIO device */ 1520 sifive_test_create(memmap[VIRT_TEST].base); 1521 1522 /* VirtIO MMIO devices */ 1523 for (i = 0; i < VIRTIO_COUNT; i++) { 1524 sysbus_create_simple("virtio-mmio", 1525 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1526 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1527 } 1528 1529 gpex_pcie_init(system_memory, pcie_irqchip, s); 1530 1531 create_platform_bus(s, mmio_irqchip); 1532 1533 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1534 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1535 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1536 1537 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1538 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1539 1540 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1541 /* Map legacy -drive if=pflash to machine properties */ 1542 pflash_cfi01_legacy_drive(s->flash[i], 1543 drive_get(IF_PFLASH, 0, i)); 1544 } 1545 virt_flash_map(s, system_memory); 1546 1547 /* load/create device tree */ 1548 if (machine->dtb) { 1549 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1550 if (!machine->fdt) { 1551 error_report("load_device_tree() failed"); 1552 exit(1); 1553 } 1554 } else { 1555 create_fdt(s, memmap); 1556 } 1557 1558 s->machine_done.notify = virt_machine_done; 1559 qemu_add_machine_init_done_notifier(&s->machine_done); 1560 } 1561 1562 static void virt_machine_instance_init(Object *obj) 1563 { 1564 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1565 1566 virt_flash_create(s); 1567 1568 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1569 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1570 s->acpi = ON_OFF_AUTO_AUTO; 1571 } 1572 1573 static char *virt_get_aia_guests(Object *obj, Error **errp) 1574 { 1575 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1576 char val[32]; 1577 1578 sprintf(val, "%d", s->aia_guests); 1579 return g_strdup(val); 1580 } 1581 1582 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1583 { 1584 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1585 1586 s->aia_guests = atoi(val); 1587 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1588 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1589 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1590 VIRT_IRQCHIP_MAX_GUESTS); 1591 } 1592 } 1593 1594 static char *virt_get_aia(Object *obj, Error **errp) 1595 { 1596 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1597 const char *val; 1598 1599 switch (s->aia_type) { 1600 case VIRT_AIA_TYPE_APLIC: 1601 val = "aplic"; 1602 break; 1603 case VIRT_AIA_TYPE_APLIC_IMSIC: 1604 val = "aplic-imsic"; 1605 break; 1606 default: 1607 val = "none"; 1608 break; 1609 }; 1610 1611 return g_strdup(val); 1612 } 1613 1614 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1615 { 1616 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1617 1618 if (!strcmp(val, "none")) { 1619 s->aia_type = VIRT_AIA_TYPE_NONE; 1620 } else if (!strcmp(val, "aplic")) { 1621 s->aia_type = VIRT_AIA_TYPE_APLIC; 1622 } else if (!strcmp(val, "aplic-imsic")) { 1623 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1624 } else { 1625 error_setg(errp, "Invalid AIA interrupt controller type"); 1626 error_append_hint(errp, "Valid values are none, aplic, and " 1627 "aplic-imsic.\n"); 1628 } 1629 } 1630 1631 static bool virt_get_aclint(Object *obj, Error **errp) 1632 { 1633 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1634 1635 return s->have_aclint; 1636 } 1637 1638 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1639 { 1640 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1641 1642 s->have_aclint = value; 1643 } 1644 1645 bool virt_is_acpi_enabled(RISCVVirtState *s) 1646 { 1647 return s->acpi != ON_OFF_AUTO_OFF; 1648 } 1649 1650 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1651 void *opaque, Error **errp) 1652 { 1653 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1654 OnOffAuto acpi = s->acpi; 1655 1656 visit_type_OnOffAuto(v, name, &acpi, errp); 1657 } 1658 1659 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1660 void *opaque, Error **errp) 1661 { 1662 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1663 1664 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1665 } 1666 1667 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1668 DeviceState *dev) 1669 { 1670 MachineClass *mc = MACHINE_GET_CLASS(machine); 1671 1672 if (device_is_dynamic_sysbus(mc, dev)) { 1673 return HOTPLUG_HANDLER(machine); 1674 } 1675 return NULL; 1676 } 1677 1678 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1679 DeviceState *dev, Error **errp) 1680 { 1681 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1682 1683 if (s->platform_bus_dev) { 1684 MachineClass *mc = MACHINE_GET_CLASS(s); 1685 1686 if (device_is_dynamic_sysbus(mc, dev)) { 1687 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1688 SYS_BUS_DEVICE(dev)); 1689 } 1690 } 1691 } 1692 1693 static void virt_machine_class_init(ObjectClass *oc, void *data) 1694 { 1695 char str[128]; 1696 MachineClass *mc = MACHINE_CLASS(oc); 1697 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1698 1699 mc->desc = "RISC-V VirtIO board"; 1700 mc->init = virt_machine_init; 1701 mc->max_cpus = VIRT_CPUS_MAX; 1702 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1703 mc->pci_allow_0_address = true; 1704 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1705 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1706 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1707 mc->numa_mem_supported = true; 1708 /* platform instead of architectural choice */ 1709 mc->cpu_cluster_has_numa_boundary = true; 1710 mc->default_ram_id = "riscv_virt_board.ram"; 1711 assert(!mc->get_hotplug_handler); 1712 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1713 1714 hc->plug = virt_machine_device_plug_cb; 1715 1716 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1717 #ifdef CONFIG_TPM 1718 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1719 #endif 1720 1721 1722 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1723 virt_set_aclint); 1724 object_class_property_set_description(oc, "aclint", 1725 "(TCG only) Set on/off to " 1726 "enable/disable emulating " 1727 "ACLINT devices"); 1728 1729 object_class_property_add_str(oc, "aia", virt_get_aia, 1730 virt_set_aia); 1731 object_class_property_set_description(oc, "aia", 1732 "Set type of AIA interrupt " 1733 "controller. Valid values are " 1734 "none, aplic, and aplic-imsic."); 1735 1736 object_class_property_add_str(oc, "aia-guests", 1737 virt_get_aia_guests, 1738 virt_set_aia_guests); 1739 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1740 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1741 object_class_property_set_description(oc, "aia-guests", str); 1742 object_class_property_add(oc, "acpi", "OnOffAuto", 1743 virt_get_acpi, virt_set_acpi, 1744 NULL, NULL); 1745 object_class_property_set_description(oc, "acpi", 1746 "Enable ACPI"); 1747 } 1748 1749 static const TypeInfo virt_machine_typeinfo = { 1750 .name = MACHINE_TYPE_NAME("virt"), 1751 .parent = TYPE_MACHINE, 1752 .class_init = virt_machine_class_init, 1753 .instance_init = virt_machine_instance_init, 1754 .instance_size = sizeof(RISCVVirtState), 1755 .interfaces = (InterfaceInfo[]) { 1756 { TYPE_HOTPLUG_HANDLER }, 1757 { } 1758 }, 1759 }; 1760 1761 static void virt_machine_init_register_types(void) 1762 { 1763 type_register_static(&virt_machine_typeinfo); 1764 } 1765 1766 type_init(virt_machine_init_register_types) 1767