1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial-mm.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/iommu.h" 36 #include "hw/riscv/riscv-iommu-bits.h" 37 #include "hw/riscv/virt.h" 38 #include "hw/riscv/boot.h" 39 #include "hw/riscv/numa.h" 40 #include "kvm/kvm_riscv.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/intc/riscv_aclint.h" 43 #include "hw/intc/riscv_aplic.h" 44 #include "hw/intc/sifive_plic.h" 45 #include "hw/misc/sifive_test.h" 46 #include "hw/platform-bus.h" 47 #include "chardev/char.h" 48 #include "system/device_tree.h" 49 #include "system/system.h" 50 #include "system/tcg.h" 51 #include "system/kvm.h" 52 #include "system/tpm.h" 53 #include "system/qtest.h" 54 #include "hw/pci/pci.h" 55 #include "hw/pci-host/gpex.h" 56 #include "hw/display/ramfb.h" 57 #include "hw/acpi/aml-build.h" 58 #include "qapi/qapi-visit-common.h" 59 #include "hw/virtio/virtio-iommu.h" 60 #include "hw/uefi/var-service-api.h" 61 62 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 63 static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type) 64 { 65 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 66 67 return riscv_is_kvm_aia_aplic_imsic(msimode); 68 } 69 70 static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type) 71 { 72 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 73 74 return riscv_use_emulated_aplic(msimode); 75 } 76 77 static bool virt_aclint_allowed(void) 78 { 79 return tcg_enabled() || qtest_enabled(); 80 } 81 82 static const MemMapEntry virt_memmap[] = { 83 [VIRT_DEBUG] = { 0x0, 0x100 }, 84 [VIRT_MROM] = { 0x1000, 0xf000 }, 85 [VIRT_TEST] = { 0x100000, 0x1000 }, 86 [VIRT_RTC] = { 0x101000, 0x1000 }, 87 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 88 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 89 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 90 [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 }, 91 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 92 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 93 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 94 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 95 [VIRT_UART0] = { 0x10000000, 0x100 }, 96 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 97 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 98 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 99 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 100 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 101 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 102 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 103 [VIRT_DRAM] = { 0x80000000, 0x0 }, 104 }; 105 106 /* PCIe high mmio is fixed for RV32 */ 107 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 108 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 109 110 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 111 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 112 113 static MemMapEntry virt_high_pcie_memmap; 114 115 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 116 117 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 118 const char *name, 119 const char *alias_prop_name) 120 { 121 /* 122 * Create a single flash device. We use the same parameters as 123 * the flash devices on the ARM virt board. 124 */ 125 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 126 127 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 128 qdev_prop_set_uint8(dev, "width", 4); 129 qdev_prop_set_uint8(dev, "device-width", 2); 130 qdev_prop_set_bit(dev, "big-endian", false); 131 qdev_prop_set_uint16(dev, "id0", 0x89); 132 qdev_prop_set_uint16(dev, "id1", 0x18); 133 qdev_prop_set_uint16(dev, "id2", 0x00); 134 qdev_prop_set_uint16(dev, "id3", 0x00); 135 qdev_prop_set_string(dev, "name", name); 136 137 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 138 object_property_add_alias(OBJECT(s), alias_prop_name, 139 OBJECT(dev), "drive"); 140 141 return PFLASH_CFI01(dev); 142 } 143 144 static void virt_flash_create(RISCVVirtState *s) 145 { 146 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 147 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 148 } 149 150 static void virt_flash_map1(PFlashCFI01 *flash, 151 hwaddr base, hwaddr size, 152 MemoryRegion *sysmem) 153 { 154 DeviceState *dev = DEVICE(flash); 155 156 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 157 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 158 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 159 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 160 161 memory_region_add_subregion(sysmem, base, 162 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 163 0)); 164 } 165 166 static void virt_flash_map(RISCVVirtState *s, 167 MemoryRegion *sysmem) 168 { 169 hwaddr flashsize = s->memmap[VIRT_FLASH].size / 2; 170 hwaddr flashbase = s->memmap[VIRT_FLASH].base; 171 172 virt_flash_map1(s->flash[0], flashbase, flashsize, 173 sysmem); 174 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 175 sysmem); 176 } 177 178 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 179 uint32_t irqchip_phandle) 180 { 181 int pin, dev; 182 uint32_t irq_map_stride = 0; 183 uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * 184 FDT_MAX_INT_MAP_WIDTH] = {}; 185 uint32_t *irq_map = full_irq_map; 186 187 /* This code creates a standard swizzle of interrupts such that 188 * each device's first interrupt is based on it's PCI_SLOT number. 189 * (See pci_swizzle_map_irq_fn()) 190 * 191 * We only need one entry per interrupt in the table (not one per 192 * possible slot) seeing the interrupt-map-mask will allow the table 193 * to wrap to any number of devices. 194 */ 195 for (dev = 0; dev < PCI_NUM_PINS; dev++) { 196 int devfn = dev * 0x8; 197 198 for (pin = 0; pin < PCI_NUM_PINS; pin++) { 199 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 200 int i = 0; 201 202 /* Fill PCI address cells */ 203 irq_map[i] = cpu_to_be32(devfn << 8); 204 i += FDT_PCI_ADDR_CELLS; 205 206 /* Fill PCI Interrupt cells */ 207 irq_map[i] = cpu_to_be32(pin + 1); 208 i += FDT_PCI_INT_CELLS; 209 210 /* Fill interrupt controller phandle and cells */ 211 irq_map[i++] = cpu_to_be32(irqchip_phandle); 212 irq_map[i++] = cpu_to_be32(irq_nr); 213 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 214 irq_map[i++] = cpu_to_be32(0x4); 215 } 216 217 if (!irq_map_stride) { 218 irq_map_stride = i; 219 } 220 irq_map += irq_map_stride; 221 } 222 } 223 224 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 225 PCI_NUM_PINS * PCI_NUM_PINS * 226 irq_map_stride * sizeof(uint32_t)); 227 228 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 229 0x1800, 0, 0, 0x7); 230 } 231 232 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 233 char *clust_name, uint32_t *phandle, 234 uint32_t *intc_phandles) 235 { 236 int cpu; 237 uint32_t cpu_phandle; 238 MachineState *ms = MACHINE(s); 239 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 240 uint8_t satp_mode_max; 241 242 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 243 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 244 g_autofree char *cpu_name = NULL; 245 g_autofree char *core_name = NULL; 246 g_autofree char *intc_name = NULL; 247 g_autofree char *sv_name = NULL; 248 249 cpu_phandle = (*phandle)++; 250 251 cpu_name = g_strdup_printf("/cpus/cpu@%d", 252 s->soc[socket].hartid_base + cpu); 253 qemu_fdt_add_subnode(ms->fdt, cpu_name); 254 255 if (cpu_ptr->cfg.satp_mode.supported != 0) { 256 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 257 sv_name = g_strdup_printf("riscv,%s", 258 satp_mode_str(satp_mode_max, is_32_bit)); 259 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 260 } 261 262 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); 263 264 if (cpu_ptr->cfg.ext_zicbom) { 265 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 266 cpu_ptr->cfg.cbom_blocksize); 267 } 268 269 if (cpu_ptr->cfg.ext_zicboz) { 270 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 271 cpu_ptr->cfg.cboz_blocksize); 272 } 273 274 if (cpu_ptr->cfg.ext_zicbop) { 275 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 276 cpu_ptr->cfg.cbop_blocksize); 277 } 278 279 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 280 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 281 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 282 s->soc[socket].hartid_base + cpu); 283 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 284 riscv_socket_fdt_write_id(ms, cpu_name, socket); 285 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 286 287 intc_phandles[cpu] = (*phandle)++; 288 289 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 290 qemu_fdt_add_subnode(ms->fdt, intc_name); 291 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 292 intc_phandles[cpu]); 293 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 294 "riscv,cpu-intc"); 295 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 296 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 297 298 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 299 qemu_fdt_add_subnode(ms->fdt, core_name); 300 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 301 } 302 } 303 304 static void create_fdt_socket_memory(RISCVVirtState *s, int socket) 305 { 306 g_autofree char *mem_name = NULL; 307 hwaddr addr; 308 uint64_t size; 309 MachineState *ms = MACHINE(s); 310 311 addr = s->memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 312 size = riscv_socket_mem_size(ms, socket); 313 mem_name = g_strdup_printf("/memory@%"HWADDR_PRIx, addr); 314 qemu_fdt_add_subnode(ms->fdt, mem_name); 315 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 316 addr >> 32, addr, size >> 32, size); 317 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 318 riscv_socket_fdt_write_id(ms, mem_name, socket); 319 } 320 321 static void create_fdt_socket_clint(RISCVVirtState *s, 322 int socket, 323 uint32_t *intc_phandles) 324 { 325 int cpu; 326 g_autofree char *clint_name = NULL; 327 g_autofree uint32_t *clint_cells = NULL; 328 unsigned long clint_addr; 329 MachineState *ms = MACHINE(s); 330 static const char * const clint_compat[2] = { 331 "sifive,clint0", "riscv,clint0" 332 }; 333 334 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 335 336 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 337 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 338 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 339 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 340 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 341 } 342 343 clint_addr = s->memmap[VIRT_CLINT].base + 344 (s->memmap[VIRT_CLINT].size * socket); 345 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 346 qemu_fdt_add_subnode(ms->fdt, clint_name); 347 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 348 (char **)&clint_compat, 349 ARRAY_SIZE(clint_compat)); 350 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 351 0x0, clint_addr, 0x0, s->memmap[VIRT_CLINT].size); 352 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 353 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 354 riscv_socket_fdt_write_id(ms, clint_name, socket); 355 } 356 357 static void create_fdt_socket_aclint(RISCVVirtState *s, 358 int socket, 359 uint32_t *intc_phandles) 360 { 361 int cpu; 362 char *name; 363 unsigned long addr, size; 364 uint32_t aclint_cells_size; 365 g_autofree uint32_t *aclint_mswi_cells = NULL; 366 g_autofree uint32_t *aclint_sswi_cells = NULL; 367 g_autofree uint32_t *aclint_mtimer_cells = NULL; 368 MachineState *ms = MACHINE(s); 369 370 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 371 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 372 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 373 374 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 375 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 376 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 377 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 378 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 379 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 380 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 381 } 382 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 383 384 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 385 addr = s->memmap[VIRT_CLINT].base + 386 (s->memmap[VIRT_CLINT].size * socket); 387 name = g_strdup_printf("/soc/mswi@%lx", addr); 388 389 qemu_fdt_add_subnode(ms->fdt, name); 390 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 391 "riscv,aclint-mswi"); 392 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 393 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 394 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 395 aclint_mswi_cells, aclint_cells_size); 396 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 397 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 398 riscv_socket_fdt_write_id(ms, name, socket); 399 g_free(name); 400 } 401 402 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 403 addr = s->memmap[VIRT_CLINT].base + 404 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 405 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 406 } else { 407 addr = s->memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 408 (s->memmap[VIRT_CLINT].size * socket); 409 size = s->memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 410 } 411 name = g_strdup_printf("/soc/mtimer@%lx", addr); 412 qemu_fdt_add_subnode(ms->fdt, name); 413 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 414 "riscv,aclint-mtimer"); 415 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 416 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 417 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 418 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 419 0x0, RISCV_ACLINT_DEFAULT_MTIME); 420 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 421 aclint_mtimer_cells, aclint_cells_size); 422 riscv_socket_fdt_write_id(ms, name, socket); 423 g_free(name); 424 425 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 426 addr = s->memmap[VIRT_ACLINT_SSWI].base + 427 (s->memmap[VIRT_ACLINT_SSWI].size * socket); 428 429 name = g_strdup_printf("/soc/sswi@%lx", addr); 430 qemu_fdt_add_subnode(ms->fdt, name); 431 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 432 "riscv,aclint-sswi"); 433 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 434 0x0, addr, 0x0, s->memmap[VIRT_ACLINT_SSWI].size); 435 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 436 aclint_sswi_cells, aclint_cells_size); 437 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 438 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 439 riscv_socket_fdt_write_id(ms, name, socket); 440 g_free(name); 441 } 442 } 443 444 static void create_fdt_socket_plic(RISCVVirtState *s, 445 int socket, 446 uint32_t *phandle, uint32_t *intc_phandles, 447 uint32_t *plic_phandles) 448 { 449 int cpu; 450 g_autofree char *plic_name = NULL; 451 g_autofree uint32_t *plic_cells; 452 unsigned long plic_addr; 453 MachineState *ms = MACHINE(s); 454 static const char * const plic_compat[2] = { 455 "sifive,plic-1.0.0", "riscv,plic0" 456 }; 457 458 plic_phandles[socket] = (*phandle)++; 459 plic_addr = s->memmap[VIRT_PLIC].base + 460 (s->memmap[VIRT_PLIC].size * socket); 461 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 462 qemu_fdt_add_subnode(ms->fdt, plic_name); 463 qemu_fdt_setprop_cell(ms->fdt, plic_name, 464 "#interrupt-cells", FDT_PLIC_INT_CELLS); 465 qemu_fdt_setprop_cell(ms->fdt, plic_name, 466 "#address-cells", FDT_PLIC_ADDR_CELLS); 467 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 468 (char **)&plic_compat, 469 ARRAY_SIZE(plic_compat)); 470 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 471 472 if (kvm_enabled()) { 473 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 474 475 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 476 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 477 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 478 } 479 480 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 481 plic_cells, 482 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 483 } else { 484 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 485 486 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 487 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 488 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 489 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 490 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 491 } 492 493 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 494 plic_cells, 495 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 496 } 497 498 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 499 0x0, plic_addr, 0x0, s->memmap[VIRT_PLIC].size); 500 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 501 VIRT_IRQCHIP_NUM_SOURCES - 1); 502 riscv_socket_fdt_write_id(ms, plic_name, socket); 503 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 504 plic_phandles[socket]); 505 506 if (!socket) { 507 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 508 s->memmap[VIRT_PLATFORM_BUS].base, 509 s->memmap[VIRT_PLATFORM_BUS].size, 510 VIRT_PLATFORM_BUS_IRQ); 511 } 512 } 513 514 uint32_t imsic_num_bits(uint32_t count) 515 { 516 uint32_t ret = 0; 517 518 while (BIT(ret) < count) { 519 ret++; 520 } 521 522 return ret; 523 } 524 525 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 526 uint32_t *intc_phandles, uint32_t msi_phandle, 527 bool m_mode, uint32_t imsic_guest_bits) 528 { 529 int cpu, socket; 530 g_autofree char *imsic_name = NULL; 531 MachineState *ms = MACHINE(s); 532 int socket_count = riscv_socket_count(ms); 533 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 534 g_autofree uint32_t *imsic_cells = NULL; 535 g_autofree uint32_t *imsic_regs = NULL; 536 static const char * const imsic_compat[2] = { 537 "qemu,imsics", "riscv,imsics" 538 }; 539 540 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 541 imsic_regs = g_new0(uint32_t, socket_count * 4); 542 543 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 544 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 545 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 546 } 547 548 imsic_max_hart_per_socket = 0; 549 for (socket = 0; socket < socket_count; socket++) { 550 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 551 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 552 s->soc[socket].num_harts; 553 imsic_regs[socket * 4 + 0] = 0; 554 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 555 imsic_regs[socket * 4 + 2] = 0; 556 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 557 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 558 imsic_max_hart_per_socket = s->soc[socket].num_harts; 559 } 560 } 561 562 imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx", 563 (unsigned long)base_addr); 564 qemu_fdt_add_subnode(ms->fdt, imsic_name); 565 qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", 566 (char **)&imsic_compat, 567 ARRAY_SIZE(imsic_compat)); 568 569 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 570 FDT_IMSIC_INT_CELLS); 571 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 572 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 573 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 574 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 575 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 576 socket_count * sizeof(uint32_t) * 4); 577 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 578 VIRT_IRQCHIP_NUM_MSIS); 579 580 if (imsic_guest_bits) { 581 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 582 imsic_guest_bits); 583 } 584 585 if (socket_count > 1) { 586 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 587 imsic_num_bits(imsic_max_hart_per_socket)); 588 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 589 imsic_num_bits(socket_count)); 590 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 591 IMSIC_MMIO_GROUP_MIN_SHIFT); 592 } 593 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 594 } 595 596 static void create_fdt_imsic(RISCVVirtState *s, 597 uint32_t *phandle, uint32_t *intc_phandles, 598 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 599 { 600 *msi_m_phandle = (*phandle)++; 601 *msi_s_phandle = (*phandle)++; 602 603 if (!kvm_enabled()) { 604 /* M-level IMSIC node */ 605 create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_M].base, intc_phandles, 606 *msi_m_phandle, true, 0); 607 } 608 609 /* S-level IMSIC node */ 610 create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_S].base, intc_phandles, 611 *msi_s_phandle, false, 612 imsic_num_bits(s->aia_guests + 1)); 613 614 } 615 616 /* Caller must free string after use */ 617 static char *fdt_get_aplic_nodename(unsigned long aplic_addr) 618 { 619 return g_strdup_printf("/soc/interrupt-controller@%lx", aplic_addr); 620 } 621 622 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 623 unsigned long aplic_addr, uint32_t aplic_size, 624 uint32_t msi_phandle, 625 uint32_t *intc_phandles, 626 uint32_t aplic_phandle, 627 uint32_t aplic_child_phandle, 628 bool m_mode, int num_harts) 629 { 630 int cpu; 631 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 632 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 633 MachineState *ms = MACHINE(s); 634 static const char * const aplic_compat[2] = { 635 "qemu,aplic", "riscv,aplic" 636 }; 637 638 for (cpu = 0; cpu < num_harts; cpu++) { 639 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 640 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 641 } 642 643 qemu_fdt_add_subnode(ms->fdt, aplic_name); 644 qemu_fdt_setprop_string_array(ms->fdt, aplic_name, "compatible", 645 (char **)&aplic_compat, 646 ARRAY_SIZE(aplic_compat)); 647 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells", 648 FDT_APLIC_ADDR_CELLS); 649 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 650 "#interrupt-cells", FDT_APLIC_INT_CELLS); 651 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 652 653 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 654 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 655 aplic_cells, num_harts * sizeof(uint32_t) * 2); 656 } else { 657 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 658 } 659 660 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 661 0x0, aplic_addr, 0x0, aplic_size); 662 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 663 VIRT_IRQCHIP_NUM_SOURCES); 664 665 if (aplic_child_phandle) { 666 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 667 aplic_child_phandle); 668 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation", 669 aplic_child_phandle, 0x1, 670 VIRT_IRQCHIP_NUM_SOURCES); 671 /* 672 * DEPRECATED_9.1: Compat property kept temporarily 673 * to allow old firmwares to work with AIA. Do *not* 674 * use 'riscv,delegate' in new code: use 675 * 'riscv,delegation' instead. 676 */ 677 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 678 aplic_child_phandle, 0x1, 679 VIRT_IRQCHIP_NUM_SOURCES); 680 } 681 682 riscv_socket_fdt_write_id(ms, aplic_name, socket); 683 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 684 } 685 686 static void create_fdt_socket_aplic(RISCVVirtState *s, 687 int socket, 688 uint32_t msi_m_phandle, 689 uint32_t msi_s_phandle, 690 uint32_t *phandle, 691 uint32_t *intc_phandles, 692 uint32_t *aplic_phandles, 693 int num_harts) 694 { 695 unsigned long aplic_addr; 696 MachineState *ms = MACHINE(s); 697 uint32_t aplic_m_phandle, aplic_s_phandle; 698 699 aplic_m_phandle = (*phandle)++; 700 aplic_s_phandle = (*phandle)++; 701 702 if (!kvm_enabled()) { 703 /* M-level APLIC node */ 704 aplic_addr = s->memmap[VIRT_APLIC_M].base + 705 (s->memmap[VIRT_APLIC_M].size * socket); 706 create_fdt_one_aplic(s, socket, aplic_addr, 707 s->memmap[VIRT_APLIC_M].size, 708 msi_m_phandle, intc_phandles, 709 aplic_m_phandle, aplic_s_phandle, 710 true, num_harts); 711 } 712 713 /* S-level APLIC node */ 714 aplic_addr = s->memmap[VIRT_APLIC_S].base + 715 (s->memmap[VIRT_APLIC_S].size * socket); 716 create_fdt_one_aplic(s, socket, aplic_addr, s->memmap[VIRT_APLIC_S].size, 717 msi_s_phandle, intc_phandles, 718 aplic_s_phandle, 0, 719 false, num_harts); 720 721 if (!socket) { 722 g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); 723 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 724 s->memmap[VIRT_PLATFORM_BUS].base, 725 s->memmap[VIRT_PLATFORM_BUS].size, 726 VIRT_PLATFORM_BUS_IRQ); 727 } 728 729 aplic_phandles[socket] = aplic_s_phandle; 730 } 731 732 static void create_fdt_pmu(RISCVVirtState *s) 733 { 734 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 735 MachineState *ms = MACHINE(s); 736 RISCVCPU hart = s->soc[0].harts[0]; 737 738 qemu_fdt_add_subnode(ms->fdt, pmu_name); 739 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 740 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 741 } 742 743 static void create_fdt_sockets(RISCVVirtState *s, 744 uint32_t *phandle, 745 uint32_t *irq_mmio_phandle, 746 uint32_t *irq_pcie_phandle, 747 uint32_t *irq_virtio_phandle, 748 uint32_t *msi_pcie_phandle) 749 { 750 int socket, phandle_pos; 751 MachineState *ms = MACHINE(s); 752 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 753 uint32_t xplic_phandles[MAX_NODES]; 754 g_autofree uint32_t *intc_phandles = NULL; 755 int socket_count = riscv_socket_count(ms); 756 757 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 758 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 759 kvm_enabled() ? 760 kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) : 761 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 762 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 763 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 764 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 765 766 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 767 768 phandle_pos = ms->smp.cpus; 769 for (socket = (socket_count - 1); socket >= 0; socket--) { 770 g_autofree char *clust_name = NULL; 771 phandle_pos -= s->soc[socket].num_harts; 772 773 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 774 qemu_fdt_add_subnode(ms->fdt, clust_name); 775 776 create_fdt_socket_cpus(s, socket, clust_name, phandle, 777 &intc_phandles[phandle_pos]); 778 779 create_fdt_socket_memory(s, socket); 780 781 if (virt_aclint_allowed() && s->have_aclint) { 782 create_fdt_socket_aclint(s, socket, 783 &intc_phandles[phandle_pos]); 784 } else if (tcg_enabled()) { 785 create_fdt_socket_clint(s, socket, 786 &intc_phandles[phandle_pos]); 787 } 788 } 789 790 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 791 create_fdt_imsic(s, phandle, intc_phandles, 792 &msi_m_phandle, &msi_s_phandle); 793 *msi_pcie_phandle = msi_s_phandle; 794 } 795 796 /* 797 * With KVM AIA aplic-imsic, using an irqchip without split 798 * mode, we'll use only one APLIC instance. 799 */ 800 if (!virt_use_emulated_aplic(s->aia_type)) { 801 create_fdt_socket_aplic(s, 0, 802 msi_m_phandle, msi_s_phandle, phandle, 803 &intc_phandles[0], xplic_phandles, 804 ms->smp.cpus); 805 806 *irq_mmio_phandle = xplic_phandles[0]; 807 *irq_virtio_phandle = xplic_phandles[0]; 808 *irq_pcie_phandle = xplic_phandles[0]; 809 } else { 810 phandle_pos = ms->smp.cpus; 811 for (socket = (socket_count - 1); socket >= 0; socket--) { 812 phandle_pos -= s->soc[socket].num_harts; 813 814 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 815 create_fdt_socket_plic(s, socket, phandle, 816 &intc_phandles[phandle_pos], 817 xplic_phandles); 818 } else { 819 create_fdt_socket_aplic(s, socket, 820 msi_m_phandle, msi_s_phandle, phandle, 821 &intc_phandles[phandle_pos], 822 xplic_phandles, 823 s->soc[socket].num_harts); 824 } 825 } 826 827 for (socket = 0; socket < socket_count; socket++) { 828 if (socket == 0) { 829 *irq_mmio_phandle = xplic_phandles[socket]; 830 *irq_virtio_phandle = xplic_phandles[socket]; 831 *irq_pcie_phandle = xplic_phandles[socket]; 832 } 833 if (socket == 1) { 834 *irq_virtio_phandle = xplic_phandles[socket]; 835 *irq_pcie_phandle = xplic_phandles[socket]; 836 } 837 if (socket == 2) { 838 *irq_pcie_phandle = xplic_phandles[socket]; 839 } 840 } 841 } 842 843 riscv_socket_fdt_write_distance_matrix(ms); 844 } 845 846 static void create_fdt_virtio(RISCVVirtState *s, uint32_t irq_virtio_phandle) 847 { 848 int i; 849 MachineState *ms = MACHINE(s); 850 hwaddr virtio_base = s->memmap[VIRT_VIRTIO].base; 851 852 for (i = 0; i < VIRTIO_COUNT; i++) { 853 g_autofree char *name = NULL; 854 uint64_t size = s->memmap[VIRT_VIRTIO].size; 855 hwaddr addr = virtio_base + i * size; 856 857 name = g_strdup_printf("/soc/virtio_mmio@%"HWADDR_PRIx, addr); 858 859 qemu_fdt_add_subnode(ms->fdt, name); 860 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 861 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 862 0x0, addr, 863 0x0, size); 864 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 865 irq_virtio_phandle); 866 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 867 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 868 VIRTIO_IRQ + i); 869 } else { 870 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 871 VIRTIO_IRQ + i, 0x4); 872 } 873 } 874 } 875 876 static void create_fdt_pcie(RISCVVirtState *s, 877 uint32_t irq_pcie_phandle, 878 uint32_t msi_pcie_phandle, 879 uint32_t iommu_sys_phandle) 880 { 881 g_autofree char *name = NULL; 882 MachineState *ms = MACHINE(s); 883 884 name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, 885 s->memmap[VIRT_PCIE_ECAM].base); 886 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 887 FDT_PCI_ADDR_CELLS); 888 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 889 FDT_PCI_INT_CELLS); 890 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 891 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 892 "pci-host-ecam-generic"); 893 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 894 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 895 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 896 s->memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 897 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 898 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 899 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 900 } 901 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 902 s->memmap[VIRT_PCIE_ECAM].base, 0, s->memmap[VIRT_PCIE_ECAM].size); 903 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 904 1, FDT_PCI_RANGE_IOPORT, 2, 0, 905 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size, 906 1, FDT_PCI_RANGE_MMIO, 907 2, s->memmap[VIRT_PCIE_MMIO].base, 908 2, s->memmap[VIRT_PCIE_MMIO].base, 2, s->memmap[VIRT_PCIE_MMIO].size, 909 1, FDT_PCI_RANGE_MMIO_64BIT, 910 2, virt_high_pcie_memmap.base, 911 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 912 913 if (virt_is_iommu_sys_enabled(s)) { 914 qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", 915 0, iommu_sys_phandle, 0, 0, 0, 916 iommu_sys_phandle, 0, 0xffff); 917 } 918 919 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 920 } 921 922 static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle) 923 { 924 char *name; 925 uint32_t test_phandle; 926 MachineState *ms = MACHINE(s); 927 928 test_phandle = (*phandle)++; 929 name = g_strdup_printf("/soc/test@%"HWADDR_PRIx, 930 s->memmap[VIRT_TEST].base); 931 qemu_fdt_add_subnode(ms->fdt, name); 932 { 933 static const char * const compat[3] = { 934 "sifive,test1", "sifive,test0", "syscon" 935 }; 936 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 937 (char **)&compat, ARRAY_SIZE(compat)); 938 } 939 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 940 0x0, s->memmap[VIRT_TEST].base, 0x0, s->memmap[VIRT_TEST].size); 941 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 942 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 943 g_free(name); 944 945 name = g_strdup_printf("/reboot"); 946 qemu_fdt_add_subnode(ms->fdt, name); 947 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 948 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 949 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 950 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 951 g_free(name); 952 953 name = g_strdup_printf("/poweroff"); 954 qemu_fdt_add_subnode(ms->fdt, name); 955 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 956 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 957 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 958 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 959 g_free(name); 960 } 961 962 static void create_fdt_uart(RISCVVirtState *s, 963 uint32_t irq_mmio_phandle) 964 { 965 g_autofree char *name = NULL; 966 MachineState *ms = MACHINE(s); 967 968 name = g_strdup_printf("/soc/serial@%"HWADDR_PRIx, 969 s->memmap[VIRT_UART0].base); 970 qemu_fdt_add_subnode(ms->fdt, name); 971 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 972 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 973 0x0, s->memmap[VIRT_UART0].base, 974 0x0, s->memmap[VIRT_UART0].size); 975 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 976 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 977 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 978 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 979 } else { 980 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 981 } 982 983 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 984 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); 985 } 986 987 static void create_fdt_rtc(RISCVVirtState *s, 988 uint32_t irq_mmio_phandle) 989 { 990 g_autofree char *name = NULL; 991 MachineState *ms = MACHINE(s); 992 993 name = g_strdup_printf("/soc/rtc@%"HWADDR_PRIx, 994 s->memmap[VIRT_RTC].base); 995 qemu_fdt_add_subnode(ms->fdt, name); 996 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 997 "google,goldfish-rtc"); 998 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 999 0x0, s->memmap[VIRT_RTC].base, 0x0, s->memmap[VIRT_RTC].size); 1000 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 1001 irq_mmio_phandle); 1002 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1003 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 1004 } else { 1005 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 1006 } 1007 } 1008 1009 static void create_fdt_flash(RISCVVirtState *s) 1010 { 1011 MachineState *ms = MACHINE(s); 1012 hwaddr flashsize = s->memmap[VIRT_FLASH].size / 2; 1013 hwaddr flashbase = s->memmap[VIRT_FLASH].base; 1014 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 1015 1016 qemu_fdt_add_subnode(ms->fdt, name); 1017 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 1018 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 1019 2, flashbase, 2, flashsize, 1020 2, flashbase + flashsize, 2, flashsize); 1021 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 1022 } 1023 1024 static void create_fdt_fw_cfg(RISCVVirtState *s) 1025 { 1026 MachineState *ms = MACHINE(s); 1027 hwaddr base = s->memmap[VIRT_FW_CFG].base; 1028 hwaddr size = s->memmap[VIRT_FW_CFG].size; 1029 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1030 1031 qemu_fdt_add_subnode(ms->fdt, nodename); 1032 qemu_fdt_setprop_string(ms->fdt, nodename, 1033 "compatible", "qemu,fw-cfg-mmio"); 1034 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1035 2, base, 2, size); 1036 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1037 } 1038 1039 static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) 1040 { 1041 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1042 void *fdt = MACHINE(s)->fdt; 1043 uint32_t iommu_phandle; 1044 g_autofree char *iommu_node = NULL; 1045 g_autofree char *pci_node = NULL; 1046 1047 pci_node = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, 1048 s->memmap[VIRT_PCIE_ECAM].base); 1049 iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, 1050 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1051 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1052 1053 qemu_fdt_add_subnode(fdt, iommu_node); 1054 1055 qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat)); 1056 qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 1057 1, bdf << 8, 1, 0, 1, 0, 1058 1, 0, 1, 0); 1059 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1060 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1061 1062 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1063 0, iommu_phandle, 0, bdf, 1064 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1065 } 1066 1067 static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, 1068 uint32_t msi_phandle, 1069 uint32_t *iommu_sys_phandle) 1070 { 1071 const char comp[] = "riscv,iommu"; 1072 void *fdt = MACHINE(s)->fdt; 1073 uint32_t iommu_phandle; 1074 g_autofree char *iommu_node = NULL; 1075 hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base; 1076 hwaddr size = s->memmap[VIRT_IOMMU_SYS].size; 1077 uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = { 1078 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, 1079 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, 1080 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, 1081 IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, 1082 }; 1083 1084 iommu_node = g_strdup_printf("/soc/iommu@%x", 1085 (unsigned int) s->memmap[VIRT_IOMMU_SYS].base); 1086 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1087 qemu_fdt_add_subnode(fdt, iommu_node); 1088 1089 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); 1090 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1091 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1092 1093 qemu_fdt_setprop_cells(fdt, iommu_node, "reg", 1094 addr >> 32, addr, size >> 32, size); 1095 qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); 1096 1097 qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", 1098 iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, 1099 iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, 1100 iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, 1101 iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); 1102 1103 qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); 1104 1105 *iommu_sys_phandle = iommu_phandle; 1106 } 1107 1108 static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) 1109 { 1110 const char comp[] = "riscv,pci-iommu"; 1111 void *fdt = MACHINE(s)->fdt; 1112 uint32_t iommu_phandle; 1113 g_autofree char *iommu_node = NULL; 1114 g_autofree char *pci_node = NULL; 1115 1116 pci_node = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, 1117 s->memmap[VIRT_PCIE_ECAM].base); 1118 iommu_node = g_strdup_printf("%s/iommu@%x", pci_node, bdf); 1119 iommu_phandle = qemu_fdt_alloc_phandle(fdt); 1120 qemu_fdt_add_subnode(fdt, iommu_node); 1121 1122 qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); 1123 qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); 1124 qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); 1125 qemu_fdt_setprop_cells(fdt, iommu_node, "reg", 1126 bdf << 8, 0, 0, 0, 0); 1127 qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", 1128 0, iommu_phandle, 0, bdf, 1129 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); 1130 s->pci_iommu_bdf = bdf; 1131 } 1132 1133 static void finalize_fdt(RISCVVirtState *s) 1134 { 1135 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1136 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1137 uint32_t iommu_sys_phandle = 1; 1138 1139 create_fdt_sockets(s, &phandle, &irq_mmio_phandle, 1140 &irq_pcie_phandle, &irq_virtio_phandle, 1141 &msi_pcie_phandle); 1142 1143 create_fdt_virtio(s, irq_virtio_phandle); 1144 1145 if (virt_is_iommu_sys_enabled(s)) { 1146 create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, 1147 &iommu_sys_phandle); 1148 } 1149 create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle, 1150 iommu_sys_phandle); 1151 1152 create_fdt_reset(s, &phandle); 1153 1154 create_fdt_uart(s, irq_mmio_phandle); 1155 1156 create_fdt_rtc(s, irq_mmio_phandle); 1157 } 1158 1159 static void create_fdt(RISCVVirtState *s) 1160 { 1161 MachineState *ms = MACHINE(s); 1162 uint8_t rng_seed[32]; 1163 g_autofree char *name = NULL; 1164 1165 ms->fdt = create_device_tree(&s->fdt_size); 1166 if (!ms->fdt) { 1167 error_report("create_device_tree() failed"); 1168 exit(1); 1169 } 1170 1171 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1172 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1173 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1174 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1175 1176 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1177 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1178 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1179 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1180 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1181 1182 /* 1183 * The "/soc/pci@..." node is needed for PCIE hotplugs 1184 * that might happen before finalize_fdt(). 1185 */ 1186 name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, 1187 s->memmap[VIRT_PCIE_ECAM].base); 1188 qemu_fdt_add_subnode(ms->fdt, name); 1189 1190 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1191 1192 /* Pass seed to RNG */ 1193 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1194 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1195 rng_seed, sizeof(rng_seed)); 1196 1197 qemu_fdt_add_subnode(ms->fdt, "/aliases"); 1198 1199 create_fdt_flash(s); 1200 create_fdt_fw_cfg(s); 1201 create_fdt_pmu(s); 1202 } 1203 1204 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1205 DeviceState *irqchip, 1206 RISCVVirtState *s) 1207 { 1208 DeviceState *dev; 1209 MemoryRegion *ecam_alias, *ecam_reg; 1210 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1211 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1212 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1213 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1214 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1215 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1216 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1217 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1218 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1219 qemu_irq irq; 1220 int i; 1221 1222 dev = qdev_new(TYPE_GPEX_HOST); 1223 1224 /* Set GPEX object properties for the virt machine */ 1225 object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE, 1226 ecam_base, NULL); 1227 object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE, 1228 ecam_size, NULL); 1229 object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE, 1230 mmio_base, NULL); 1231 object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE, 1232 mmio_size, NULL); 1233 object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE, 1234 high_mmio_base, NULL); 1235 object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1236 high_mmio_size, NULL); 1237 object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE, 1238 pio_base, NULL); 1239 object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, 1240 pio_size, NULL); 1241 1242 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1243 1244 ecam_alias = g_new0(MemoryRegion, 1); 1245 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1246 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1247 ecam_reg, 0, ecam_size); 1248 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1249 1250 mmio_alias = g_new0(MemoryRegion, 1); 1251 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1252 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1253 mmio_reg, mmio_base, mmio_size); 1254 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1255 1256 /* Map high MMIO space */ 1257 high_mmio_alias = g_new0(MemoryRegion, 1); 1258 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1259 mmio_reg, high_mmio_base, high_mmio_size); 1260 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1261 high_mmio_alias); 1262 1263 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1264 1265 for (i = 0; i < PCI_NUM_PINS; i++) { 1266 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1267 1268 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1269 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1270 } 1271 1272 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus; 1273 return dev; 1274 } 1275 1276 static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) 1277 { 1278 FWCfgState *fw_cfg; 1279 1280 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1281 &address_space_memory); 1282 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1283 1284 return fw_cfg; 1285 } 1286 1287 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1288 int base_hartid, int hart_count) 1289 { 1290 g_autofree char *plic_hart_config = NULL; 1291 1292 /* Per-socket PLIC hart topology configuration string */ 1293 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1294 1295 /* Per-socket PLIC */ 1296 return sifive_plic_create( 1297 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1298 plic_hart_config, hart_count, base_hartid, 1299 VIRT_IRQCHIP_NUM_SOURCES, 1300 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1301 VIRT_PLIC_PRIORITY_BASE, VIRT_PLIC_PENDING_BASE, 1302 VIRT_PLIC_ENABLE_BASE, VIRT_PLIC_ENABLE_STRIDE, 1303 VIRT_PLIC_CONTEXT_BASE, 1304 VIRT_PLIC_CONTEXT_STRIDE, 1305 memmap[VIRT_PLIC].size); 1306 } 1307 1308 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1309 const MemMapEntry *memmap, int socket, 1310 int base_hartid, int hart_count) 1311 { 1312 int i; 1313 hwaddr addr = 0; 1314 uint32_t guest_bits; 1315 DeviceState *aplic_s = NULL; 1316 DeviceState *aplic_m = NULL; 1317 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1318 1319 if (msimode) { 1320 if (!kvm_enabled()) { 1321 /* Per-socket M-level IMSICs */ 1322 addr = memmap[VIRT_IMSIC_M].base + 1323 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1324 for (i = 0; i < hart_count; i++) { 1325 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1326 base_hartid + i, true, 1, 1327 VIRT_IRQCHIP_NUM_MSIS); 1328 } 1329 } 1330 1331 /* Per-socket S-level IMSICs */ 1332 guest_bits = imsic_num_bits(aia_guests + 1); 1333 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1334 for (i = 0; i < hart_count; i++) { 1335 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1336 base_hartid + i, false, 1 + aia_guests, 1337 VIRT_IRQCHIP_NUM_MSIS); 1338 } 1339 } 1340 1341 if (!kvm_enabled()) { 1342 /* Per-socket M-level APLIC */ 1343 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1344 socket * memmap[VIRT_APLIC_M].size, 1345 memmap[VIRT_APLIC_M].size, 1346 (msimode) ? 0 : base_hartid, 1347 (msimode) ? 0 : hart_count, 1348 VIRT_IRQCHIP_NUM_SOURCES, 1349 VIRT_IRQCHIP_NUM_PRIO_BITS, 1350 msimode, true, NULL); 1351 } 1352 1353 /* Per-socket S-level APLIC */ 1354 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1355 socket * memmap[VIRT_APLIC_S].size, 1356 memmap[VIRT_APLIC_S].size, 1357 (msimode) ? 0 : base_hartid, 1358 (msimode) ? 0 : hart_count, 1359 VIRT_IRQCHIP_NUM_SOURCES, 1360 VIRT_IRQCHIP_NUM_PRIO_BITS, 1361 msimode, false, aplic_m); 1362 1363 if (kvm_enabled() && msimode) { 1364 riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr); 1365 } 1366 1367 return kvm_enabled() ? aplic_s : aplic_m; 1368 } 1369 1370 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1371 { 1372 DeviceState *dev; 1373 SysBusDevice *sysbus; 1374 int i; 1375 MemoryRegion *sysmem = get_system_memory(); 1376 1377 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1378 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1379 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1380 qdev_prop_set_uint32(dev, "mmio_size", s->memmap[VIRT_PLATFORM_BUS].size); 1381 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1382 s->platform_bus_dev = dev; 1383 1384 sysbus = SYS_BUS_DEVICE(dev); 1385 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1386 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1387 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1388 } 1389 1390 memory_region_add_subregion(sysmem, 1391 s->memmap[VIRT_PLATFORM_BUS].base, 1392 sysbus_mmio_get_region(sysbus, 0)); 1393 } 1394 1395 static void virt_build_smbios(RISCVVirtState *s) 1396 { 1397 MachineClass *mc = MACHINE_GET_CLASS(s); 1398 MachineState *ms = MACHINE(s); 1399 uint8_t *smbios_tables, *smbios_anchor; 1400 size_t smbios_tables_len, smbios_anchor_len; 1401 struct smbios_phys_mem_area mem_array; 1402 const char *product = "QEMU Virtual Machine"; 1403 1404 if (kvm_enabled()) { 1405 product = "KVM Virtual Machine"; 1406 } 1407 1408 smbios_set_defaults("QEMU", product, mc->name); 1409 1410 if (riscv_is_32bit(&s->soc[0])) { 1411 smbios_set_default_processor_family(0x200); 1412 } else { 1413 smbios_set_default_processor_family(0x201); 1414 } 1415 1416 /* build the array of physical mem area from base_memmap */ 1417 mem_array.address = s->memmap[VIRT_DRAM].base; 1418 mem_array.length = ms->ram_size; 1419 1420 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 1421 &mem_array, 1, 1422 &smbios_tables, &smbios_tables_len, 1423 &smbios_anchor, &smbios_anchor_len, 1424 &error_fatal); 1425 1426 if (smbios_anchor) { 1427 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables", 1428 smbios_tables, smbios_tables_len); 1429 fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor", 1430 smbios_anchor, smbios_anchor_len); 1431 } 1432 } 1433 1434 static void virt_machine_done(Notifier *notifier, void *data) 1435 { 1436 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1437 machine_done); 1438 MachineState *machine = MACHINE(s); 1439 hwaddr start_addr = s->memmap[VIRT_DRAM].base; 1440 target_ulong firmware_end_addr, kernel_start_addr; 1441 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1442 uint64_t fdt_load_addr; 1443 uint64_t kernel_entry = 0; 1444 BlockBackend *pflash_blk0; 1445 RISCVBootInfo boot_info; 1446 1447 /* 1448 * An user provided dtb must include everything, including 1449 * dynamic sysbus devices. Our FDT needs to be finalized. 1450 */ 1451 if (machine->dtb == NULL) { 1452 finalize_fdt(s); 1453 } 1454 1455 /* 1456 * Only direct boot kernel is currently supported for KVM VM, 1457 * so the "-bios" parameter is not supported when KVM is enabled. 1458 */ 1459 if (kvm_enabled()) { 1460 if (machine->firmware) { 1461 if (strcmp(machine->firmware, "none")) { 1462 error_report("Machine mode firmware is not supported in " 1463 "combination with KVM."); 1464 exit(1); 1465 } 1466 } else { 1467 machine->firmware = g_strdup("none"); 1468 } 1469 } 1470 1471 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1472 &start_addr, NULL); 1473 1474 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1475 if (pflash_blk0) { 1476 if (machine->firmware && !strcmp(machine->firmware, "none") && 1477 !kvm_enabled()) { 1478 /* 1479 * Pflash was supplied but bios is none and not KVM guest, 1480 * let's overwrite the address we jump to after reset to 1481 * the base of the flash. 1482 */ 1483 start_addr = s->memmap[VIRT_FLASH].base; 1484 } else { 1485 /* 1486 * Pflash was supplied but either KVM guest or bios is not none. 1487 * In this case, base of the flash would contain S-mode payload. 1488 */ 1489 riscv_setup_firmware_boot(machine); 1490 kernel_entry = s->memmap[VIRT_FLASH].base; 1491 } 1492 } 1493 1494 riscv_boot_info_init(&boot_info, &s->soc[0]); 1495 1496 if (machine->kernel_filename && !kernel_entry) { 1497 kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info, 1498 firmware_end_addr); 1499 riscv_load_kernel(machine, &boot_info, kernel_start_addr, 1500 true, NULL); 1501 kernel_entry = boot_info.image_low_addr; 1502 } 1503 1504 fdt_load_addr = riscv_compute_fdt_addr(s->memmap[VIRT_DRAM].base, 1505 s->memmap[VIRT_DRAM].size, 1506 machine, &boot_info); 1507 riscv_load_fdt(fdt_load_addr, machine->fdt); 1508 1509 /* load the reset vector */ 1510 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1511 s->memmap[VIRT_MROM].base, 1512 s->memmap[VIRT_MROM].size, kernel_entry, 1513 fdt_load_addr); 1514 1515 /* 1516 * Only direct boot kernel is currently supported for KVM VM, 1517 * So here setup kernel start address and fdt address. 1518 * TODO:Support firmware loading and integrate to TCG start 1519 */ 1520 if (kvm_enabled()) { 1521 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1522 } 1523 1524 virt_build_smbios(s); 1525 1526 if (virt_is_acpi_enabled(s)) { 1527 virt_acpi_setup(s); 1528 } 1529 } 1530 1531 static void virt_machine_init(MachineState *machine) 1532 { 1533 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1534 MemoryRegion *system_memory = get_system_memory(); 1535 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1536 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1537 int i, base_hartid, hart_count; 1538 int socket_count = riscv_socket_count(machine); 1539 1540 s->memmap = virt_memmap; 1541 1542 /* Check socket count limit */ 1543 if (VIRT_SOCKETS_MAX < socket_count) { 1544 error_report("number of sockets/nodes should be less than %d", 1545 VIRT_SOCKETS_MAX); 1546 exit(1); 1547 } 1548 1549 if (!virt_aclint_allowed() && s->have_aclint) { 1550 error_report("'aclint' is only available with TCG acceleration"); 1551 exit(1); 1552 } 1553 1554 /* Initialize sockets */ 1555 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1556 for (i = 0; i < socket_count; i++) { 1557 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1558 1559 if (!riscv_socket_check_hartids(machine, i)) { 1560 error_report("discontinuous hartids in socket%d", i); 1561 exit(1); 1562 } 1563 1564 base_hartid = riscv_socket_first_hartid(machine, i); 1565 if (base_hartid < 0) { 1566 error_report("can't find hartid base for socket%d", i); 1567 exit(1); 1568 } 1569 1570 hart_count = riscv_socket_hart_count(machine, i); 1571 if (hart_count < 0) { 1572 error_report("can't find hart count for socket%d", i); 1573 exit(1); 1574 } 1575 1576 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1577 TYPE_RISCV_HART_ARRAY); 1578 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1579 machine->cpu_type, &error_abort); 1580 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1581 base_hartid, &error_abort); 1582 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1583 hart_count, &error_abort); 1584 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1585 1586 if (virt_aclint_allowed() && s->have_aclint) { 1587 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1588 /* Per-socket ACLINT MTIMER */ 1589 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + 1590 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1591 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1592 base_hartid, hart_count, 1593 RISCV_ACLINT_DEFAULT_MTIMECMP, 1594 RISCV_ACLINT_DEFAULT_MTIME, 1595 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1596 } else { 1597 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1598 riscv_aclint_swi_create(s->memmap[VIRT_CLINT].base + 1599 i * s->memmap[VIRT_CLINT].size, 1600 base_hartid, hart_count, false); 1601 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + 1602 i * s->memmap[VIRT_CLINT].size + 1603 RISCV_ACLINT_SWI_SIZE, 1604 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1605 base_hartid, hart_count, 1606 RISCV_ACLINT_DEFAULT_MTIMECMP, 1607 RISCV_ACLINT_DEFAULT_MTIME, 1608 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1609 riscv_aclint_swi_create(s->memmap[VIRT_ACLINT_SSWI].base + 1610 i * s->memmap[VIRT_ACLINT_SSWI].size, 1611 base_hartid, hart_count, true); 1612 } 1613 } else if (tcg_enabled()) { 1614 /* Per-socket SiFive CLINT */ 1615 riscv_aclint_swi_create( 1616 s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size, 1617 base_hartid, hart_count, false); 1618 riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + 1619 i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1620 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1621 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1622 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1623 } 1624 1625 /* Per-socket interrupt controller */ 1626 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1627 s->irqchip[i] = virt_create_plic(s->memmap, i, 1628 base_hartid, hart_count); 1629 } else { 1630 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1631 s->memmap, i, base_hartid, 1632 hart_count); 1633 } 1634 1635 /* Try to use different IRQCHIP instance based device type */ 1636 if (i == 0) { 1637 mmio_irqchip = s->irqchip[i]; 1638 virtio_irqchip = s->irqchip[i]; 1639 pcie_irqchip = s->irqchip[i]; 1640 } 1641 if (i == 1) { 1642 virtio_irqchip = s->irqchip[i]; 1643 pcie_irqchip = s->irqchip[i]; 1644 } 1645 if (i == 2) { 1646 pcie_irqchip = s->irqchip[i]; 1647 } 1648 } 1649 1650 if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) { 1651 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1652 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1653 s->memmap[VIRT_APLIC_S].base, 1654 s->memmap[VIRT_IMSIC_S].base, 1655 s->aia_guests); 1656 } 1657 1658 if (riscv_is_32bit(&s->soc[0])) { 1659 #if HOST_LONG_BITS == 64 1660 /* limit RAM size in a 32-bit system */ 1661 if (machine->ram_size > 10 * GiB) { 1662 machine->ram_size = 10 * GiB; 1663 error_report("Limiting RAM size to 10 GiB"); 1664 } 1665 #endif 1666 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1667 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1668 } else { 1669 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1670 virt_high_pcie_memmap.base = s->memmap[VIRT_DRAM].base + 1671 machine->ram_size; 1672 virt_high_pcie_memmap.base = 1673 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1674 } 1675 1676 /* register system main memory (actual RAM) */ 1677 memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base, 1678 machine->ram); 1679 1680 /* boot rom */ 1681 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1682 s->memmap[VIRT_MROM].size, &error_fatal); 1683 memory_region_add_subregion(system_memory, s->memmap[VIRT_MROM].base, 1684 mask_rom); 1685 1686 /* 1687 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1688 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1689 */ 1690 s->fw_cfg = create_fw_cfg(machine, s->memmap[VIRT_FW_CFG].base); 1691 rom_set_fw(s->fw_cfg); 1692 1693 /* SiFive Test MMIO device */ 1694 sifive_test_create(s->memmap[VIRT_TEST].base); 1695 1696 /* VirtIO MMIO devices */ 1697 for (i = 0; i < VIRTIO_COUNT; i++) { 1698 sysbus_create_simple("virtio-mmio", 1699 s->memmap[VIRT_VIRTIO].base + i * s->memmap[VIRT_VIRTIO].size, 1700 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1701 } 1702 1703 gpex_pcie_init(system_memory, pcie_irqchip, s); 1704 1705 create_platform_bus(s, mmio_irqchip); 1706 1707 serial_mm_init(system_memory, s->memmap[VIRT_UART0].base, 1708 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1709 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1710 1711 sysbus_create_simple("goldfish_rtc", s->memmap[VIRT_RTC].base, 1712 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1713 1714 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1715 /* Map legacy -drive if=pflash to machine properties */ 1716 pflash_cfi01_legacy_drive(s->flash[i], 1717 drive_get(IF_PFLASH, 0, i)); 1718 } 1719 virt_flash_map(s, system_memory); 1720 1721 /* load/create device tree */ 1722 if (machine->dtb) { 1723 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1724 if (!machine->fdt) { 1725 error_report("load_device_tree() failed"); 1726 exit(1); 1727 } 1728 } else { 1729 create_fdt(s); 1730 } 1731 1732 if (virt_is_iommu_sys_enabled(s)) { 1733 DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS); 1734 1735 object_property_set_uint(OBJECT(iommu_sys), "addr", 1736 s->memmap[VIRT_IOMMU_SYS].base, 1737 &error_fatal); 1738 object_property_set_uint(OBJECT(iommu_sys), "base-irq", 1739 IOMMU_SYS_IRQ, 1740 &error_fatal); 1741 object_property_set_link(OBJECT(iommu_sys), "irqchip", 1742 OBJECT(mmio_irqchip), 1743 &error_fatal); 1744 1745 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal); 1746 } 1747 1748 s->machine_done.notify = virt_machine_done; 1749 qemu_add_machine_init_done_notifier(&s->machine_done); 1750 } 1751 1752 static void virt_machine_instance_init(Object *obj) 1753 { 1754 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1755 1756 virt_flash_create(s); 1757 1758 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1759 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1760 s->acpi = ON_OFF_AUTO_AUTO; 1761 s->iommu_sys = ON_OFF_AUTO_AUTO; 1762 } 1763 1764 static char *virt_get_aia_guests(Object *obj, Error **errp) 1765 { 1766 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1767 1768 return g_strdup_printf("%d", s->aia_guests); 1769 } 1770 1771 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1772 { 1773 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1774 1775 s->aia_guests = atoi(val); 1776 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1777 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1778 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1779 VIRT_IRQCHIP_MAX_GUESTS); 1780 } 1781 } 1782 1783 static char *virt_get_aia(Object *obj, Error **errp) 1784 { 1785 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1786 const char *val; 1787 1788 switch (s->aia_type) { 1789 case VIRT_AIA_TYPE_APLIC: 1790 val = "aplic"; 1791 break; 1792 case VIRT_AIA_TYPE_APLIC_IMSIC: 1793 val = "aplic-imsic"; 1794 break; 1795 default: 1796 val = "none"; 1797 break; 1798 }; 1799 1800 return g_strdup(val); 1801 } 1802 1803 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1804 { 1805 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1806 1807 if (!strcmp(val, "none")) { 1808 s->aia_type = VIRT_AIA_TYPE_NONE; 1809 } else if (!strcmp(val, "aplic")) { 1810 s->aia_type = VIRT_AIA_TYPE_APLIC; 1811 } else if (!strcmp(val, "aplic-imsic")) { 1812 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1813 } else { 1814 error_setg(errp, "Invalid AIA interrupt controller type"); 1815 error_append_hint(errp, "Valid values are none, aplic, and " 1816 "aplic-imsic.\n"); 1817 } 1818 } 1819 1820 static bool virt_get_aclint(Object *obj, Error **errp) 1821 { 1822 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1823 1824 return s->have_aclint; 1825 } 1826 1827 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1828 { 1829 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1830 1831 s->have_aclint = value; 1832 } 1833 1834 bool virt_is_iommu_sys_enabled(RISCVVirtState *s) 1835 { 1836 return s->iommu_sys == ON_OFF_AUTO_ON; 1837 } 1838 1839 static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name, 1840 void *opaque, Error **errp) 1841 { 1842 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1843 OnOffAuto iommu_sys = s->iommu_sys; 1844 1845 visit_type_OnOffAuto(v, name, &iommu_sys, errp); 1846 } 1847 1848 static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name, 1849 void *opaque, Error **errp) 1850 { 1851 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1852 1853 visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); 1854 } 1855 1856 bool virt_is_acpi_enabled(RISCVVirtState *s) 1857 { 1858 return s->acpi != ON_OFF_AUTO_OFF; 1859 } 1860 1861 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1862 void *opaque, Error **errp) 1863 { 1864 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1865 OnOffAuto acpi = s->acpi; 1866 1867 visit_type_OnOffAuto(v, name, &acpi, errp); 1868 } 1869 1870 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1871 void *opaque, Error **errp) 1872 { 1873 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1874 1875 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1876 } 1877 1878 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1879 DeviceState *dev) 1880 { 1881 MachineClass *mc = MACHINE_GET_CLASS(machine); 1882 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1883 1884 if (device_is_dynamic_sysbus(mc, dev) || 1885 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1886 object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { 1887 s->iommu_sys = ON_OFF_AUTO_OFF; 1888 return HOTPLUG_HANDLER(machine); 1889 } 1890 1891 return NULL; 1892 } 1893 1894 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1895 DeviceState *dev, Error **errp) 1896 { 1897 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1898 1899 if (s->platform_bus_dev) { 1900 MachineClass *mc = MACHINE_GET_CLASS(s); 1901 1902 if (device_is_dynamic_sysbus(mc, dev)) { 1903 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1904 SYS_BUS_DEVICE(dev)); 1905 } 1906 } 1907 1908 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1909 create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1910 } 1911 1912 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { 1913 create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); 1914 s->iommu_sys = ON_OFF_AUTO_OFF; 1915 } 1916 } 1917 1918 static void virt_machine_class_init(ObjectClass *oc, const void *data) 1919 { 1920 MachineClass *mc = MACHINE_CLASS(oc); 1921 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1922 1923 mc->desc = "RISC-V VirtIO board"; 1924 mc->init = virt_machine_init; 1925 mc->max_cpus = VIRT_CPUS_MAX; 1926 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1927 mc->block_default_type = IF_VIRTIO; 1928 mc->no_cdrom = 1; 1929 mc->pci_allow_0_address = true; 1930 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1931 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1932 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1933 mc->numa_mem_supported = true; 1934 /* platform instead of architectural choice */ 1935 mc->cpu_cluster_has_numa_boundary = true; 1936 mc->default_ram_id = "riscv_virt_board.ram"; 1937 assert(!mc->get_hotplug_handler); 1938 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1939 1940 hc->plug = virt_machine_device_plug_cb; 1941 1942 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1943 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); 1944 #ifdef CONFIG_TPM 1945 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1946 #endif 1947 1948 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1949 virt_set_aclint); 1950 object_class_property_set_description(oc, "aclint", 1951 "(TCG only) Set on/off to " 1952 "enable/disable emulating " 1953 "ACLINT devices"); 1954 1955 object_class_property_add_str(oc, "aia", virt_get_aia, 1956 virt_set_aia); 1957 object_class_property_set_description(oc, "aia", 1958 "Set type of AIA interrupt " 1959 "controller. Valid values are " 1960 "none, aplic, and aplic-imsic."); 1961 1962 object_class_property_add_str(oc, "aia-guests", 1963 virt_get_aia_guests, 1964 virt_set_aia_guests); 1965 { 1966 g_autofree char *str = 1967 g_strdup_printf("Set number of guest MMIO pages for AIA IMSIC. " 1968 "Valid value should be between 0 and %d.", 1969 VIRT_IRQCHIP_MAX_GUESTS); 1970 object_class_property_set_description(oc, "aia-guests", str); 1971 } 1972 1973 object_class_property_add(oc, "acpi", "OnOffAuto", 1974 virt_get_acpi, virt_set_acpi, 1975 NULL, NULL); 1976 object_class_property_set_description(oc, "acpi", 1977 "Enable ACPI"); 1978 1979 object_class_property_add(oc, "iommu-sys", "OnOffAuto", 1980 virt_get_iommu_sys, virt_set_iommu_sys, 1981 NULL, NULL); 1982 object_class_property_set_description(oc, "iommu-sys", 1983 "Enable IOMMU platform device"); 1984 } 1985 1986 static const TypeInfo virt_machine_typeinfo = { 1987 .name = MACHINE_TYPE_NAME("virt"), 1988 .parent = TYPE_MACHINE, 1989 .class_init = virt_machine_class_init, 1990 .instance_init = virt_machine_instance_init, 1991 .instance_size = sizeof(RISCVVirtState), 1992 .interfaces = (const InterfaceInfo[]) { 1993 { TYPE_HOTPLUG_HANDLER }, 1994 { } 1995 }, 1996 }; 1997 1998 static void virt_machine_init_register_types(void) 1999 { 2000 type_register_static(&virt_machine_typeinfo); 2001 } 2002 2003 type_init(virt_machine_init_register_types) 2004