1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "hw/intc/riscv_aclint.h" 39 #include "hw/intc/riscv_aplic.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "hw/intc/sifive_plic.h" 42 #include "hw/misc/sifive_test.h" 43 #include "hw/platform-bus.h" 44 #include "chardev/char.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/tpm.h" 49 #include "hw/pci/pci.h" 50 #include "hw/pci-host/gpex.h" 51 #include "hw/display/ramfb.h" 52 53 /* 54 * The virt machine physical address space used by some of the devices 55 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 56 * number of CPUs, and number of IMSIC guest files. 57 * 58 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 59 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 60 * of virt machine physical address space. 61 */ 62 63 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 64 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 65 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 66 #error "Can't accomodate single IMSIC group in address space" 67 #endif 68 69 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 70 VIRT_IMSIC_GROUP_MAX_SIZE) 71 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 72 #error "Can't accomodate all IMSIC groups in address space" 73 #endif 74 75 static const MemMapEntry virt_memmap[] = { 76 [VIRT_DEBUG] = { 0x0, 0x100 }, 77 [VIRT_MROM] = { 0x1000, 0xf000 }, 78 [VIRT_TEST] = { 0x100000, 0x1000 }, 79 [VIRT_RTC] = { 0x101000, 0x1000 }, 80 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 81 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 82 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 83 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 84 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 85 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 86 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 87 [VIRT_UART0] = { 0x10000000, 0x100 }, 88 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 89 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 90 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 91 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 92 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 93 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 94 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 95 [VIRT_DRAM] = { 0x80000000, 0x0 }, 96 }; 97 98 /* PCIe high mmio is fixed for RV32 */ 99 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 100 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 101 102 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 103 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 104 105 static MemMapEntry virt_high_pcie_memmap; 106 107 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 108 109 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 110 const char *name, 111 const char *alias_prop_name) 112 { 113 /* 114 * Create a single flash device. We use the same parameters as 115 * the flash devices on the ARM virt board. 116 */ 117 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 118 119 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 120 qdev_prop_set_uint8(dev, "width", 4); 121 qdev_prop_set_uint8(dev, "device-width", 2); 122 qdev_prop_set_bit(dev, "big-endian", false); 123 qdev_prop_set_uint16(dev, "id0", 0x89); 124 qdev_prop_set_uint16(dev, "id1", 0x18); 125 qdev_prop_set_uint16(dev, "id2", 0x00); 126 qdev_prop_set_uint16(dev, "id3", 0x00); 127 qdev_prop_set_string(dev, "name", name); 128 129 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 130 object_property_add_alias(OBJECT(s), alias_prop_name, 131 OBJECT(dev), "drive"); 132 133 return PFLASH_CFI01(dev); 134 } 135 136 static void virt_flash_create(RISCVVirtState *s) 137 { 138 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 139 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 140 } 141 142 static void virt_flash_map1(PFlashCFI01 *flash, 143 hwaddr base, hwaddr size, 144 MemoryRegion *sysmem) 145 { 146 DeviceState *dev = DEVICE(flash); 147 148 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 149 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 150 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 151 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 152 153 memory_region_add_subregion(sysmem, base, 154 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 155 0)); 156 } 157 158 static void virt_flash_map(RISCVVirtState *s, 159 MemoryRegion *sysmem) 160 { 161 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 162 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 163 164 virt_flash_map1(s->flash[0], flashbase, flashsize, 165 sysmem); 166 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 167 sysmem); 168 } 169 170 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 171 uint32_t irqchip_phandle) 172 { 173 int pin, dev; 174 uint32_t irq_map_stride = 0; 175 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 176 FDT_MAX_INT_MAP_WIDTH] = {}; 177 uint32_t *irq_map = full_irq_map; 178 179 /* This code creates a standard swizzle of interrupts such that 180 * each device's first interrupt is based on it's PCI_SLOT number. 181 * (See pci_swizzle_map_irq_fn()) 182 * 183 * We only need one entry per interrupt in the table (not one per 184 * possible slot) seeing the interrupt-map-mask will allow the table 185 * to wrap to any number of devices. 186 */ 187 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 188 int devfn = dev * 0x8; 189 190 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 191 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 192 int i = 0; 193 194 /* Fill PCI address cells */ 195 irq_map[i] = cpu_to_be32(devfn << 8); 196 i += FDT_PCI_ADDR_CELLS; 197 198 /* Fill PCI Interrupt cells */ 199 irq_map[i] = cpu_to_be32(pin + 1); 200 i += FDT_PCI_INT_CELLS; 201 202 /* Fill interrupt controller phandle and cells */ 203 irq_map[i++] = cpu_to_be32(irqchip_phandle); 204 irq_map[i++] = cpu_to_be32(irq_nr); 205 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 206 irq_map[i++] = cpu_to_be32(0x4); 207 } 208 209 if (!irq_map_stride) { 210 irq_map_stride = i; 211 } 212 irq_map += irq_map_stride; 213 } 214 } 215 216 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 217 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 218 irq_map_stride * sizeof(uint32_t)); 219 220 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 221 0x1800, 0, 0, 0x7); 222 } 223 224 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 225 char *clust_name, uint32_t *phandle, 226 uint32_t *intc_phandles) 227 { 228 int cpu; 229 uint32_t cpu_phandle; 230 MachineState *mc = MACHINE(s); 231 char *name, *cpu_name, *core_name, *intc_name; 232 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 233 234 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 235 cpu_phandle = (*phandle)++; 236 237 cpu_name = g_strdup_printf("/cpus/cpu@%d", 238 s->soc[socket].hartid_base + cpu); 239 qemu_fdt_add_subnode(mc->fdt, cpu_name); 240 if (riscv_feature(&s->soc[socket].harts[cpu].env, 241 RISCV_FEATURE_MMU)) { 242 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 243 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 244 } else { 245 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 246 "riscv,none"); 247 } 248 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 249 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); 250 g_free(name); 251 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); 252 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); 253 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", 254 s->soc[socket].hartid_base + cpu); 255 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); 256 riscv_socket_fdt_write_id(mc, cpu_name, socket); 257 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); 258 259 intc_phandles[cpu] = (*phandle)++; 260 261 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 262 qemu_fdt_add_subnode(mc->fdt, intc_name); 263 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", 264 intc_phandles[cpu]); 265 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", 266 "riscv,cpu-intc"); 267 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); 268 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); 269 270 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 271 qemu_fdt_add_subnode(mc->fdt, core_name); 272 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); 273 274 g_free(core_name); 275 g_free(intc_name); 276 g_free(cpu_name); 277 } 278 } 279 280 static void create_fdt_socket_memory(RISCVVirtState *s, 281 const MemMapEntry *memmap, int socket) 282 { 283 char *mem_name; 284 uint64_t addr, size; 285 MachineState *mc = MACHINE(s); 286 287 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 288 size = riscv_socket_mem_size(mc, socket); 289 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 290 qemu_fdt_add_subnode(mc->fdt, mem_name); 291 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", 292 addr >> 32, addr, size >> 32, size); 293 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); 294 riscv_socket_fdt_write_id(mc, mem_name, socket); 295 g_free(mem_name); 296 } 297 298 static void create_fdt_socket_clint(RISCVVirtState *s, 299 const MemMapEntry *memmap, int socket, 300 uint32_t *intc_phandles) 301 { 302 int cpu; 303 char *clint_name; 304 uint32_t *clint_cells; 305 unsigned long clint_addr; 306 MachineState *mc = MACHINE(s); 307 static const char * const clint_compat[2] = { 308 "sifive,clint0", "riscv,clint0" 309 }; 310 311 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 312 313 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 314 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 315 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 316 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 317 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 318 } 319 320 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 321 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 322 qemu_fdt_add_subnode(mc->fdt, clint_name); 323 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", 324 (char **)&clint_compat, 325 ARRAY_SIZE(clint_compat)); 326 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", 327 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 328 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", 329 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 330 riscv_socket_fdt_write_id(mc, clint_name, socket); 331 g_free(clint_name); 332 333 g_free(clint_cells); 334 } 335 336 static void create_fdt_socket_aclint(RISCVVirtState *s, 337 const MemMapEntry *memmap, int socket, 338 uint32_t *intc_phandles) 339 { 340 int cpu; 341 char *name; 342 unsigned long addr, size; 343 uint32_t aclint_cells_size; 344 uint32_t *aclint_mswi_cells; 345 uint32_t *aclint_sswi_cells; 346 uint32_t *aclint_mtimer_cells; 347 MachineState *mc = MACHINE(s); 348 349 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 350 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 351 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 352 353 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 354 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 355 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 356 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 357 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 358 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 359 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 360 } 361 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 362 363 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 364 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 365 name = g_strdup_printf("/soc/mswi@%lx", addr); 366 qemu_fdt_add_subnode(mc->fdt, name); 367 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 368 "riscv,aclint-mswi"); 369 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 370 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 371 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 372 aclint_mswi_cells, aclint_cells_size); 373 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 374 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 375 riscv_socket_fdt_write_id(mc, name, socket); 376 g_free(name); 377 } 378 379 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 380 addr = memmap[VIRT_CLINT].base + 381 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 382 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 383 } else { 384 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 385 (memmap[VIRT_CLINT].size * socket); 386 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 387 } 388 name = g_strdup_printf("/soc/mtimer@%lx", addr); 389 qemu_fdt_add_subnode(mc->fdt, name); 390 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 391 "riscv,aclint-mtimer"); 392 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 393 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 394 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 395 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 396 0x0, RISCV_ACLINT_DEFAULT_MTIME); 397 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 398 aclint_mtimer_cells, aclint_cells_size); 399 riscv_socket_fdt_write_id(mc, name, socket); 400 g_free(name); 401 402 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 403 addr = memmap[VIRT_ACLINT_SSWI].base + 404 (memmap[VIRT_ACLINT_SSWI].size * socket); 405 name = g_strdup_printf("/soc/sswi@%lx", addr); 406 qemu_fdt_add_subnode(mc->fdt, name); 407 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 408 "riscv,aclint-sswi"); 409 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 410 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 411 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 412 aclint_sswi_cells, aclint_cells_size); 413 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 414 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 415 riscv_socket_fdt_write_id(mc, name, socket); 416 g_free(name); 417 } 418 419 g_free(aclint_mswi_cells); 420 g_free(aclint_mtimer_cells); 421 g_free(aclint_sswi_cells); 422 } 423 424 static void create_fdt_socket_plic(RISCVVirtState *s, 425 const MemMapEntry *memmap, int socket, 426 uint32_t *phandle, uint32_t *intc_phandles, 427 uint32_t *plic_phandles) 428 { 429 int cpu; 430 char *plic_name; 431 uint32_t *plic_cells; 432 unsigned long plic_addr; 433 MachineState *mc = MACHINE(s); 434 static const char * const plic_compat[2] = { 435 "sifive,plic-1.0.0", "riscv,plic0" 436 }; 437 438 if (kvm_enabled()) { 439 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 440 } else { 441 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 442 } 443 444 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 445 if (kvm_enabled()) { 446 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 447 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 448 } else { 449 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 450 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 451 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 452 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 453 } 454 } 455 456 plic_phandles[socket] = (*phandle)++; 457 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 458 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 459 qemu_fdt_add_subnode(mc->fdt, plic_name); 460 qemu_fdt_setprop_cell(mc->fdt, plic_name, 461 "#interrupt-cells", FDT_PLIC_INT_CELLS); 462 qemu_fdt_setprop_cell(mc->fdt, plic_name, 463 "#address-cells", FDT_PLIC_ADDR_CELLS); 464 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", 465 (char **)&plic_compat, 466 ARRAY_SIZE(plic_compat)); 467 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); 468 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", 469 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 470 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", 471 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 472 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", 473 VIRT_IRQCHIP_NUM_SOURCES - 1); 474 riscv_socket_fdt_write_id(mc, plic_name, socket); 475 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", 476 plic_phandles[socket]); 477 478 if (!socket) { 479 platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, 480 memmap[VIRT_PLATFORM_BUS].base, 481 memmap[VIRT_PLATFORM_BUS].size, 482 VIRT_PLATFORM_BUS_IRQ); 483 } 484 485 g_free(plic_name); 486 487 g_free(plic_cells); 488 } 489 490 static uint32_t imsic_num_bits(uint32_t count) 491 { 492 uint32_t ret = 0; 493 494 while (BIT(ret) < count) { 495 ret++; 496 } 497 498 return ret; 499 } 500 501 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 502 uint32_t *phandle, uint32_t *intc_phandles, 503 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 504 { 505 int cpu, socket; 506 char *imsic_name; 507 MachineState *mc = MACHINE(s); 508 uint32_t imsic_max_hart_per_socket, imsic_guest_bits; 509 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 510 511 *msi_m_phandle = (*phandle)++; 512 *msi_s_phandle = (*phandle)++; 513 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); 514 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); 515 516 /* M-level IMSIC node */ 517 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 518 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 519 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 520 } 521 imsic_max_hart_per_socket = 0; 522 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 523 imsic_addr = memmap[VIRT_IMSIC_M].base + 524 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 525 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; 526 imsic_regs[socket * 4 + 0] = 0; 527 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 528 imsic_regs[socket * 4 + 2] = 0; 529 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 530 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 531 imsic_max_hart_per_socket = s->soc[socket].num_harts; 532 } 533 } 534 imsic_name = g_strdup_printf("/soc/imsics@%lx", 535 (unsigned long)memmap[VIRT_IMSIC_M].base); 536 qemu_fdt_add_subnode(mc->fdt, imsic_name); 537 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 538 "riscv,imsics"); 539 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 540 FDT_IMSIC_INT_CELLS); 541 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 542 NULL, 0); 543 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 544 NULL, 0); 545 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 546 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 547 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 548 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 549 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 550 VIRT_IRQCHIP_NUM_MSIS); 551 if (riscv_socket_count(mc) > 1) { 552 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 553 imsic_num_bits(imsic_max_hart_per_socket)); 554 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 555 imsic_num_bits(riscv_socket_count(mc))); 556 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 557 IMSIC_MMIO_GROUP_MIN_SHIFT); 558 } 559 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); 560 561 g_free(imsic_name); 562 563 /* S-level IMSIC node */ 564 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 565 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 566 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 567 } 568 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); 569 imsic_max_hart_per_socket = 0; 570 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 571 imsic_addr = memmap[VIRT_IMSIC_S].base + 572 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 573 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 574 s->soc[socket].num_harts; 575 imsic_regs[socket * 4 + 0] = 0; 576 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 577 imsic_regs[socket * 4 + 2] = 0; 578 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 579 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 580 imsic_max_hart_per_socket = s->soc[socket].num_harts; 581 } 582 } 583 imsic_name = g_strdup_printf("/soc/imsics@%lx", 584 (unsigned long)memmap[VIRT_IMSIC_S].base); 585 qemu_fdt_add_subnode(mc->fdt, imsic_name); 586 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 587 "riscv,imsics"); 588 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 589 FDT_IMSIC_INT_CELLS); 590 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 591 NULL, 0); 592 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 593 NULL, 0); 594 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 595 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 596 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 597 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 598 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 599 VIRT_IRQCHIP_NUM_MSIS); 600 if (imsic_guest_bits) { 601 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", 602 imsic_guest_bits); 603 } 604 if (riscv_socket_count(mc) > 1) { 605 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 606 imsic_num_bits(imsic_max_hart_per_socket)); 607 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 608 imsic_num_bits(riscv_socket_count(mc))); 609 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 610 IMSIC_MMIO_GROUP_MIN_SHIFT); 611 } 612 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); 613 g_free(imsic_name); 614 615 g_free(imsic_regs); 616 g_free(imsic_cells); 617 } 618 619 static void create_fdt_socket_aplic(RISCVVirtState *s, 620 const MemMapEntry *memmap, int socket, 621 uint32_t msi_m_phandle, 622 uint32_t msi_s_phandle, 623 uint32_t *phandle, 624 uint32_t *intc_phandles, 625 uint32_t *aplic_phandles) 626 { 627 int cpu; 628 char *aplic_name; 629 uint32_t *aplic_cells; 630 unsigned long aplic_addr; 631 MachineState *mc = MACHINE(s); 632 uint32_t aplic_m_phandle, aplic_s_phandle; 633 634 aplic_m_phandle = (*phandle)++; 635 aplic_s_phandle = (*phandle)++; 636 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 637 638 /* M-level APLIC node */ 639 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 640 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 641 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 642 } 643 aplic_addr = memmap[VIRT_APLIC_M].base + 644 (memmap[VIRT_APLIC_M].size * socket); 645 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 646 qemu_fdt_add_subnode(mc->fdt, aplic_name); 647 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 648 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 649 "#interrupt-cells", FDT_APLIC_INT_CELLS); 650 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 651 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 652 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 653 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 654 } else { 655 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 656 msi_m_phandle); 657 } 658 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 659 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); 660 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 661 VIRT_IRQCHIP_NUM_SOURCES); 662 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", 663 aplic_s_phandle); 664 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", 665 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); 666 riscv_socket_fdt_write_id(mc, aplic_name, socket); 667 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); 668 g_free(aplic_name); 669 670 /* S-level APLIC node */ 671 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 672 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 673 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 674 } 675 aplic_addr = memmap[VIRT_APLIC_S].base + 676 (memmap[VIRT_APLIC_S].size * socket); 677 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 678 qemu_fdt_add_subnode(mc->fdt, aplic_name); 679 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 680 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 681 "#interrupt-cells", FDT_APLIC_INT_CELLS); 682 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 683 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 684 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 685 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 686 } else { 687 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 688 msi_s_phandle); 689 } 690 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 691 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); 692 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 693 VIRT_IRQCHIP_NUM_SOURCES); 694 riscv_socket_fdt_write_id(mc, aplic_name, socket); 695 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); 696 697 if (!socket) { 698 platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, 699 memmap[VIRT_PLATFORM_BUS].base, 700 memmap[VIRT_PLATFORM_BUS].size, 701 VIRT_PLATFORM_BUS_IRQ); 702 } 703 704 g_free(aplic_name); 705 706 g_free(aplic_cells); 707 aplic_phandles[socket] = aplic_s_phandle; 708 } 709 710 static void create_fdt_pmu(RISCVVirtState *s) 711 { 712 char *pmu_name; 713 MachineState *mc = MACHINE(s); 714 RISCVCPU hart = s->soc[0].harts[0]; 715 716 pmu_name = g_strdup_printf("/soc/pmu"); 717 qemu_fdt_add_subnode(mc->fdt, pmu_name); 718 qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); 719 riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); 720 721 g_free(pmu_name); 722 } 723 724 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 725 uint32_t *phandle, 726 uint32_t *irq_mmio_phandle, 727 uint32_t *irq_pcie_phandle, 728 uint32_t *irq_virtio_phandle, 729 uint32_t *msi_pcie_phandle) 730 { 731 char *clust_name; 732 int socket, phandle_pos; 733 MachineState *mc = MACHINE(s); 734 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 735 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 736 737 qemu_fdt_add_subnode(mc->fdt, "/cpus"); 738 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", 739 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 740 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); 741 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); 742 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); 743 744 intc_phandles = g_new0(uint32_t, mc->smp.cpus); 745 746 phandle_pos = mc->smp.cpus; 747 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 748 phandle_pos -= s->soc[socket].num_harts; 749 750 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 751 qemu_fdt_add_subnode(mc->fdt, clust_name); 752 753 create_fdt_socket_cpus(s, socket, clust_name, phandle, 754 &intc_phandles[phandle_pos]); 755 756 create_fdt_socket_memory(s, memmap, socket); 757 758 g_free(clust_name); 759 760 if (!kvm_enabled()) { 761 if (s->have_aclint) { 762 create_fdt_socket_aclint(s, memmap, socket, 763 &intc_phandles[phandle_pos]); 764 } else { 765 create_fdt_socket_clint(s, memmap, socket, 766 &intc_phandles[phandle_pos]); 767 } 768 } 769 } 770 771 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 772 create_fdt_imsic(s, memmap, phandle, intc_phandles, 773 &msi_m_phandle, &msi_s_phandle); 774 *msi_pcie_phandle = msi_s_phandle; 775 } 776 777 phandle_pos = mc->smp.cpus; 778 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 779 phandle_pos -= s->soc[socket].num_harts; 780 781 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 782 create_fdt_socket_plic(s, memmap, socket, phandle, 783 &intc_phandles[phandle_pos], xplic_phandles); 784 } else { 785 create_fdt_socket_aplic(s, memmap, socket, 786 msi_m_phandle, msi_s_phandle, phandle, 787 &intc_phandles[phandle_pos], xplic_phandles); 788 } 789 } 790 791 g_free(intc_phandles); 792 793 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 794 if (socket == 0) { 795 *irq_mmio_phandle = xplic_phandles[socket]; 796 *irq_virtio_phandle = xplic_phandles[socket]; 797 *irq_pcie_phandle = xplic_phandles[socket]; 798 } 799 if (socket == 1) { 800 *irq_virtio_phandle = xplic_phandles[socket]; 801 *irq_pcie_phandle = xplic_phandles[socket]; 802 } 803 if (socket == 2) { 804 *irq_pcie_phandle = xplic_phandles[socket]; 805 } 806 } 807 808 riscv_socket_fdt_write_distance_matrix(mc); 809 } 810 811 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 812 uint32_t irq_virtio_phandle) 813 { 814 int i; 815 char *name; 816 MachineState *mc = MACHINE(s); 817 818 for (i = 0; i < VIRTIO_COUNT; i++) { 819 name = g_strdup_printf("/soc/virtio_mmio@%lx", 820 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 821 qemu_fdt_add_subnode(mc->fdt, name); 822 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); 823 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 824 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 825 0x0, memmap[VIRT_VIRTIO].size); 826 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 827 irq_virtio_phandle); 828 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 829 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", 830 VIRTIO_IRQ + i); 831 } else { 832 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", 833 VIRTIO_IRQ + i, 0x4); 834 } 835 g_free(name); 836 } 837 } 838 839 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 840 uint32_t irq_pcie_phandle, 841 uint32_t msi_pcie_phandle) 842 { 843 char *name; 844 MachineState *mc = MACHINE(s); 845 846 name = g_strdup_printf("/soc/pci@%lx", 847 (long) memmap[VIRT_PCIE_ECAM].base); 848 qemu_fdt_add_subnode(mc->fdt, name); 849 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", 850 FDT_PCI_ADDR_CELLS); 851 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 852 FDT_PCI_INT_CELLS); 853 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); 854 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 855 "pci-host-ecam-generic"); 856 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); 857 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); 858 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, 859 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 860 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); 861 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 862 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); 863 } 864 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, 865 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 866 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", 867 1, FDT_PCI_RANGE_IOPORT, 2, 0, 868 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 869 1, FDT_PCI_RANGE_MMIO, 870 2, memmap[VIRT_PCIE_MMIO].base, 871 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 872 1, FDT_PCI_RANGE_MMIO_64BIT, 873 2, virt_high_pcie_memmap.base, 874 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 875 876 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); 877 g_free(name); 878 } 879 880 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 881 uint32_t *phandle) 882 { 883 char *name; 884 uint32_t test_phandle; 885 MachineState *mc = MACHINE(s); 886 887 test_phandle = (*phandle)++; 888 name = g_strdup_printf("/soc/test@%lx", 889 (long)memmap[VIRT_TEST].base); 890 qemu_fdt_add_subnode(mc->fdt, name); 891 { 892 static const char * const compat[3] = { 893 "sifive,test1", "sifive,test0", "syscon" 894 }; 895 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", 896 (char **)&compat, ARRAY_SIZE(compat)); 897 } 898 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 899 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 900 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); 901 test_phandle = qemu_fdt_get_phandle(mc->fdt, name); 902 g_free(name); 903 904 name = g_strdup_printf("/reboot"); 905 qemu_fdt_add_subnode(mc->fdt, name); 906 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); 907 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 908 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 909 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); 910 g_free(name); 911 912 name = g_strdup_printf("/poweroff"); 913 qemu_fdt_add_subnode(mc->fdt, name); 914 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); 915 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 916 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 917 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); 918 g_free(name); 919 } 920 921 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 922 uint32_t irq_mmio_phandle) 923 { 924 char *name; 925 MachineState *mc = MACHINE(s); 926 927 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 928 qemu_fdt_add_subnode(mc->fdt, name); 929 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); 930 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 931 0x0, memmap[VIRT_UART0].base, 932 0x0, memmap[VIRT_UART0].size); 933 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); 934 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); 935 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 936 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); 937 } else { 938 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); 939 } 940 941 qemu_fdt_add_subnode(mc->fdt, "/chosen"); 942 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); 943 g_free(name); 944 } 945 946 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 947 uint32_t irq_mmio_phandle) 948 { 949 char *name; 950 MachineState *mc = MACHINE(s); 951 952 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 953 qemu_fdt_add_subnode(mc->fdt, name); 954 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 955 "google,goldfish-rtc"); 956 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 957 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 958 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 959 irq_mmio_phandle); 960 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 961 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); 962 } else { 963 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); 964 } 965 g_free(name); 966 } 967 968 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 969 { 970 char *name; 971 MachineState *mc = MACHINE(s); 972 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 973 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 974 975 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 976 qemu_fdt_add_subnode(mc->fdt, name); 977 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 978 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 979 2, flashbase, 2, flashsize, 980 2, flashbase + flashsize, 2, flashsize); 981 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 982 g_free(name); 983 } 984 985 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 986 { 987 char *nodename; 988 MachineState *mc = MACHINE(s); 989 hwaddr base = memmap[VIRT_FW_CFG].base; 990 hwaddr size = memmap[VIRT_FW_CFG].size; 991 992 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 993 qemu_fdt_add_subnode(mc->fdt, nodename); 994 qemu_fdt_setprop_string(mc->fdt, nodename, 995 "compatible", "qemu,fw-cfg-mmio"); 996 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 997 2, base, 2, size); 998 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 999 g_free(nodename); 1000 } 1001 1002 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 1003 { 1004 MachineState *mc = MACHINE(s); 1005 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1006 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1007 uint8_t rng_seed[32]; 1008 1009 if (mc->dtb) { 1010 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 1011 if (!mc->fdt) { 1012 error_report("load_device_tree() failed"); 1013 exit(1); 1014 } 1015 } else { 1016 mc->fdt = create_device_tree(&s->fdt_size); 1017 if (!mc->fdt) { 1018 error_report("create_device_tree() failed"); 1019 exit(1); 1020 } 1021 } 1022 1023 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); 1024 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); 1025 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); 1026 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); 1027 1028 qemu_fdt_add_subnode(mc->fdt, "/soc"); 1029 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); 1030 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); 1031 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); 1032 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); 1033 1034 create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, 1035 &irq_pcie_phandle, &irq_virtio_phandle, 1036 &msi_pcie_phandle); 1037 1038 create_fdt_virtio(s, memmap, irq_virtio_phandle); 1039 1040 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); 1041 1042 create_fdt_reset(s, memmap, &phandle); 1043 1044 create_fdt_uart(s, memmap, irq_mmio_phandle); 1045 1046 create_fdt_rtc(s, memmap, irq_mmio_phandle); 1047 1048 create_fdt_flash(s, memmap); 1049 create_fdt_fw_cfg(s, memmap); 1050 create_fdt_pmu(s); 1051 1052 /* Pass seed to RNG */ 1053 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1054 qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); 1055 } 1056 1057 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1058 hwaddr ecam_base, hwaddr ecam_size, 1059 hwaddr mmio_base, hwaddr mmio_size, 1060 hwaddr high_mmio_base, 1061 hwaddr high_mmio_size, 1062 hwaddr pio_base, 1063 DeviceState *irqchip) 1064 { 1065 DeviceState *dev; 1066 MemoryRegion *ecam_alias, *ecam_reg; 1067 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1068 qemu_irq irq; 1069 int i; 1070 1071 dev = qdev_new(TYPE_GPEX_HOST); 1072 1073 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1074 1075 ecam_alias = g_new0(MemoryRegion, 1); 1076 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1077 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1078 ecam_reg, 0, ecam_size); 1079 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1080 1081 mmio_alias = g_new0(MemoryRegion, 1); 1082 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1083 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1084 mmio_reg, mmio_base, mmio_size); 1085 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1086 1087 /* Map high MMIO space */ 1088 high_mmio_alias = g_new0(MemoryRegion, 1); 1089 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1090 mmio_reg, high_mmio_base, high_mmio_size); 1091 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1092 high_mmio_alias); 1093 1094 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1095 1096 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1097 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1098 1099 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1100 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1101 } 1102 1103 return dev; 1104 } 1105 1106 static FWCfgState *create_fw_cfg(const MachineState *mc) 1107 { 1108 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1109 FWCfgState *fw_cfg; 1110 1111 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1112 &address_space_memory); 1113 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 1114 1115 return fw_cfg; 1116 } 1117 1118 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1119 int base_hartid, int hart_count) 1120 { 1121 DeviceState *ret; 1122 char *plic_hart_config; 1123 1124 /* Per-socket PLIC hart topology configuration string */ 1125 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1126 1127 /* Per-socket PLIC */ 1128 ret = sifive_plic_create( 1129 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1130 plic_hart_config, hart_count, base_hartid, 1131 VIRT_IRQCHIP_NUM_SOURCES, 1132 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1133 VIRT_PLIC_PRIORITY_BASE, 1134 VIRT_PLIC_PENDING_BASE, 1135 VIRT_PLIC_ENABLE_BASE, 1136 VIRT_PLIC_ENABLE_STRIDE, 1137 VIRT_PLIC_CONTEXT_BASE, 1138 VIRT_PLIC_CONTEXT_STRIDE, 1139 memmap[VIRT_PLIC].size); 1140 1141 g_free(plic_hart_config); 1142 1143 return ret; 1144 } 1145 1146 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1147 const MemMapEntry *memmap, int socket, 1148 int base_hartid, int hart_count) 1149 { 1150 int i; 1151 hwaddr addr; 1152 uint32_t guest_bits; 1153 DeviceState *aplic_m; 1154 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; 1155 1156 if (msimode) { 1157 /* Per-socket M-level IMSICs */ 1158 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1159 for (i = 0; i < hart_count; i++) { 1160 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1161 base_hartid + i, true, 1, 1162 VIRT_IRQCHIP_NUM_MSIS); 1163 } 1164 1165 /* Per-socket S-level IMSICs */ 1166 guest_bits = imsic_num_bits(aia_guests + 1); 1167 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1168 for (i = 0; i < hart_count; i++) { 1169 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1170 base_hartid + i, false, 1 + aia_guests, 1171 VIRT_IRQCHIP_NUM_MSIS); 1172 } 1173 } 1174 1175 /* Per-socket M-level APLIC */ 1176 aplic_m = riscv_aplic_create( 1177 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, 1178 memmap[VIRT_APLIC_M].size, 1179 (msimode) ? 0 : base_hartid, 1180 (msimode) ? 0 : hart_count, 1181 VIRT_IRQCHIP_NUM_SOURCES, 1182 VIRT_IRQCHIP_NUM_PRIO_BITS, 1183 msimode, true, NULL); 1184 1185 if (aplic_m) { 1186 /* Per-socket S-level APLIC */ 1187 riscv_aplic_create( 1188 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, 1189 memmap[VIRT_APLIC_S].size, 1190 (msimode) ? 0 : base_hartid, 1191 (msimode) ? 0 : hart_count, 1192 VIRT_IRQCHIP_NUM_SOURCES, 1193 VIRT_IRQCHIP_NUM_PRIO_BITS, 1194 msimode, false, aplic_m); 1195 } 1196 1197 return aplic_m; 1198 } 1199 1200 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1201 { 1202 DeviceState *dev; 1203 SysBusDevice *sysbus; 1204 const MemMapEntry *memmap = virt_memmap; 1205 int i; 1206 MemoryRegion *sysmem = get_system_memory(); 1207 1208 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1209 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1210 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1211 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1212 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1213 s->platform_bus_dev = dev; 1214 1215 sysbus = SYS_BUS_DEVICE(dev); 1216 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1217 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1218 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1219 } 1220 1221 memory_region_add_subregion(sysmem, 1222 memmap[VIRT_PLATFORM_BUS].base, 1223 sysbus_mmio_get_region(sysbus, 0)); 1224 } 1225 1226 static void virt_machine_done(Notifier *notifier, void *data) 1227 { 1228 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1229 machine_done); 1230 const MemMapEntry *memmap = virt_memmap; 1231 MachineState *machine = MACHINE(s); 1232 target_ulong start_addr = memmap[VIRT_DRAM].base; 1233 target_ulong firmware_end_addr, kernel_start_addr; 1234 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1235 uint32_t fdt_load_addr; 1236 uint64_t kernel_entry; 1237 1238 /* 1239 * Only direct boot kernel is currently supported for KVM VM, 1240 * so the "-bios" parameter is not supported when KVM is enabled. 1241 */ 1242 if (kvm_enabled()) { 1243 if (machine->firmware) { 1244 if (strcmp(machine->firmware, "none")) { 1245 error_report("Machine mode firmware is not supported in " 1246 "combination with KVM."); 1247 exit(1); 1248 } 1249 } else { 1250 machine->firmware = g_strdup("none"); 1251 } 1252 } 1253 1254 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1255 start_addr, NULL); 1256 1257 if (drive_get(IF_PFLASH, 0, 1)) { 1258 /* 1259 * S-mode FW like EDK2 will be kept in second plash (unit 1). 1260 * When both kernel, initrd and pflash options are provided in the 1261 * command line, the kernel and initrd will be copied to the fw_cfg 1262 * table and opensbi will jump to the flash address which is the 1263 * entry point of S-mode FW. It is the job of the S-mode FW to load 1264 * the kernel and initrd using fw_cfg table. 1265 * 1266 * If only pflash is given but not -kernel, then it is the job of 1267 * of the S-mode firmware to locate and load the kernel. 1268 * In either case, the next_addr for opensbi will be the flash address. 1269 */ 1270 riscv_setup_firmware_boot(machine); 1271 kernel_entry = virt_memmap[VIRT_FLASH].base + 1272 virt_memmap[VIRT_FLASH].size / 2; 1273 } else if (machine->kernel_filename) { 1274 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1275 firmware_end_addr); 1276 1277 kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); 1278 1279 if (machine->initrd_filename) { 1280 riscv_load_initrd(machine, kernel_entry); 1281 } 1282 1283 if (machine->kernel_cmdline && *machine->kernel_cmdline) { 1284 qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", 1285 machine->kernel_cmdline); 1286 } 1287 } else { 1288 /* 1289 * If dynamic firmware is used, it doesn't know where is the next mode 1290 * if kernel argument is not set. 1291 */ 1292 kernel_entry = 0; 1293 } 1294 1295 if (drive_get(IF_PFLASH, 0, 0)) { 1296 /* 1297 * Pflash was supplied, let's overwrite the address we jump to after 1298 * reset to the base of the flash. 1299 */ 1300 start_addr = virt_memmap[VIRT_FLASH].base; 1301 } 1302 1303 /* Compute the fdt load address in dram */ 1304 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 1305 machine->ram_size, machine->fdt); 1306 /* load the reset vector */ 1307 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1308 virt_memmap[VIRT_MROM].base, 1309 virt_memmap[VIRT_MROM].size, kernel_entry, 1310 fdt_load_addr); 1311 1312 /* 1313 * Only direct boot kernel is currently supported for KVM VM, 1314 * So here setup kernel start address and fdt address. 1315 * TODO:Support firmware loading and integrate to TCG start 1316 */ 1317 if (kvm_enabled()) { 1318 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1319 } 1320 } 1321 1322 static void virt_machine_init(MachineState *machine) 1323 { 1324 const MemMapEntry *memmap = virt_memmap; 1325 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1326 MemoryRegion *system_memory = get_system_memory(); 1327 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1328 char *soc_name; 1329 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1330 int i, base_hartid, hart_count; 1331 1332 /* Check socket count limit */ 1333 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 1334 error_report("number of sockets/nodes should be less than %d", 1335 VIRT_SOCKETS_MAX); 1336 exit(1); 1337 } 1338 1339 /* Initialize sockets */ 1340 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1341 for (i = 0; i < riscv_socket_count(machine); i++) { 1342 if (!riscv_socket_check_hartids(machine, i)) { 1343 error_report("discontinuous hartids in socket%d", i); 1344 exit(1); 1345 } 1346 1347 base_hartid = riscv_socket_first_hartid(machine, i); 1348 if (base_hartid < 0) { 1349 error_report("can't find hartid base for socket%d", i); 1350 exit(1); 1351 } 1352 1353 hart_count = riscv_socket_hart_count(machine, i); 1354 if (hart_count < 0) { 1355 error_report("can't find hart count for socket%d", i); 1356 exit(1); 1357 } 1358 1359 soc_name = g_strdup_printf("soc%d", i); 1360 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1361 TYPE_RISCV_HART_ARRAY); 1362 g_free(soc_name); 1363 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1364 machine->cpu_type, &error_abort); 1365 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1366 base_hartid, &error_abort); 1367 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1368 hart_count, &error_abort); 1369 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1370 1371 if (!kvm_enabled()) { 1372 if (s->have_aclint) { 1373 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1374 /* Per-socket ACLINT MTIMER */ 1375 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1376 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1377 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1378 base_hartid, hart_count, 1379 RISCV_ACLINT_DEFAULT_MTIMECMP, 1380 RISCV_ACLINT_DEFAULT_MTIME, 1381 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1382 } else { 1383 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1384 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1385 i * memmap[VIRT_CLINT].size, 1386 base_hartid, hart_count, false); 1387 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1388 i * memmap[VIRT_CLINT].size + 1389 RISCV_ACLINT_SWI_SIZE, 1390 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1391 base_hartid, hart_count, 1392 RISCV_ACLINT_DEFAULT_MTIMECMP, 1393 RISCV_ACLINT_DEFAULT_MTIME, 1394 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1395 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1396 i * memmap[VIRT_ACLINT_SSWI].size, 1397 base_hartid, hart_count, true); 1398 } 1399 } else { 1400 /* Per-socket SiFive CLINT */ 1401 riscv_aclint_swi_create( 1402 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1403 base_hartid, hart_count, false); 1404 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1405 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1406 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1407 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1408 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1409 } 1410 } 1411 1412 /* Per-socket interrupt controller */ 1413 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1414 s->irqchip[i] = virt_create_plic(memmap, i, 1415 base_hartid, hart_count); 1416 } else { 1417 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1418 memmap, i, base_hartid, 1419 hart_count); 1420 } 1421 1422 /* Try to use different IRQCHIP instance based device type */ 1423 if (i == 0) { 1424 mmio_irqchip = s->irqchip[i]; 1425 virtio_irqchip = s->irqchip[i]; 1426 pcie_irqchip = s->irqchip[i]; 1427 } 1428 if (i == 1) { 1429 virtio_irqchip = s->irqchip[i]; 1430 pcie_irqchip = s->irqchip[i]; 1431 } 1432 if (i == 2) { 1433 pcie_irqchip = s->irqchip[i]; 1434 } 1435 } 1436 1437 if (riscv_is_32bit(&s->soc[0])) { 1438 #if HOST_LONG_BITS == 64 1439 /* limit RAM size in a 32-bit system */ 1440 if (machine->ram_size > 10 * GiB) { 1441 machine->ram_size = 10 * GiB; 1442 error_report("Limiting RAM size to 10 GiB"); 1443 } 1444 #endif 1445 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1446 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1447 } else { 1448 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1449 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1450 virt_high_pcie_memmap.base = 1451 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1452 } 1453 1454 /* register system main memory (actual RAM) */ 1455 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1456 machine->ram); 1457 1458 /* boot rom */ 1459 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1460 memmap[VIRT_MROM].size, &error_fatal); 1461 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1462 mask_rom); 1463 1464 /* 1465 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1466 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1467 */ 1468 s->fw_cfg = create_fw_cfg(machine); 1469 rom_set_fw(s->fw_cfg); 1470 1471 /* SiFive Test MMIO device */ 1472 sifive_test_create(memmap[VIRT_TEST].base); 1473 1474 /* VirtIO MMIO devices */ 1475 for (i = 0; i < VIRTIO_COUNT; i++) { 1476 sysbus_create_simple("virtio-mmio", 1477 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1478 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); 1479 } 1480 1481 gpex_pcie_init(system_memory, 1482 memmap[VIRT_PCIE_ECAM].base, 1483 memmap[VIRT_PCIE_ECAM].size, 1484 memmap[VIRT_PCIE_MMIO].base, 1485 memmap[VIRT_PCIE_MMIO].size, 1486 virt_high_pcie_memmap.base, 1487 virt_high_pcie_memmap.size, 1488 memmap[VIRT_PCIE_PIO].base, 1489 DEVICE(pcie_irqchip)); 1490 1491 create_platform_bus(s, DEVICE(mmio_irqchip)); 1492 1493 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1494 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, 1495 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1496 1497 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1498 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); 1499 1500 virt_flash_create(s); 1501 1502 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1503 /* Map legacy -drive if=pflash to machine properties */ 1504 pflash_cfi01_legacy_drive(s->flash[i], 1505 drive_get(IF_PFLASH, 0, i)); 1506 } 1507 virt_flash_map(s, system_memory); 1508 1509 /* create device tree */ 1510 create_fdt(s, memmap); 1511 1512 s->machine_done.notify = virt_machine_done; 1513 qemu_add_machine_init_done_notifier(&s->machine_done); 1514 } 1515 1516 static void virt_machine_instance_init(Object *obj) 1517 { 1518 } 1519 1520 static char *virt_get_aia_guests(Object *obj, Error **errp) 1521 { 1522 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1523 char val[32]; 1524 1525 sprintf(val, "%d", s->aia_guests); 1526 return g_strdup(val); 1527 } 1528 1529 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1530 { 1531 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1532 1533 s->aia_guests = atoi(val); 1534 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1535 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1536 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1537 VIRT_IRQCHIP_MAX_GUESTS); 1538 } 1539 } 1540 1541 static char *virt_get_aia(Object *obj, Error **errp) 1542 { 1543 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1544 const char *val; 1545 1546 switch (s->aia_type) { 1547 case VIRT_AIA_TYPE_APLIC: 1548 val = "aplic"; 1549 break; 1550 case VIRT_AIA_TYPE_APLIC_IMSIC: 1551 val = "aplic-imsic"; 1552 break; 1553 default: 1554 val = "none"; 1555 break; 1556 }; 1557 1558 return g_strdup(val); 1559 } 1560 1561 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1562 { 1563 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1564 1565 if (!strcmp(val, "none")) { 1566 s->aia_type = VIRT_AIA_TYPE_NONE; 1567 } else if (!strcmp(val, "aplic")) { 1568 s->aia_type = VIRT_AIA_TYPE_APLIC; 1569 } else if (!strcmp(val, "aplic-imsic")) { 1570 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1571 } else { 1572 error_setg(errp, "Invalid AIA interrupt controller type"); 1573 error_append_hint(errp, "Valid values are none, aplic, and " 1574 "aplic-imsic.\n"); 1575 } 1576 } 1577 1578 static bool virt_get_aclint(Object *obj, Error **errp) 1579 { 1580 MachineState *ms = MACHINE(obj); 1581 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1582 1583 return s->have_aclint; 1584 } 1585 1586 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1587 { 1588 MachineState *ms = MACHINE(obj); 1589 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1590 1591 s->have_aclint = value; 1592 } 1593 1594 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1595 DeviceState *dev) 1596 { 1597 MachineClass *mc = MACHINE_GET_CLASS(machine); 1598 1599 if (device_is_dynamic_sysbus(mc, dev)) { 1600 return HOTPLUG_HANDLER(machine); 1601 } 1602 return NULL; 1603 } 1604 1605 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1606 DeviceState *dev, Error **errp) 1607 { 1608 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1609 1610 if (s->platform_bus_dev) { 1611 MachineClass *mc = MACHINE_GET_CLASS(s); 1612 1613 if (device_is_dynamic_sysbus(mc, dev)) { 1614 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1615 SYS_BUS_DEVICE(dev)); 1616 } 1617 } 1618 } 1619 1620 static void virt_machine_class_init(ObjectClass *oc, void *data) 1621 { 1622 char str[128]; 1623 MachineClass *mc = MACHINE_CLASS(oc); 1624 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1625 1626 mc->desc = "RISC-V VirtIO board"; 1627 mc->init = virt_machine_init; 1628 mc->max_cpus = VIRT_CPUS_MAX; 1629 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1630 mc->pci_allow_0_address = true; 1631 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1632 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1633 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1634 mc->numa_mem_supported = true; 1635 mc->default_ram_id = "riscv_virt_board.ram"; 1636 assert(!mc->get_hotplug_handler); 1637 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1638 1639 hc->plug = virt_machine_device_plug_cb; 1640 1641 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1642 #ifdef CONFIG_TPM 1643 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1644 #endif 1645 1646 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1647 virt_set_aclint); 1648 object_class_property_set_description(oc, "aclint", 1649 "Set on/off to enable/disable " 1650 "emulating ACLINT devices"); 1651 1652 object_class_property_add_str(oc, "aia", virt_get_aia, 1653 virt_set_aia); 1654 object_class_property_set_description(oc, "aia", 1655 "Set type of AIA interrupt " 1656 "conttoller. Valid values are " 1657 "none, aplic, and aplic-imsic."); 1658 1659 object_class_property_add_str(oc, "aia-guests", 1660 virt_get_aia_guests, 1661 virt_set_aia_guests); 1662 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1663 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1664 object_class_property_set_description(oc, "aia-guests", str); 1665 } 1666 1667 static const TypeInfo virt_machine_typeinfo = { 1668 .name = MACHINE_TYPE_NAME("virt"), 1669 .parent = TYPE_MACHINE, 1670 .class_init = virt_machine_class_init, 1671 .instance_init = virt_machine_instance_init, 1672 .instance_size = sizeof(RISCVVirtState), 1673 .interfaces = (InterfaceInfo[]) { 1674 { TYPE_HOTPLUG_HANDLER }, 1675 { } 1676 }, 1677 }; 1678 1679 static void virt_machine_init_register_types(void) 1680 { 1681 type_register_static(&virt_machine_typeinfo); 1682 } 1683 1684 type_init(virt_machine_init_register_types) 1685