xref: /openbmc/qemu/hw/riscv/virt.c (revision 332dab68785bba0381790fef94f4f433e8e806ea)
1  /*
2   * QEMU RISC-V VirtIO Board
3   *
4   * Copyright (c) 2017 SiFive, Inc.
5   *
6   * RISC-V machine with 16550a UART and VirtIO MMIO
7   *
8   * This program is free software; you can redistribute it and/or modify it
9   * under the terms and conditions of the GNU General Public License,
10   * version 2 or later, as published by the Free Software Foundation.
11   *
12   * This program is distributed in the hope it will be useful, but WITHOUT
13   * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14   * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15   * more details.
16   *
17   * You should have received a copy of the GNU General Public License along with
18   * this program.  If not, see <http://www.gnu.org/licenses/>.
19   */
20  
21  #include "qemu/osdep.h"
22  #include "qemu/units.h"
23  #include "qemu/error-report.h"
24  #include "qapi/error.h"
25  #include "hw/boards.h"
26  #include "hw/loader.h"
27  #include "hw/sysbus.h"
28  #include "hw/qdev-properties.h"
29  #include "hw/char/serial.h"
30  #include "target/riscv/cpu.h"
31  #include "hw/riscv/riscv_hart.h"
32  #include "hw/riscv/virt.h"
33  #include "hw/riscv/boot.h"
34  #include "hw/riscv/numa.h"
35  #include "hw/intc/riscv_aclint.h"
36  #include "hw/intc/sifive_plic.h"
37  #include "hw/misc/sifive_test.h"
38  #include "chardev/char.h"
39  #include "sysemu/device_tree.h"
40  #include "sysemu/sysemu.h"
41  #include "hw/pci/pci.h"
42  #include "hw/pci-host/gpex.h"
43  #include "hw/display/ramfb.h"
44  
45  static const MemMapEntry virt_memmap[] = {
46      [VIRT_DEBUG] =       {        0x0,         0x100 },
47      [VIRT_MROM] =        {     0x1000,        0xf000 },
48      [VIRT_TEST] =        {   0x100000,        0x1000 },
49      [VIRT_RTC] =         {   0x101000,        0x1000 },
50      [VIRT_CLINT] =       {  0x2000000,       0x10000 },
51      [VIRT_ACLINT_SSWI] = {  0x2F00000,        0x4000 },
52      [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
53      [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
54      [VIRT_UART0] =       { 0x10000000,         0x100 },
55      [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
56      [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
57      [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
58      [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
59      [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
60      [VIRT_DRAM] =        { 0x80000000,           0x0 },
61  };
62  
63  /* PCIe high mmio is fixed for RV32 */
64  #define VIRT32_HIGH_PCIE_MMIO_BASE  0x300000000ULL
65  #define VIRT32_HIGH_PCIE_MMIO_SIZE  (4 * GiB)
66  
67  /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
68  #define VIRT64_HIGH_PCIE_MMIO_SIZE  (16 * GiB)
69  
70  static MemMapEntry virt_high_pcie_memmap;
71  
72  #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
73  
74  static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
75                                         const char *name,
76                                         const char *alias_prop_name)
77  {
78      /*
79       * Create a single flash device.  We use the same parameters as
80       * the flash devices on the ARM virt board.
81       */
82      DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
83  
84      qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
85      qdev_prop_set_uint8(dev, "width", 4);
86      qdev_prop_set_uint8(dev, "device-width", 2);
87      qdev_prop_set_bit(dev, "big-endian", false);
88      qdev_prop_set_uint16(dev, "id0", 0x89);
89      qdev_prop_set_uint16(dev, "id1", 0x18);
90      qdev_prop_set_uint16(dev, "id2", 0x00);
91      qdev_prop_set_uint16(dev, "id3", 0x00);
92      qdev_prop_set_string(dev, "name", name);
93  
94      object_property_add_child(OBJECT(s), name, OBJECT(dev));
95      object_property_add_alias(OBJECT(s), alias_prop_name,
96                                OBJECT(dev), "drive");
97  
98      return PFLASH_CFI01(dev);
99  }
100  
101  static void virt_flash_create(RISCVVirtState *s)
102  {
103      s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
104      s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
105  }
106  
107  static void virt_flash_map1(PFlashCFI01 *flash,
108                              hwaddr base, hwaddr size,
109                              MemoryRegion *sysmem)
110  {
111      DeviceState *dev = DEVICE(flash);
112  
113      assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
114      assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
115      qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
116      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
117  
118      memory_region_add_subregion(sysmem, base,
119                                  sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
120                                                         0));
121  }
122  
123  static void virt_flash_map(RISCVVirtState *s,
124                             MemoryRegion *sysmem)
125  {
126      hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
127      hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
128  
129      virt_flash_map1(s->flash[0], flashbase, flashsize,
130                      sysmem);
131      virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
132                      sysmem);
133  }
134  
135  static void create_pcie_irq_map(void *fdt, char *nodename,
136                                  uint32_t plic_phandle)
137  {
138      int pin, dev;
139      uint32_t
140          full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
141      uint32_t *irq_map = full_irq_map;
142  
143      /* This code creates a standard swizzle of interrupts such that
144       * each device's first interrupt is based on it's PCI_SLOT number.
145       * (See pci_swizzle_map_irq_fn())
146       *
147       * We only need one entry per interrupt in the table (not one per
148       * possible slot) seeing the interrupt-map-mask will allow the table
149       * to wrap to any number of devices.
150       */
151      for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
152          int devfn = dev * 0x8;
153  
154          for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
155              int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
156              int i = 0;
157  
158              irq_map[i] = cpu_to_be32(devfn << 8);
159  
160              i += FDT_PCI_ADDR_CELLS;
161              irq_map[i] = cpu_to_be32(pin + 1);
162  
163              i += FDT_PCI_INT_CELLS;
164              irq_map[i++] = cpu_to_be32(plic_phandle);
165  
166              i += FDT_PLIC_ADDR_CELLS;
167              irq_map[i] = cpu_to_be32(irq_nr);
168  
169              irq_map += FDT_INT_MAP_WIDTH;
170          }
171      }
172  
173      qemu_fdt_setprop(fdt, nodename, "interrupt-map",
174                       full_irq_map, sizeof(full_irq_map));
175  
176      qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
177                             0x1800, 0, 0, 0x7);
178  }
179  
180  static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
181                                     char *clust_name, uint32_t *phandle,
182                                     bool is_32_bit, uint32_t *intc_phandles)
183  {
184      int cpu;
185      uint32_t cpu_phandle;
186      MachineState *mc = MACHINE(s);
187      char *name, *cpu_name, *core_name, *intc_name;
188  
189      for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
190          cpu_phandle = (*phandle)++;
191  
192          cpu_name = g_strdup_printf("/cpus/cpu@%d",
193              s->soc[socket].hartid_base + cpu);
194          qemu_fdt_add_subnode(mc->fdt, cpu_name);
195          qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
196              (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
197          name = riscv_isa_string(&s->soc[socket].harts[cpu]);
198          qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
199          g_free(name);
200          qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv");
201          qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay");
202          qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
203              s->soc[socket].hartid_base + cpu);
204          qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
205          riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket);
206          qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
207  
208          intc_phandles[cpu] = (*phandle)++;
209  
210          intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
211          qemu_fdt_add_subnode(mc->fdt, intc_name);
212          qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
213              intc_phandles[cpu]);
214          qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
215              "riscv,cpu-intc");
216          qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
217          qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
218  
219          core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
220          qemu_fdt_add_subnode(mc->fdt, core_name);
221          qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle);
222  
223          g_free(core_name);
224          g_free(intc_name);
225          g_free(cpu_name);
226      }
227  }
228  
229  static void create_fdt_socket_memory(RISCVVirtState *s,
230                                       const MemMapEntry *memmap, int socket)
231  {
232      char *mem_name;
233      uint64_t addr, size;
234      MachineState *mc = MACHINE(s);
235  
236      addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
237      size = riscv_socket_mem_size(mc, socket);
238      mem_name = g_strdup_printf("/memory@%lx", (long)addr);
239      qemu_fdt_add_subnode(mc->fdt, mem_name);
240      qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
241          addr >> 32, addr, size >> 32, size);
242      qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
243      riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket);
244      g_free(mem_name);
245  }
246  
247  static void create_fdt_socket_clint(RISCVVirtState *s,
248                                      const MemMapEntry *memmap, int socket,
249                                      uint32_t *intc_phandles)
250  {
251      int cpu;
252      char *clint_name;
253      uint32_t *clint_cells;
254      unsigned long clint_addr;
255      MachineState *mc = MACHINE(s);
256      static const char * const clint_compat[2] = {
257          "sifive,clint0", "riscv,clint0"
258      };
259  
260      clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
261  
262      for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
263          clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
264          clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
265          clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
266          clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
267      }
268  
269      clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
270      clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
271      qemu_fdt_add_subnode(mc->fdt, clint_name);
272      qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible",
273                                    (char **)&clint_compat,
274                                    ARRAY_SIZE(clint_compat));
275      qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg",
276          0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
277      qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
278          clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
279      riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket);
280      g_free(clint_name);
281  
282      g_free(clint_cells);
283  }
284  
285  static void create_fdt_socket_aclint(RISCVVirtState *s,
286                                       const MemMapEntry *memmap, int socket,
287                                       uint32_t *intc_phandles)
288  {
289      int cpu;
290      char *name;
291      unsigned long addr;
292      uint32_t aclint_cells_size;
293      uint32_t *aclint_mswi_cells;
294      uint32_t *aclint_sswi_cells;
295      uint32_t *aclint_mtimer_cells;
296      MachineState *mc = MACHINE(s);
297  
298      aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
299      aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
300      aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
301  
302      for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
303          aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
304          aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT);
305          aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
306          aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
307          aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
308          aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT);
309      }
310      aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
311  
312      addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
313      name = g_strdup_printf("/soc/mswi@%lx", addr);
314      qemu_fdt_add_subnode(mc->fdt, name);
315      qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-mswi");
316      qemu_fdt_setprop_cells(mc->fdt, name, "reg",
317          0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
318      qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
319          aclint_mswi_cells, aclint_cells_size);
320      qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
321      qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
322      riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
323      g_free(name);
324  
325      addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
326          (memmap[VIRT_CLINT].size * socket);
327      name = g_strdup_printf("/soc/mtimer@%lx", addr);
328      qemu_fdt_add_subnode(mc->fdt, name);
329      qemu_fdt_setprop_string(mc->fdt, name, "compatible",
330          "riscv,aclint-mtimer");
331      qemu_fdt_setprop_cells(mc->fdt, name, "reg",
332          0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
333          0x0, memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE -
334               RISCV_ACLINT_DEFAULT_MTIME,
335          0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
336          0x0, RISCV_ACLINT_DEFAULT_MTIME);
337      qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
338          aclint_mtimer_cells, aclint_cells_size);
339      riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
340      g_free(name);
341  
342      addr = memmap[VIRT_ACLINT_SSWI].base +
343          (memmap[VIRT_ACLINT_SSWI].size * socket);
344      name = g_strdup_printf("/soc/sswi@%lx", addr);
345      qemu_fdt_add_subnode(mc->fdt, name);
346      qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-sswi");
347      qemu_fdt_setprop_cells(mc->fdt, name, "reg",
348          0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
349      qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
350          aclint_sswi_cells, aclint_cells_size);
351      qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
352      qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
353      riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
354      g_free(name);
355  
356      g_free(aclint_mswi_cells);
357      g_free(aclint_mtimer_cells);
358      g_free(aclint_sswi_cells);
359  }
360  
361  static void create_fdt_socket_plic(RISCVVirtState *s,
362                                     const MemMapEntry *memmap, int socket,
363                                     uint32_t *phandle, uint32_t *intc_phandles,
364                                     uint32_t *plic_phandles)
365  {
366      int cpu;
367      char *plic_name;
368      uint32_t *plic_cells;
369      unsigned long plic_addr;
370      MachineState *mc = MACHINE(s);
371      static const char * const plic_compat[2] = {
372          "sifive,plic-1.0.0", "riscv,plic0"
373      };
374  
375      plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
376  
377      for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
378          plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
379          plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
380          plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
381          plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
382      }
383  
384      plic_phandles[socket] = (*phandle)++;
385      plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
386      plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
387      qemu_fdt_add_subnode(mc->fdt, plic_name);
388      qemu_fdt_setprop_cell(mc->fdt, plic_name,
389          "#address-cells", FDT_PLIC_ADDR_CELLS);
390      qemu_fdt_setprop_cell(mc->fdt, plic_name,
391          "#interrupt-cells", FDT_PLIC_INT_CELLS);
392      qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
393                                    (char **)&plic_compat,
394                                    ARRAY_SIZE(plic_compat));
395      qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0);
396      qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended",
397          plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
398      qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
399          0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
400      qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
401      riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
402      qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
403          plic_phandles[socket]);
404      g_free(plic_name);
405  
406      g_free(plic_cells);
407  }
408  
409  static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
410                                 bool is_32_bit, uint32_t *phandle,
411                                 uint32_t *irq_mmio_phandle,
412                                 uint32_t *irq_pcie_phandle,
413                                 uint32_t *irq_virtio_phandle)
414  {
415      int socket;
416      char *clust_name;
417      uint32_t *intc_phandles;
418      MachineState *mc = MACHINE(s);
419      uint32_t xplic_phandles[MAX_NODES];
420  
421      qemu_fdt_add_subnode(mc->fdt, "/cpus");
422      qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
423                            RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
424      qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0);
425      qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
426      qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
427  
428      for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
429          clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
430          qemu_fdt_add_subnode(mc->fdt, clust_name);
431  
432          intc_phandles = g_new0(uint32_t, s->soc[socket].num_harts);
433  
434          create_fdt_socket_cpus(s, socket, clust_name, phandle,
435              is_32_bit, intc_phandles);
436  
437          create_fdt_socket_memory(s, memmap, socket);
438  
439          if (s->have_aclint) {
440              create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
441          } else {
442              create_fdt_socket_clint(s, memmap, socket, intc_phandles);
443          }
444  
445          create_fdt_socket_plic(s, memmap, socket, phandle,
446              intc_phandles, xplic_phandles);
447  
448          g_free(intc_phandles);
449          g_free(clust_name);
450      }
451  
452      for (socket = 0; socket < riscv_socket_count(mc); socket++) {
453          if (socket == 0) {
454              *irq_mmio_phandle = xplic_phandles[socket];
455              *irq_virtio_phandle = xplic_phandles[socket];
456              *irq_pcie_phandle = xplic_phandles[socket];
457          }
458          if (socket == 1) {
459              *irq_virtio_phandle = xplic_phandles[socket];
460              *irq_pcie_phandle = xplic_phandles[socket];
461          }
462          if (socket == 2) {
463              *irq_pcie_phandle = xplic_phandles[socket];
464          }
465      }
466  
467      riscv_socket_fdt_write_distance_matrix(mc, mc->fdt);
468  }
469  
470  static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
471                                uint32_t irq_virtio_phandle)
472  {
473      int i;
474      char *name;
475      MachineState *mc = MACHINE(s);
476  
477      for (i = 0; i < VIRTIO_COUNT; i++) {
478          name = g_strdup_printf("/soc/virtio_mmio@%lx",
479              (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
480          qemu_fdt_add_subnode(mc->fdt, name);
481          qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio");
482          qemu_fdt_setprop_cells(mc->fdt, name, "reg",
483              0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
484              0x0, memmap[VIRT_VIRTIO].size);
485          qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
486              irq_virtio_phandle);
487          qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", VIRTIO_IRQ + i);
488          g_free(name);
489      }
490  }
491  
492  static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
493                              uint32_t irq_pcie_phandle)
494  {
495      char *name;
496      MachineState *mc = MACHINE(s);
497  
498      name = g_strdup_printf("/soc/pci@%lx",
499          (long) memmap[VIRT_PCIE_ECAM].base);
500      qemu_fdt_add_subnode(mc->fdt, name);
501      qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells",
502          FDT_PCI_ADDR_CELLS);
503      qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells",
504          FDT_PCI_INT_CELLS);
505      qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2);
506      qemu_fdt_setprop_string(mc->fdt, name, "compatible",
507          "pci-host-ecam-generic");
508      qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci");
509      qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0);
510      qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
511          memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
512      qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
513      qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
514          memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
515      qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
516          1, FDT_PCI_RANGE_IOPORT, 2, 0,
517          2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
518          1, FDT_PCI_RANGE_MMIO,
519          2, memmap[VIRT_PCIE_MMIO].base,
520          2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
521          1, FDT_PCI_RANGE_MMIO_64BIT,
522          2, virt_high_pcie_memmap.base,
523          2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
524  
525      create_pcie_irq_map(mc->fdt, name, irq_pcie_phandle);
526      g_free(name);
527  }
528  
529  static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap,
530                               uint32_t *phandle)
531  {
532      char *name;
533      uint32_t test_phandle;
534      MachineState *mc = MACHINE(s);
535  
536      test_phandle = (*phandle)++;
537      name = g_strdup_printf("/soc/test@%lx",
538          (long)memmap[VIRT_TEST].base);
539      qemu_fdt_add_subnode(mc->fdt, name);
540      {
541          static const char * const compat[3] = {
542              "sifive,test1", "sifive,test0", "syscon"
543          };
544          qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
545                                        (char **)&compat, ARRAY_SIZE(compat));
546      }
547      qemu_fdt_setprop_cells(mc->fdt, name, "reg",
548          0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
549      qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle);
550      test_phandle = qemu_fdt_get_phandle(mc->fdt, name);
551      g_free(name);
552  
553      name = g_strdup_printf("/soc/reboot");
554      qemu_fdt_add_subnode(mc->fdt, name);
555      qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot");
556      qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
557      qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
558      qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET);
559      g_free(name);
560  
561      name = g_strdup_printf("/soc/poweroff");
562      qemu_fdt_add_subnode(mc->fdt, name);
563      qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff");
564      qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
565      qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
566      qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS);
567      g_free(name);
568  }
569  
570  static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
571                              uint32_t irq_mmio_phandle)
572  {
573      char *name;
574      MachineState *mc = MACHINE(s);
575  
576      name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
577      qemu_fdt_add_subnode(mc->fdt, name);
578      qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
579      qemu_fdt_setprop_cells(mc->fdt, name, "reg",
580          0x0, memmap[VIRT_UART0].base,
581          0x0, memmap[VIRT_UART0].size);
582      qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
583      qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
584      qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
585  
586      qemu_fdt_add_subnode(mc->fdt, "/chosen");
587      qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
588      g_free(name);
589  }
590  
591  static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
592                             uint32_t irq_mmio_phandle)
593  {
594      char *name;
595      MachineState *mc = MACHINE(s);
596  
597      name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
598      qemu_fdt_add_subnode(mc->fdt, name);
599      qemu_fdt_setprop_string(mc->fdt, name, "compatible",
600          "google,goldfish-rtc");
601      qemu_fdt_setprop_cells(mc->fdt, name, "reg",
602          0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
603      qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
604          irq_mmio_phandle);
605      qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
606      g_free(name);
607  }
608  
609  static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
610  {
611      char *name;
612      MachineState *mc = MACHINE(s);
613      hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
614      hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
615  
616      name = g_strdup_printf("/flash@%" PRIx64, flashbase);
617      qemu_fdt_add_subnode(mc->fdt, name);
618      qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
619      qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
620                                   2, flashbase, 2, flashsize,
621                                   2, flashbase + flashsize, 2, flashsize);
622      qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
623      g_free(name);
624  }
625  
626  static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
627                         uint64_t mem_size, const char *cmdline, bool is_32_bit)
628  {
629      MachineState *mc = MACHINE(s);
630      uint32_t phandle = 1, irq_mmio_phandle = 1;
631      uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
632  
633      if (mc->dtb) {
634          mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
635          if (!mc->fdt) {
636              error_report("load_device_tree() failed");
637              exit(1);
638          }
639          goto update_bootargs;
640      } else {
641          mc->fdt = create_device_tree(&s->fdt_size);
642          if (!mc->fdt) {
643              error_report("create_device_tree() failed");
644              exit(1);
645          }
646      }
647  
648      qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu");
649      qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio");
650      qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2);
651      qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2);
652  
653      qemu_fdt_add_subnode(mc->fdt, "/soc");
654      qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0);
655      qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus");
656      qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
657      qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
658  
659      create_fdt_sockets(s, memmap, is_32_bit, &phandle,
660          &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle);
661  
662      create_fdt_virtio(s, memmap, irq_virtio_phandle);
663  
664      create_fdt_pcie(s, memmap, irq_pcie_phandle);
665  
666      create_fdt_reset(s, memmap, &phandle);
667  
668      create_fdt_uart(s, memmap, irq_mmio_phandle);
669  
670      create_fdt_rtc(s, memmap, irq_mmio_phandle);
671  
672      create_fdt_flash(s, memmap);
673  
674  update_bootargs:
675      if (cmdline) {
676          qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
677      }
678  }
679  
680  static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
681                                            hwaddr ecam_base, hwaddr ecam_size,
682                                            hwaddr mmio_base, hwaddr mmio_size,
683                                            hwaddr high_mmio_base,
684                                            hwaddr high_mmio_size,
685                                            hwaddr pio_base,
686                                            DeviceState *plic)
687  {
688      DeviceState *dev;
689      MemoryRegion *ecam_alias, *ecam_reg;
690      MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
691      qemu_irq irq;
692      int i;
693  
694      dev = qdev_new(TYPE_GPEX_HOST);
695  
696      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
697  
698      ecam_alias = g_new0(MemoryRegion, 1);
699      ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
700      memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
701                               ecam_reg, 0, ecam_size);
702      memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
703  
704      mmio_alias = g_new0(MemoryRegion, 1);
705      mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
706      memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
707                               mmio_reg, mmio_base, mmio_size);
708      memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
709  
710      /* Map high MMIO space */
711      high_mmio_alias = g_new0(MemoryRegion, 1);
712      memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
713                               mmio_reg, high_mmio_base, high_mmio_size);
714      memory_region_add_subregion(get_system_memory(), high_mmio_base,
715                                  high_mmio_alias);
716  
717      sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
718  
719      for (i = 0; i < GPEX_NUM_IRQS; i++) {
720          irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
721  
722          sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
723          gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
724      }
725  
726      return dev;
727  }
728  
729  static FWCfgState *create_fw_cfg(const MachineState *mc)
730  {
731      hwaddr base = virt_memmap[VIRT_FW_CFG].base;
732      hwaddr size = virt_memmap[VIRT_FW_CFG].size;
733      FWCfgState *fw_cfg;
734      char *nodename;
735  
736      fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
737                                    &address_space_memory);
738      fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
739  
740      nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
741      qemu_fdt_add_subnode(mc->fdt, nodename);
742      qemu_fdt_setprop_string(mc->fdt, nodename,
743                              "compatible", "qemu,fw-cfg-mmio");
744      qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
745                                   2, base, 2, size);
746      qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
747      g_free(nodename);
748      return fw_cfg;
749  }
750  
751  static void virt_machine_init(MachineState *machine)
752  {
753      const MemMapEntry *memmap = virt_memmap;
754      RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
755      MemoryRegion *system_memory = get_system_memory();
756      MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
757      char *plic_hart_config, *soc_name;
758      target_ulong start_addr = memmap[VIRT_DRAM].base;
759      target_ulong firmware_end_addr, kernel_start_addr;
760      uint32_t fdt_load_addr;
761      uint64_t kernel_entry;
762      DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
763      int i, base_hartid, hart_count;
764  
765      /* Check socket count limit */
766      if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
767          error_report("number of sockets/nodes should be less than %d",
768              VIRT_SOCKETS_MAX);
769          exit(1);
770      }
771  
772      /* Initialize sockets */
773      mmio_plic = virtio_plic = pcie_plic = NULL;
774      for (i = 0; i < riscv_socket_count(machine); i++) {
775          if (!riscv_socket_check_hartids(machine, i)) {
776              error_report("discontinuous hartids in socket%d", i);
777              exit(1);
778          }
779  
780          base_hartid = riscv_socket_first_hartid(machine, i);
781          if (base_hartid < 0) {
782              error_report("can't find hartid base for socket%d", i);
783              exit(1);
784          }
785  
786          hart_count = riscv_socket_hart_count(machine, i);
787          if (hart_count < 0) {
788              error_report("can't find hart count for socket%d", i);
789              exit(1);
790          }
791  
792          soc_name = g_strdup_printf("soc%d", i);
793          object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
794                                  TYPE_RISCV_HART_ARRAY);
795          g_free(soc_name);
796          object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
797                                  machine->cpu_type, &error_abort);
798          object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
799                                  base_hartid, &error_abort);
800          object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
801                                  hart_count, &error_abort);
802          sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
803  
804          /* Per-socket CLINT */
805          riscv_aclint_swi_create(
806              memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
807              base_hartid, hart_count, false);
808          riscv_aclint_mtimer_create(
809              memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
810                  RISCV_ACLINT_SWI_SIZE,
811              RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
812              RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
813              RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
814  
815          /* Per-socket ACLINT SSWI */
816          if (s->have_aclint) {
817              riscv_aclint_swi_create(
818                  memmap[VIRT_ACLINT_SSWI].base +
819                      i * memmap[VIRT_ACLINT_SSWI].size,
820                  base_hartid, hart_count, true);
821          }
822  
823          /* Per-socket PLIC hart topology configuration string */
824          plic_hart_config = riscv_plic_hart_config_string(hart_count);
825  
826          /* Per-socket PLIC */
827          s->plic[i] = sifive_plic_create(
828              memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
829              plic_hart_config, hart_count, base_hartid,
830              VIRT_PLIC_NUM_SOURCES,
831              VIRT_PLIC_NUM_PRIORITIES,
832              VIRT_PLIC_PRIORITY_BASE,
833              VIRT_PLIC_PENDING_BASE,
834              VIRT_PLIC_ENABLE_BASE,
835              VIRT_PLIC_ENABLE_STRIDE,
836              VIRT_PLIC_CONTEXT_BASE,
837              VIRT_PLIC_CONTEXT_STRIDE,
838              memmap[VIRT_PLIC].size);
839          g_free(plic_hart_config);
840  
841          /* Try to use different PLIC instance based device type */
842          if (i == 0) {
843              mmio_plic = s->plic[i];
844              virtio_plic = s->plic[i];
845              pcie_plic = s->plic[i];
846          }
847          if (i == 1) {
848              virtio_plic = s->plic[i];
849              pcie_plic = s->plic[i];
850          }
851          if (i == 2) {
852              pcie_plic = s->plic[i];
853          }
854      }
855  
856      if (riscv_is_32bit(&s->soc[0])) {
857  #if HOST_LONG_BITS == 64
858          /* limit RAM size in a 32-bit system */
859          if (machine->ram_size > 10 * GiB) {
860              machine->ram_size = 10 * GiB;
861              error_report("Limiting RAM size to 10 GiB");
862          }
863  #endif
864          virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
865          virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
866      } else {
867          virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
868          virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
869          virt_high_pcie_memmap.base =
870              ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
871      }
872  
873      /* register system main memory (actual RAM) */
874      memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
875          machine->ram);
876  
877      /* create device tree */
878      create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
879                 riscv_is_32bit(&s->soc[0]));
880  
881      /* boot rom */
882      memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
883                             memmap[VIRT_MROM].size, &error_fatal);
884      memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
885                                  mask_rom);
886  
887      if (riscv_is_32bit(&s->soc[0])) {
888          firmware_end_addr = riscv_find_and_load_firmware(machine,
889                                      RISCV32_BIOS_BIN, start_addr, NULL);
890      } else {
891          firmware_end_addr = riscv_find_and_load_firmware(machine,
892                                      RISCV64_BIOS_BIN, start_addr, NULL);
893      }
894  
895      if (machine->kernel_filename) {
896          kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
897                                                           firmware_end_addr);
898  
899          kernel_entry = riscv_load_kernel(machine->kernel_filename,
900                                           kernel_start_addr, NULL);
901  
902          if (machine->initrd_filename) {
903              hwaddr start;
904              hwaddr end = riscv_load_initrd(machine->initrd_filename,
905                                             machine->ram_size, kernel_entry,
906                                             &start);
907              qemu_fdt_setprop_cell(machine->fdt, "/chosen",
908                                    "linux,initrd-start", start);
909              qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
910                                    end);
911          }
912      } else {
913         /*
914          * If dynamic firmware is used, it doesn't know where is the next mode
915          * if kernel argument is not set.
916          */
917          kernel_entry = 0;
918      }
919  
920      if (drive_get(IF_PFLASH, 0, 0)) {
921          /*
922           * Pflash was supplied, let's overwrite the address we jump to after
923           * reset to the base of the flash.
924           */
925          start_addr = virt_memmap[VIRT_FLASH].base;
926      }
927  
928      /*
929       * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
930       * tree cannot be altered and we get FDT_ERR_NOSPACE.
931       */
932      s->fw_cfg = create_fw_cfg(machine);
933      rom_set_fw(s->fw_cfg);
934  
935      /* Compute the fdt load address in dram */
936      fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
937                                     machine->ram_size, machine->fdt);
938      /* load the reset vector */
939      riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
940                                virt_memmap[VIRT_MROM].base,
941                                virt_memmap[VIRT_MROM].size, kernel_entry,
942                                fdt_load_addr, machine->fdt);
943  
944      /* SiFive Test MMIO device */
945      sifive_test_create(memmap[VIRT_TEST].base);
946  
947      /* VirtIO MMIO devices */
948      for (i = 0; i < VIRTIO_COUNT; i++) {
949          sysbus_create_simple("virtio-mmio",
950              memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
951              qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
952      }
953  
954      gpex_pcie_init(system_memory,
955                     memmap[VIRT_PCIE_ECAM].base,
956                     memmap[VIRT_PCIE_ECAM].size,
957                     memmap[VIRT_PCIE_MMIO].base,
958                     memmap[VIRT_PCIE_MMIO].size,
959                     virt_high_pcie_memmap.base,
960                     virt_high_pcie_memmap.size,
961                     memmap[VIRT_PCIE_PIO].base,
962                     DEVICE(pcie_plic));
963  
964      serial_mm_init(system_memory, memmap[VIRT_UART0].base,
965          0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
966          serial_hd(0), DEVICE_LITTLE_ENDIAN);
967  
968      sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
969          qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
970  
971      virt_flash_create(s);
972  
973      for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
974          /* Map legacy -drive if=pflash to machine properties */
975          pflash_cfi01_legacy_drive(s->flash[i],
976                                    drive_get(IF_PFLASH, 0, i));
977      }
978      virt_flash_map(s, system_memory);
979  }
980  
981  static void virt_machine_instance_init(Object *obj)
982  {
983  }
984  
985  static bool virt_get_aclint(Object *obj, Error **errp)
986  {
987      MachineState *ms = MACHINE(obj);
988      RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
989  
990      return s->have_aclint;
991  }
992  
993  static void virt_set_aclint(Object *obj, bool value, Error **errp)
994  {
995      MachineState *ms = MACHINE(obj);
996      RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
997  
998      s->have_aclint = value;
999  }
1000  
1001  static void virt_machine_class_init(ObjectClass *oc, void *data)
1002  {
1003      MachineClass *mc = MACHINE_CLASS(oc);
1004  
1005      mc->desc = "RISC-V VirtIO board";
1006      mc->init = virt_machine_init;
1007      mc->max_cpus = VIRT_CPUS_MAX;
1008      mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
1009      mc->pci_allow_0_address = true;
1010      mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
1011      mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
1012      mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
1013      mc->numa_mem_supported = true;
1014      mc->default_ram_id = "riscv_virt_board.ram";
1015  
1016      machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1017  
1018      object_class_property_add_bool(oc, "aclint", virt_get_aclint,
1019                                     virt_set_aclint);
1020      object_class_property_set_description(oc, "aclint",
1021                                            "Set on/off to enable/disable "
1022                                            "emulating ACLINT devices");
1023  }
1024  
1025  static const TypeInfo virt_machine_typeinfo = {
1026      .name       = MACHINE_TYPE_NAME("virt"),
1027      .parent     = TYPE_MACHINE,
1028      .class_init = virt_machine_class_init,
1029      .instance_init = virt_machine_instance_init,
1030      .instance_size = sizeof(RISCVVirtState),
1031  };
1032  
1033  static void virt_machine_init_register_types(void)
1034  {
1035      type_register_static(&virt_machine_typeinfo);
1036  }
1037  
1038  type_init(virt_machine_init_register_types)
1039