1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/log.h" 24 #include "qemu/error-report.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/riscv/riscv_hart.h" 33 #include "hw/riscv/virt.h" 34 #include "hw/riscv/boot.h" 35 #include "hw/riscv/numa.h" 36 #include "hw/intc/sifive_clint.h" 37 #include "hw/intc/sifive_plic.h" 38 #include "hw/misc/sifive_test.h" 39 #include "chardev/char.h" 40 #include "sysemu/arch_init.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/sysemu.h" 43 #include "hw/pci/pci.h" 44 #include "hw/pci-host/gpex.h" 45 46 #if defined(TARGET_RISCV32) 47 # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" 48 #else 49 # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" 50 #endif 51 52 static const struct MemmapEntry { 53 hwaddr base; 54 hwaddr size; 55 } virt_memmap[] = { 56 [VIRT_DEBUG] = { 0x0, 0x100 }, 57 [VIRT_MROM] = { 0x1000, 0xf000 }, 58 [VIRT_TEST] = { 0x100000, 0x1000 }, 59 [VIRT_RTC] = { 0x101000, 0x1000 }, 60 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 61 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 62 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 63 [VIRT_UART0] = { 0x10000000, 0x100 }, 64 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 65 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 66 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 67 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 68 [VIRT_DRAM] = { 0x80000000, 0x0 }, 69 }; 70 71 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 72 73 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 74 const char *name, 75 const char *alias_prop_name) 76 { 77 /* 78 * Create a single flash device. We use the same parameters as 79 * the flash devices on the ARM virt board. 80 */ 81 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 82 83 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 84 qdev_prop_set_uint8(dev, "width", 4); 85 qdev_prop_set_uint8(dev, "device-width", 2); 86 qdev_prop_set_bit(dev, "big-endian", false); 87 qdev_prop_set_uint16(dev, "id0", 0x89); 88 qdev_prop_set_uint16(dev, "id1", 0x18); 89 qdev_prop_set_uint16(dev, "id2", 0x00); 90 qdev_prop_set_uint16(dev, "id3", 0x00); 91 qdev_prop_set_string(dev, "name", name); 92 93 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 94 object_property_add_alias(OBJECT(s), alias_prop_name, 95 OBJECT(dev), "drive"); 96 97 return PFLASH_CFI01(dev); 98 } 99 100 static void virt_flash_create(RISCVVirtState *s) 101 { 102 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 103 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 104 } 105 106 static void virt_flash_map1(PFlashCFI01 *flash, 107 hwaddr base, hwaddr size, 108 MemoryRegion *sysmem) 109 { 110 DeviceState *dev = DEVICE(flash); 111 112 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 113 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 114 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 115 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 116 117 memory_region_add_subregion(sysmem, base, 118 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 119 0)); 120 } 121 122 static void virt_flash_map(RISCVVirtState *s, 123 MemoryRegion *sysmem) 124 { 125 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 126 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 127 128 virt_flash_map1(s->flash[0], flashbase, flashsize, 129 sysmem); 130 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 131 sysmem); 132 } 133 134 static void create_pcie_irq_map(void *fdt, char *nodename, 135 uint32_t plic_phandle) 136 { 137 int pin, dev; 138 uint32_t 139 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; 140 uint32_t *irq_map = full_irq_map; 141 142 /* This code creates a standard swizzle of interrupts such that 143 * each device's first interrupt is based on it's PCI_SLOT number. 144 * (See pci_swizzle_map_irq_fn()) 145 * 146 * We only need one entry per interrupt in the table (not one per 147 * possible slot) seeing the interrupt-map-mask will allow the table 148 * to wrap to any number of devices. 149 */ 150 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 151 int devfn = dev * 0x8; 152 153 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 154 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 155 int i = 0; 156 157 irq_map[i] = cpu_to_be32(devfn << 8); 158 159 i += FDT_PCI_ADDR_CELLS; 160 irq_map[i] = cpu_to_be32(pin + 1); 161 162 i += FDT_PCI_INT_CELLS; 163 irq_map[i++] = cpu_to_be32(plic_phandle); 164 165 i += FDT_PLIC_ADDR_CELLS; 166 irq_map[i] = cpu_to_be32(irq_nr); 167 168 irq_map += FDT_INT_MAP_WIDTH; 169 } 170 } 171 172 qemu_fdt_setprop(fdt, nodename, "interrupt-map", 173 full_irq_map, sizeof(full_irq_map)); 174 175 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 176 0x1800, 0, 0, 0x7); 177 } 178 179 static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, 180 uint64_t mem_size, const char *cmdline) 181 { 182 void *fdt; 183 int i, cpu, socket; 184 const char *dtb_filename; 185 MachineState *mc = MACHINE(s); 186 uint64_t addr, size; 187 uint32_t *clint_cells, *plic_cells; 188 unsigned long clint_addr, plic_addr; 189 uint32_t plic_phandle[MAX_NODES]; 190 uint32_t cpu_phandle, intc_phandle, test_phandle; 191 uint32_t phandle = 1, plic_mmio_phandle = 1; 192 uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; 193 char *mem_name, *cpu_name, *core_name, *intc_name; 194 char *name, *clint_name, *plic_name, *clust_name; 195 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 196 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 197 198 dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 199 if (dtb_filename) { 200 fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size); 201 if (!fdt) { 202 error_report("load_device_tree() failed"); 203 exit(1); 204 } 205 goto update_bootargs; 206 } else { 207 fdt = s->fdt = create_device_tree(&s->fdt_size); 208 if (!fdt) { 209 error_report("create_device_tree() failed"); 210 exit(1); 211 } 212 } 213 214 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); 215 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); 216 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 217 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 218 219 qemu_fdt_add_subnode(fdt, "/soc"); 220 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 221 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 222 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 223 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 224 225 qemu_fdt_add_subnode(fdt, "/cpus"); 226 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 227 SIFIVE_CLINT_TIMEBASE_FREQ); 228 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 229 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 230 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 231 232 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 233 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 234 qemu_fdt_add_subnode(fdt, clust_name); 235 236 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 237 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 238 239 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 240 cpu_phandle = phandle++; 241 242 cpu_name = g_strdup_printf("/cpus/cpu@%d", 243 s->soc[socket].hartid_base + cpu); 244 qemu_fdt_add_subnode(fdt, cpu_name); 245 #if defined(TARGET_RISCV32) 246 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 247 #else 248 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 249 #endif 250 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 251 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 252 g_free(name); 253 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 254 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 255 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 256 s->soc[socket].hartid_base + cpu); 257 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 258 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 259 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 260 261 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 262 qemu_fdt_add_subnode(fdt, intc_name); 263 intc_phandle = phandle++; 264 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 265 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 266 "riscv,cpu-intc"); 267 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 268 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 269 270 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 271 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 272 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 273 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 274 275 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 276 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 277 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 278 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 279 280 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 281 qemu_fdt_add_subnode(fdt, core_name); 282 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 283 284 g_free(core_name); 285 g_free(intc_name); 286 g_free(cpu_name); 287 } 288 289 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 290 size = riscv_socket_mem_size(mc, socket); 291 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 292 qemu_fdt_add_subnode(fdt, mem_name); 293 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 294 addr >> 32, addr, size >> 32, size); 295 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 296 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 297 g_free(mem_name); 298 299 clint_addr = memmap[VIRT_CLINT].base + 300 (memmap[VIRT_CLINT].size * socket); 301 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 302 qemu_fdt_add_subnode(fdt, clint_name); 303 qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); 304 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 305 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 306 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 307 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 308 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 309 g_free(clint_name); 310 311 plic_phandle[socket] = phandle++; 312 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 313 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 314 qemu_fdt_add_subnode(fdt, plic_name); 315 qemu_fdt_setprop_cell(fdt, plic_name, 316 "#address-cells", FDT_PLIC_ADDR_CELLS); 317 qemu_fdt_setprop_cell(fdt, plic_name, 318 "#interrupt-cells", FDT_PLIC_INT_CELLS); 319 qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); 320 qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); 321 qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", 322 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 323 qemu_fdt_setprop_cells(fdt, plic_name, "reg", 324 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 325 qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 326 riscv_socket_fdt_write_id(mc, fdt, plic_name, socket); 327 qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]); 328 g_free(plic_name); 329 330 g_free(clint_cells); 331 g_free(plic_cells); 332 g_free(clust_name); 333 } 334 335 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 336 if (socket == 0) { 337 plic_mmio_phandle = plic_phandle[socket]; 338 plic_virtio_phandle = plic_phandle[socket]; 339 plic_pcie_phandle = plic_phandle[socket]; 340 } 341 if (socket == 1) { 342 plic_virtio_phandle = plic_phandle[socket]; 343 plic_pcie_phandle = plic_phandle[socket]; 344 } 345 if (socket == 2) { 346 plic_pcie_phandle = plic_phandle[socket]; 347 } 348 } 349 350 riscv_socket_fdt_write_distance_matrix(mc, fdt); 351 352 for (i = 0; i < VIRTIO_COUNT; i++) { 353 name = g_strdup_printf("/soc/virtio_mmio@%lx", 354 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 355 qemu_fdt_add_subnode(fdt, name); 356 qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); 357 qemu_fdt_setprop_cells(fdt, name, "reg", 358 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 359 0x0, memmap[VIRT_VIRTIO].size); 360 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", 361 plic_virtio_phandle); 362 qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); 363 g_free(name); 364 } 365 366 name = g_strdup_printf("/soc/pci@%lx", 367 (long) memmap[VIRT_PCIE_ECAM].base); 368 qemu_fdt_add_subnode(fdt, name); 369 qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); 370 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); 371 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); 372 qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); 373 qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); 374 qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); 375 qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, 376 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 377 qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); 378 qemu_fdt_setprop_cells(fdt, name, "reg", 0, 379 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 380 qemu_fdt_setprop_sized_cells(fdt, name, "ranges", 381 1, FDT_PCI_RANGE_IOPORT, 2, 0, 382 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 383 1, FDT_PCI_RANGE_MMIO, 384 2, memmap[VIRT_PCIE_MMIO].base, 385 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); 386 create_pcie_irq_map(fdt, name, plic_pcie_phandle); 387 g_free(name); 388 389 test_phandle = phandle++; 390 name = g_strdup_printf("/soc/test@%lx", 391 (long)memmap[VIRT_TEST].base); 392 qemu_fdt_add_subnode(fdt, name); 393 { 394 const char compat[] = "sifive,test1\0sifive,test0\0syscon"; 395 qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat)); 396 } 397 qemu_fdt_setprop_cells(fdt, name, "reg", 398 0x0, memmap[VIRT_TEST].base, 399 0x0, memmap[VIRT_TEST].size); 400 qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); 401 test_phandle = qemu_fdt_get_phandle(fdt, name); 402 g_free(name); 403 404 name = g_strdup_printf("/soc/reboot"); 405 qemu_fdt_add_subnode(fdt, name); 406 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); 407 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 408 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 409 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); 410 g_free(name); 411 412 name = g_strdup_printf("/soc/poweroff"); 413 qemu_fdt_add_subnode(fdt, name); 414 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); 415 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 416 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 417 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); 418 g_free(name); 419 420 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 421 qemu_fdt_add_subnode(fdt, name); 422 qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); 423 qemu_fdt_setprop_cells(fdt, name, "reg", 424 0x0, memmap[VIRT_UART0].base, 425 0x0, memmap[VIRT_UART0].size); 426 qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); 427 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 428 qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); 429 430 qemu_fdt_add_subnode(fdt, "/chosen"); 431 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); 432 g_free(name); 433 434 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 435 qemu_fdt_add_subnode(fdt, name); 436 qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); 437 qemu_fdt_setprop_cells(fdt, name, "reg", 438 0x0, memmap[VIRT_RTC].base, 439 0x0, memmap[VIRT_RTC].size); 440 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 441 qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); 442 g_free(name); 443 444 name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); 445 qemu_fdt_add_subnode(s->fdt, name); 446 qemu_fdt_setprop_string(s->fdt, name, "compatible", "cfi-flash"); 447 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 448 2, flashbase, 2, flashsize, 449 2, flashbase + flashsize, 2, flashsize); 450 qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4); 451 g_free(name); 452 453 update_bootargs: 454 if (cmdline) { 455 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 456 } 457 } 458 459 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 460 hwaddr ecam_base, hwaddr ecam_size, 461 hwaddr mmio_base, hwaddr mmio_size, 462 hwaddr pio_base, 463 DeviceState *plic, bool link_up) 464 { 465 DeviceState *dev; 466 MemoryRegion *ecam_alias, *ecam_reg; 467 MemoryRegion *mmio_alias, *mmio_reg; 468 qemu_irq irq; 469 int i; 470 471 dev = qdev_new(TYPE_GPEX_HOST); 472 473 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 474 475 ecam_alias = g_new0(MemoryRegion, 1); 476 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 477 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 478 ecam_reg, 0, ecam_size); 479 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 480 481 mmio_alias = g_new0(MemoryRegion, 1); 482 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 483 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 484 mmio_reg, mmio_base, mmio_size); 485 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 486 487 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 488 489 for (i = 0; i < GPEX_NUM_IRQS; i++) { 490 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); 491 492 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 493 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 494 } 495 496 return dev; 497 } 498 499 static void virt_machine_init(MachineState *machine) 500 { 501 const struct MemmapEntry *memmap = virt_memmap; 502 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 503 MemoryRegion *system_memory = get_system_memory(); 504 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 505 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 506 char *plic_hart_config, *soc_name; 507 size_t plic_hart_config_len; 508 target_ulong start_addr = memmap[VIRT_DRAM].base; 509 target_ulong firmware_end_addr, kernel_start_addr; 510 uint32_t fdt_load_addr; 511 uint64_t kernel_entry; 512 DeviceState *mmio_plic, *virtio_plic, *pcie_plic; 513 int i, j, base_hartid, hart_count; 514 515 /* Check socket count limit */ 516 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 517 error_report("number of sockets/nodes should be less than %d", 518 VIRT_SOCKETS_MAX); 519 exit(1); 520 } 521 522 /* Initialize sockets */ 523 mmio_plic = virtio_plic = pcie_plic = NULL; 524 for (i = 0; i < riscv_socket_count(machine); i++) { 525 if (!riscv_socket_check_hartids(machine, i)) { 526 error_report("discontinuous hartids in socket%d", i); 527 exit(1); 528 } 529 530 base_hartid = riscv_socket_first_hartid(machine, i); 531 if (base_hartid < 0) { 532 error_report("can't find hartid base for socket%d", i); 533 exit(1); 534 } 535 536 hart_count = riscv_socket_hart_count(machine, i); 537 if (hart_count < 0) { 538 error_report("can't find hart count for socket%d", i); 539 exit(1); 540 } 541 542 soc_name = g_strdup_printf("soc%d", i); 543 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 544 TYPE_RISCV_HART_ARRAY); 545 g_free(soc_name); 546 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 547 machine->cpu_type, &error_abort); 548 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 549 base_hartid, &error_abort); 550 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 551 hart_count, &error_abort); 552 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 553 554 /* Per-socket CLINT */ 555 sifive_clint_create( 556 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 557 memmap[VIRT_CLINT].size, base_hartid, hart_count, 558 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 559 SIFIVE_CLINT_TIMEBASE_FREQ, true); 560 561 /* Per-socket PLIC hart topology configuration string */ 562 plic_hart_config_len = 563 (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count; 564 plic_hart_config = g_malloc0(plic_hart_config_len); 565 for (j = 0; j < hart_count; j++) { 566 if (j != 0) { 567 strncat(plic_hart_config, ",", plic_hart_config_len); 568 } 569 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, 570 plic_hart_config_len); 571 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); 572 } 573 574 /* Per-socket PLIC */ 575 s->plic[i] = sifive_plic_create( 576 memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, 577 plic_hart_config, base_hartid, 578 VIRT_PLIC_NUM_SOURCES, 579 VIRT_PLIC_NUM_PRIORITIES, 580 VIRT_PLIC_PRIORITY_BASE, 581 VIRT_PLIC_PENDING_BASE, 582 VIRT_PLIC_ENABLE_BASE, 583 VIRT_PLIC_ENABLE_STRIDE, 584 VIRT_PLIC_CONTEXT_BASE, 585 VIRT_PLIC_CONTEXT_STRIDE, 586 memmap[VIRT_PLIC].size); 587 g_free(plic_hart_config); 588 589 /* Try to use different PLIC instance based device type */ 590 if (i == 0) { 591 mmio_plic = s->plic[i]; 592 virtio_plic = s->plic[i]; 593 pcie_plic = s->plic[i]; 594 } 595 if (i == 1) { 596 virtio_plic = s->plic[i]; 597 pcie_plic = s->plic[i]; 598 } 599 if (i == 2) { 600 pcie_plic = s->plic[i]; 601 } 602 } 603 604 /* register system main memory (actual RAM) */ 605 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", 606 machine->ram_size, &error_fatal); 607 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 608 main_mem); 609 610 /* create device tree */ 611 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 612 613 /* boot rom */ 614 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 615 memmap[VIRT_MROM].size, &error_fatal); 616 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 617 mask_rom); 618 619 firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, 620 start_addr, NULL); 621 622 if (machine->kernel_filename) { 623 kernel_start_addr = riscv_calc_kernel_start_addr(machine, 624 firmware_end_addr); 625 626 kernel_entry = riscv_load_kernel(machine->kernel_filename, 627 kernel_start_addr, NULL); 628 629 if (machine->initrd_filename) { 630 hwaddr start; 631 hwaddr end = riscv_load_initrd(machine->initrd_filename, 632 machine->ram_size, kernel_entry, 633 &start); 634 qemu_fdt_setprop_cell(s->fdt, "/chosen", 635 "linux,initrd-start", start); 636 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 637 end); 638 } 639 } else { 640 /* 641 * If dynamic firmware is used, it doesn't know where is the next mode 642 * if kernel argument is not set. 643 */ 644 kernel_entry = 0; 645 } 646 647 if (drive_get(IF_PFLASH, 0, 0)) { 648 /* 649 * Pflash was supplied, let's overwrite the address we jump to after 650 * reset to the base of the flash. 651 */ 652 start_addr = virt_memmap[VIRT_FLASH].base; 653 } 654 655 /* Compute the fdt load address in dram */ 656 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 657 machine->ram_size, s->fdt); 658 /* load the reset vector */ 659 riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, 660 virt_memmap[VIRT_MROM].size, kernel_entry, 661 fdt_load_addr, s->fdt); 662 663 /* SiFive Test MMIO device */ 664 sifive_test_create(memmap[VIRT_TEST].base); 665 666 /* VirtIO MMIO devices */ 667 for (i = 0; i < VIRTIO_COUNT; i++) { 668 sysbus_create_simple("virtio-mmio", 669 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 670 qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); 671 } 672 673 gpex_pcie_init(system_memory, 674 memmap[VIRT_PCIE_ECAM].base, 675 memmap[VIRT_PCIE_ECAM].size, 676 memmap[VIRT_PCIE_MMIO].base, 677 memmap[VIRT_PCIE_MMIO].size, 678 memmap[VIRT_PCIE_PIO].base, 679 DEVICE(pcie_plic), true); 680 681 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 682 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, 683 serial_hd(0), DEVICE_LITTLE_ENDIAN); 684 685 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 686 qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); 687 688 virt_flash_create(s); 689 690 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 691 /* Map legacy -drive if=pflash to machine properties */ 692 pflash_cfi01_legacy_drive(s->flash[i], 693 drive_get(IF_PFLASH, 0, i)); 694 } 695 virt_flash_map(s, system_memory); 696 } 697 698 static void virt_machine_instance_init(Object *obj) 699 { 700 } 701 702 static void virt_machine_class_init(ObjectClass *oc, void *data) 703 { 704 MachineClass *mc = MACHINE_CLASS(oc); 705 706 mc->desc = "RISC-V VirtIO board"; 707 mc->init = virt_machine_init; 708 mc->max_cpus = VIRT_CPUS_MAX; 709 mc->default_cpu_type = VIRT_CPU; 710 mc->pci_allow_0_address = true; 711 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 712 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 713 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 714 mc->numa_mem_supported = true; 715 } 716 717 static const TypeInfo virt_machine_typeinfo = { 718 .name = MACHINE_TYPE_NAME("virt"), 719 .parent = TYPE_MACHINE, 720 .class_init = virt_machine_class_init, 721 .instance_init = virt_machine_instance_init, 722 .instance_size = sizeof(RISCVVirtState), 723 }; 724 725 static void virt_machine_init_register_types(void) 726 { 727 type_register_static(&virt_machine_typeinfo); 728 } 729 730 type_init(virt_machine_init_register_types) 731