1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "kvm/kvm_riscv.h" 39 #include "hw/intc/riscv_aclint.h" 40 #include "hw/intc/riscv_aplic.h" 41 #include "hw/intc/sifive_plic.h" 42 #include "hw/misc/sifive_test.h" 43 #include "hw/platform-bus.h" 44 #include "chardev/char.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/tcg.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/tpm.h" 50 #include "hw/pci/pci.h" 51 #include "hw/pci-host/gpex.h" 52 #include "hw/display/ramfb.h" 53 #include "hw/acpi/aml-build.h" 54 #include "qapi/qapi-visit-common.h" 55 56 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ 57 static bool virt_use_kvm_aia(RISCVVirtState *s) 58 { 59 return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 60 } 61 62 static const MemMapEntry virt_memmap[] = { 63 [VIRT_DEBUG] = { 0x0, 0x100 }, 64 [VIRT_MROM] = { 0x1000, 0xf000 }, 65 [VIRT_TEST] = { 0x100000, 0x1000 }, 66 [VIRT_RTC] = { 0x101000, 0x1000 }, 67 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 68 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 69 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 70 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 71 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 72 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 73 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 74 [VIRT_UART0] = { 0x10000000, 0x100 }, 75 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 76 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 77 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 78 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 79 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 80 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 81 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 82 [VIRT_DRAM] = { 0x80000000, 0x0 }, 83 }; 84 85 /* PCIe high mmio is fixed for RV32 */ 86 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 87 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 88 89 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 90 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 91 92 static MemMapEntry virt_high_pcie_memmap; 93 94 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 95 96 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 97 const char *name, 98 const char *alias_prop_name) 99 { 100 /* 101 * Create a single flash device. We use the same parameters as 102 * the flash devices on the ARM virt board. 103 */ 104 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 105 106 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 107 qdev_prop_set_uint8(dev, "width", 4); 108 qdev_prop_set_uint8(dev, "device-width", 2); 109 qdev_prop_set_bit(dev, "big-endian", false); 110 qdev_prop_set_uint16(dev, "id0", 0x89); 111 qdev_prop_set_uint16(dev, "id1", 0x18); 112 qdev_prop_set_uint16(dev, "id2", 0x00); 113 qdev_prop_set_uint16(dev, "id3", 0x00); 114 qdev_prop_set_string(dev, "name", name); 115 116 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 117 object_property_add_alias(OBJECT(s), alias_prop_name, 118 OBJECT(dev), "drive"); 119 120 return PFLASH_CFI01(dev); 121 } 122 123 static void virt_flash_create(RISCVVirtState *s) 124 { 125 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 126 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 127 } 128 129 static void virt_flash_map1(PFlashCFI01 *flash, 130 hwaddr base, hwaddr size, 131 MemoryRegion *sysmem) 132 { 133 DeviceState *dev = DEVICE(flash); 134 135 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 136 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 137 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 138 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 139 140 memory_region_add_subregion(sysmem, base, 141 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 142 0)); 143 } 144 145 static void virt_flash_map(RISCVVirtState *s, 146 MemoryRegion *sysmem) 147 { 148 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 149 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 150 151 virt_flash_map1(s->flash[0], flashbase, flashsize, 152 sysmem); 153 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 154 sysmem); 155 } 156 157 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 158 uint32_t irqchip_phandle) 159 { 160 int pin, dev; 161 uint32_t irq_map_stride = 0; 162 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 163 FDT_MAX_INT_MAP_WIDTH] = {}; 164 uint32_t *irq_map = full_irq_map; 165 166 /* This code creates a standard swizzle of interrupts such that 167 * each device's first interrupt is based on it's PCI_SLOT number. 168 * (See pci_swizzle_map_irq_fn()) 169 * 170 * We only need one entry per interrupt in the table (not one per 171 * possible slot) seeing the interrupt-map-mask will allow the table 172 * to wrap to any number of devices. 173 */ 174 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 175 int devfn = dev * 0x8; 176 177 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 178 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 179 int i = 0; 180 181 /* Fill PCI address cells */ 182 irq_map[i] = cpu_to_be32(devfn << 8); 183 i += FDT_PCI_ADDR_CELLS; 184 185 /* Fill PCI Interrupt cells */ 186 irq_map[i] = cpu_to_be32(pin + 1); 187 i += FDT_PCI_INT_CELLS; 188 189 /* Fill interrupt controller phandle and cells */ 190 irq_map[i++] = cpu_to_be32(irqchip_phandle); 191 irq_map[i++] = cpu_to_be32(irq_nr); 192 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 193 irq_map[i++] = cpu_to_be32(0x4); 194 } 195 196 if (!irq_map_stride) { 197 irq_map_stride = i; 198 } 199 irq_map += irq_map_stride; 200 } 201 } 202 203 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 204 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 205 irq_map_stride * sizeof(uint32_t)); 206 207 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 208 0x1800, 0, 0, 0x7); 209 } 210 211 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 212 char *clust_name, uint32_t *phandle, 213 uint32_t *intc_phandles) 214 { 215 int cpu; 216 uint32_t cpu_phandle; 217 MachineState *ms = MACHINE(s); 218 bool is_32_bit = riscv_is_32bit(&s->soc[0]); 219 uint8_t satp_mode_max; 220 221 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 222 RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; 223 g_autofree char *cpu_name = NULL; 224 g_autofree char *core_name = NULL; 225 g_autofree char *intc_name = NULL; 226 g_autofree char *sv_name = NULL; 227 228 cpu_phandle = (*phandle)++; 229 230 cpu_name = g_strdup_printf("/cpus/cpu@%d", 231 s->soc[socket].hartid_base + cpu); 232 qemu_fdt_add_subnode(ms->fdt, cpu_name); 233 234 if (cpu_ptr->cfg.satp_mode.supported != 0) { 235 satp_mode_max = satp_mode_max_from_map(cpu_ptr->cfg.satp_mode.map); 236 sv_name = g_strdup_printf("riscv,%s", 237 satp_mode_str(satp_mode_max, is_32_bit)); 238 qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); 239 } 240 241 riscv_isa_write_fdt(cpu_ptr, ms->fdt, cpu_name); 242 243 if (cpu_ptr->cfg.ext_zicbom) { 244 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size", 245 cpu_ptr->cfg.cbom_blocksize); 246 } 247 248 if (cpu_ptr->cfg.ext_zicboz) { 249 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size", 250 cpu_ptr->cfg.cboz_blocksize); 251 } 252 253 if (cpu_ptr->cfg.ext_zicbop) { 254 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-size", 255 cpu_ptr->cfg.cbop_blocksize); 256 } 257 258 qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); 259 qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); 260 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", 261 s->soc[socket].hartid_base + cpu); 262 qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); 263 riscv_socket_fdt_write_id(ms, cpu_name, socket); 264 qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); 265 266 intc_phandles[cpu] = (*phandle)++; 267 268 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 269 qemu_fdt_add_subnode(ms->fdt, intc_name); 270 qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", 271 intc_phandles[cpu]); 272 qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", 273 "riscv,cpu-intc"); 274 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); 275 qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); 276 277 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 278 qemu_fdt_add_subnode(ms->fdt, core_name); 279 qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); 280 } 281 } 282 283 static void create_fdt_socket_memory(RISCVVirtState *s, 284 const MemMapEntry *memmap, int socket) 285 { 286 g_autofree char *mem_name = NULL; 287 uint64_t addr, size; 288 MachineState *ms = MACHINE(s); 289 290 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); 291 size = riscv_socket_mem_size(ms, socket); 292 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 293 qemu_fdt_add_subnode(ms->fdt, mem_name); 294 qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", 295 addr >> 32, addr, size >> 32, size); 296 qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); 297 riscv_socket_fdt_write_id(ms, mem_name, socket); 298 } 299 300 static void create_fdt_socket_clint(RISCVVirtState *s, 301 const MemMapEntry *memmap, int socket, 302 uint32_t *intc_phandles) 303 { 304 int cpu; 305 g_autofree char *clint_name = NULL; 306 g_autofree uint32_t *clint_cells = NULL; 307 unsigned long clint_addr; 308 MachineState *ms = MACHINE(s); 309 static const char * const clint_compat[2] = { 310 "sifive,clint0", "riscv,clint0" 311 }; 312 313 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 314 315 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 316 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 317 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 318 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 319 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 320 } 321 322 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 323 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 324 qemu_fdt_add_subnode(ms->fdt, clint_name); 325 qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", 326 (char **)&clint_compat, 327 ARRAY_SIZE(clint_compat)); 328 qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 329 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 330 qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", 331 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 332 riscv_socket_fdt_write_id(ms, clint_name, socket); 333 } 334 335 static void create_fdt_socket_aclint(RISCVVirtState *s, 336 const MemMapEntry *memmap, int socket, 337 uint32_t *intc_phandles) 338 { 339 int cpu; 340 char *name; 341 unsigned long addr, size; 342 uint32_t aclint_cells_size; 343 g_autofree uint32_t *aclint_mswi_cells = NULL; 344 g_autofree uint32_t *aclint_sswi_cells = NULL; 345 g_autofree uint32_t *aclint_mtimer_cells = NULL; 346 MachineState *ms = MACHINE(s); 347 348 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 349 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 350 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 351 352 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 353 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 354 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 355 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 356 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 357 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 358 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 359 } 360 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 361 362 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 363 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 364 name = g_strdup_printf("/soc/mswi@%lx", addr); 365 qemu_fdt_add_subnode(ms->fdt, name); 366 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 367 "riscv,aclint-mswi"); 368 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 369 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 370 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 371 aclint_mswi_cells, aclint_cells_size); 372 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 373 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 374 riscv_socket_fdt_write_id(ms, name, socket); 375 g_free(name); 376 } 377 378 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 379 addr = memmap[VIRT_CLINT].base + 380 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 381 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 382 } else { 383 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 384 (memmap[VIRT_CLINT].size * socket); 385 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 386 } 387 name = g_strdup_printf("/soc/mtimer@%lx", addr); 388 qemu_fdt_add_subnode(ms->fdt, name); 389 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 390 "riscv,aclint-mtimer"); 391 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 392 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 393 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 394 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 395 0x0, RISCV_ACLINT_DEFAULT_MTIME); 396 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 397 aclint_mtimer_cells, aclint_cells_size); 398 riscv_socket_fdt_write_id(ms, name, socket); 399 g_free(name); 400 401 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 402 addr = memmap[VIRT_ACLINT_SSWI].base + 403 (memmap[VIRT_ACLINT_SSWI].size * socket); 404 name = g_strdup_printf("/soc/sswi@%lx", addr); 405 qemu_fdt_add_subnode(ms->fdt, name); 406 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 407 "riscv,aclint-sswi"); 408 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 409 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 410 qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", 411 aclint_sswi_cells, aclint_cells_size); 412 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); 413 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); 414 riscv_socket_fdt_write_id(ms, name, socket); 415 g_free(name); 416 } 417 } 418 419 static void create_fdt_socket_plic(RISCVVirtState *s, 420 const MemMapEntry *memmap, int socket, 421 uint32_t *phandle, uint32_t *intc_phandles, 422 uint32_t *plic_phandles) 423 { 424 int cpu; 425 g_autofree char *plic_name = NULL; 426 g_autofree uint32_t *plic_cells; 427 unsigned long plic_addr; 428 MachineState *ms = MACHINE(s); 429 static const char * const plic_compat[2] = { 430 "sifive,plic-1.0.0", "riscv,plic0" 431 }; 432 433 plic_phandles[socket] = (*phandle)++; 434 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 435 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 436 qemu_fdt_add_subnode(ms->fdt, plic_name); 437 qemu_fdt_setprop_cell(ms->fdt, plic_name, 438 "#interrupt-cells", FDT_PLIC_INT_CELLS); 439 qemu_fdt_setprop_cell(ms->fdt, plic_name, 440 "#address-cells", FDT_PLIC_ADDR_CELLS); 441 qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", 442 (char **)&plic_compat, 443 ARRAY_SIZE(plic_compat)); 444 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); 445 446 if (kvm_enabled()) { 447 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 448 449 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 450 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 451 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 452 } 453 454 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 455 plic_cells, 456 s->soc[socket].num_harts * sizeof(uint32_t) * 2); 457 } else { 458 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 459 460 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 461 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 462 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 463 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 464 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 465 } 466 467 qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", 468 plic_cells, 469 s->soc[socket].num_harts * sizeof(uint32_t) * 4); 470 } 471 472 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 473 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 474 qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", 475 VIRT_IRQCHIP_NUM_SOURCES - 1); 476 riscv_socket_fdt_write_id(ms, plic_name, socket); 477 qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", 478 plic_phandles[socket]); 479 480 if (!socket) { 481 platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, 482 memmap[VIRT_PLATFORM_BUS].base, 483 memmap[VIRT_PLATFORM_BUS].size, 484 VIRT_PLATFORM_BUS_IRQ); 485 } 486 } 487 488 uint32_t imsic_num_bits(uint32_t count) 489 { 490 uint32_t ret = 0; 491 492 while (BIT(ret) < count) { 493 ret++; 494 } 495 496 return ret; 497 } 498 499 static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, 500 uint32_t *intc_phandles, uint32_t msi_phandle, 501 bool m_mode, uint32_t imsic_guest_bits) 502 { 503 int cpu, socket; 504 g_autofree char *imsic_name = NULL; 505 MachineState *ms = MACHINE(s); 506 int socket_count = riscv_socket_count(ms); 507 uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; 508 g_autofree uint32_t *imsic_cells = NULL; 509 g_autofree uint32_t *imsic_regs = NULL; 510 511 imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); 512 imsic_regs = g_new0(uint32_t, socket_count * 4); 513 514 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 515 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 516 imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 517 } 518 519 imsic_max_hart_per_socket = 0; 520 for (socket = 0; socket < socket_count; socket++) { 521 imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 522 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 523 s->soc[socket].num_harts; 524 imsic_regs[socket * 4 + 0] = 0; 525 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 526 imsic_regs[socket * 4 + 2] = 0; 527 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 528 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 529 imsic_max_hart_per_socket = s->soc[socket].num_harts; 530 } 531 } 532 533 imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr); 534 qemu_fdt_add_subnode(ms->fdt, imsic_name); 535 qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); 536 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", 537 FDT_IMSIC_INT_CELLS); 538 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); 539 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); 540 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", 541 imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); 542 qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, 543 socket_count * sizeof(uint32_t) * 4); 544 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", 545 VIRT_IRQCHIP_NUM_MSIS); 546 547 if (imsic_guest_bits) { 548 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", 549 imsic_guest_bits); 550 } 551 552 if (socket_count > 1) { 553 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", 554 imsic_num_bits(imsic_max_hart_per_socket)); 555 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", 556 imsic_num_bits(socket_count)); 557 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", 558 IMSIC_MMIO_GROUP_MIN_SHIFT); 559 } 560 qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); 561 } 562 563 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 564 uint32_t *phandle, uint32_t *intc_phandles, 565 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 566 { 567 *msi_m_phandle = (*phandle)++; 568 *msi_s_phandle = (*phandle)++; 569 570 if (!kvm_enabled()) { 571 /* M-level IMSIC node */ 572 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, 573 *msi_m_phandle, true, 0); 574 } 575 576 /* S-level IMSIC node */ 577 create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, 578 *msi_s_phandle, false, 579 imsic_num_bits(s->aia_guests + 1)); 580 581 } 582 583 static void create_fdt_one_aplic(RISCVVirtState *s, int socket, 584 unsigned long aplic_addr, uint32_t aplic_size, 585 uint32_t msi_phandle, 586 uint32_t *intc_phandles, 587 uint32_t aplic_phandle, 588 uint32_t aplic_child_phandle, 589 bool m_mode, int num_harts) 590 { 591 int cpu; 592 g_autofree char *aplic_name = NULL; 593 g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); 594 MachineState *ms = MACHINE(s); 595 596 for (cpu = 0; cpu < num_harts; cpu++) { 597 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 598 aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); 599 } 600 601 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 602 qemu_fdt_add_subnode(ms->fdt, aplic_name); 603 qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); 604 qemu_fdt_setprop_cell(ms->fdt, aplic_name, 605 "#interrupt-cells", FDT_APLIC_INT_CELLS); 606 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); 607 608 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 609 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", 610 aplic_cells, num_harts * sizeof(uint32_t) * 2); 611 } else { 612 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); 613 } 614 615 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 616 0x0, aplic_addr, 0x0, aplic_size); 617 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", 618 VIRT_IRQCHIP_NUM_SOURCES); 619 620 if (aplic_child_phandle) { 621 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", 622 aplic_child_phandle); 623 qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", 624 aplic_child_phandle, 0x1, 625 VIRT_IRQCHIP_NUM_SOURCES); 626 } 627 628 riscv_socket_fdt_write_id(ms, aplic_name, socket); 629 qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); 630 } 631 632 static void create_fdt_socket_aplic(RISCVVirtState *s, 633 const MemMapEntry *memmap, int socket, 634 uint32_t msi_m_phandle, 635 uint32_t msi_s_phandle, 636 uint32_t *phandle, 637 uint32_t *intc_phandles, 638 uint32_t *aplic_phandles, 639 int num_harts) 640 { 641 g_autofree char *aplic_name = NULL; 642 unsigned long aplic_addr; 643 MachineState *ms = MACHINE(s); 644 uint32_t aplic_m_phandle, aplic_s_phandle; 645 646 aplic_m_phandle = (*phandle)++; 647 aplic_s_phandle = (*phandle)++; 648 649 if (!kvm_enabled()) { 650 /* M-level APLIC node */ 651 aplic_addr = memmap[VIRT_APLIC_M].base + 652 (memmap[VIRT_APLIC_M].size * socket); 653 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, 654 msi_m_phandle, intc_phandles, 655 aplic_m_phandle, aplic_s_phandle, 656 true, num_harts); 657 } 658 659 /* S-level APLIC node */ 660 aplic_addr = memmap[VIRT_APLIC_S].base + 661 (memmap[VIRT_APLIC_S].size * socket); 662 create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, 663 msi_s_phandle, intc_phandles, 664 aplic_s_phandle, 0, 665 false, num_harts); 666 667 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 668 669 if (!socket) { 670 platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, 671 memmap[VIRT_PLATFORM_BUS].base, 672 memmap[VIRT_PLATFORM_BUS].size, 673 VIRT_PLATFORM_BUS_IRQ); 674 } 675 676 aplic_phandles[socket] = aplic_s_phandle; 677 } 678 679 static void create_fdt_pmu(RISCVVirtState *s) 680 { 681 g_autofree char *pmu_name = g_strdup_printf("/pmu"); 682 MachineState *ms = MACHINE(s); 683 RISCVCPU hart = s->soc[0].harts[0]; 684 685 qemu_fdt_add_subnode(ms->fdt, pmu_name); 686 qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); 687 riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); 688 } 689 690 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 691 uint32_t *phandle, 692 uint32_t *irq_mmio_phandle, 693 uint32_t *irq_pcie_phandle, 694 uint32_t *irq_virtio_phandle, 695 uint32_t *msi_pcie_phandle) 696 { 697 int socket, phandle_pos; 698 MachineState *ms = MACHINE(s); 699 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 700 uint32_t xplic_phandles[MAX_NODES]; 701 g_autofree uint32_t *intc_phandles = NULL; 702 int socket_count = riscv_socket_count(ms); 703 704 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 705 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", 706 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 707 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 708 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 709 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 710 711 intc_phandles = g_new0(uint32_t, ms->smp.cpus); 712 713 phandle_pos = ms->smp.cpus; 714 for (socket = (socket_count - 1); socket >= 0; socket--) { 715 g_autofree char *clust_name = NULL; 716 phandle_pos -= s->soc[socket].num_harts; 717 718 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 719 qemu_fdt_add_subnode(ms->fdt, clust_name); 720 721 create_fdt_socket_cpus(s, socket, clust_name, phandle, 722 &intc_phandles[phandle_pos]); 723 724 create_fdt_socket_memory(s, memmap, socket); 725 726 if (tcg_enabled()) { 727 if (s->have_aclint) { 728 create_fdt_socket_aclint(s, memmap, socket, 729 &intc_phandles[phandle_pos]); 730 } else { 731 create_fdt_socket_clint(s, memmap, socket, 732 &intc_phandles[phandle_pos]); 733 } 734 } 735 } 736 737 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 738 create_fdt_imsic(s, memmap, phandle, intc_phandles, 739 &msi_m_phandle, &msi_s_phandle); 740 *msi_pcie_phandle = msi_s_phandle; 741 } 742 743 /* KVM AIA only has one APLIC instance */ 744 if (kvm_enabled() && virt_use_kvm_aia(s)) { 745 create_fdt_socket_aplic(s, memmap, 0, 746 msi_m_phandle, msi_s_phandle, phandle, 747 &intc_phandles[0], xplic_phandles, 748 ms->smp.cpus); 749 } else { 750 phandle_pos = ms->smp.cpus; 751 for (socket = (socket_count - 1); socket >= 0; socket--) { 752 phandle_pos -= s->soc[socket].num_harts; 753 754 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 755 create_fdt_socket_plic(s, memmap, socket, phandle, 756 &intc_phandles[phandle_pos], 757 xplic_phandles); 758 } else { 759 create_fdt_socket_aplic(s, memmap, socket, 760 msi_m_phandle, msi_s_phandle, phandle, 761 &intc_phandles[phandle_pos], 762 xplic_phandles, 763 s->soc[socket].num_harts); 764 } 765 } 766 } 767 768 if (kvm_enabled() && virt_use_kvm_aia(s)) { 769 *irq_mmio_phandle = xplic_phandles[0]; 770 *irq_virtio_phandle = xplic_phandles[0]; 771 *irq_pcie_phandle = xplic_phandles[0]; 772 } else { 773 for (socket = 0; socket < socket_count; socket++) { 774 if (socket == 0) { 775 *irq_mmio_phandle = xplic_phandles[socket]; 776 *irq_virtio_phandle = xplic_phandles[socket]; 777 *irq_pcie_phandle = xplic_phandles[socket]; 778 } 779 if (socket == 1) { 780 *irq_virtio_phandle = xplic_phandles[socket]; 781 *irq_pcie_phandle = xplic_phandles[socket]; 782 } 783 if (socket == 2) { 784 *irq_pcie_phandle = xplic_phandles[socket]; 785 } 786 } 787 } 788 789 riscv_socket_fdt_write_distance_matrix(ms); 790 } 791 792 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 793 uint32_t irq_virtio_phandle) 794 { 795 int i; 796 MachineState *ms = MACHINE(s); 797 798 for (i = 0; i < VIRTIO_COUNT; i++) { 799 g_autofree char *name = g_strdup_printf("/soc/virtio_mmio@%lx", 800 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 801 802 qemu_fdt_add_subnode(ms->fdt, name); 803 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); 804 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 805 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 806 0x0, memmap[VIRT_VIRTIO].size); 807 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 808 irq_virtio_phandle); 809 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 810 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", 811 VIRTIO_IRQ + i); 812 } else { 813 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", 814 VIRTIO_IRQ + i, 0x4); 815 } 816 } 817 } 818 819 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 820 uint32_t irq_pcie_phandle, 821 uint32_t msi_pcie_phandle) 822 { 823 g_autofree char *name = NULL; 824 MachineState *ms = MACHINE(s); 825 826 name = g_strdup_printf("/soc/pci@%lx", 827 (long) memmap[VIRT_PCIE_ECAM].base); 828 qemu_fdt_add_subnode(ms->fdt, name); 829 qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", 830 FDT_PCI_ADDR_CELLS); 831 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 832 FDT_PCI_INT_CELLS); 833 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); 834 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 835 "pci-host-ecam-generic"); 836 qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); 837 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); 838 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, 839 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 840 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); 841 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 842 qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); 843 } 844 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, 845 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 846 qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 847 1, FDT_PCI_RANGE_IOPORT, 2, 0, 848 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 849 1, FDT_PCI_RANGE_MMIO, 850 2, memmap[VIRT_PCIE_MMIO].base, 851 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 852 1, FDT_PCI_RANGE_MMIO_64BIT, 853 2, virt_high_pcie_memmap.base, 854 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 855 856 create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); 857 } 858 859 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 860 uint32_t *phandle) 861 { 862 char *name; 863 uint32_t test_phandle; 864 MachineState *ms = MACHINE(s); 865 866 test_phandle = (*phandle)++; 867 name = g_strdup_printf("/soc/test@%lx", 868 (long)memmap[VIRT_TEST].base); 869 qemu_fdt_add_subnode(ms->fdt, name); 870 { 871 static const char * const compat[3] = { 872 "sifive,test1", "sifive,test0", "syscon" 873 }; 874 qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", 875 (char **)&compat, ARRAY_SIZE(compat)); 876 } 877 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 878 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 879 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); 880 test_phandle = qemu_fdt_get_phandle(ms->fdt, name); 881 g_free(name); 882 883 name = g_strdup_printf("/reboot"); 884 qemu_fdt_add_subnode(ms->fdt, name); 885 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); 886 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 887 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 888 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); 889 g_free(name); 890 891 name = g_strdup_printf("/poweroff"); 892 qemu_fdt_add_subnode(ms->fdt, name); 893 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); 894 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); 895 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); 896 qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); 897 g_free(name); 898 } 899 900 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 901 uint32_t irq_mmio_phandle) 902 { 903 g_autofree char *name = NULL; 904 MachineState *ms = MACHINE(s); 905 906 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 907 qemu_fdt_add_subnode(ms->fdt, name); 908 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); 909 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 910 0x0, memmap[VIRT_UART0].base, 911 0x0, memmap[VIRT_UART0].size); 912 qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); 913 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); 914 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 915 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); 916 } else { 917 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); 918 } 919 920 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); 921 } 922 923 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 924 uint32_t irq_mmio_phandle) 925 { 926 g_autofree char *name = NULL; 927 MachineState *ms = MACHINE(s); 928 929 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 930 qemu_fdt_add_subnode(ms->fdt, name); 931 qemu_fdt_setprop_string(ms->fdt, name, "compatible", 932 "google,goldfish-rtc"); 933 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 934 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 935 qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", 936 irq_mmio_phandle); 937 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 938 qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); 939 } else { 940 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); 941 } 942 } 943 944 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 945 { 946 MachineState *ms = MACHINE(s); 947 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 948 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 949 g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); 950 951 qemu_fdt_add_subnode(ms->fdt, name); 952 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); 953 qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 954 2, flashbase, 2, flashsize, 955 2, flashbase + flashsize, 2, flashsize); 956 qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); 957 } 958 959 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 960 { 961 MachineState *ms = MACHINE(s); 962 hwaddr base = memmap[VIRT_FW_CFG].base; 963 hwaddr size = memmap[VIRT_FW_CFG].size; 964 g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 965 966 qemu_fdt_add_subnode(ms->fdt, nodename); 967 qemu_fdt_setprop_string(ms->fdt, nodename, 968 "compatible", "qemu,fw-cfg-mmio"); 969 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 970 2, base, 2, size); 971 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 972 } 973 974 static void finalize_fdt(RISCVVirtState *s) 975 { 976 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 977 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 978 979 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, 980 &irq_pcie_phandle, &irq_virtio_phandle, 981 &msi_pcie_phandle); 982 983 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); 984 985 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); 986 987 create_fdt_reset(s, virt_memmap, &phandle); 988 989 create_fdt_uart(s, virt_memmap, irq_mmio_phandle); 990 991 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); 992 } 993 994 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) 995 { 996 MachineState *ms = MACHINE(s); 997 uint8_t rng_seed[32]; 998 999 ms->fdt = create_device_tree(&s->fdt_size); 1000 if (!ms->fdt) { 1001 error_report("create_device_tree() failed"); 1002 exit(1); 1003 } 1004 1005 qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); 1006 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); 1007 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 1008 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 1009 1010 qemu_fdt_add_subnode(ms->fdt, "/soc"); 1011 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); 1012 qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); 1013 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); 1014 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); 1015 1016 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 1017 1018 /* Pass seed to RNG */ 1019 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1020 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", 1021 rng_seed, sizeof(rng_seed)); 1022 1023 create_fdt_flash(s, memmap); 1024 create_fdt_fw_cfg(s, memmap); 1025 create_fdt_pmu(s); 1026 } 1027 1028 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1029 DeviceState *irqchip, 1030 RISCVVirtState *s) 1031 { 1032 DeviceState *dev; 1033 MemoryRegion *ecam_alias, *ecam_reg; 1034 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1035 hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; 1036 hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; 1037 hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; 1038 hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; 1039 hwaddr high_mmio_base = virt_high_pcie_memmap.base; 1040 hwaddr high_mmio_size = virt_high_pcie_memmap.size; 1041 hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; 1042 hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; 1043 qemu_irq irq; 1044 int i; 1045 1046 dev = qdev_new(TYPE_GPEX_HOST); 1047 1048 /* Set GPEX object properties for the virt machine */ 1049 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, 1050 ecam_base, NULL); 1051 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, 1052 ecam_size, NULL); 1053 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1054 PCI_HOST_BELOW_4G_MMIO_BASE, 1055 mmio_base, NULL); 1056 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, 1057 mmio_size, NULL); 1058 object_property_set_uint(OBJECT(GPEX_HOST(dev)), 1059 PCI_HOST_ABOVE_4G_MMIO_BASE, 1060 high_mmio_base, NULL); 1061 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, 1062 high_mmio_size, NULL); 1063 object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, 1064 pio_base, NULL); 1065 object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, 1066 pio_size, NULL); 1067 1068 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1069 1070 ecam_alias = g_new0(MemoryRegion, 1); 1071 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1072 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1073 ecam_reg, 0, ecam_size); 1074 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1075 1076 mmio_alias = g_new0(MemoryRegion, 1); 1077 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1078 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1079 mmio_reg, mmio_base, mmio_size); 1080 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1081 1082 /* Map high MMIO space */ 1083 high_mmio_alias = g_new0(MemoryRegion, 1); 1084 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1085 mmio_reg, high_mmio_base, high_mmio_size); 1086 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1087 high_mmio_alias); 1088 1089 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1090 1091 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1092 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1093 1094 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1095 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1096 } 1097 1098 GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; 1099 return dev; 1100 } 1101 1102 static FWCfgState *create_fw_cfg(const MachineState *ms) 1103 { 1104 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1105 FWCfgState *fw_cfg; 1106 1107 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1108 &address_space_memory); 1109 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1110 1111 return fw_cfg; 1112 } 1113 1114 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1115 int base_hartid, int hart_count) 1116 { 1117 DeviceState *ret; 1118 g_autofree char *plic_hart_config = NULL; 1119 1120 /* Per-socket PLIC hart topology configuration string */ 1121 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1122 1123 /* Per-socket PLIC */ 1124 ret = sifive_plic_create( 1125 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1126 plic_hart_config, hart_count, base_hartid, 1127 VIRT_IRQCHIP_NUM_SOURCES, 1128 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1129 VIRT_PLIC_PRIORITY_BASE, 1130 VIRT_PLIC_PENDING_BASE, 1131 VIRT_PLIC_ENABLE_BASE, 1132 VIRT_PLIC_ENABLE_STRIDE, 1133 VIRT_PLIC_CONTEXT_BASE, 1134 VIRT_PLIC_CONTEXT_STRIDE, 1135 memmap[VIRT_PLIC].size); 1136 1137 return ret; 1138 } 1139 1140 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1141 const MemMapEntry *memmap, int socket, 1142 int base_hartid, int hart_count) 1143 { 1144 int i; 1145 hwaddr addr; 1146 uint32_t guest_bits; 1147 DeviceState *aplic_s = NULL; 1148 DeviceState *aplic_m = NULL; 1149 bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; 1150 1151 if (msimode) { 1152 if (!kvm_enabled()) { 1153 /* Per-socket M-level IMSICs */ 1154 addr = memmap[VIRT_IMSIC_M].base + 1155 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1156 for (i = 0; i < hart_count; i++) { 1157 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1158 base_hartid + i, true, 1, 1159 VIRT_IRQCHIP_NUM_MSIS); 1160 } 1161 } 1162 1163 /* Per-socket S-level IMSICs */ 1164 guest_bits = imsic_num_bits(aia_guests + 1); 1165 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1166 for (i = 0; i < hart_count; i++) { 1167 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1168 base_hartid + i, false, 1 + aia_guests, 1169 VIRT_IRQCHIP_NUM_MSIS); 1170 } 1171 } 1172 1173 if (!kvm_enabled()) { 1174 /* Per-socket M-level APLIC */ 1175 aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + 1176 socket * memmap[VIRT_APLIC_M].size, 1177 memmap[VIRT_APLIC_M].size, 1178 (msimode) ? 0 : base_hartid, 1179 (msimode) ? 0 : hart_count, 1180 VIRT_IRQCHIP_NUM_SOURCES, 1181 VIRT_IRQCHIP_NUM_PRIO_BITS, 1182 msimode, true, NULL); 1183 } 1184 1185 /* Per-socket S-level APLIC */ 1186 aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + 1187 socket * memmap[VIRT_APLIC_S].size, 1188 memmap[VIRT_APLIC_S].size, 1189 (msimode) ? 0 : base_hartid, 1190 (msimode) ? 0 : hart_count, 1191 VIRT_IRQCHIP_NUM_SOURCES, 1192 VIRT_IRQCHIP_NUM_PRIO_BITS, 1193 msimode, false, aplic_m); 1194 1195 return kvm_enabled() ? aplic_s : aplic_m; 1196 } 1197 1198 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1199 { 1200 DeviceState *dev; 1201 SysBusDevice *sysbus; 1202 const MemMapEntry *memmap = virt_memmap; 1203 int i; 1204 MemoryRegion *sysmem = get_system_memory(); 1205 1206 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1207 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1208 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1209 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1210 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1211 s->platform_bus_dev = dev; 1212 1213 sysbus = SYS_BUS_DEVICE(dev); 1214 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1215 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1216 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1217 } 1218 1219 memory_region_add_subregion(sysmem, 1220 memmap[VIRT_PLATFORM_BUS].base, 1221 sysbus_mmio_get_region(sysbus, 0)); 1222 } 1223 1224 static void virt_machine_done(Notifier *notifier, void *data) 1225 { 1226 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1227 machine_done); 1228 const MemMapEntry *memmap = virt_memmap; 1229 MachineState *machine = MACHINE(s); 1230 target_ulong start_addr = memmap[VIRT_DRAM].base; 1231 target_ulong firmware_end_addr, kernel_start_addr; 1232 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); 1233 uint64_t fdt_load_addr; 1234 uint64_t kernel_entry = 0; 1235 BlockBackend *pflash_blk0; 1236 1237 /* 1238 * An user provided dtb must include everything, including 1239 * dynamic sysbus devices. Our FDT needs to be finalized. 1240 */ 1241 if (machine->dtb == NULL) { 1242 finalize_fdt(s); 1243 } 1244 1245 /* 1246 * Only direct boot kernel is currently supported for KVM VM, 1247 * so the "-bios" parameter is not supported when KVM is enabled. 1248 */ 1249 if (kvm_enabled()) { 1250 if (machine->firmware) { 1251 if (strcmp(machine->firmware, "none")) { 1252 error_report("Machine mode firmware is not supported in " 1253 "combination with KVM."); 1254 exit(1); 1255 } 1256 } else { 1257 machine->firmware = g_strdup("none"); 1258 } 1259 } 1260 1261 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 1262 start_addr, NULL); 1263 1264 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); 1265 if (pflash_blk0) { 1266 if (machine->firmware && !strcmp(machine->firmware, "none") && 1267 !kvm_enabled()) { 1268 /* 1269 * Pflash was supplied but bios is none and not KVM guest, 1270 * let's overwrite the address we jump to after reset to 1271 * the base of the flash. 1272 */ 1273 start_addr = virt_memmap[VIRT_FLASH].base; 1274 } else { 1275 /* 1276 * Pflash was supplied but either KVM guest or bios is not none. 1277 * In this case, base of the flash would contain S-mode payload. 1278 */ 1279 riscv_setup_firmware_boot(machine); 1280 kernel_entry = virt_memmap[VIRT_FLASH].base; 1281 } 1282 } 1283 1284 if (machine->kernel_filename && !kernel_entry) { 1285 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1286 firmware_end_addr); 1287 1288 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 1289 kernel_start_addr, true, NULL); 1290 } 1291 1292 fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, 1293 memmap[VIRT_DRAM].size, 1294 machine); 1295 riscv_load_fdt(fdt_load_addr, machine->fdt); 1296 1297 /* load the reset vector */ 1298 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1299 virt_memmap[VIRT_MROM].base, 1300 virt_memmap[VIRT_MROM].size, kernel_entry, 1301 fdt_load_addr); 1302 1303 /* 1304 * Only direct boot kernel is currently supported for KVM VM, 1305 * So here setup kernel start address and fdt address. 1306 * TODO:Support firmware loading and integrate to TCG start 1307 */ 1308 if (kvm_enabled()) { 1309 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1310 } 1311 1312 if (virt_is_acpi_enabled(s)) { 1313 virt_acpi_setup(s); 1314 } 1315 } 1316 1317 static void virt_machine_init(MachineState *machine) 1318 { 1319 const MemMapEntry *memmap = virt_memmap; 1320 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1321 MemoryRegion *system_memory = get_system_memory(); 1322 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1323 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1324 int i, base_hartid, hart_count; 1325 int socket_count = riscv_socket_count(machine); 1326 1327 /* Check socket count limit */ 1328 if (VIRT_SOCKETS_MAX < socket_count) { 1329 error_report("number of sockets/nodes should be less than %d", 1330 VIRT_SOCKETS_MAX); 1331 exit(1); 1332 } 1333 1334 if (!tcg_enabled() && s->have_aclint) { 1335 error_report("'aclint' is only available with TCG acceleration"); 1336 exit(1); 1337 } 1338 1339 /* Initialize sockets */ 1340 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1341 for (i = 0; i < socket_count; i++) { 1342 g_autofree char *soc_name = g_strdup_printf("soc%d", i); 1343 1344 if (!riscv_socket_check_hartids(machine, i)) { 1345 error_report("discontinuous hartids in socket%d", i); 1346 exit(1); 1347 } 1348 1349 base_hartid = riscv_socket_first_hartid(machine, i); 1350 if (base_hartid < 0) { 1351 error_report("can't find hartid base for socket%d", i); 1352 exit(1); 1353 } 1354 1355 hart_count = riscv_socket_hart_count(machine, i); 1356 if (hart_count < 0) { 1357 error_report("can't find hart count for socket%d", i); 1358 exit(1); 1359 } 1360 1361 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1362 TYPE_RISCV_HART_ARRAY); 1363 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1364 machine->cpu_type, &error_abort); 1365 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1366 base_hartid, &error_abort); 1367 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1368 hart_count, &error_abort); 1369 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1370 1371 if (tcg_enabled()) { 1372 if (s->have_aclint) { 1373 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1374 /* Per-socket ACLINT MTIMER */ 1375 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1376 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1377 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1378 base_hartid, hart_count, 1379 RISCV_ACLINT_DEFAULT_MTIMECMP, 1380 RISCV_ACLINT_DEFAULT_MTIME, 1381 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1382 } else { 1383 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1384 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1385 i * memmap[VIRT_CLINT].size, 1386 base_hartid, hart_count, false); 1387 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1388 i * memmap[VIRT_CLINT].size + 1389 RISCV_ACLINT_SWI_SIZE, 1390 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1391 base_hartid, hart_count, 1392 RISCV_ACLINT_DEFAULT_MTIMECMP, 1393 RISCV_ACLINT_DEFAULT_MTIME, 1394 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1395 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1396 i * memmap[VIRT_ACLINT_SSWI].size, 1397 base_hartid, hart_count, true); 1398 } 1399 } else { 1400 /* Per-socket SiFive CLINT */ 1401 riscv_aclint_swi_create( 1402 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1403 base_hartid, hart_count, false); 1404 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1405 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1406 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1407 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1408 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1409 } 1410 } 1411 1412 /* Per-socket interrupt controller */ 1413 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1414 s->irqchip[i] = virt_create_plic(memmap, i, 1415 base_hartid, hart_count); 1416 } else { 1417 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1418 memmap, i, base_hartid, 1419 hart_count); 1420 } 1421 1422 /* Try to use different IRQCHIP instance based device type */ 1423 if (i == 0) { 1424 mmio_irqchip = s->irqchip[i]; 1425 virtio_irqchip = s->irqchip[i]; 1426 pcie_irqchip = s->irqchip[i]; 1427 } 1428 if (i == 1) { 1429 virtio_irqchip = s->irqchip[i]; 1430 pcie_irqchip = s->irqchip[i]; 1431 } 1432 if (i == 2) { 1433 pcie_irqchip = s->irqchip[i]; 1434 } 1435 } 1436 1437 if (kvm_enabled() && virt_use_kvm_aia(s)) { 1438 kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, 1439 VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, 1440 memmap[VIRT_APLIC_S].base, 1441 memmap[VIRT_IMSIC_S].base, 1442 s->aia_guests); 1443 } 1444 1445 if (riscv_is_32bit(&s->soc[0])) { 1446 #if HOST_LONG_BITS == 64 1447 /* limit RAM size in a 32-bit system */ 1448 if (machine->ram_size > 10 * GiB) { 1449 machine->ram_size = 10 * GiB; 1450 error_report("Limiting RAM size to 10 GiB"); 1451 } 1452 #endif 1453 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1454 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1455 } else { 1456 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1457 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1458 virt_high_pcie_memmap.base = 1459 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1460 } 1461 1462 s->memmap = virt_memmap; 1463 1464 /* register system main memory (actual RAM) */ 1465 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1466 machine->ram); 1467 1468 /* boot rom */ 1469 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1470 memmap[VIRT_MROM].size, &error_fatal); 1471 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1472 mask_rom); 1473 1474 /* 1475 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the 1476 * device tree cannot be altered and we get FDT_ERR_NOSPACE. 1477 */ 1478 s->fw_cfg = create_fw_cfg(machine); 1479 rom_set_fw(s->fw_cfg); 1480 1481 /* SiFive Test MMIO device */ 1482 sifive_test_create(memmap[VIRT_TEST].base); 1483 1484 /* VirtIO MMIO devices */ 1485 for (i = 0; i < VIRTIO_COUNT; i++) { 1486 sysbus_create_simple("virtio-mmio", 1487 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1488 qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); 1489 } 1490 1491 gpex_pcie_init(system_memory, pcie_irqchip, s); 1492 1493 create_platform_bus(s, mmio_irqchip); 1494 1495 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1496 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, 1497 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1498 1499 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1500 qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 1501 1502 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1503 /* Map legacy -drive if=pflash to machine properties */ 1504 pflash_cfi01_legacy_drive(s->flash[i], 1505 drive_get(IF_PFLASH, 0, i)); 1506 } 1507 virt_flash_map(s, system_memory); 1508 1509 /* load/create device tree */ 1510 if (machine->dtb) { 1511 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 1512 if (!machine->fdt) { 1513 error_report("load_device_tree() failed"); 1514 exit(1); 1515 } 1516 } else { 1517 create_fdt(s, memmap); 1518 } 1519 1520 s->machine_done.notify = virt_machine_done; 1521 qemu_add_machine_init_done_notifier(&s->machine_done); 1522 } 1523 1524 static void virt_machine_instance_init(Object *obj) 1525 { 1526 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1527 1528 virt_flash_create(s); 1529 1530 s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1531 s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1532 s->acpi = ON_OFF_AUTO_AUTO; 1533 } 1534 1535 static char *virt_get_aia_guests(Object *obj, Error **errp) 1536 { 1537 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1538 char val[32]; 1539 1540 sprintf(val, "%d", s->aia_guests); 1541 return g_strdup(val); 1542 } 1543 1544 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1545 { 1546 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1547 1548 s->aia_guests = atoi(val); 1549 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1550 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1551 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1552 VIRT_IRQCHIP_MAX_GUESTS); 1553 } 1554 } 1555 1556 static char *virt_get_aia(Object *obj, Error **errp) 1557 { 1558 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1559 const char *val; 1560 1561 switch (s->aia_type) { 1562 case VIRT_AIA_TYPE_APLIC: 1563 val = "aplic"; 1564 break; 1565 case VIRT_AIA_TYPE_APLIC_IMSIC: 1566 val = "aplic-imsic"; 1567 break; 1568 default: 1569 val = "none"; 1570 break; 1571 }; 1572 1573 return g_strdup(val); 1574 } 1575 1576 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1577 { 1578 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1579 1580 if (!strcmp(val, "none")) { 1581 s->aia_type = VIRT_AIA_TYPE_NONE; 1582 } else if (!strcmp(val, "aplic")) { 1583 s->aia_type = VIRT_AIA_TYPE_APLIC; 1584 } else if (!strcmp(val, "aplic-imsic")) { 1585 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1586 } else { 1587 error_setg(errp, "Invalid AIA interrupt controller type"); 1588 error_append_hint(errp, "Valid values are none, aplic, and " 1589 "aplic-imsic.\n"); 1590 } 1591 } 1592 1593 static bool virt_get_aclint(Object *obj, Error **errp) 1594 { 1595 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1596 1597 return s->have_aclint; 1598 } 1599 1600 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1601 { 1602 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1603 1604 s->have_aclint = value; 1605 } 1606 1607 bool virt_is_acpi_enabled(RISCVVirtState *s) 1608 { 1609 return s->acpi != ON_OFF_AUTO_OFF; 1610 } 1611 1612 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1613 void *opaque, Error **errp) 1614 { 1615 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1616 OnOffAuto acpi = s->acpi; 1617 1618 visit_type_OnOffAuto(v, name, &acpi, errp); 1619 } 1620 1621 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1622 void *opaque, Error **errp) 1623 { 1624 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1625 1626 visit_type_OnOffAuto(v, name, &s->acpi, errp); 1627 } 1628 1629 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1630 DeviceState *dev) 1631 { 1632 MachineClass *mc = MACHINE_GET_CLASS(machine); 1633 1634 if (device_is_dynamic_sysbus(mc, dev)) { 1635 return HOTPLUG_HANDLER(machine); 1636 } 1637 return NULL; 1638 } 1639 1640 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1641 DeviceState *dev, Error **errp) 1642 { 1643 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1644 1645 if (s->platform_bus_dev) { 1646 MachineClass *mc = MACHINE_GET_CLASS(s); 1647 1648 if (device_is_dynamic_sysbus(mc, dev)) { 1649 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1650 SYS_BUS_DEVICE(dev)); 1651 } 1652 } 1653 } 1654 1655 static void virt_machine_class_init(ObjectClass *oc, void *data) 1656 { 1657 char str[128]; 1658 MachineClass *mc = MACHINE_CLASS(oc); 1659 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1660 1661 mc->desc = "RISC-V VirtIO board"; 1662 mc->init = virt_machine_init; 1663 mc->max_cpus = VIRT_CPUS_MAX; 1664 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1665 mc->pci_allow_0_address = true; 1666 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1667 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1668 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1669 mc->numa_mem_supported = true; 1670 /* platform instead of architectural choice */ 1671 mc->cpu_cluster_has_numa_boundary = true; 1672 mc->default_ram_id = "riscv_virt_board.ram"; 1673 assert(!mc->get_hotplug_handler); 1674 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1675 1676 hc->plug = virt_machine_device_plug_cb; 1677 1678 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1679 #ifdef CONFIG_TPM 1680 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1681 #endif 1682 1683 1684 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1685 virt_set_aclint); 1686 object_class_property_set_description(oc, "aclint", 1687 "(TCG only) Set on/off to " 1688 "enable/disable emulating " 1689 "ACLINT devices"); 1690 1691 object_class_property_add_str(oc, "aia", virt_get_aia, 1692 virt_set_aia); 1693 object_class_property_set_description(oc, "aia", 1694 "Set type of AIA interrupt " 1695 "controller. Valid values are " 1696 "none, aplic, and aplic-imsic."); 1697 1698 object_class_property_add_str(oc, "aia-guests", 1699 virt_get_aia_guests, 1700 virt_set_aia_guests); 1701 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1702 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1703 object_class_property_set_description(oc, "aia-guests", str); 1704 object_class_property_add(oc, "acpi", "OnOffAuto", 1705 virt_get_acpi, virt_set_acpi, 1706 NULL, NULL); 1707 object_class_property_set_description(oc, "acpi", 1708 "Enable ACPI"); 1709 } 1710 1711 static const TypeInfo virt_machine_typeinfo = { 1712 .name = MACHINE_TYPE_NAME("virt"), 1713 .parent = TYPE_MACHINE, 1714 .class_init = virt_machine_class_init, 1715 .instance_init = virt_machine_instance_init, 1716 .instance_size = sizeof(RISCVVirtState), 1717 .interfaces = (InterfaceInfo[]) { 1718 { TYPE_HOTPLUG_HANDLER }, 1719 { } 1720 }, 1721 }; 1722 1723 static void virt_machine_init_register_types(void) 1724 { 1725 type_register_static(&virt_machine_typeinfo); 1726 } 1727 1728 type_init(virt_machine_init_register_types) 1729