1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "hw/riscv/riscv_hart.h" 34 #include "hw/riscv/virt.h" 35 #include "hw/riscv/boot.h" 36 #include "hw/riscv/numa.h" 37 #include "hw/intc/riscv_aclint.h" 38 #include "hw/intc/riscv_aplic.h" 39 #include "hw/intc/riscv_imsic.h" 40 #include "hw/intc/sifive_plic.h" 41 #include "hw/misc/sifive_test.h" 42 #include "hw/platform-bus.h" 43 #include "chardev/char.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/sysemu.h" 46 #include "sysemu/kvm.h" 47 #include "sysemu/tpm.h" 48 #include "hw/pci/pci.h" 49 #include "hw/pci-host/gpex.h" 50 #include "hw/display/ramfb.h" 51 52 /* 53 * The virt machine physical address space used by some of the devices 54 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 55 * number of CPUs, and number of IMSIC guest files. 56 * 57 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 58 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 59 * of virt machine physical address space. 60 */ 61 62 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 63 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 64 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 65 #error "Can't accomodate single IMSIC group in address space" 66 #endif 67 68 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 69 VIRT_IMSIC_GROUP_MAX_SIZE) 70 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 71 #error "Can't accomodate all IMSIC groups in address space" 72 #endif 73 74 static const MemMapEntry virt_memmap[] = { 75 [VIRT_DEBUG] = { 0x0, 0x100 }, 76 [VIRT_MROM] = { 0x1000, 0xf000 }, 77 [VIRT_TEST] = { 0x100000, 0x1000 }, 78 [VIRT_RTC] = { 0x101000, 0x1000 }, 79 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 80 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 81 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 82 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 83 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 84 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 85 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 86 [VIRT_UART0] = { 0x10000000, 0x100 }, 87 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 88 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 89 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 90 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 91 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 92 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 93 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 94 [VIRT_DRAM] = { 0x80000000, 0x0 }, 95 }; 96 97 /* PCIe high mmio is fixed for RV32 */ 98 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 99 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 100 101 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 102 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 103 104 static MemMapEntry virt_high_pcie_memmap; 105 106 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 107 108 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 109 const char *name, 110 const char *alias_prop_name) 111 { 112 /* 113 * Create a single flash device. We use the same parameters as 114 * the flash devices on the ARM virt board. 115 */ 116 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 117 118 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 119 qdev_prop_set_uint8(dev, "width", 4); 120 qdev_prop_set_uint8(dev, "device-width", 2); 121 qdev_prop_set_bit(dev, "big-endian", false); 122 qdev_prop_set_uint16(dev, "id0", 0x89); 123 qdev_prop_set_uint16(dev, "id1", 0x18); 124 qdev_prop_set_uint16(dev, "id2", 0x00); 125 qdev_prop_set_uint16(dev, "id3", 0x00); 126 qdev_prop_set_string(dev, "name", name); 127 128 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 129 object_property_add_alias(OBJECT(s), alias_prop_name, 130 OBJECT(dev), "drive"); 131 132 return PFLASH_CFI01(dev); 133 } 134 135 static void virt_flash_create(RISCVVirtState *s) 136 { 137 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 138 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 139 } 140 141 static void virt_flash_map1(PFlashCFI01 *flash, 142 hwaddr base, hwaddr size, 143 MemoryRegion *sysmem) 144 { 145 DeviceState *dev = DEVICE(flash); 146 147 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 148 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 149 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 150 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 151 152 memory_region_add_subregion(sysmem, base, 153 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 154 0)); 155 } 156 157 static void virt_flash_map(RISCVVirtState *s, 158 MemoryRegion *sysmem) 159 { 160 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 161 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 162 163 virt_flash_map1(s->flash[0], flashbase, flashsize, 164 sysmem); 165 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 166 sysmem); 167 } 168 169 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 170 uint32_t irqchip_phandle) 171 { 172 int pin, dev; 173 uint32_t irq_map_stride = 0; 174 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 175 FDT_MAX_INT_MAP_WIDTH] = {}; 176 uint32_t *irq_map = full_irq_map; 177 178 /* This code creates a standard swizzle of interrupts such that 179 * each device's first interrupt is based on it's PCI_SLOT number. 180 * (See pci_swizzle_map_irq_fn()) 181 * 182 * We only need one entry per interrupt in the table (not one per 183 * possible slot) seeing the interrupt-map-mask will allow the table 184 * to wrap to any number of devices. 185 */ 186 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 187 int devfn = dev * 0x8; 188 189 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 190 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 191 int i = 0; 192 193 /* Fill PCI address cells */ 194 irq_map[i] = cpu_to_be32(devfn << 8); 195 i += FDT_PCI_ADDR_CELLS; 196 197 /* Fill PCI Interrupt cells */ 198 irq_map[i] = cpu_to_be32(pin + 1); 199 i += FDT_PCI_INT_CELLS; 200 201 /* Fill interrupt controller phandle and cells */ 202 irq_map[i++] = cpu_to_be32(irqchip_phandle); 203 irq_map[i++] = cpu_to_be32(irq_nr); 204 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 205 irq_map[i++] = cpu_to_be32(0x4); 206 } 207 208 if (!irq_map_stride) { 209 irq_map_stride = i; 210 } 211 irq_map += irq_map_stride; 212 } 213 } 214 215 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 216 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 217 irq_map_stride * sizeof(uint32_t)); 218 219 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 220 0x1800, 0, 0, 0x7); 221 } 222 223 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 224 char *clust_name, uint32_t *phandle, 225 bool is_32_bit, uint32_t *intc_phandles) 226 { 227 int cpu; 228 uint32_t cpu_phandle; 229 MachineState *mc = MACHINE(s); 230 char *name, *cpu_name, *core_name, *intc_name; 231 232 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 233 cpu_phandle = (*phandle)++; 234 235 cpu_name = g_strdup_printf("/cpus/cpu@%d", 236 s->soc[socket].hartid_base + cpu); 237 qemu_fdt_add_subnode(mc->fdt, cpu_name); 238 if (riscv_feature(&s->soc[socket].harts[cpu].env, 239 RISCV_FEATURE_MMU)) { 240 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 241 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 242 } else { 243 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 244 "riscv,none"); 245 } 246 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 247 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); 248 g_free(name); 249 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); 250 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); 251 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", 252 s->soc[socket].hartid_base + cpu); 253 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); 254 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); 255 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); 256 257 intc_phandles[cpu] = (*phandle)++; 258 259 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 260 qemu_fdt_add_subnode(mc->fdt, intc_name); 261 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", 262 intc_phandles[cpu]); 263 if (riscv_feature(&s->soc[socket].harts[cpu].env, 264 RISCV_FEATURE_AIA)) { 265 static const char * const compat[2] = { 266 "riscv,cpu-intc-aia", "riscv,cpu-intc" 267 }; 268 qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible", 269 (char **)&compat, ARRAY_SIZE(compat)); 270 } else { 271 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", 272 "riscv,cpu-intc"); 273 } 274 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); 275 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); 276 277 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 278 qemu_fdt_add_subnode(mc->fdt, core_name); 279 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); 280 281 g_free(core_name); 282 g_free(intc_name); 283 g_free(cpu_name); 284 } 285 } 286 287 static void create_fdt_socket_memory(RISCVVirtState *s, 288 const MemMapEntry *memmap, int socket) 289 { 290 char *mem_name; 291 uint64_t addr, size; 292 MachineState *mc = MACHINE(s); 293 294 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 295 size = riscv_socket_mem_size(mc, socket); 296 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 297 qemu_fdt_add_subnode(mc->fdt, mem_name); 298 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", 299 addr >> 32, addr, size >> 32, size); 300 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); 301 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); 302 g_free(mem_name); 303 } 304 305 static void create_fdt_socket_clint(RISCVVirtState *s, 306 const MemMapEntry *memmap, int socket, 307 uint32_t *intc_phandles) 308 { 309 int cpu; 310 char *clint_name; 311 uint32_t *clint_cells; 312 unsigned long clint_addr; 313 MachineState *mc = MACHINE(s); 314 static const char * const clint_compat[2] = { 315 "sifive,clint0", "riscv,clint0" 316 }; 317 318 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 319 320 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 321 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 322 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 323 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 324 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 325 } 326 327 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 328 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 329 qemu_fdt_add_subnode(mc->fdt, clint_name); 330 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", 331 (char **)&clint_compat, 332 ARRAY_SIZE(clint_compat)); 333 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", 334 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 335 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", 336 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 337 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); 338 g_free(clint_name); 339 340 g_free(clint_cells); 341 } 342 343 static void create_fdt_socket_aclint(RISCVVirtState *s, 344 const MemMapEntry *memmap, int socket, 345 uint32_t *intc_phandles) 346 { 347 int cpu; 348 char *name; 349 unsigned long addr, size; 350 uint32_t aclint_cells_size; 351 uint32_t *aclint_mswi_cells; 352 uint32_t *aclint_sswi_cells; 353 uint32_t *aclint_mtimer_cells; 354 MachineState *mc = MACHINE(s); 355 356 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 357 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 358 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 359 360 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 361 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 362 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 363 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 364 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 365 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 366 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 367 } 368 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 369 370 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 371 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 372 name = g_strdup_printf("/soc/mswi@%lx", addr); 373 qemu_fdt_add_subnode(mc->fdt, name); 374 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 375 "riscv,aclint-mswi"); 376 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 377 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 378 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 379 aclint_mswi_cells, aclint_cells_size); 380 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 381 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 382 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 383 g_free(name); 384 } 385 386 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 387 addr = memmap[VIRT_CLINT].base + 388 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 389 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 390 } else { 391 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 392 (memmap[VIRT_CLINT].size * socket); 393 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 394 } 395 name = g_strdup_printf("/soc/mtimer@%lx", addr); 396 qemu_fdt_add_subnode(mc->fdt, name); 397 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 398 "riscv,aclint-mtimer"); 399 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 400 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 401 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 402 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 403 0x0, RISCV_ACLINT_DEFAULT_MTIME); 404 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 405 aclint_mtimer_cells, aclint_cells_size); 406 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 407 g_free(name); 408 409 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 410 addr = memmap[VIRT_ACLINT_SSWI].base + 411 (memmap[VIRT_ACLINT_SSWI].size * socket); 412 name = g_strdup_printf("/soc/sswi@%lx", addr); 413 qemu_fdt_add_subnode(mc->fdt, name); 414 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 415 "riscv,aclint-sswi"); 416 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 417 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 418 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 419 aclint_sswi_cells, aclint_cells_size); 420 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 421 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 422 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 423 g_free(name); 424 } 425 426 g_free(aclint_mswi_cells); 427 g_free(aclint_mtimer_cells); 428 g_free(aclint_sswi_cells); 429 } 430 431 static void create_fdt_socket_plic(RISCVVirtState *s, 432 const MemMapEntry *memmap, int socket, 433 uint32_t *phandle, uint32_t *intc_phandles, 434 uint32_t *plic_phandles) 435 { 436 int cpu; 437 char *plic_name; 438 uint32_t *plic_cells; 439 unsigned long plic_addr; 440 MachineState *mc = MACHINE(s); 441 static const char * const plic_compat[2] = { 442 "sifive,plic-1.0.0", "riscv,plic0" 443 }; 444 445 if (kvm_enabled()) { 446 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 447 } else { 448 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 449 } 450 451 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 452 if (kvm_enabled()) { 453 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 454 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 455 } else { 456 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 457 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 458 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 459 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 460 } 461 } 462 463 plic_phandles[socket] = (*phandle)++; 464 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 465 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 466 qemu_fdt_add_subnode(mc->fdt, plic_name); 467 qemu_fdt_setprop_cell(mc->fdt, plic_name, 468 "#interrupt-cells", FDT_PLIC_INT_CELLS); 469 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", 470 (char **)&plic_compat, 471 ARRAY_SIZE(plic_compat)); 472 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); 473 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", 474 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 475 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", 476 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 477 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 478 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); 479 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", 480 plic_phandles[socket]); 481 482 if (!socket) { 483 platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, 484 memmap[VIRT_PLATFORM_BUS].base, 485 memmap[VIRT_PLATFORM_BUS].size, 486 VIRT_PLATFORM_BUS_IRQ); 487 } 488 489 g_free(plic_name); 490 491 g_free(plic_cells); 492 } 493 494 static uint32_t imsic_num_bits(uint32_t count) 495 { 496 uint32_t ret = 0; 497 498 while (BIT(ret) < count) { 499 ret++; 500 } 501 502 return ret; 503 } 504 505 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 506 uint32_t *phandle, uint32_t *intc_phandles, 507 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 508 { 509 int cpu, socket; 510 char *imsic_name; 511 MachineState *mc = MACHINE(s); 512 uint32_t imsic_max_hart_per_socket, imsic_guest_bits; 513 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 514 515 *msi_m_phandle = (*phandle)++; 516 *msi_s_phandle = (*phandle)++; 517 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); 518 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); 519 520 /* M-level IMSIC node */ 521 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 522 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 523 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 524 } 525 imsic_max_hart_per_socket = 0; 526 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 527 imsic_addr = memmap[VIRT_IMSIC_M].base + 528 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 529 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; 530 imsic_regs[socket * 4 + 0] = 0; 531 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 532 imsic_regs[socket * 4 + 2] = 0; 533 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 534 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 535 imsic_max_hart_per_socket = s->soc[socket].num_harts; 536 } 537 } 538 imsic_name = g_strdup_printf("/soc/imsics@%lx", 539 (unsigned long)memmap[VIRT_IMSIC_M].base); 540 qemu_fdt_add_subnode(mc->fdt, imsic_name); 541 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 542 "riscv,imsics"); 543 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 544 FDT_IMSIC_INT_CELLS); 545 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 546 NULL, 0); 547 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 548 NULL, 0); 549 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 550 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 551 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 552 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 553 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 554 VIRT_IRQCHIP_NUM_MSIS); 555 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 556 VIRT_IRQCHIP_IPI_MSI); 557 if (riscv_socket_count(mc) > 1) { 558 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 559 imsic_num_bits(imsic_max_hart_per_socket)); 560 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 561 imsic_num_bits(riscv_socket_count(mc))); 562 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 563 IMSIC_MMIO_GROUP_MIN_SHIFT); 564 } 565 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); 566 567 g_free(imsic_name); 568 569 /* S-level IMSIC node */ 570 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 571 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 572 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 573 } 574 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); 575 imsic_max_hart_per_socket = 0; 576 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 577 imsic_addr = memmap[VIRT_IMSIC_S].base + 578 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 579 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 580 s->soc[socket].num_harts; 581 imsic_regs[socket * 4 + 0] = 0; 582 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 583 imsic_regs[socket * 4 + 2] = 0; 584 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 585 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 586 imsic_max_hart_per_socket = s->soc[socket].num_harts; 587 } 588 } 589 imsic_name = g_strdup_printf("/soc/imsics@%lx", 590 (unsigned long)memmap[VIRT_IMSIC_S].base); 591 qemu_fdt_add_subnode(mc->fdt, imsic_name); 592 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 593 "riscv,imsics"); 594 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 595 FDT_IMSIC_INT_CELLS); 596 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 597 NULL, 0); 598 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 599 NULL, 0); 600 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 601 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 602 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 603 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 604 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 605 VIRT_IRQCHIP_NUM_MSIS); 606 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 607 VIRT_IRQCHIP_IPI_MSI); 608 if (imsic_guest_bits) { 609 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", 610 imsic_guest_bits); 611 } 612 if (riscv_socket_count(mc) > 1) { 613 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 614 imsic_num_bits(imsic_max_hart_per_socket)); 615 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 616 imsic_num_bits(riscv_socket_count(mc))); 617 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 618 IMSIC_MMIO_GROUP_MIN_SHIFT); 619 } 620 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); 621 g_free(imsic_name); 622 623 g_free(imsic_regs); 624 g_free(imsic_cells); 625 } 626 627 static void create_fdt_socket_aplic(RISCVVirtState *s, 628 const MemMapEntry *memmap, int socket, 629 uint32_t msi_m_phandle, 630 uint32_t msi_s_phandle, 631 uint32_t *phandle, 632 uint32_t *intc_phandles, 633 uint32_t *aplic_phandles) 634 { 635 int cpu; 636 char *aplic_name; 637 uint32_t *aplic_cells; 638 unsigned long aplic_addr; 639 MachineState *mc = MACHINE(s); 640 uint32_t aplic_m_phandle, aplic_s_phandle; 641 642 aplic_m_phandle = (*phandle)++; 643 aplic_s_phandle = (*phandle)++; 644 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 645 646 /* M-level APLIC node */ 647 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 648 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 649 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 650 } 651 aplic_addr = memmap[VIRT_APLIC_M].base + 652 (memmap[VIRT_APLIC_M].size * socket); 653 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 654 qemu_fdt_add_subnode(mc->fdt, aplic_name); 655 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 656 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 657 "#interrupt-cells", FDT_APLIC_INT_CELLS); 658 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 659 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 660 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 661 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 662 } else { 663 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 664 msi_m_phandle); 665 } 666 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 667 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); 668 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 669 VIRT_IRQCHIP_NUM_SOURCES); 670 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", 671 aplic_s_phandle); 672 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", 673 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); 674 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 675 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); 676 g_free(aplic_name); 677 678 /* S-level APLIC node */ 679 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 680 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 681 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 682 } 683 aplic_addr = memmap[VIRT_APLIC_S].base + 684 (memmap[VIRT_APLIC_S].size * socket); 685 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 686 qemu_fdt_add_subnode(mc->fdt, aplic_name); 687 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 688 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 689 "#interrupt-cells", FDT_APLIC_INT_CELLS); 690 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 691 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 692 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 693 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 694 } else { 695 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 696 msi_s_phandle); 697 } 698 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 699 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); 700 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 701 VIRT_IRQCHIP_NUM_SOURCES); 702 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 703 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); 704 705 if (!socket) { 706 platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, 707 memmap[VIRT_PLATFORM_BUS].base, 708 memmap[VIRT_PLATFORM_BUS].size, 709 VIRT_PLATFORM_BUS_IRQ); 710 } 711 712 g_free(aplic_name); 713 714 g_free(aplic_cells); 715 aplic_phandles[socket] = aplic_s_phandle; 716 } 717 718 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 719 bool is_32_bit, uint32_t *phandle, 720 uint32_t *irq_mmio_phandle, 721 uint32_t *irq_pcie_phandle, 722 uint32_t *irq_virtio_phandle, 723 uint32_t *msi_pcie_phandle) 724 { 725 char *clust_name; 726 int socket, phandle_pos; 727 MachineState *mc = MACHINE(s); 728 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 729 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 730 731 qemu_fdt_add_subnode(mc->fdt, "/cpus"); 732 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", 733 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 734 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); 735 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); 736 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); 737 738 intc_phandles = g_new0(uint32_t, mc->smp.cpus); 739 740 phandle_pos = mc->smp.cpus; 741 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 742 phandle_pos -= s->soc[socket].num_harts; 743 744 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 745 qemu_fdt_add_subnode(mc->fdt, clust_name); 746 747 create_fdt_socket_cpus(s, socket, clust_name, phandle, 748 is_32_bit, &intc_phandles[phandle_pos]); 749 750 create_fdt_socket_memory(s, memmap, socket); 751 752 g_free(clust_name); 753 754 if (!kvm_enabled()) { 755 if (s->have_aclint) { 756 create_fdt_socket_aclint(s, memmap, socket, 757 &intc_phandles[phandle_pos]); 758 } else { 759 create_fdt_socket_clint(s, memmap, socket, 760 &intc_phandles[phandle_pos]); 761 } 762 } 763 } 764 765 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 766 create_fdt_imsic(s, memmap, phandle, intc_phandles, 767 &msi_m_phandle, &msi_s_phandle); 768 *msi_pcie_phandle = msi_s_phandle; 769 } 770 771 phandle_pos = mc->smp.cpus; 772 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 773 phandle_pos -= s->soc[socket].num_harts; 774 775 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 776 create_fdt_socket_plic(s, memmap, socket, phandle, 777 &intc_phandles[phandle_pos], xplic_phandles); 778 } else { 779 create_fdt_socket_aplic(s, memmap, socket, 780 msi_m_phandle, msi_s_phandle, phandle, 781 &intc_phandles[phandle_pos], xplic_phandles); 782 } 783 } 784 785 g_free(intc_phandles); 786 787 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 788 if (socket == 0) { 789 *irq_mmio_phandle = xplic_phandles[socket]; 790 *irq_virtio_phandle = xplic_phandles[socket]; 791 *irq_pcie_phandle = xplic_phandles[socket]; 792 } 793 if (socket == 1) { 794 *irq_virtio_phandle = xplic_phandles[socket]; 795 *irq_pcie_phandle = xplic_phandles[socket]; 796 } 797 if (socket == 2) { 798 *irq_pcie_phandle = xplic_phandles[socket]; 799 } 800 } 801 802 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); 803 } 804 805 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 806 uint32_t irq_virtio_phandle) 807 { 808 int i; 809 char *name; 810 MachineState *mc = MACHINE(s); 811 812 for (i = 0; i < VIRTIO_COUNT; i++) { 813 name = g_strdup_printf("/soc/virtio_mmio@%lx", 814 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 815 qemu_fdt_add_subnode(mc->fdt, name); 816 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); 817 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 818 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 819 0x0, memmap[VIRT_VIRTIO].size); 820 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 821 irq_virtio_phandle); 822 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 823 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", 824 VIRTIO_IRQ + i); 825 } else { 826 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", 827 VIRTIO_IRQ + i, 0x4); 828 } 829 g_free(name); 830 } 831 } 832 833 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 834 uint32_t irq_pcie_phandle, 835 uint32_t msi_pcie_phandle) 836 { 837 char *name; 838 MachineState *mc = MACHINE(s); 839 840 name = g_strdup_printf("/soc/pci@%lx", 841 (long) memmap[VIRT_PCIE_ECAM].base); 842 qemu_fdt_add_subnode(mc->fdt, name); 843 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", 844 FDT_PCI_ADDR_CELLS); 845 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 846 FDT_PCI_INT_CELLS); 847 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); 848 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 849 "pci-host-ecam-generic"); 850 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); 851 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); 852 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, 853 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 854 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); 855 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 856 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); 857 } 858 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, 859 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 860 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", 861 1, FDT_PCI_RANGE_IOPORT, 2, 0, 862 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 863 1, FDT_PCI_RANGE_MMIO, 864 2, memmap[VIRT_PCIE_MMIO].base, 865 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 866 1, FDT_PCI_RANGE_MMIO_64BIT, 867 2, virt_high_pcie_memmap.base, 868 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 869 870 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); 871 g_free(name); 872 } 873 874 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 875 uint32_t *phandle) 876 { 877 char *name; 878 uint32_t test_phandle; 879 MachineState *mc = MACHINE(s); 880 881 test_phandle = (*phandle)++; 882 name = g_strdup_printf("/soc/test@%lx", 883 (long)memmap[VIRT_TEST].base); 884 qemu_fdt_add_subnode(mc->fdt, name); 885 { 886 static const char * const compat[3] = { 887 "sifive,test1", "sifive,test0", "syscon" 888 }; 889 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", 890 (char **)&compat, ARRAY_SIZE(compat)); 891 } 892 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 893 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 894 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); 895 test_phandle = qemu_fdt_get_phandle(mc->fdt, name); 896 g_free(name); 897 898 name = g_strdup_printf("/soc/reboot"); 899 qemu_fdt_add_subnode(mc->fdt, name); 900 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); 901 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 902 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 903 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); 904 g_free(name); 905 906 name = g_strdup_printf("/soc/poweroff"); 907 qemu_fdt_add_subnode(mc->fdt, name); 908 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); 909 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 910 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 911 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); 912 g_free(name); 913 } 914 915 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 916 uint32_t irq_mmio_phandle) 917 { 918 char *name; 919 MachineState *mc = MACHINE(s); 920 921 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 922 qemu_fdt_add_subnode(mc->fdt, name); 923 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); 924 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 925 0x0, memmap[VIRT_UART0].base, 926 0x0, memmap[VIRT_UART0].size); 927 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); 928 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); 929 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 930 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); 931 } else { 932 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); 933 } 934 935 qemu_fdt_add_subnode(mc->fdt, "/chosen"); 936 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); 937 g_free(name); 938 } 939 940 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 941 uint32_t irq_mmio_phandle) 942 { 943 char *name; 944 MachineState *mc = MACHINE(s); 945 946 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 947 qemu_fdt_add_subnode(mc->fdt, name); 948 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 949 "google,goldfish-rtc"); 950 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 951 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 952 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 953 irq_mmio_phandle); 954 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 955 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); 956 } else { 957 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); 958 } 959 g_free(name); 960 } 961 962 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 963 { 964 char *name; 965 MachineState *mc = MACHINE(s); 966 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 967 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 968 969 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 970 qemu_fdt_add_subnode(mc->fdt, name); 971 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 972 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 973 2, flashbase, 2, flashsize, 974 2, flashbase + flashsize, 2, flashsize); 975 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 976 g_free(name); 977 } 978 979 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 980 { 981 char *nodename; 982 MachineState *mc = MACHINE(s); 983 hwaddr base = memmap[VIRT_FW_CFG].base; 984 hwaddr size = memmap[VIRT_FW_CFG].size; 985 986 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 987 qemu_fdt_add_subnode(mc->fdt, nodename); 988 qemu_fdt_setprop_string(mc->fdt, nodename, 989 "compatible", "qemu,fw-cfg-mmio"); 990 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 991 2, base, 2, size); 992 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 993 g_free(nodename); 994 } 995 996 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 997 uint64_t mem_size, const char *cmdline, bool is_32_bit) 998 { 999 MachineState *mc = MACHINE(s); 1000 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1001 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1002 uint8_t rng_seed[32]; 1003 1004 if (mc->dtb) { 1005 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 1006 if (!mc->fdt) { 1007 error_report("load_device_tree() failed"); 1008 exit(1); 1009 } 1010 goto update_bootargs; 1011 } else { 1012 mc->fdt = create_device_tree(&s->fdt_size); 1013 if (!mc->fdt) { 1014 error_report("create_device_tree() failed"); 1015 exit(1); 1016 } 1017 } 1018 1019 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); 1020 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); 1021 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); 1022 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); 1023 1024 qemu_fdt_add_subnode(mc->fdt, "/soc"); 1025 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); 1026 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); 1027 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); 1028 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); 1029 1030 create_fdt_sockets(s, memmap, is_32_bit, &phandle, 1031 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, 1032 &msi_pcie_phandle); 1033 1034 create_fdt_virtio(s, memmap, irq_virtio_phandle); 1035 1036 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); 1037 1038 create_fdt_reset(s, memmap, &phandle); 1039 1040 create_fdt_uart(s, memmap, irq_mmio_phandle); 1041 1042 create_fdt_rtc(s, memmap, irq_mmio_phandle); 1043 1044 create_fdt_flash(s, memmap); 1045 create_fdt_fw_cfg(s, memmap); 1046 1047 update_bootargs: 1048 if (cmdline && *cmdline) { 1049 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); 1050 } 1051 1052 /* Pass seed to RNG */ 1053 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1054 qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); 1055 } 1056 1057 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1058 hwaddr ecam_base, hwaddr ecam_size, 1059 hwaddr mmio_base, hwaddr mmio_size, 1060 hwaddr high_mmio_base, 1061 hwaddr high_mmio_size, 1062 hwaddr pio_base, 1063 DeviceState *irqchip) 1064 { 1065 DeviceState *dev; 1066 MemoryRegion *ecam_alias, *ecam_reg; 1067 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1068 qemu_irq irq; 1069 int i; 1070 1071 dev = qdev_new(TYPE_GPEX_HOST); 1072 1073 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1074 1075 ecam_alias = g_new0(MemoryRegion, 1); 1076 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1077 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1078 ecam_reg, 0, ecam_size); 1079 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1080 1081 mmio_alias = g_new0(MemoryRegion, 1); 1082 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1083 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1084 mmio_reg, mmio_base, mmio_size); 1085 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1086 1087 /* Map high MMIO space */ 1088 high_mmio_alias = g_new0(MemoryRegion, 1); 1089 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1090 mmio_reg, high_mmio_base, high_mmio_size); 1091 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1092 high_mmio_alias); 1093 1094 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1095 1096 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1097 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1098 1099 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1100 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1101 } 1102 1103 return dev; 1104 } 1105 1106 static FWCfgState *create_fw_cfg(const MachineState *mc) 1107 { 1108 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1109 FWCfgState *fw_cfg; 1110 1111 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1112 &address_space_memory); 1113 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 1114 1115 return fw_cfg; 1116 } 1117 1118 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1119 int base_hartid, int hart_count) 1120 { 1121 DeviceState *ret; 1122 char *plic_hart_config; 1123 1124 /* Per-socket PLIC hart topology configuration string */ 1125 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1126 1127 /* Per-socket PLIC */ 1128 ret = sifive_plic_create( 1129 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1130 plic_hart_config, hart_count, base_hartid, 1131 VIRT_IRQCHIP_NUM_SOURCES, 1132 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1133 VIRT_PLIC_PRIORITY_BASE, 1134 VIRT_PLIC_PENDING_BASE, 1135 VIRT_PLIC_ENABLE_BASE, 1136 VIRT_PLIC_ENABLE_STRIDE, 1137 VIRT_PLIC_CONTEXT_BASE, 1138 VIRT_PLIC_CONTEXT_STRIDE, 1139 memmap[VIRT_PLIC].size); 1140 1141 g_free(plic_hart_config); 1142 1143 return ret; 1144 } 1145 1146 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1147 const MemMapEntry *memmap, int socket, 1148 int base_hartid, int hart_count) 1149 { 1150 int i; 1151 hwaddr addr; 1152 uint32_t guest_bits; 1153 DeviceState *aplic_m; 1154 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; 1155 1156 if (msimode) { 1157 /* Per-socket M-level IMSICs */ 1158 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1159 for (i = 0; i < hart_count; i++) { 1160 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1161 base_hartid + i, true, 1, 1162 VIRT_IRQCHIP_NUM_MSIS); 1163 } 1164 1165 /* Per-socket S-level IMSICs */ 1166 guest_bits = imsic_num_bits(aia_guests + 1); 1167 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1168 for (i = 0; i < hart_count; i++) { 1169 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1170 base_hartid + i, false, 1 + aia_guests, 1171 VIRT_IRQCHIP_NUM_MSIS); 1172 } 1173 } 1174 1175 /* Per-socket M-level APLIC */ 1176 aplic_m = riscv_aplic_create( 1177 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, 1178 memmap[VIRT_APLIC_M].size, 1179 (msimode) ? 0 : base_hartid, 1180 (msimode) ? 0 : hart_count, 1181 VIRT_IRQCHIP_NUM_SOURCES, 1182 VIRT_IRQCHIP_NUM_PRIO_BITS, 1183 msimode, true, NULL); 1184 1185 if (aplic_m) { 1186 /* Per-socket S-level APLIC */ 1187 riscv_aplic_create( 1188 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, 1189 memmap[VIRT_APLIC_S].size, 1190 (msimode) ? 0 : base_hartid, 1191 (msimode) ? 0 : hart_count, 1192 VIRT_IRQCHIP_NUM_SOURCES, 1193 VIRT_IRQCHIP_NUM_PRIO_BITS, 1194 msimode, false, aplic_m); 1195 } 1196 1197 return aplic_m; 1198 } 1199 1200 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1201 { 1202 DeviceState *dev; 1203 SysBusDevice *sysbus; 1204 const MemMapEntry *memmap = virt_memmap; 1205 int i; 1206 MemoryRegion *sysmem = get_system_memory(); 1207 1208 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1209 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1210 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1211 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1212 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1213 s->platform_bus_dev = dev; 1214 1215 sysbus = SYS_BUS_DEVICE(dev); 1216 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1217 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1218 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1219 } 1220 1221 memory_region_add_subregion(sysmem, 1222 memmap[VIRT_PLATFORM_BUS].base, 1223 sysbus_mmio_get_region(sysbus, 0)); 1224 } 1225 1226 static void virt_machine_done(Notifier *notifier, void *data) 1227 { 1228 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1229 machine_done); 1230 const MemMapEntry *memmap = virt_memmap; 1231 MachineState *machine = MACHINE(s); 1232 target_ulong start_addr = memmap[VIRT_DRAM].base; 1233 target_ulong firmware_end_addr, kernel_start_addr; 1234 uint32_t fdt_load_addr; 1235 uint64_t kernel_entry; 1236 1237 /* 1238 * Only direct boot kernel is currently supported for KVM VM, 1239 * so the "-bios" parameter is not supported when KVM is enabled. 1240 */ 1241 if (kvm_enabled()) { 1242 if (machine->firmware) { 1243 if (strcmp(machine->firmware, "none")) { 1244 error_report("Machine mode firmware is not supported in " 1245 "combination with KVM."); 1246 exit(1); 1247 } 1248 } else { 1249 machine->firmware = g_strdup("none"); 1250 } 1251 } 1252 1253 if (riscv_is_32bit(&s->soc[0])) { 1254 firmware_end_addr = riscv_find_and_load_firmware(machine, 1255 RISCV32_BIOS_BIN, start_addr, NULL); 1256 } else { 1257 firmware_end_addr = riscv_find_and_load_firmware(machine, 1258 RISCV64_BIOS_BIN, start_addr, NULL); 1259 } 1260 1261 if (machine->kernel_filename) { 1262 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1263 firmware_end_addr); 1264 1265 kernel_entry = riscv_load_kernel(machine->kernel_filename, 1266 kernel_start_addr, NULL); 1267 1268 if (machine->initrd_filename) { 1269 hwaddr start; 1270 hwaddr end = riscv_load_initrd(machine->initrd_filename, 1271 machine->ram_size, kernel_entry, 1272 &start); 1273 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 1274 "linux,initrd-start", start); 1275 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 1276 end); 1277 } 1278 } else { 1279 /* 1280 * If dynamic firmware is used, it doesn't know where is the next mode 1281 * if kernel argument is not set. 1282 */ 1283 kernel_entry = 0; 1284 } 1285 1286 if (drive_get(IF_PFLASH, 0, 0)) { 1287 /* 1288 * Pflash was supplied, let's overwrite the address we jump to after 1289 * reset to the base of the flash. 1290 */ 1291 start_addr = virt_memmap[VIRT_FLASH].base; 1292 } 1293 1294 /* 1295 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 1296 * tree cannot be altered and we get FDT_ERR_NOSPACE. 1297 */ 1298 s->fw_cfg = create_fw_cfg(machine); 1299 rom_set_fw(s->fw_cfg); 1300 1301 /* Compute the fdt load address in dram */ 1302 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 1303 machine->ram_size, machine->fdt); 1304 /* load the reset vector */ 1305 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1306 virt_memmap[VIRT_MROM].base, 1307 virt_memmap[VIRT_MROM].size, kernel_entry, 1308 fdt_load_addr, machine->fdt); 1309 1310 /* 1311 * Only direct boot kernel is currently supported for KVM VM, 1312 * So here setup kernel start address and fdt address. 1313 * TODO:Support firmware loading and integrate to TCG start 1314 */ 1315 if (kvm_enabled()) { 1316 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1317 } 1318 } 1319 1320 static void virt_machine_init(MachineState *machine) 1321 { 1322 const MemMapEntry *memmap = virt_memmap; 1323 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1324 MemoryRegion *system_memory = get_system_memory(); 1325 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1326 char *soc_name; 1327 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1328 int i, base_hartid, hart_count; 1329 1330 /* Check socket count limit */ 1331 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 1332 error_report("number of sockets/nodes should be less than %d", 1333 VIRT_SOCKETS_MAX); 1334 exit(1); 1335 } 1336 1337 /* Initialize sockets */ 1338 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1339 for (i = 0; i < riscv_socket_count(machine); i++) { 1340 if (!riscv_socket_check_hartids(machine, i)) { 1341 error_report("discontinuous hartids in socket%d", i); 1342 exit(1); 1343 } 1344 1345 base_hartid = riscv_socket_first_hartid(machine, i); 1346 if (base_hartid < 0) { 1347 error_report("can't find hartid base for socket%d", i); 1348 exit(1); 1349 } 1350 1351 hart_count = riscv_socket_hart_count(machine, i); 1352 if (hart_count < 0) { 1353 error_report("can't find hart count for socket%d", i); 1354 exit(1); 1355 } 1356 1357 soc_name = g_strdup_printf("soc%d", i); 1358 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1359 TYPE_RISCV_HART_ARRAY); 1360 g_free(soc_name); 1361 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1362 machine->cpu_type, &error_abort); 1363 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1364 base_hartid, &error_abort); 1365 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1366 hart_count, &error_abort); 1367 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1368 1369 if (!kvm_enabled()) { 1370 if (s->have_aclint) { 1371 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1372 /* Per-socket ACLINT MTIMER */ 1373 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1374 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1375 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1376 base_hartid, hart_count, 1377 RISCV_ACLINT_DEFAULT_MTIMECMP, 1378 RISCV_ACLINT_DEFAULT_MTIME, 1379 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1380 } else { 1381 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1382 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1383 i * memmap[VIRT_CLINT].size, 1384 base_hartid, hart_count, false); 1385 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1386 i * memmap[VIRT_CLINT].size + 1387 RISCV_ACLINT_SWI_SIZE, 1388 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1389 base_hartid, hart_count, 1390 RISCV_ACLINT_DEFAULT_MTIMECMP, 1391 RISCV_ACLINT_DEFAULT_MTIME, 1392 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1393 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1394 i * memmap[VIRT_ACLINT_SSWI].size, 1395 base_hartid, hart_count, true); 1396 } 1397 } else { 1398 /* Per-socket SiFive CLINT */ 1399 riscv_aclint_swi_create( 1400 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1401 base_hartid, hart_count, false); 1402 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1403 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1404 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1405 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1406 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1407 } 1408 } 1409 1410 /* Per-socket interrupt controller */ 1411 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1412 s->irqchip[i] = virt_create_plic(memmap, i, 1413 base_hartid, hart_count); 1414 } else { 1415 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1416 memmap, i, base_hartid, 1417 hart_count); 1418 } 1419 1420 /* Try to use different IRQCHIP instance based device type */ 1421 if (i == 0) { 1422 mmio_irqchip = s->irqchip[i]; 1423 virtio_irqchip = s->irqchip[i]; 1424 pcie_irqchip = s->irqchip[i]; 1425 } 1426 if (i == 1) { 1427 virtio_irqchip = s->irqchip[i]; 1428 pcie_irqchip = s->irqchip[i]; 1429 } 1430 if (i == 2) { 1431 pcie_irqchip = s->irqchip[i]; 1432 } 1433 } 1434 1435 if (riscv_is_32bit(&s->soc[0])) { 1436 #if HOST_LONG_BITS == 64 1437 /* limit RAM size in a 32-bit system */ 1438 if (machine->ram_size > 10 * GiB) { 1439 machine->ram_size = 10 * GiB; 1440 error_report("Limiting RAM size to 10 GiB"); 1441 } 1442 #endif 1443 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1444 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1445 } else { 1446 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1447 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1448 virt_high_pcie_memmap.base = 1449 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1450 } 1451 1452 /* register system main memory (actual RAM) */ 1453 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1454 machine->ram); 1455 1456 /* boot rom */ 1457 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1458 memmap[VIRT_MROM].size, &error_fatal); 1459 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1460 mask_rom); 1461 1462 /* SiFive Test MMIO device */ 1463 sifive_test_create(memmap[VIRT_TEST].base); 1464 1465 /* VirtIO MMIO devices */ 1466 for (i = 0; i < VIRTIO_COUNT; i++) { 1467 sysbus_create_simple("virtio-mmio", 1468 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1469 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); 1470 } 1471 1472 gpex_pcie_init(system_memory, 1473 memmap[VIRT_PCIE_ECAM].base, 1474 memmap[VIRT_PCIE_ECAM].size, 1475 memmap[VIRT_PCIE_MMIO].base, 1476 memmap[VIRT_PCIE_MMIO].size, 1477 virt_high_pcie_memmap.base, 1478 virt_high_pcie_memmap.size, 1479 memmap[VIRT_PCIE_PIO].base, 1480 DEVICE(pcie_irqchip)); 1481 1482 create_platform_bus(s, DEVICE(mmio_irqchip)); 1483 1484 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1485 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, 1486 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1487 1488 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1489 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); 1490 1491 virt_flash_create(s); 1492 1493 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1494 /* Map legacy -drive if=pflash to machine properties */ 1495 pflash_cfi01_legacy_drive(s->flash[i], 1496 drive_get(IF_PFLASH, 0, i)); 1497 } 1498 virt_flash_map(s, system_memory); 1499 1500 /* create device tree */ 1501 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 1502 riscv_is_32bit(&s->soc[0])); 1503 1504 s->machine_done.notify = virt_machine_done; 1505 qemu_add_machine_init_done_notifier(&s->machine_done); 1506 } 1507 1508 static void virt_machine_instance_init(Object *obj) 1509 { 1510 } 1511 1512 static char *virt_get_aia_guests(Object *obj, Error **errp) 1513 { 1514 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1515 char val[32]; 1516 1517 sprintf(val, "%d", s->aia_guests); 1518 return g_strdup(val); 1519 } 1520 1521 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1522 { 1523 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1524 1525 s->aia_guests = atoi(val); 1526 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1527 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1528 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1529 VIRT_IRQCHIP_MAX_GUESTS); 1530 } 1531 } 1532 1533 static char *virt_get_aia(Object *obj, Error **errp) 1534 { 1535 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1536 const char *val; 1537 1538 switch (s->aia_type) { 1539 case VIRT_AIA_TYPE_APLIC: 1540 val = "aplic"; 1541 break; 1542 case VIRT_AIA_TYPE_APLIC_IMSIC: 1543 val = "aplic-imsic"; 1544 break; 1545 default: 1546 val = "none"; 1547 break; 1548 }; 1549 1550 return g_strdup(val); 1551 } 1552 1553 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1554 { 1555 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1556 1557 if (!strcmp(val, "none")) { 1558 s->aia_type = VIRT_AIA_TYPE_NONE; 1559 } else if (!strcmp(val, "aplic")) { 1560 s->aia_type = VIRT_AIA_TYPE_APLIC; 1561 } else if (!strcmp(val, "aplic-imsic")) { 1562 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1563 } else { 1564 error_setg(errp, "Invalid AIA interrupt controller type"); 1565 error_append_hint(errp, "Valid values are none, aplic, and " 1566 "aplic-imsic.\n"); 1567 } 1568 } 1569 1570 static bool virt_get_aclint(Object *obj, Error **errp) 1571 { 1572 MachineState *ms = MACHINE(obj); 1573 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1574 1575 return s->have_aclint; 1576 } 1577 1578 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1579 { 1580 MachineState *ms = MACHINE(obj); 1581 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1582 1583 s->have_aclint = value; 1584 } 1585 1586 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1587 DeviceState *dev) 1588 { 1589 MachineClass *mc = MACHINE_GET_CLASS(machine); 1590 1591 if (device_is_dynamic_sysbus(mc, dev)) { 1592 return HOTPLUG_HANDLER(machine); 1593 } 1594 return NULL; 1595 } 1596 1597 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1598 DeviceState *dev, Error **errp) 1599 { 1600 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1601 1602 if (s->platform_bus_dev) { 1603 MachineClass *mc = MACHINE_GET_CLASS(s); 1604 1605 if (device_is_dynamic_sysbus(mc, dev)) { 1606 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1607 SYS_BUS_DEVICE(dev)); 1608 } 1609 } 1610 } 1611 1612 static void virt_machine_class_init(ObjectClass *oc, void *data) 1613 { 1614 char str[128]; 1615 MachineClass *mc = MACHINE_CLASS(oc); 1616 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1617 1618 mc->desc = "RISC-V VirtIO board"; 1619 mc->init = virt_machine_init; 1620 mc->max_cpus = VIRT_CPUS_MAX; 1621 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1622 mc->pci_allow_0_address = true; 1623 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1624 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1625 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1626 mc->numa_mem_supported = true; 1627 mc->default_ram_id = "riscv_virt_board.ram"; 1628 assert(!mc->get_hotplug_handler); 1629 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1630 1631 hc->plug = virt_machine_device_plug_cb; 1632 1633 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1634 #ifdef CONFIG_TPM 1635 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1636 #endif 1637 1638 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1639 virt_set_aclint); 1640 object_class_property_set_description(oc, "aclint", 1641 "Set on/off to enable/disable " 1642 "emulating ACLINT devices"); 1643 1644 object_class_property_add_str(oc, "aia", virt_get_aia, 1645 virt_set_aia); 1646 object_class_property_set_description(oc, "aia", 1647 "Set type of AIA interrupt " 1648 "conttoller. Valid values are " 1649 "none, aplic, and aplic-imsic."); 1650 1651 object_class_property_add_str(oc, "aia-guests", 1652 virt_get_aia_guests, 1653 virt_set_aia_guests); 1654 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1655 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1656 object_class_property_set_description(oc, "aia-guests", str); 1657 } 1658 1659 static const TypeInfo virt_machine_typeinfo = { 1660 .name = MACHINE_TYPE_NAME("virt"), 1661 .parent = TYPE_MACHINE, 1662 .class_init = virt_machine_class_init, 1663 .instance_init = virt_machine_instance_init, 1664 .instance_size = sizeof(RISCVVirtState), 1665 .interfaces = (InterfaceInfo[]) { 1666 { TYPE_HOTPLUG_HANDLER }, 1667 { } 1668 }, 1669 }; 1670 1671 static void virt_machine_init_register_types(void) 1672 { 1673 type_register_static(&virt_machine_typeinfo); 1674 } 1675 1676 type_init(virt_machine_init_register_types) 1677