1 /* 2 * Support for generating ACPI tables and passing them to Guests 3 * 4 * RISC-V virt ACPI generation 5 * 6 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 7 * Copyright (C) 2006 Fabrice Bellard 8 * Copyright (C) 2013 Red Hat Inc 9 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 10 * Copyright (C) 2021-2023 Ventana Micro Systems Inc 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 22 * You should have received a copy of the GNU General Public License along 23 * with this program; if not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/acpi/acpi-defs.h" 28 #include "hw/acpi/acpi.h" 29 #include "hw/acpi/aml-build.h" 30 #include "hw/acpi/pci.h" 31 #include "hw/acpi/utils.h" 32 #include "hw/intc/riscv_aclint.h" 33 #include "hw/nvram/fw_cfg_acpi.h" 34 #include "hw/pci-host/gpex.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/numa.h" 37 #include "hw/virtio/virtio-acpi.h" 38 #include "migration/vmstate.h" 39 #include "qapi/error.h" 40 #include "qemu/error-report.h" 41 #include "sysemu/reset.h" 42 43 #define ACPI_BUILD_TABLE_SIZE 0x20000 44 #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) 45 46 typedef struct AcpiBuildState { 47 /* Copy of table in RAM (for patching) */ 48 MemoryRegion *table_mr; 49 MemoryRegion *rsdp_mr; 50 MemoryRegion *linker_mr; 51 /* Is table patched? */ 52 bool patched; 53 } AcpiBuildState; 54 55 static void acpi_align_size(GArray *blob, unsigned align) 56 { 57 /* 58 * Align size to multiple of given size. This reduces the chance 59 * we need to change size in the future (breaking cross version migration). 60 */ 61 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 62 } 63 64 static void riscv_acpi_madt_add_rintc(uint32_t uid, 65 const CPUArchIdList *arch_ids, 66 GArray *entry, 67 RISCVVirtState *s) 68 { 69 uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); 70 uint64_t hart_id = arch_ids->cpus[uid].arch_id; 71 uint32_t imsic_size, local_cpu_id, socket_id; 72 uint64_t imsic_socket_addr, imsic_addr; 73 MachineState *ms = MACHINE(s); 74 75 socket_id = arch_ids->cpus[uid].props.node_id; 76 local_cpu_id = (arch_ids->cpus[uid].arch_id - 77 riscv_socket_first_hartid(ms, socket_id)) % 78 riscv_socket_hart_count(ms, socket_id); 79 imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + 80 (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE); 81 imsic_size = IMSIC_HART_SIZE(guest_index_bits); 82 imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size; 83 build_append_int_noprefix(entry, 0x18, 1); /* Type */ 84 build_append_int_noprefix(entry, 36, 1); /* Length */ 85 build_append_int_noprefix(entry, 1, 1); /* Version */ 86 build_append_int_noprefix(entry, 0, 1); /* Reserved */ 87 build_append_int_noprefix(entry, 0x1, 4); /* Flags */ 88 build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */ 89 build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */ 90 /* External Interrupt Controller ID */ 91 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 92 build_append_int_noprefix(entry, 93 ACPI_BUILD_INTC_ID( 94 arch_ids->cpus[uid].props.node_id, 95 local_cpu_id), 96 4); 97 } else if (s->aia_type == VIRT_AIA_TYPE_NONE) { 98 build_append_int_noprefix(entry, 99 ACPI_BUILD_INTC_ID( 100 arch_ids->cpus[uid].props.node_id, 101 2 * local_cpu_id + 1), 102 4); 103 } else { 104 build_append_int_noprefix(entry, 0, 4); 105 } 106 107 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 108 /* IMSIC Base address */ 109 build_append_int_noprefix(entry, imsic_addr, 8); 110 /* IMSIC Size */ 111 build_append_int_noprefix(entry, imsic_size, 4); 112 } else { 113 build_append_int_noprefix(entry, 0, 8); 114 build_append_int_noprefix(entry, 0, 4); 115 } 116 } 117 118 static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) 119 { 120 MachineClass *mc = MACHINE_GET_CLASS(s); 121 MachineState *ms = MACHINE(s); 122 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); 123 124 for (int i = 0; i < arch_ids->len; i++) { 125 Aml *dev; 126 GArray *madt_buf = g_array_new(0, 1, 1); 127 128 dev = aml_device("C%.03X", i); 129 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 130 aml_append(dev, aml_name_decl("_UID", 131 aml_int(arch_ids->cpus[i].arch_id))); 132 133 /* build _MAT object */ 134 riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s); 135 aml_append(dev, aml_name_decl("_MAT", 136 aml_buffer(madt_buf->len, 137 (uint8_t *)madt_buf->data))); 138 g_array_free(madt_buf, true); 139 140 aml_append(scope, dev); 141 } 142 } 143 144 static void 145 acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 146 uint32_t uart_irq) 147 { 148 Aml *dev = aml_device("COM0"); 149 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501"))); 150 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 151 152 Aml *crs = aml_resource_template(); 153 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 154 uart_memmap->size, AML_READ_WRITE)); 155 aml_append(crs, 156 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 157 AML_EXCLUSIVE, &uart_irq, 1)); 158 aml_append(dev, aml_name_decl("_CRS", crs)); 159 160 Aml *pkg = aml_package(2); 161 aml_append(pkg, aml_string("clock-frequency")); 162 aml_append(pkg, aml_int(3686400)); 163 164 Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301"); 165 166 Aml *pkg1 = aml_package(1); 167 aml_append(pkg1, pkg); 168 169 Aml *package = aml_package(2); 170 aml_append(package, UUID); 171 aml_append(package, pkg1); 172 173 aml_append(dev, aml_name_decl("_DSD", package)); 174 aml_append(scope, dev); 175 } 176 177 /* 178 * Serial Port Console Redirection Table (SPCR) 179 * Rev: 1.07 180 */ 181 182 static void 183 spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s) 184 { 185 AcpiSpcrData serial = { 186 .interface_type = 0, /* 16550 compatible */ 187 .base_addr.id = AML_AS_SYSTEM_MEMORY, 188 .base_addr.width = 32, 189 .base_addr.offset = 0, 190 .base_addr.size = 1, 191 .base_addr.addr = s->memmap[VIRT_UART0].base, 192 .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */ 193 .pc_interrupt = 0, 194 .interrupt = UART0_IRQ, 195 .baud_rate = 7, /* 15200 */ 196 .parity = 0, 197 .stop_bits = 1, 198 .flow_control = 0, 199 .terminal_type = 3, /* ANSI */ 200 .language = 0, /* Language */ 201 .pci_device_id = 0xffff, /* not a PCI device*/ 202 .pci_vendor_id = 0xffff, /* not a PCI device*/ 203 .pci_bus = 0, 204 .pci_device = 0, 205 .pci_function = 0, 206 .pci_flags = 0, 207 .pci_segment = 0, 208 }; 209 210 build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id); 211 } 212 213 /* RHCT Node[N] starts at offset 56 */ 214 #define RHCT_NODE_ARRAY_OFFSET 56 215 216 /* 217 * ACPI spec, Revision 6.5+ 218 * 5.2.36 RISC-V Hart Capabilities Table (RHCT) 219 * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16 220 * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view 221 * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view 222 */ 223 static void build_rhct(GArray *table_data, 224 BIOSLinker *linker, 225 RISCVVirtState *s) 226 { 227 MachineClass *mc = MACHINE_GET_CLASS(s); 228 MachineState *ms = MACHINE(s); 229 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); 230 size_t len, aligned_len; 231 uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0; 232 RISCVCPU *cpu = &s->soc[0].harts[0]; 233 uint32_t mmu_offset = 0; 234 uint8_t satp_mode_max; 235 g_autofree char *isa = NULL; 236 237 AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, 238 .oem_table_id = s->oem_table_id }; 239 240 acpi_table_begin(&table, table_data); 241 242 build_append_int_noprefix(table_data, 0x0, 4); /* Reserved */ 243 244 /* Time Base Frequency */ 245 build_append_int_noprefix(table_data, 246 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8); 247 248 /* ISA + N hart info */ 249 num_rhct_nodes = 1 + ms->smp.cpus; 250 if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { 251 num_rhct_nodes++; 252 } 253 254 if (cpu->cfg.satp_mode.supported != 0) { 255 num_rhct_nodes++; 256 } 257 258 /* Number of RHCT nodes*/ 259 build_append_int_noprefix(table_data, num_rhct_nodes, 4); 260 261 /* Offset to the RHCT node array */ 262 build_append_int_noprefix(table_data, RHCT_NODE_ARRAY_OFFSET, 4); 263 264 /* ISA String Node */ 265 isa_offset = table_data->len - table.table_offset; 266 build_append_int_noprefix(table_data, 0, 2); /* Type 0 */ 267 268 isa = riscv_isa_string(cpu); 269 len = 8 + strlen(isa) + 1; 270 aligned_len = (len % 2) ? (len + 1) : len; 271 272 build_append_int_noprefix(table_data, aligned_len, 2); /* Length */ 273 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 274 275 /* ISA string length including NUL */ 276 build_append_int_noprefix(table_data, strlen(isa) + 1, 2); 277 g_array_append_vals(table_data, isa, strlen(isa) + 1); /* ISA string */ 278 279 if (aligned_len != len) { 280 build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */ 281 } 282 283 /* CMO node */ 284 if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { 285 cmo_offset = table_data->len - table.table_offset; 286 build_append_int_noprefix(table_data, 1, 2); /* Type */ 287 build_append_int_noprefix(table_data, 10, 2); /* Length */ 288 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 289 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 290 291 /* CBOM block size */ 292 if (cpu->cfg.cbom_blocksize) { 293 build_append_int_noprefix(table_data, 294 __builtin_ctz(cpu->cfg.cbom_blocksize), 295 1); 296 } else { 297 build_append_int_noprefix(table_data, 0, 1); 298 } 299 300 /* CBOP block size */ 301 build_append_int_noprefix(table_data, 0, 1); 302 303 /* CBOZ block size */ 304 if (cpu->cfg.cboz_blocksize) { 305 build_append_int_noprefix(table_data, 306 __builtin_ctz(cpu->cfg.cboz_blocksize), 307 1); 308 } else { 309 build_append_int_noprefix(table_data, 0, 1); 310 } 311 } 312 313 /* MMU node structure */ 314 if (cpu->cfg.satp_mode.supported != 0) { 315 satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 316 mmu_offset = table_data->len - table.table_offset; 317 build_append_int_noprefix(table_data, 2, 2); /* Type */ 318 build_append_int_noprefix(table_data, 8, 2); /* Length */ 319 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 320 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 321 /* MMU Type */ 322 if (satp_mode_max == VM_1_10_SV57) { 323 build_append_int_noprefix(table_data, 2, 1); /* Sv57 */ 324 } else if (satp_mode_max == VM_1_10_SV48) { 325 build_append_int_noprefix(table_data, 1, 1); /* Sv48 */ 326 } else if (satp_mode_max == VM_1_10_SV39) { 327 build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ 328 } else { 329 assert(1); 330 } 331 } 332 333 /* Hart Info Node */ 334 for (int i = 0; i < arch_ids->len; i++) { 335 len = 16; 336 int num_offsets = 1; 337 build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */ 338 339 /* Length */ 340 if (cmo_offset) { 341 len += 4; 342 num_offsets++; 343 } 344 345 if (mmu_offset) { 346 len += 4; 347 num_offsets++; 348 } 349 350 build_append_int_noprefix(table_data, len, 2); 351 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 352 /* Number of offsets */ 353 build_append_int_noprefix(table_data, num_offsets, 2); 354 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 355 /* Offsets */ 356 build_append_int_noprefix(table_data, isa_offset, 4); 357 if (cmo_offset) { 358 build_append_int_noprefix(table_data, cmo_offset, 4); 359 } 360 361 if (mmu_offset) { 362 build_append_int_noprefix(table_data, mmu_offset, 4); 363 } 364 } 365 366 acpi_table_end(linker, &table); 367 } 368 369 /* FADT */ 370 static void build_fadt_rev6(GArray *table_data, 371 BIOSLinker *linker, 372 RISCVVirtState *s, 373 unsigned dsdt_tbl_offset) 374 { 375 AcpiFadtData fadt = { 376 .rev = 6, 377 .minor_ver = 5, 378 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 379 .xdsdt_tbl_offset = &dsdt_tbl_offset, 380 }; 381 382 build_fadt(table_data, linker, &fadt, s->oem_id, s->oem_table_id); 383 } 384 385 /* DSDT */ 386 static void build_dsdt(GArray *table_data, 387 BIOSLinker *linker, 388 RISCVVirtState *s) 389 { 390 Aml *scope, *dsdt; 391 MachineState *ms = MACHINE(s); 392 uint8_t socket_count; 393 const MemMapEntry *memmap = s->memmap; 394 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id, 395 .oem_table_id = s->oem_table_id }; 396 397 398 acpi_table_begin(&table, table_data); 399 dsdt = init_aml_allocator(); 400 401 /* 402 * When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 403 * While UEFI can use libfdt to disable the RTC device node in the DTB that 404 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 405 * the RTC ACPI device at all when using UEFI. 406 */ 407 scope = aml_scope("\\_SB"); 408 acpi_dsdt_add_cpus(scope, s); 409 410 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); 411 412 socket_count = riscv_socket_count(ms); 413 414 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ); 415 416 if (socket_count == 1) { 417 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, 418 memmap[VIRT_VIRTIO].size, 419 VIRTIO_IRQ, 0, VIRTIO_COUNT); 420 acpi_dsdt_add_gpex_host(scope, PCIE_IRQ); 421 } else if (socket_count == 2) { 422 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, 423 memmap[VIRT_VIRTIO].size, 424 VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0, 425 VIRTIO_COUNT); 426 acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES); 427 } else { 428 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, 429 memmap[VIRT_VIRTIO].size, 430 VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0, 431 VIRTIO_COUNT); 432 acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2); 433 } 434 435 aml_append(dsdt, scope); 436 437 /* copy AML table into ACPI tables blob and patch header there */ 438 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 439 440 acpi_table_end(linker, &table); 441 free_aml_allocator(); 442 } 443 444 /* 445 * ACPI spec, Revision 6.5+ 446 * 5.2.12 Multiple APIC Description Table (MADT) 447 * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15 448 * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view 449 * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view 450 */ 451 static void build_madt(GArray *table_data, 452 BIOSLinker *linker, 453 RISCVVirtState *s) 454 { 455 MachineClass *mc = MACHINE_GET_CLASS(s); 456 MachineState *ms = MACHINE(s); 457 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); 458 uint8_t group_index_bits = imsic_num_bits(riscv_socket_count(ms)); 459 uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); 460 uint16_t imsic_max_hart_per_socket = 0; 461 uint8_t hart_index_bits; 462 uint64_t aplic_addr; 463 uint32_t gsi_base; 464 uint8_t socket; 465 466 for (socket = 0; socket < riscv_socket_count(ms); socket++) { 467 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 468 imsic_max_hart_per_socket = s->soc[socket].num_harts; 469 } 470 } 471 472 hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket); 473 474 AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id, 475 .oem_table_id = s->oem_table_id }; 476 477 acpi_table_begin(&table, table_data); 478 /* Local Interrupt Controller Address */ 479 build_append_int_noprefix(table_data, 0, 4); 480 build_append_int_noprefix(table_data, 0, 4); /* MADT Flags */ 481 482 /* RISC-V Local INTC structures per HART */ 483 for (int i = 0; i < arch_ids->len; i++) { 484 riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s); 485 } 486 487 /* IMSIC */ 488 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 489 /* IMSIC */ 490 build_append_int_noprefix(table_data, 0x19, 1); /* Type */ 491 build_append_int_noprefix(table_data, 16, 1); /* Length */ 492 build_append_int_noprefix(table_data, 1, 1); /* Version */ 493 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 494 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 495 /* Number of supervisor mode Interrupt Identities */ 496 build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2); 497 /* Number of guest mode Interrupt Identities */ 498 build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2); 499 /* Guest Index Bits */ 500 build_append_int_noprefix(table_data, guest_index_bits, 1); 501 /* Hart Index Bits */ 502 build_append_int_noprefix(table_data, hart_index_bits, 1); 503 /* Group Index Bits */ 504 build_append_int_noprefix(table_data, group_index_bits, 1); 505 /* Group Index Shift */ 506 build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1); 507 } 508 509 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 510 /* APLICs */ 511 for (socket = 0; socket < riscv_socket_count(ms); socket++) { 512 aplic_addr = s->memmap[VIRT_APLIC_S].base + 513 s->memmap[VIRT_APLIC_S].size * socket; 514 gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; 515 build_append_int_noprefix(table_data, 0x1A, 1); /* Type */ 516 build_append_int_noprefix(table_data, 36, 1); /* Length */ 517 build_append_int_noprefix(table_data, 1, 1); /* Version */ 518 build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */ 519 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 520 build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */ 521 /* Number of IDCs */ 522 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 523 build_append_int_noprefix(table_data, 524 s->soc[socket].num_harts, 525 2); 526 } else { 527 build_append_int_noprefix(table_data, 0, 2); 528 } 529 /* Total External Interrupt Sources Supported */ 530 build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2); 531 /* Global System Interrupt Base */ 532 build_append_int_noprefix(table_data, gsi_base, 4); 533 /* APLIC Address */ 534 build_append_int_noprefix(table_data, aplic_addr, 8); 535 /* APLIC size */ 536 build_append_int_noprefix(table_data, 537 s->memmap[VIRT_APLIC_S].size, 4); 538 } 539 } else { 540 /* PLICs */ 541 for (socket = 0; socket < riscv_socket_count(ms); socket++) { 542 aplic_addr = s->memmap[VIRT_PLIC].base + 543 s->memmap[VIRT_PLIC].size * socket; 544 gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; 545 build_append_int_noprefix(table_data, 0x1B, 1); /* Type */ 546 build_append_int_noprefix(table_data, 36, 1); /* Length */ 547 build_append_int_noprefix(table_data, 1, 1); /* Version */ 548 build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */ 549 build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */ 550 /* Total External Interrupt Sources Supported */ 551 build_append_int_noprefix(table_data, 552 VIRT_IRQCHIP_NUM_SOURCES - 1, 2); 553 build_append_int_noprefix(table_data, 0, 2); /* Max Priority */ 554 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 555 /* PLIC Size */ 556 build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size, 4); 557 /* PLIC Address */ 558 build_append_int_noprefix(table_data, aplic_addr, 8); 559 /* Global System Interrupt Vector Base */ 560 build_append_int_noprefix(table_data, gsi_base, 4); 561 } 562 } 563 564 acpi_table_end(linker, &table); 565 } 566 567 /* 568 * ACPI spec, Revision 6.5+ 569 * 5.2.16 System Resource Affinity Table (SRAT) 570 * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/25 571 * https://drive.google.com/file/d/1YTdDx2IPm5IeZjAW932EYU-tUtgS08tX/view 572 */ 573 static void 574 build_srat(GArray *table_data, BIOSLinker *linker, RISCVVirtState *vms) 575 { 576 int i; 577 uint64_t mem_base; 578 MachineClass *mc = MACHINE_GET_CLASS(vms); 579 MachineState *ms = MACHINE(vms); 580 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 581 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, 582 .oem_table_id = vms->oem_table_id }; 583 584 acpi_table_begin(&table, table_data); 585 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 586 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 587 588 for (i = 0; i < cpu_list->len; ++i) { 589 uint32_t nodeid = cpu_list->cpus[i].props.node_id; 590 /* 591 * 5.2.16.8 RINTC Affinity Structure 592 */ 593 build_append_int_noprefix(table_data, 7, 1); /* Type */ 594 build_append_int_noprefix(table_data, 20, 1); /* Length */ 595 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 596 build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ 597 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 598 /* Flags, Table 5-70 */ 599 build_append_int_noprefix(table_data, 1 /* Flags: Enabled */, 4); 600 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 601 } 602 603 mem_base = vms->memmap[VIRT_DRAM].base; 604 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 605 if (ms->numa_state->nodes[i].node_mem > 0) { 606 build_srat_memory(table_data, mem_base, 607 ms->numa_state->nodes[i].node_mem, i, 608 MEM_AFFINITY_ENABLED); 609 mem_base += ms->numa_state->nodes[i].node_mem; 610 } 611 } 612 613 acpi_table_end(linker, &table); 614 } 615 616 static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) 617 { 618 GArray *table_offsets; 619 unsigned dsdt, xsdt; 620 GArray *tables_blob = tables->table_data; 621 MachineState *ms = MACHINE(s); 622 623 table_offsets = g_array_new(false, true, 624 sizeof(uint32_t)); 625 626 bios_linker_loader_alloc(tables->linker, 627 ACPI_BUILD_TABLE_FILE, tables_blob, 628 64, false); 629 630 /* DSDT is pointed to by FADT */ 631 dsdt = tables_blob->len; 632 build_dsdt(tables_blob, tables->linker, s); 633 634 /* FADT and others pointed to by XSDT */ 635 acpi_add_table(table_offsets, tables_blob); 636 build_fadt_rev6(tables_blob, tables->linker, s, dsdt); 637 638 acpi_add_table(table_offsets, tables_blob); 639 build_madt(tables_blob, tables->linker, s); 640 641 acpi_add_table(table_offsets, tables_blob); 642 build_rhct(tables_blob, tables->linker, s); 643 644 acpi_add_table(table_offsets, tables_blob); 645 spcr_setup(tables_blob, tables->linker, s); 646 647 acpi_add_table(table_offsets, tables_blob); 648 { 649 AcpiMcfgInfo mcfg = { 650 .base = s->memmap[VIRT_PCIE_ECAM].base, 651 .size = s->memmap[VIRT_PCIE_ECAM].size, 652 }; 653 build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id, 654 s->oem_table_id); 655 } 656 657 if (ms->numa_state->num_nodes > 0) { 658 acpi_add_table(table_offsets, tables_blob); 659 build_srat(tables_blob, tables->linker, s); 660 if (ms->numa_state->have_numa_distance) { 661 acpi_add_table(table_offsets, tables_blob); 662 build_slit(tables_blob, tables->linker, ms, s->oem_id, 663 s->oem_table_id); 664 } 665 } 666 667 /* XSDT is pointed to by RSDP */ 668 xsdt = tables_blob->len; 669 build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id, 670 s->oem_table_id); 671 672 /* RSDP is in FSEG memory, so allocate it separately */ 673 { 674 AcpiRsdpData rsdp_data = { 675 .revision = 2, 676 .oem_id = s->oem_id, 677 .xsdt_tbl_offset = &xsdt, 678 .rsdt_tbl_offset = NULL, 679 }; 680 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 681 } 682 683 /* 684 * The align size is 128, warn if 64k is not enough therefore 685 * the align size could be resized. 686 */ 687 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 688 warn_report("ACPI table size %u exceeds %d bytes," 689 " migration may not work", 690 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 691 error_printf("Try removing some objects."); 692 } 693 694 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 695 696 /* Clean up memory that's no longer used */ 697 g_array_free(table_offsets, true); 698 } 699 700 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 701 { 702 uint32_t size = acpi_data_len(data); 703 704 /* 705 * Make sure RAM size is correct - in case it got changed 706 * e.g. by migration 707 */ 708 memory_region_ram_resize(mr, size, &error_abort); 709 710 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 711 memory_region_set_dirty(mr, 0, size); 712 } 713 714 static void virt_acpi_build_update(void *build_opaque) 715 { 716 AcpiBuildState *build_state = build_opaque; 717 AcpiBuildTables tables; 718 719 /* No state to update or already patched? Nothing to do. */ 720 if (!build_state || build_state->patched) { 721 return; 722 } 723 724 build_state->patched = true; 725 726 acpi_build_tables_init(&tables); 727 728 virt_acpi_build(RISCV_VIRT_MACHINE(qdev_get_machine()), &tables); 729 730 acpi_ram_update(build_state->table_mr, tables.table_data); 731 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 732 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 733 734 acpi_build_tables_cleanup(&tables, true); 735 } 736 737 static void virt_acpi_build_reset(void *build_opaque) 738 { 739 AcpiBuildState *build_state = build_opaque; 740 build_state->patched = false; 741 } 742 743 static const VMStateDescription vmstate_virt_acpi_build = { 744 .name = "virt_acpi_build", 745 .version_id = 1, 746 .minimum_version_id = 1, 747 .fields = (const VMStateField[]) { 748 VMSTATE_BOOL(patched, AcpiBuildState), 749 VMSTATE_END_OF_LIST() 750 }, 751 }; 752 753 void virt_acpi_setup(RISCVVirtState *s) 754 { 755 AcpiBuildTables tables; 756 AcpiBuildState *build_state; 757 758 build_state = g_malloc0(sizeof *build_state); 759 760 acpi_build_tables_init(&tables); 761 virt_acpi_build(s, &tables); 762 763 /* Now expose it all to Guest */ 764 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 765 build_state, tables.table_data, 766 ACPI_BUILD_TABLE_FILE); 767 assert(build_state->table_mr != NULL); 768 769 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, 770 build_state, 771 tables.linker->cmd_blob, 772 ACPI_BUILD_LOADER_FILE); 773 774 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 775 build_state, tables.rsdp, 776 ACPI_BUILD_RSDP_FILE); 777 778 qemu_register_reset(virt_acpi_build_reset, build_state); 779 virt_acpi_build_reset(build_state); 780 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 781 782 /* 783 * Clean up tables but don't free the memory: we track it 784 * in build_state. 785 */ 786 acpi_build_tables_cleanup(&tables, false); 787 } 788