1 /* 2 * Support for generating ACPI tables and passing them to Guests 3 * 4 * RISC-V virt ACPI generation 5 * 6 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 7 * Copyright (C) 2006 Fabrice Bellard 8 * Copyright (C) 2013 Red Hat Inc 9 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 10 * Copyright (C) 2021-2023 Ventana Micro Systems Inc 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 22 * You should have received a copy of the GNU General Public License along 23 * with this program; if not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/acpi/acpi-defs.h" 28 #include "hw/acpi/acpi.h" 29 #include "hw/acpi/aml-build.h" 30 #include "hw/acpi/pci.h" 31 #include "hw/acpi/utils.h" 32 #include "hw/intc/riscv_aclint.h" 33 #include "hw/nvram/fw_cfg_acpi.h" 34 #include "hw/pci-host/gpex.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/numa.h" 37 #include "hw/virtio/virtio-acpi.h" 38 #include "migration/vmstate.h" 39 #include "qapi/error.h" 40 #include "qemu/error-report.h" 41 #include "sysemu/reset.h" 42 43 #define ACPI_BUILD_TABLE_SIZE 0x20000 44 #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) 45 46 typedef struct AcpiBuildState { 47 /* Copy of table in RAM (for patching) */ 48 MemoryRegion *table_mr; 49 MemoryRegion *rsdp_mr; 50 MemoryRegion *linker_mr; 51 /* Is table patched? */ 52 bool patched; 53 } AcpiBuildState; 54 55 static void acpi_align_size(GArray *blob, unsigned align) 56 { 57 /* 58 * Align size to multiple of given size. This reduces the chance 59 * we need to change size in the future (breaking cross version migration). 60 */ 61 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 62 } 63 64 static void riscv_acpi_madt_add_rintc(uint32_t uid, 65 const CPUArchIdList *arch_ids, 66 GArray *entry, 67 RISCVVirtState *s) 68 { 69 uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); 70 uint64_t hart_id = arch_ids->cpus[uid].arch_id; 71 uint32_t imsic_size, local_cpu_id, socket_id; 72 uint64_t imsic_socket_addr, imsic_addr; 73 MachineState *ms = MACHINE(s); 74 75 socket_id = arch_ids->cpus[uid].props.node_id; 76 local_cpu_id = (arch_ids->cpus[uid].arch_id - 77 riscv_socket_first_hartid(ms, socket_id)) % 78 riscv_socket_hart_count(ms, socket_id); 79 imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + 80 (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE); 81 imsic_size = IMSIC_HART_SIZE(guest_index_bits); 82 imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size; 83 build_append_int_noprefix(entry, 0x18, 1); /* Type */ 84 build_append_int_noprefix(entry, 36, 1); /* Length */ 85 build_append_int_noprefix(entry, 1, 1); /* Version */ 86 build_append_int_noprefix(entry, 0, 1); /* Reserved */ 87 build_append_int_noprefix(entry, 0x1, 4); /* Flags */ 88 build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */ 89 build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */ 90 /* External Interrupt Controller ID */ 91 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 92 build_append_int_noprefix(entry, 93 ACPI_BUILD_INTC_ID( 94 arch_ids->cpus[uid].props.node_id, 95 local_cpu_id), 96 4); 97 } else if (s->aia_type == VIRT_AIA_TYPE_NONE) { 98 build_append_int_noprefix(entry, 99 ACPI_BUILD_INTC_ID( 100 arch_ids->cpus[uid].props.node_id, 101 2 * local_cpu_id + 1), 102 4); 103 } else { 104 build_append_int_noprefix(entry, 0, 4); 105 } 106 107 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 108 /* IMSIC Base address */ 109 build_append_int_noprefix(entry, imsic_addr, 8); 110 /* IMSIC Size */ 111 build_append_int_noprefix(entry, imsic_size, 4); 112 } else { 113 build_append_int_noprefix(entry, 0, 8); 114 build_append_int_noprefix(entry, 0, 4); 115 } 116 } 117 118 static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) 119 { 120 MachineClass *mc = MACHINE_GET_CLASS(s); 121 MachineState *ms = MACHINE(s); 122 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); 123 124 for (int i = 0; i < arch_ids->len; i++) { 125 Aml *dev; 126 GArray *madt_buf = g_array_new(0, 1, 1); 127 128 dev = aml_device("C%.03X", i); 129 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 130 aml_append(dev, aml_name_decl("_UID", 131 aml_int(arch_ids->cpus[i].arch_id))); 132 133 /* build _MAT object */ 134 riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s); 135 aml_append(dev, aml_name_decl("_MAT", 136 aml_buffer(madt_buf->len, 137 (uint8_t *)madt_buf->data))); 138 g_array_free(madt_buf, true); 139 140 aml_append(scope, dev); 141 } 142 } 143 144 static void 145 acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 146 uint32_t uart_irq) 147 { 148 Aml *dev = aml_device("COM0"); 149 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501"))); 150 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 151 152 Aml *crs = aml_resource_template(); 153 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 154 uart_memmap->size, AML_READ_WRITE)); 155 aml_append(crs, 156 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 157 AML_EXCLUSIVE, &uart_irq, 1)); 158 aml_append(dev, aml_name_decl("_CRS", crs)); 159 160 Aml *pkg = aml_package(2); 161 aml_append(pkg, aml_string("clock-frequency")); 162 aml_append(pkg, aml_int(3686400)); 163 164 Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301"); 165 166 Aml *pkg1 = aml_package(1); 167 aml_append(pkg1, pkg); 168 169 Aml *package = aml_package(2); 170 aml_append(package, UUID); 171 aml_append(package, pkg1); 172 173 aml_append(dev, aml_name_decl("_DSD", package)); 174 aml_append(scope, dev); 175 } 176 177 /* RHCT Node[N] starts at offset 56 */ 178 #define RHCT_NODE_ARRAY_OFFSET 56 179 180 /* 181 * ACPI spec, Revision 6.5+ 182 * 5.2.36 RISC-V Hart Capabilities Table (RHCT) 183 * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16 184 * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view 185 * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view 186 */ 187 static void build_rhct(GArray *table_data, 188 BIOSLinker *linker, 189 RISCVVirtState *s) 190 { 191 MachineClass *mc = MACHINE_GET_CLASS(s); 192 MachineState *ms = MACHINE(s); 193 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); 194 size_t len, aligned_len; 195 uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0; 196 RISCVCPU *cpu = &s->soc[0].harts[0]; 197 uint32_t mmu_offset = 0; 198 uint8_t satp_mode_max; 199 char *isa; 200 201 AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, 202 .oem_table_id = s->oem_table_id }; 203 204 acpi_table_begin(&table, table_data); 205 206 build_append_int_noprefix(table_data, 0x0, 4); /* Reserved */ 207 208 /* Time Base Frequency */ 209 build_append_int_noprefix(table_data, 210 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8); 211 212 /* ISA + N hart info */ 213 num_rhct_nodes = 1 + ms->smp.cpus; 214 if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { 215 num_rhct_nodes++; 216 } 217 218 if (cpu->cfg.satp_mode.supported != 0) { 219 num_rhct_nodes++; 220 } 221 222 /* Number of RHCT nodes*/ 223 build_append_int_noprefix(table_data, num_rhct_nodes, 4); 224 225 /* Offset to the RHCT node array */ 226 build_append_int_noprefix(table_data, RHCT_NODE_ARRAY_OFFSET, 4); 227 228 /* ISA String Node */ 229 isa_offset = table_data->len - table.table_offset; 230 build_append_int_noprefix(table_data, 0, 2); /* Type 0 */ 231 232 isa = riscv_isa_string(cpu); 233 len = 8 + strlen(isa) + 1; 234 aligned_len = (len % 2) ? (len + 1) : len; 235 236 build_append_int_noprefix(table_data, aligned_len, 2); /* Length */ 237 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 238 239 /* ISA string length including NUL */ 240 build_append_int_noprefix(table_data, strlen(isa) + 1, 2); 241 g_array_append_vals(table_data, isa, strlen(isa) + 1); /* ISA string */ 242 243 if (aligned_len != len) { 244 build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */ 245 } 246 247 /* CMO node */ 248 if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { 249 cmo_offset = table_data->len - table.table_offset; 250 build_append_int_noprefix(table_data, 1, 2); /* Type */ 251 build_append_int_noprefix(table_data, 10, 2); /* Length */ 252 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 253 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 254 255 /* CBOM block size */ 256 if (cpu->cfg.cbom_blocksize) { 257 build_append_int_noprefix(table_data, 258 __builtin_ctz(cpu->cfg.cbom_blocksize), 259 1); 260 } else { 261 build_append_int_noprefix(table_data, 0, 1); 262 } 263 264 /* CBOP block size */ 265 build_append_int_noprefix(table_data, 0, 1); 266 267 /* CBOZ block size */ 268 if (cpu->cfg.cboz_blocksize) { 269 build_append_int_noprefix(table_data, 270 __builtin_ctz(cpu->cfg.cboz_blocksize), 271 1); 272 } else { 273 build_append_int_noprefix(table_data, 0, 1); 274 } 275 } 276 277 /* MMU node structure */ 278 if (cpu->cfg.satp_mode.supported != 0) { 279 satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 280 mmu_offset = table_data->len - table.table_offset; 281 build_append_int_noprefix(table_data, 2, 2); /* Type */ 282 build_append_int_noprefix(table_data, 8, 2); /* Length */ 283 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 284 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 285 /* MMU Type */ 286 if (satp_mode_max == VM_1_10_SV57) { 287 build_append_int_noprefix(table_data, 2, 1); /* Sv57 */ 288 } else if (satp_mode_max == VM_1_10_SV48) { 289 build_append_int_noprefix(table_data, 1, 1); /* Sv48 */ 290 } else if (satp_mode_max == VM_1_10_SV39) { 291 build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ 292 } else { 293 assert(1); 294 } 295 } 296 297 /* Hart Info Node */ 298 for (int i = 0; i < arch_ids->len; i++) { 299 len = 16; 300 int num_offsets = 1; 301 build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */ 302 303 /* Length */ 304 if (cmo_offset) { 305 len += 4; 306 num_offsets++; 307 } 308 309 if (mmu_offset) { 310 len += 4; 311 num_offsets++; 312 } 313 314 build_append_int_noprefix(table_data, len, 2); 315 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 316 /* Number of offsets */ 317 build_append_int_noprefix(table_data, num_offsets, 2); 318 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 319 /* Offsets */ 320 build_append_int_noprefix(table_data, isa_offset, 4); 321 if (cmo_offset) { 322 build_append_int_noprefix(table_data, cmo_offset, 4); 323 } 324 325 if (mmu_offset) { 326 build_append_int_noprefix(table_data, mmu_offset, 4); 327 } 328 } 329 330 acpi_table_end(linker, &table); 331 } 332 333 /* FADT */ 334 static void build_fadt_rev6(GArray *table_data, 335 BIOSLinker *linker, 336 RISCVVirtState *s, 337 unsigned dsdt_tbl_offset) 338 { 339 AcpiFadtData fadt = { 340 .rev = 6, 341 .minor_ver = 5, 342 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 343 .xdsdt_tbl_offset = &dsdt_tbl_offset, 344 }; 345 346 build_fadt(table_data, linker, &fadt, s->oem_id, s->oem_table_id); 347 } 348 349 /* DSDT */ 350 static void build_dsdt(GArray *table_data, 351 BIOSLinker *linker, 352 RISCVVirtState *s) 353 { 354 Aml *scope, *dsdt; 355 MachineState *ms = MACHINE(s); 356 uint8_t socket_count; 357 const MemMapEntry *memmap = s->memmap; 358 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id, 359 .oem_table_id = s->oem_table_id }; 360 361 362 acpi_table_begin(&table, table_data); 363 dsdt = init_aml_allocator(); 364 365 /* 366 * When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 367 * While UEFI can use libfdt to disable the RTC device node in the DTB that 368 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 369 * the RTC ACPI device at all when using UEFI. 370 */ 371 scope = aml_scope("\\_SB"); 372 acpi_dsdt_add_cpus(scope, s); 373 374 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); 375 376 socket_count = riscv_socket_count(ms); 377 378 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ); 379 380 if (socket_count == 1) { 381 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, 382 memmap[VIRT_VIRTIO].size, 383 VIRTIO_IRQ, 0, VIRTIO_COUNT); 384 acpi_dsdt_add_gpex_host(scope, PCIE_IRQ); 385 } else if (socket_count == 2) { 386 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, 387 memmap[VIRT_VIRTIO].size, 388 VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0, 389 VIRTIO_COUNT); 390 acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES); 391 } else { 392 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, 393 memmap[VIRT_VIRTIO].size, 394 VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0, 395 VIRTIO_COUNT); 396 acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2); 397 } 398 399 aml_append(dsdt, scope); 400 401 /* copy AML table into ACPI tables blob and patch header there */ 402 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 403 404 acpi_table_end(linker, &table); 405 free_aml_allocator(); 406 } 407 408 /* 409 * ACPI spec, Revision 6.5+ 410 * 5.2.12 Multiple APIC Description Table (MADT) 411 * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15 412 * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view 413 * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view 414 */ 415 static void build_madt(GArray *table_data, 416 BIOSLinker *linker, 417 RISCVVirtState *s) 418 { 419 MachineClass *mc = MACHINE_GET_CLASS(s); 420 MachineState *ms = MACHINE(s); 421 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); 422 uint8_t group_index_bits = imsic_num_bits(riscv_socket_count(ms)); 423 uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); 424 uint16_t imsic_max_hart_per_socket = 0; 425 uint8_t hart_index_bits; 426 uint64_t aplic_addr; 427 uint32_t gsi_base; 428 uint8_t socket; 429 430 for (socket = 0; socket < riscv_socket_count(ms); socket++) { 431 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 432 imsic_max_hart_per_socket = s->soc[socket].num_harts; 433 } 434 } 435 436 hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket); 437 438 AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id, 439 .oem_table_id = s->oem_table_id }; 440 441 acpi_table_begin(&table, table_data); 442 /* Local Interrupt Controller Address */ 443 build_append_int_noprefix(table_data, 0, 4); 444 build_append_int_noprefix(table_data, 0, 4); /* MADT Flags */ 445 446 /* RISC-V Local INTC structures per HART */ 447 for (int i = 0; i < arch_ids->len; i++) { 448 riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s); 449 } 450 451 /* IMSIC */ 452 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 453 /* IMSIC */ 454 build_append_int_noprefix(table_data, 0x19, 1); /* Type */ 455 build_append_int_noprefix(table_data, 16, 1); /* Length */ 456 build_append_int_noprefix(table_data, 1, 1); /* Version */ 457 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 458 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 459 /* Number of supervisor mode Interrupt Identities */ 460 build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2); 461 /* Number of guest mode Interrupt Identities */ 462 build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2); 463 /* Guest Index Bits */ 464 build_append_int_noprefix(table_data, guest_index_bits, 1); 465 /* Hart Index Bits */ 466 build_append_int_noprefix(table_data, hart_index_bits, 1); 467 /* Group Index Bits */ 468 build_append_int_noprefix(table_data, group_index_bits, 1); 469 /* Group Index Shift */ 470 build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1); 471 } 472 473 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 474 /* APLICs */ 475 for (socket = 0; socket < riscv_socket_count(ms); socket++) { 476 aplic_addr = s->memmap[VIRT_APLIC_S].base + 477 s->memmap[VIRT_APLIC_S].size * socket; 478 gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; 479 build_append_int_noprefix(table_data, 0x1A, 1); /* Type */ 480 build_append_int_noprefix(table_data, 36, 1); /* Length */ 481 build_append_int_noprefix(table_data, 1, 1); /* Version */ 482 build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */ 483 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 484 build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */ 485 /* Number of IDCs */ 486 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 487 build_append_int_noprefix(table_data, 488 s->soc[socket].num_harts, 489 2); 490 } else { 491 build_append_int_noprefix(table_data, 0, 2); 492 } 493 /* Total External Interrupt Sources Supported */ 494 build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2); 495 /* Global System Interrupt Base */ 496 build_append_int_noprefix(table_data, gsi_base, 4); 497 /* APLIC Address */ 498 build_append_int_noprefix(table_data, aplic_addr, 8); 499 /* APLIC size */ 500 build_append_int_noprefix(table_data, 501 s->memmap[VIRT_APLIC_S].size, 4); 502 } 503 } else { 504 /* PLICs */ 505 for (socket = 0; socket < riscv_socket_count(ms); socket++) { 506 aplic_addr = s->memmap[VIRT_PLIC].base + 507 s->memmap[VIRT_PLIC].size * socket; 508 gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; 509 build_append_int_noprefix(table_data, 0x1B, 1); /* Type */ 510 build_append_int_noprefix(table_data, 36, 1); /* Length */ 511 build_append_int_noprefix(table_data, 1, 1); /* Version */ 512 build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */ 513 build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */ 514 /* Total External Interrupt Sources Supported */ 515 build_append_int_noprefix(table_data, 516 VIRT_IRQCHIP_NUM_SOURCES - 1, 2); 517 build_append_int_noprefix(table_data, 0, 2); /* Max Priority */ 518 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 519 /* PLIC Size */ 520 build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size, 4); 521 /* PLIC Address */ 522 build_append_int_noprefix(table_data, aplic_addr, 8); 523 /* Global System Interrupt Vector Base */ 524 build_append_int_noprefix(table_data, gsi_base, 4); 525 } 526 } 527 528 acpi_table_end(linker, &table); 529 } 530 531 static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) 532 { 533 GArray *table_offsets; 534 unsigned dsdt, xsdt; 535 GArray *tables_blob = tables->table_data; 536 537 table_offsets = g_array_new(false, true, 538 sizeof(uint32_t)); 539 540 bios_linker_loader_alloc(tables->linker, 541 ACPI_BUILD_TABLE_FILE, tables_blob, 542 64, false); 543 544 /* DSDT is pointed to by FADT */ 545 dsdt = tables_blob->len; 546 build_dsdt(tables_blob, tables->linker, s); 547 548 /* FADT and others pointed to by XSDT */ 549 acpi_add_table(table_offsets, tables_blob); 550 build_fadt_rev6(tables_blob, tables->linker, s, dsdt); 551 552 acpi_add_table(table_offsets, tables_blob); 553 build_madt(tables_blob, tables->linker, s); 554 555 acpi_add_table(table_offsets, tables_blob); 556 build_rhct(tables_blob, tables->linker, s); 557 558 acpi_add_table(table_offsets, tables_blob); 559 { 560 AcpiMcfgInfo mcfg = { 561 .base = s->memmap[VIRT_PCIE_MMIO].base, 562 .size = s->memmap[VIRT_PCIE_MMIO].size, 563 }; 564 build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id, 565 s->oem_table_id); 566 } 567 568 /* XSDT is pointed to by RSDP */ 569 xsdt = tables_blob->len; 570 build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id, 571 s->oem_table_id); 572 573 /* RSDP is in FSEG memory, so allocate it separately */ 574 { 575 AcpiRsdpData rsdp_data = { 576 .revision = 2, 577 .oem_id = s->oem_id, 578 .xsdt_tbl_offset = &xsdt, 579 .rsdt_tbl_offset = NULL, 580 }; 581 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 582 } 583 584 /* 585 * The align size is 128, warn if 64k is not enough therefore 586 * the align size could be resized. 587 */ 588 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 589 warn_report("ACPI table size %u exceeds %d bytes," 590 " migration may not work", 591 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 592 error_printf("Try removing some objects."); 593 } 594 595 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 596 597 /* Clean up memory that's no longer used */ 598 g_array_free(table_offsets, true); 599 } 600 601 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 602 { 603 uint32_t size = acpi_data_len(data); 604 605 /* 606 * Make sure RAM size is correct - in case it got changed 607 * e.g. by migration 608 */ 609 memory_region_ram_resize(mr, size, &error_abort); 610 611 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 612 memory_region_set_dirty(mr, 0, size); 613 } 614 615 static void virt_acpi_build_update(void *build_opaque) 616 { 617 AcpiBuildState *build_state = build_opaque; 618 AcpiBuildTables tables; 619 620 /* No state to update or already patched? Nothing to do. */ 621 if (!build_state || build_state->patched) { 622 return; 623 } 624 625 build_state->patched = true; 626 627 acpi_build_tables_init(&tables); 628 629 virt_acpi_build(RISCV_VIRT_MACHINE(qdev_get_machine()), &tables); 630 631 acpi_ram_update(build_state->table_mr, tables.table_data); 632 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 633 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 634 635 acpi_build_tables_cleanup(&tables, true); 636 } 637 638 static void virt_acpi_build_reset(void *build_opaque) 639 { 640 AcpiBuildState *build_state = build_opaque; 641 build_state->patched = false; 642 } 643 644 static const VMStateDescription vmstate_virt_acpi_build = { 645 .name = "virt_acpi_build", 646 .version_id = 1, 647 .minimum_version_id = 1, 648 .fields = (const VMStateField[]) { 649 VMSTATE_BOOL(patched, AcpiBuildState), 650 VMSTATE_END_OF_LIST() 651 }, 652 }; 653 654 void virt_acpi_setup(RISCVVirtState *s) 655 { 656 AcpiBuildTables tables; 657 AcpiBuildState *build_state; 658 659 build_state = g_malloc0(sizeof *build_state); 660 661 acpi_build_tables_init(&tables); 662 virt_acpi_build(s, &tables); 663 664 /* Now expose it all to Guest */ 665 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 666 build_state, tables.table_data, 667 ACPI_BUILD_TABLE_FILE); 668 assert(build_state->table_mr != NULL); 669 670 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, 671 build_state, 672 tables.linker->cmd_blob, 673 ACPI_BUILD_LOADER_FILE); 674 675 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 676 build_state, tables.rsdp, 677 ACPI_BUILD_RSDP_FILE); 678 679 qemu_register_reset(virt_acpi_build_reset, build_state); 680 virt_acpi_build_reset(build_state); 681 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 682 683 /* 684 * Clean up tables but don't free the memory: we track it 685 * in build_state. 686 */ 687 acpi_build_tables_cleanup(&tables, false); 688 } 689