1 /* 2 * QEMU RISC-V Spike Board 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This provides a RISC-V Board with the following devices: 8 * 9 * 0) HTIF Console and Poweroff 10 * 1) CLINT (Timer and IPI) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms and conditions of the GNU General Public License, 15 * version 2 or later, as published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * You should have received a copy of the GNU General Public License along with 23 * this program. If not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/log.h" 28 #include "qemu/error-report.h" 29 #include "qapi/error.h" 30 #include "hw/boards.h" 31 #include "hw/loader.h" 32 #include "hw/sysbus.h" 33 #include "target/riscv/cpu.h" 34 #include "hw/riscv/riscv_htif.h" 35 #include "hw/riscv/riscv_hart.h" 36 #include "hw/riscv/sifive_clint.h" 37 #include "hw/riscv/spike.h" 38 #include "hw/riscv/boot.h" 39 #include "chardev/char.h" 40 #include "sysemu/arch_init.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/qtest.h" 43 #include "sysemu/sysemu.h" 44 #include "exec/address-spaces.h" 45 46 #include <libfdt.h> 47 48 static const struct MemmapEntry { 49 hwaddr base; 50 hwaddr size; 51 } spike_memmap[] = { 52 [SPIKE_MROM] = { 0x1000, 0x11000 }, 53 [SPIKE_CLINT] = { 0x2000000, 0x10000 }, 54 [SPIKE_DRAM] = { 0x80000000, 0x0 }, 55 }; 56 57 static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, 58 uint64_t mem_size, const char *cmdline) 59 { 60 void *fdt; 61 int cpu; 62 uint32_t *cells; 63 char *nodename; 64 65 fdt = s->fdt = create_device_tree(&s->fdt_size); 66 if (!fdt) { 67 error_report("create_device_tree() failed"); 68 exit(1); 69 } 70 71 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 72 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 73 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 74 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 75 76 qemu_fdt_add_subnode(fdt, "/htif"); 77 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); 78 79 qemu_fdt_add_subnode(fdt, "/soc"); 80 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 81 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 82 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 83 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 84 85 nodename = g_strdup_printf("/memory@%lx", 86 (long)memmap[SPIKE_DRAM].base); 87 qemu_fdt_add_subnode(fdt, nodename); 88 qemu_fdt_setprop_cells(fdt, nodename, "reg", 89 memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base, 90 mem_size >> 32, mem_size); 91 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 92 g_free(nodename); 93 94 qemu_fdt_add_subnode(fdt, "/cpus"); 95 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 96 SIFIVE_CLINT_TIMEBASE_FREQ); 97 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 98 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 99 100 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { 101 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 102 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 103 char *isa = riscv_isa_string(&s->soc.harts[cpu]); 104 qemu_fdt_add_subnode(fdt, nodename); 105 #if defined(TARGET_RISCV32) 106 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 107 #else 108 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 109 #endif 110 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 111 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 112 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 113 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 114 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 115 qemu_fdt_add_subnode(fdt, intc); 116 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); 117 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 118 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 119 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 120 g_free(isa); 121 g_free(intc); 122 g_free(nodename); 123 } 124 125 cells = g_new0(uint32_t, s->soc.num_harts * 4); 126 for (cpu = 0; cpu < s->soc.num_harts; cpu++) { 127 nodename = 128 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 129 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 130 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 131 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 132 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 133 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 134 g_free(nodename); 135 } 136 nodename = g_strdup_printf("/soc/clint@%lx", 137 (long)memmap[SPIKE_CLINT].base); 138 qemu_fdt_add_subnode(fdt, nodename); 139 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 140 qemu_fdt_setprop_cells(fdt, nodename, "reg", 141 0x0, memmap[SPIKE_CLINT].base, 142 0x0, memmap[SPIKE_CLINT].size); 143 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 144 cells, s->soc.num_harts * sizeof(uint32_t) * 4); 145 g_free(cells); 146 g_free(nodename); 147 148 if (cmdline) { 149 qemu_fdt_add_subnode(fdt, "/chosen"); 150 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 151 } 152 } 153 154 static void spike_board_init(MachineState *machine) 155 { 156 const struct MemmapEntry *memmap = spike_memmap; 157 158 SpikeState *s = g_new0(SpikeState, 1); 159 MemoryRegion *system_memory = get_system_memory(); 160 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 161 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 162 int i; 163 unsigned int smp_cpus = machine->smp.cpus; 164 165 /* Initialize SOC */ 166 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 167 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 168 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", 169 &error_abort); 170 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 171 &error_abort); 172 object_property_set_bool(OBJECT(&s->soc), true, "realized", 173 &error_abort); 174 175 /* register system main memory (actual RAM) */ 176 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 177 machine->ram_size, &error_fatal); 178 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 179 main_mem); 180 181 /* create device tree */ 182 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 183 184 /* boot rom */ 185 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 186 memmap[SPIKE_MROM].size, &error_fatal); 187 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 188 mask_rom); 189 190 if (machine->kernel_filename) { 191 riscv_load_kernel(machine->kernel_filename, htif_symbol_callback); 192 } 193 194 /* reset vector */ 195 uint32_t reset_vec[8] = { 196 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 197 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 198 0xf1402573, /* csrr a0, mhartid */ 199 #if defined(TARGET_RISCV32) 200 0x0182a283, /* lw t0, 24(t0) */ 201 #elif defined(TARGET_RISCV64) 202 0x0182b283, /* ld t0, 24(t0) */ 203 #endif 204 0x00028067, /* jr t0 */ 205 0x00000000, 206 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ 207 0x00000000, 208 /* dtb: */ 209 }; 210 211 /* copy in the reset vector in little_endian byte order */ 212 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 213 reset_vec[i] = cpu_to_le32(reset_vec[i]); 214 } 215 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 216 memmap[SPIKE_MROM].base, &address_space_memory); 217 218 /* copy in the device tree */ 219 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 220 memmap[SPIKE_MROM].size - sizeof(reset_vec)) { 221 error_report("not enough space to store device-tree"); 222 exit(1); 223 } 224 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 225 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 226 memmap[SPIKE_MROM].base + sizeof(reset_vec), 227 &address_space_memory); 228 229 /* initialize HTIF using symbols found in load_kernel */ 230 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); 231 232 /* Core Local Interruptor (timer and IPI) */ 233 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, 234 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 235 false); 236 } 237 238 static void spike_v1_10_0_board_init(MachineState *machine) 239 { 240 const struct MemmapEntry *memmap = spike_memmap; 241 242 SpikeState *s = g_new0(SpikeState, 1); 243 MemoryRegion *system_memory = get_system_memory(); 244 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 245 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 246 int i; 247 unsigned int smp_cpus = machine->smp.cpus; 248 249 if (!qtest_enabled()) { 250 info_report("The Spike v1.10.0 machine has been deprecated. " 251 "Please use the generic spike machine and specify the ISA " 252 "versions using -cpu."); 253 } 254 255 /* Initialize SOC */ 256 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 257 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 258 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type", 259 &error_abort); 260 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 261 &error_abort); 262 object_property_set_bool(OBJECT(&s->soc), true, "realized", 263 &error_abort); 264 265 /* register system main memory (actual RAM) */ 266 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 267 machine->ram_size, &error_fatal); 268 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 269 main_mem); 270 271 /* create device tree */ 272 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 273 274 /* boot rom */ 275 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 276 memmap[SPIKE_MROM].size, &error_fatal); 277 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 278 mask_rom); 279 280 if (machine->kernel_filename) { 281 riscv_load_kernel(machine->kernel_filename, htif_symbol_callback); 282 } 283 284 /* reset vector */ 285 uint32_t reset_vec[8] = { 286 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 287 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 288 0xf1402573, /* csrr a0, mhartid */ 289 #if defined(TARGET_RISCV32) 290 0x0182a283, /* lw t0, 24(t0) */ 291 #elif defined(TARGET_RISCV64) 292 0x0182b283, /* ld t0, 24(t0) */ 293 #endif 294 0x00028067, /* jr t0 */ 295 0x00000000, 296 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ 297 0x00000000, 298 /* dtb: */ 299 }; 300 301 /* copy in the reset vector in little_endian byte order */ 302 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 303 reset_vec[i] = cpu_to_le32(reset_vec[i]); 304 } 305 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 306 memmap[SPIKE_MROM].base, &address_space_memory); 307 308 /* copy in the device tree */ 309 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 310 memmap[SPIKE_MROM].size - sizeof(reset_vec)) { 311 error_report("not enough space to store device-tree"); 312 exit(1); 313 } 314 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 315 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 316 memmap[SPIKE_MROM].base + sizeof(reset_vec), 317 &address_space_memory); 318 319 /* initialize HTIF using symbols found in load_kernel */ 320 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); 321 322 /* Core Local Interruptor (timer and IPI) */ 323 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, 324 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 325 false); 326 } 327 328 static void spike_v1_09_1_board_init(MachineState *machine) 329 { 330 const struct MemmapEntry *memmap = spike_memmap; 331 332 SpikeState *s = g_new0(SpikeState, 1); 333 MemoryRegion *system_memory = get_system_memory(); 334 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 335 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 336 int i; 337 unsigned int smp_cpus = machine->smp.cpus; 338 339 if (!qtest_enabled()) { 340 info_report("The Spike v1.09.1 machine has been deprecated. " 341 "Please use the generic spike machine and specify the ISA " 342 "versions using -cpu."); 343 } 344 345 /* Initialize SOC */ 346 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 347 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 348 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type", 349 &error_abort); 350 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 351 &error_abort); 352 object_property_set_bool(OBJECT(&s->soc), true, "realized", 353 &error_abort); 354 355 /* register system main memory (actual RAM) */ 356 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 357 machine->ram_size, &error_fatal); 358 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 359 main_mem); 360 361 /* boot rom */ 362 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 363 memmap[SPIKE_MROM].size, &error_fatal); 364 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 365 mask_rom); 366 367 if (machine->kernel_filename) { 368 riscv_load_kernel(machine->kernel_filename, htif_symbol_callback); 369 } 370 371 /* reset vector */ 372 uint32_t reset_vec[8] = { 373 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */ 374 0x00028067, /* jump to DRAM_BASE */ 375 0x00000000, /* reserved */ 376 memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */ 377 0, 0, 0, 0 /* trap vector */ 378 }; 379 380 /* part one of config string - before memory size specified */ 381 const char *config_string_tmpl = 382 "platform {\n" 383 " vendor ucb;\n" 384 " arch spike;\n" 385 "};\n" 386 "rtc {\n" 387 " addr 0x%" PRIx64 "x;\n" 388 "};\n" 389 "ram {\n" 390 " 0 {\n" 391 " addr 0x%" PRIx64 "x;\n" 392 " size 0x%" PRIx64 "x;\n" 393 " };\n" 394 "};\n" 395 "core {\n" 396 " 0" " {\n" 397 " " "0 {\n" 398 " isa %s;\n" 399 " timecmp 0x%" PRIx64 "x;\n" 400 " ipi 0x%" PRIx64 "x;\n" 401 " };\n" 402 " };\n" 403 "};\n"; 404 405 /* build config string with supplied memory size */ 406 char *isa = riscv_isa_string(&s->soc.harts[0]); 407 char *config_string = g_strdup_printf(config_string_tmpl, 408 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE, 409 (uint64_t)memmap[SPIKE_DRAM].base, 410 (uint64_t)ram_size, isa, 411 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE, 412 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE); 413 g_free(isa); 414 size_t config_string_len = strlen(config_string); 415 416 /* copy in the reset vector in little_endian byte order */ 417 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 418 reset_vec[i] = cpu_to_le32(reset_vec[i]); 419 } 420 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 421 memmap[SPIKE_MROM].base, &address_space_memory); 422 423 /* copy in the config string */ 424 rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len, 425 memmap[SPIKE_MROM].base + sizeof(reset_vec), 426 &address_space_memory); 427 428 /* initialize HTIF using symbols found in load_kernel */ 429 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); 430 431 /* Core Local Interruptor (timer and IPI) */ 432 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, 433 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 434 false); 435 436 g_free(config_string); 437 } 438 439 static void spike_v1_09_1_machine_init(MachineClass *mc) 440 { 441 mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)"; 442 mc->init = spike_v1_09_1_board_init; 443 mc->max_cpus = 1; 444 } 445 446 static void spike_v1_10_0_machine_init(MachineClass *mc) 447 { 448 mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)"; 449 mc->init = spike_v1_10_0_board_init; 450 mc->max_cpus = 1; 451 } 452 453 static void spike_machine_init(MachineClass *mc) 454 { 455 mc->desc = "RISC-V Spike Board"; 456 mc->init = spike_board_init; 457 mc->max_cpus = 1; 458 mc->is_default = true; 459 mc->default_cpu_type = SPIKE_V1_10_0_CPU; 460 } 461 462 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) 463 DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) 464 DEFINE_MACHINE("spike", spike_machine_init) 465